Autonomous Tracking Unit(New Name -- Same Great Project)

John Berglund

Randy Cuaycong

Wes Day

Andrew Fikes

Kamran Shah

Spring 1999 CPSC 483 Midterm Evaluation

Project Status

Project Goals (Revised):• Develop a 2-dimensional servo control system • Develop a camera platform• Implement an FPGA to camera interface• Develop a memory and camera control system • Develop a motion tracking algorithm• Implement the algorithm in hardware• Integrate components

Objective:

• Develop an autonomous camera that can identify and track an object in motion

System Diagram (Revised)

SRAM

Motion Detection Hardware

Camera Interface

Camera

Servo Control

Memory & Camera Control

Servos

• Divides the pulse into 10000 increments.

• Minimum pulse = 625 increments• Maximum pulse = 875 increments• Problem

– Large CLB requirement due to 14-bit counter.

10000 increments

20ms

Servo Control Design #1

• Test the MSB for minimum pulse length.

• 6-bit input angle and a 7-bit internal counter

• Problems

– Wrong range of pulse duty cycle. Not 1.25-1.75ms

– Did not provide small enough increments.

Bit 6 5 4 3 2 1 0

If (bit 6 == 0) {Minimum pulse not reached

} else {Minimum pulse reachedTest for angle

}

If (bit5:0 == angle) {Minimum+angle pulse length generated.

Pulse = 0;}

Servo Control Design #2

• Use 8-bit counter twice• Increment for minimum pulse length.• Reset and increment angle.• Problem

– CLB count increased as in Design #1

• Backed up to Design #2.

• 8-bit input angle with 9-bit internal counter.

• Test for MSB.

• Minimum pulse length => 1|0000|0000 - minimum number of pulses

Servo Control Design #3

Final Design

Servo Control Final Design

Camera Platform

Servo

Camera

Camera Interface I

• Supports all QuickCam nibble-mode commands

• Reduced Xilinx footprint from previous implementations

• Fully tested and operational

• Speed is limited by handshaking protocol

• Difficult for outside logic to control and initialize camera

Memory and Camera

Control

Camera Interface Module

QuickCamInstruction (8)

Parameter (8)

Start

Hold

Send

Rdy

Valid

Data (8)

Nibble (4)

PCAck

Reset

Command (8)

CamRdy

Camera Interface II

Memory and Camera

Control

Camera Interface Module

QuickCam

Start

Hold

Send

Valid

Data (8)

Nibble (4)

PCAck

Reset

Command

CamRdy

Command (8) • Removes handshaking protocol

• Reduces complexity of controlling logic

• Initialization and video frame size are configurable

• Easily integrated into other team’s projects

Camera Interface II Components

MemoryControlModule

Executing aninstruction ?

WhichInstruction?

Is thealgorithmmodulesending aninstruction?

Yes

No

Yes Get theInstructionand BeginExecuting

it.

No

Get VideoFrame

Get VideoFrame

Read Data

Read DataFrom

Memory

Memory & Camera ControlFlow Chart

Memory & Camera Control Block Diagram

Algorithm Test & Development

• Goal was to develop and test several algorithms

• Use software to help us visually compare solutions

• Tests will compare performance in different scenarios

Project TimelineDate GoalsTues. March 30 Restore working camera design (old version)

Complete wiring of project board and SRAMSuccessfully download memory control module to FPGA

Thurs. April 1 Finish memory control module testingComplete wrapper around old camera designAlgorithm options coded in JAVA

Tues. April 6 Complete algorithm testing and selectionIntegrate memory control module with camera interface

Thurs. April 8 Algorithm coded in VerilogTues. April 13 Algorithm downloaded and tested in FPGAThurs. April 18 System integration (algorithm to memory control module)Tues. April 23 System integration (servos to algorithm/memory control module)Thurs. April 25 System improvementTues. April 27 Documentation and final report preparationThurs. April 29 Final presentation (WHOOP!)

Project Ratings

Project Difficulty (Overall) 2 Camera Interface I 2 Camera Interface II 1 Servo Control 2 Camera Platform 3 Memory & Camera Control 2

Team Coordination 2Lab Support 2