automotive mcu
TRANSCRIPT
Freescale SemiconductorProduct Brief
9S12XDFAMPPRev. 2.16, 27-May-2006
MC9S12XD Family16-bit Microprocessor Family (covers MC9S12XD64 throughMC9S12XDP512 and MC3S12XDT256/MC3S12XDG128)
Introduction
Targeted at automotive multiplexing applications, the MC9S12XD Family will deliver 32-bit performancewith all the advantages and efficiencies of a 16-bit MCU. The S12X is designed to retain the low cost, lowpower consumption, excellent EMC performance and code-size efficiency advantages enjoyed by usersof Freescale's previous 16-bit MC9S12 MCU family.
Based around an enhanced S12 core, the MC9S12XD Family will deliver two to five times theperformance of a 25 MHz S12 whilst retaining a high degree of pin and code compatibility with the originalS12D - family.
The MC9S12XD Family features the performance boosting XGATE co-processor. The XGATE, which isprogrammable in "C" language, has an instruction set which is optimized for data movement, logic andbit manipulation instructions. It runs at twice the bus frequency of the S12X and off-loads the CPU byproviding high speed data transfer (and data processing) between any peripheral module, RAM and I/Oports. This is particularly useful in applications such as automotive gateways where there are multiplebusses carrying heavy data traffic which would otherwise exert a heavy interrupt/processing load on theCPU.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Features
The MC9S12XD Family will feature an enhanced MSCAN module which, when used in conjunction withXGATE, delivers FullCAN performance with virtually unlimited number of mailboxes and retainsbackwards compatibility with the MSCAN module featured on previous S12 products.
Memory options will range from 64 Kbytes to 512 Kbytes of Freescale's industry-leading, full automotivespec SG-Flash with additional integrated EEPROM.
In addition to the rich S12 peripheral set, the MC9S12XD Family will feature more RAM, extra A/Dchannels, new timer features and additional LIN-compatible SCI ports compared with the original S12 D-Family. The MC9S12XD Family also features a new flexible interrupt handler which allows multilevelnested interrupts.
The MC9S12XD Family has full 16-bit data paths throughout. The non-multiplexed expanded businterface available on the 144-pin versions allows an easy interface to external memories. The inclusionof a PLL circuit allows power consumption and performance to be adjusted to suit operationalrequirements. System power consumption is further improved with the new “fast exit from STOP mode”feature and an ultra low power wakeup timer.
In addition to the I/O ports available in each module, up to 25 further I/O ports are available with interruptcapability allowing wakeup from STOP or WAIT mode.
The MC9S12XD Family will be available in 144-pin LQFP (with optional external bus), 112-pin, and 80-pinoptions.
Features
Features of the MC9S12XD Family are listed here. Please see Table 1 for memory options and Table 2for the peripheral features that are available on the different family members.
16-bit CPU12X
• Upward compatible with MC9S12 instruction set
• Enhanced indexed addressing
• Additional (superset) instructions to improve 32-bit calculations andsemaphore handling
• Access large data segments independent of PPAGE
Enhanced InterruptModule
• Eight levels of nested interrupt
• Flexible assignment of interrupt sources to each interrupt level.
• One non-maskable high priority interrupt (XIRQ)
• Wakeup interrupt inputs– IRQ and non-maskable XIRQ
MC9S12XD Family, Rev. 2.16
2 Freescale Semiconductor
Features
XGATE
• Programmable, high performance I/O co-processor module — up to80 MIPS RISC performance
• Transfers data to or from all peripherals and RAM without CPUintervention or CPU wait states
• Performs logical, shifts, arithmetic, and bit operations on data
• Enables FullCAN capability when used in conjunction with MSCANmodule
• Full LIN master or slave capability when used in conjunction with thesix integrated LIN SCI modules
• Can interrupt the HCS12X CPU signalling transfer completion
• Triggers from any hardware module as well as from the CPU possible
Memory Options
• 64K, 128K, 256K, 384K and 512K byte Flash
• 128K and 256K ROM
• Flash General Features– Automated program and erase algorithm– Fast sector erase and word program operation– 2-stage command pipeline for faster multi-word program times– Sector erase abort feature for critical interrupt response– Protection scheme to prevent accidental program or erase– Automated program and erase algorithm– Fast sector erase and word program operation– 2-stage command pipeline for faster multi-word program times– Sector erase abort feature for critical interrupt response– Protection scheme to prevent accidental program or erase
• 4K, 8K, 12K, 14K, 16K, 20K, 32K Byte RAM
Oscillator (OSC_LCP)
• Loop control Pierce oscillator using a 0.5 MHz to 16 MHz crystal
• Option for full-swing Pierce without internal feedback resistor using a0.5 MHz to 40 MHz crystal
• Current gain control on amplitude output– Signal with low harmonic distortion– Low power– Good noise immunity– Eliminates need for external current limiting resistor
• Transconductance sized for optimum start-up margin for typicalcrystals
• Clock monitor
MC9S12XD Family, Rev. 2.16
Freescale Semiconductor 3
Features
Clock and ResetGenerator (CRG)
• Phase-locked-loop clock frequency multiplier– Reference divider– Automatic bandwidth control mode for low-jitter operation– Automatic frequency lock detector
• Fast wakeup from STOP in self clock mode for power saving andimmediate program execution
• Computer operating properly (COP) watchdog with optional safetywindow to initialize timeout counter
• Real time interrupt for task scheduling purposes or cyclic wakeupfrom low power modes
• System reset generation
Non-MultiplexedExternal Bus
(144 Pin package only)
• 16 bit data
• Support for external WAIT input or internal wait cycles to adapt MCUspeed to peripheral speed requirements
• Up to four chip select outputs to select 16K, 1M, 2M and 4M byteaddress spaces
• Supports glue-less interface to popular asynchronous RAMs andFlash devices
• External address space 4M byte for data and program space
Analog-to-DigitalConverter (ATD)
• Programmable sample time
• Left/right, signed/unsigned result data
• Continuous conversion mode
• Multiple channel scans
• Pins can also be used as digital I/O
Enhanced CaptureTimer (ECT)
• Eight 16-bit channels for input capture or output compare
• One 16-bit free-running counter with 8-bit precision prescaler
• One 16-bit modulus down counter with 8-bit precision prescaler
• Four 8-bit or two 16-bit pulse accumulators
• Four channels have enhanced input capture capabilities:– Delay counter for noise immunity– 16-bit capture buffer– 8-bit pulse accumulator buffer
Periodic InterruptTimer (PIT)
• Four channel x 24-bit modulus down-count timers– Timeout interrupt– Timeout peripheral trigger
• Start of timers can be aligned
MC9S12XD Family, Rev. 2.16
4 Freescale Semiconductor
Features
Pulse WidthModulator (PWM)
• Eight channel x 8-bit or four channel x 16-bit pulse width modulator
• Programmable period and duty cycle per channel
• Center-aligned or left-aligned outputs
• Programmable clock select logic with a wide range of frequencies
Multi-scalableController
Area Networks(MSCAN)
• Up to five MSCAN modules (see )
• CAN 2.0 A, B software compatible– Standard and extended data frames– 0–8 bytes data length– Programmable bit rate up to 1 Mbps
• Five receive buffers with FIFO storage scheme
• Three transmit buffers with internal prioritization
• Flexible identifier acceptance filter programmable as:– 2 x 32-bit– 4 x 16-bit– 8 x 8-bit
• Wakeup with integrated low-pass filter option
• Loop back for self test
• Listen-only mode to monitor CAN bus
• Bus-off recovery by software intervention or automatically
• 16-bit time stamp of transmitted/received messages
• FullCAN capability when used in conjunction with XGATE
Serial PeripheralInterface (SPI)
• Up to three SPI modules (see )
• Full-duplex or single-wire bidirectional
• Double-buffered transmit and receive
• Master or slave mode
• MSB-first or LSB-first shifting
• Serial clock phase and polarity options
Serial CommunicationInterfaces (SCI)
• Up to six SCI modules (see )
• Full-duplex or single wire operation
• Standard mark/space non-return-to-zero (NRZ) format
• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format withprogrammable pulse widths
• 13-bit baud rate selection
• Programmable character length
• Programmable polarity for transmitter and receiver
• Receive wakeup on active edge
• Break detect and transmit collision detect supporting LIN
MC9S12XD Family, Rev. 2.16
Freescale Semiconductor 5
Features
Inter IC Module (IIC)
• Up to two IIC modules (see )
• Compatible with I2C Bus standard
• Multi-master operation
• Software programmable for one of 256 different serial clockfrequencies
• Software selectable acknowledge bit
• Interrupt driven byte-by-byte data transfer
• Arbitration lost interrupt with automatic mode switching from masterto slave
• Calling address identification interrupt
• Start and stop signal generation/detection
• Repeated start signal generation
• Acknowledge bit generation/detection
• Bus busy detection
• supports 400 Kbps
Background Debug(BDM)
•– Non-intrusive memory access commands– Supports in-circuit programming of on-chip non-volatile memory– Supports security
Debugger (XDBG)
– Each can monitor CPU or XGATE busses– A and C compares 23-bit address bus and 16-bit data bus with
mask register– Three modes: simple address/data match, inside address range
or outside address range
•
System Protection• Power-on reset (POR)
• with interrupt or reset
Input/Output
• up to 117 general-purpose input/output (I/O) pins depending on thepackage option and 2 input-only pins
• Hysteresis and configurable pullup/pulldown device on all input pins
• Configurable drive strength on all output pins
Package Options
• 144-pin low-profile quad flat-pack (LQFP)
• 112-pin low-profile quad flat-pack (LQFP)
• 80-pin quad flat-pack (QFP)
MC9S12XD Family, Rev. 2.16
6 Freescale Semiconductor
Features
Operating Conditions
• Ambient temperature range -40°C to 125°C• Temperature options:
– -40°C to 85°C– -40°C to 105°C– -40°C to 125°C
• Supply voltage 3.15V to 5.5V
• Internal voltage regulator providing 2.5 V logic supply– 40 MHz maximum CPU bus frequency in single chip mode– 80 MHz maximum XGATE bus frequency
MC9S12XD Family, Rev. 2.16
Freescale Semiconductor 7
MC9S12XD Family Block Diagram
MC9S12XD Family Block Diagram
MC9S12XD Family, Rev. 2.16
8 Freescale Semiconductor
MC9S12XD Family Block Diagram
512K/384K/256k/128K/64K Byte Flash
32K/20K/16K/14K/12K/8K/4K Byte RAM
Enhanced Capture
RESET
EXTALXTAL
SCI0
4K/2K/1K Byte EEPROM
BKGD
R/W/WE
MODB/TAGHI
XIRQ
ECLKX2/XCLKS
VDDR
CPU12X
Periodic InterruptCOP WatchdogClock Monitor
Single-wire Background
Breakpoints
PLLVSSPLL
XFCVDDPLL
VDDAVSSA
VRHVRLATD0
IRQ
LSTRB/LDS/EROMCTLECLKMODA/RE/TAGLO
PA4PA3PA2PA1PA0
PA7PA6PA5
TEST
ADDR12ADDR11ADDR10ADDR9ADDR8
ADDR15ADDR14ADDR13
PB4PB3PB2PB1PB0
PB7PB6PB5
ADDR4ADDR3ADDR2ADDR1
ADDR7ADDR6ADDR5
PE3PE4PE5PE6PE7
PE0PE1PE2
AN2
AN6
AN0
AN7
AN1
AN3AN4AN5
PAD03PAD04PAD05PAD06PAD07
PAD00PAD01PAD02
IOC2
IOC6
IOC0
IOC7
IOC1
IOC3IOC4IOC5
PT3PT4PT5PT6PT7
PT0PT1PT2
RXDTXD
MISOMOSI
PS3PS4PS5
PS0PS1PS2SCI1
RXDTXD
PP3PP4PP5PP6PP7
PP0PP1PP2
SCKSS
PS6PS7
SPI0
IIC0SDASCL
PJ2 CS1PJ4 CS0
CAN0RXCANTXCAN PM1
PM0
CAN1RXCANTXCAN
PM2PM3
CAN2RXCANTXCAN
PM4PM5PM6PM7
KWH2
KWH6
KWH0
KWH7
KWH1
KWH3KWH4KWH5
PH3PH4PH5PH6PH7
PH0PH1PH2
KWJ0KWJ1
PJ0 CS3PJ1
DD
RA
DD
RB
PT
AP
TB
DD
RE
PT
E
DD
RA
D0
& A
D0
PT
T
DD
RT
PT
P
DD
RP
PT
S
DD
RS
PT
M
DD
RM
PT
H
DD
RH
PT
J
DD
RJ
Clock andResetGenerationModule
Voltage RegulatorVSSR
Debug Module
VDD1,2VSS1,2
VREGEN
VDDR1,2VSSR1,2
Voltage Regulator 3-5V
CAN4RXCANTXCAN
MISOMOSISCK
SS
SPI2
MISOMOSISCK
SS
SPI1
KWP2
KWP6
KWP0
KWP7
KWP1
KWP3KWP4KWP5
KWJ2KWJ4
Timer
Sign
als
show
n in
Bold
-Ital
ics
are
neith
er a
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ble
on th
e 11
2 Pi
n no
r on
the
80 P
in P
acka
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n
Mod
ule
to P
ort R
outin
g
PWM2
PWM6
PWM0
PWM7
PWM1
PWM3PWM4PWM5
PWM
8 Bit PPAGEIQSTAT2
IQSTAT0IQSTAT1
ACC2
PK3
PK6
PK0PK1
ADDR19
EWAIT
ADDR16ADDR17ADDR18 P
TK
DD
RK
PK2
ACC1PK4PK5
ADDR20ADDR21
ROMCTL/EWAITPK7ADDR22
VRHVRL
VDDAVSSA
VRHVRLATD1
AN10
AN14
AN8
AN15
AN9
AN11AN12AN13
PAD11PAD12PAD13PAD14PAD15
PAD08PAD09PAD10
VDDAVSSA
DD
RA
D1
& A
D1
AN18
AN22
AN16
AN23
AN17
AN19AN20AN21
PAD19PAD20PAD21PAD22PAD23
PAD16PAD17PAD18
PC4PC3PC2PC1PC0
PC7PC6PC5
DATA12DATA11DATA10DATA9DATA8
DATA15DATA14DATA13
PD4PD3PD2PD1PD0
PD7PD6PD5
DATA4DATA3DATA2DATA1DATA0
DATA7DATA6DATA5
DD
RC
DD
RD
PT
CP
TD
SCI2RXDTXD
PJ6PJ7
PJ5 CS2KWJ5KWJ6KWJ7
Non
-Mul
tiple
xed
Ext
erna
l Bus
Inte
rfac
e (E
BI)
VDDX1,2VSSX1,2
I/O Supply 3-5V
VDDAVSSA
Analog Supply 3-5V
VDDPLLVSSPLL
PLL Supply 2.5V
Enhanced MultilevelInterrupt Module
XGATEPeripheral Co-Processor
VDD1,2VSS1,2
Digital Supply 2.5V
Sign
als
show
n in
Bold
are
not
ava
ilabl
e on
the
80 P
in P
acka
ge
Allows 4MByteProgram space
SCI3RXDTXD
SCI4RXDTXD
SCI5RXDTXD
IIC1SDASCL
Timer4 channel
16 bit with Prescalerfor internal timebases
CAN3RXCANTXCAN
ADDR0UDS
IQSTAT3ACC0
MC9S12XD Family, Rev. 2.16
Freescale Semiconductor 9
MC9S12XD Family Block Diagram
Table 1. Package and Memory Options of MC9S12XD Family Members
Device Package Flash RAM EEPROM ROM
9S12XDP512144 LQFP
512K
32K
4K
112 LQFP
9S12XDT512
144 LQFP
20K112 LQFP
80 QFP
9S12XDT384
144 LQFP
384K 20K112 LQFP
80 QFP
9S12XDQ256
144 LQFP
256K
16K
112 LQFP
80 QFP
9S12XDT256
144 LQFP
112 LQFP
80 QFP
9S12XD256
144 LQFP
14K112 LQFP
80 QFP
3S12XDT256
144 LQFP
16K (1)
NOTES:1. No EEPROM is available on ROM versions.
256K112 LQFP
80 QFP
9S12XDG128112 LQFP
128K
12K
2K80 QFP
3S12XDG128112 LQFP
(1) 128K80 QFP
9S12XD128112 LQFP
128K 8K 2K80 QFP
9S12XD64 80 QFP 64K 4K 1K
MC9S12XD Family, Rev. 2.16
10 Freescale Semiconductor
MC9S12XD Family Block Diagram
Table 2. Peripheral Options of MC9S12XD Family Members
Device Package XGATE CAN SCI SPI IIC ECT PIT A/D I/O
9S12XDP512144LQFP
yes
5 6 3 2 8 4 2/24 119
112LQFP 5 6 3 1 8 4 2/16 91
9S12XDT512
144LQFP 3 6 3 1 8 4 2/24 119
112LQFP 3 6 3 1 8 4 2/16 91
80QFP 3 2 3 1 8 4 1/8 59
9S12XDT384
144LQFP 3 4 3 1 8 4 2/24 119
112LQFP 3 4 3 1 8 4 2/16 91
80QFP 3 2 3 1 8 4 1/8 59
9S12XDQ256
144LQFP 4 4 3 1 8 4 2/24 119
112LQFP 4 4 3 1 8 4 2/16 91
80QFP 4 2 3 1 8 4 1/8 59
9S12XDT256
144LQFP 3 4 3 1 8 4 2/24 119
112LQFP 3 4 3 1 8 4 2/16 91
80QFP 3 2 3 1 8 4 1/8 59
9S12XD256
144LQFP 1 4 3 1 8 4 2/24 119
112LQFP 1 4 3 1 8 4 2/16 91
80QFP 1 2 3 1 8 4 1/8 59
3S12XDT256
144LQFP 3 4 3 1 8 4 2/24 119
112LQFP 3 4 3 1 8 4 2/16 91
80QFP 3 2 3 1 8 4 1/8 59
9S12XDG128112LQFP
yes(1)
2 2 2 1 8 4 1/16(2) 91
80QFP 2 2 2 1 8 4 1/8 59
3S12XDG128112LQFP 2 2 2 1 8 4 1/16(2) 91
80QFP 2 2 2 1 8 4 1/8 59
9S12XD128112LQFP 1 2 2 1 8 4 1/16(2) 91
80QFP 1 2 2 1 8 4 1/8 59
9S12XD64 80QFP 1 2 2 1 8 2 1/8 59
NOTES:1. Can execute code only from RAM2. ATD1 routed to PAD00-15 instead of PAD08-23.
MC9S12XD Family, Rev. 2.16
Freescale Semiconductor 11
MC9S12XD Family Block Diagram
Pinout explanations:
• A/D is the number of modules/total number of A/D channels.
• I/O is the sum of ports capable to act as digital input or output.
– 144 Pin Packages:Port A = 8, B = 8, C=8, D=8, E = 6 + 2 input only,H = 8, J = 7, K = 8, M = 8, P = 8, S = 8, T = 8, PAD = 2425 inputs provide Interrupt capability (H =8, P= 8, J = 7, IRQ, XIRQ)
– 112 Pin Packages:Port A = 8, B = 8, E = 6 + 2 input only, H = 8, J = 4, K = 7, M = 8, P = 8, S = 8, T = 8, PAD = 1622 inputs provide Interrupt capability (H =8, P= 8, J = 4, IRQ, XIRQ)
– 80 Pin Packages:Port A = 8, B = 8, E = 6 + 2 input only, J = 2, M = 6, P = 7, S = 4, T = 8, PAD = 811 inputs provide Interrupt capability (P= 7, J = 2, IRQ, XIRQ)
• CAN0 can be routed under software control from PM[1:0] to pins PM[3:2] or PM[5:4] or PJ[7:6].
• CAN4 pins are shared between IIC0 pins.
• CAN4 can be routed under software control from PJ[7:6] to pins PM[5:4] or PM[7:6].
• Versions with 5 CAN modules will have CAN0, CAN1, CAN2, CAN3 and CAN4
• Versions with 4 CAN modules will have CAN0, CAN1, CAN2 and CAN4
• Versions with 3 CAN modules will have CAN0, CAN1 and CAN4.
• Versions with 2 CAN modules will have CAN0 and CAN4.
• Versions with 1 CAN modules will have CAN0
• Versions with 2 SPI modules will have SPI0 and SPI1.
• Versions with 4 SCI modules will have SCI0, SCI1, SCI2 and SCI4.
• Versions with 2 SCI modules will have SCI0 and SCI1.
• Versions with 1 IIC module will have IIC0.
• SPI0 can be routed to either Ports PS[7:4] or PM[5:2].
• SPI1 pins are shared with PWM[3:0]; In 144 and 112-pin versions, SPI1 can be routed undersoftware control to PH[3:0].
• SPI2 pins are shared with PWM[7:4]; In 144 and 112-pin versions, SPI2 can be routed undersoftware control to PH[7:4]. In 80-pin packages, SS-signal of SPI2 is not bonded out!
MC9S12XD Family, Rev. 2.16
12 Freescale Semiconductor
Pin Assignments
Pin Assignments
Table 3. Port and Peripheral Availability by Package Option
Port 144 LQFP 112 LQFP 80 QFP
Port AD/ADC Channels 24/24 16/16 8/8
Port A pins 8 8 8
Port B pins 8 8 8
Port C pins 8 0 0
Port D pins 8 0 0
Port E pins incl. IRQ/XIRQ input only 8 8 8
Port H pins 8 8 0
Port J pins 7 4 2
Port K pins 8 7 0
Port M pins 8 8 6
Port P pins 8 8 7
Port S pins 8 8 4
Port T pins 8 8 8
Sum of Ports 119 91 59
VDDX/VSSX 4/4 3/3 2/2
Table 4. Peripheral–Port Cross Reference(1)
CA
N0
CA
N1
CA
N2
CA
N3
CA
N4
SC
I0
SC
I1
SC
I2
SC
I3
SC
I4
SC
I5
SP
I0
SP
I1
SP
I2
IIC0
IIC1
PJ1:0 X
PJ3:2
PJ5:4 X
PJ7:6 O X X
PM1:0 X
PM3:2 O X O
PM5:4 O X O
PM7:6 X O X
PS1:0 X
PS3:2 X
PS7:4 X
PH3:0 O
MC9S12XD Family, Rev. 2.16
Freescale Semiconductor 13
Pin Assignments
PH5:4 X O
PH7:6 X O
PP3:0 X
PP7:4 X
NOTES:1. X denotes the reset condition and O denotes a possible rerouting under software control
Table 5. Pin-Out Summary(1)
LQFP144
LQFP112
QFP80 Pin 2nd
Function3rd
Function4th
Function5th
Function
1 1 1 PP3 KWP3 PWM3 SS1
2 2 2 PP2 KWP2 PWM2 SCK1
3 3 3 PP1 KWP1 PWM1 MOSI1
4 4 4 PP0 KWP0 PWM0 MISO1
5 PJ2 KWJ2 CS1
6 PK6 ADDR22 NOACC
7 5 PK3 ADDR19
8 6 PK2 ADDR18 IQSTAT2
9 7 PK1 ADDR17 IQSTAT1
10 8 PK0 ADDR16 IQSTAT0
11 9 5 PT0 IOC0
12 10 6 PT1 IOC1
13 11 7 PT2 IOC2
14 12 8 PT3 IOC3
15 13 9 VDD1
16 14 10 VSS1
17 15 11 PT4 IOC4
18 16 12 PT5 IOC5
19 17 13 PT6 IOC6
20 18 14 PT7 IOC7
21 19 PK5 ADDR21
22 20 PK4 ADDR20
23 21 PJ1 KWJ1 TXD2
24 22 PJ0 KWJ0 RXD2
Table 4. Peripheral–Port Cross Reference(1)
CA
N0
CA
N1
CA
N2
CA
N3
CA
N4
SC
I0
SC
I1
SC
I2
SC
I3
SC
I4
SC
I5
SP
I0
SP
I1
SP
I2
IIC0
IIC1
MC9S12XD Family, Rev. 2.16
14 Freescale Semiconductor
Pin Assignments
25 23 15 BKGD MODC
26 VDDX2
27 VSSX2
28 PC0 DATA8
29 PC1 DATA9
30 PC2 DATA10
31 PC3 DATA11
32 24 16 PB0 ADDR0 UDS
33 25 17 PB1 ADDR1
34 26 18 PB2 ADDR2
35 27 19 PB3 ADDR3
36 28 20 PB4 ADDR4
37 29 21 PB5 ADDR5
38 30 22 PB6 ADDR6
39 31 23 PB7 ADDR7
40 PC4 DATA12
41 PC5 DATA13
42 PC6 DATA14
43 PC7 DATA15
44 32 PH7 KWH7 SS2 TXD5
45 33 PH6 KWH6 SCK2 RXD5
46 34 PH5 KWH5 MOSI2 TXD4
47 35 PH4 KWH4 MISO2 RXD4
48 36 24 PE7 XCLKS ECLKX2
49 37 25 PE6 MODB TAGHI
50 38 26 PE5 MODA TAGLO RE
51 39 27 PE4 ECLK
52 40 28 VSSR
53 41 29 VDDR
54 42 30 RESET
55 43 31 VDDPLL
56 44 32 XFC
57 45 33 VSSPLL
58 46 34 EXTAL
59 47 35 XTAL
60 48 36 TEST
61 49 PH3 KWH3 SS1 TXD7
Table 5. Pin-Out Summary(1)
LQFP144
LQFP112
QFP80 Pin 2nd
Function3rd
Function4th
Function5th
Function
MC9S12XD Family, Rev. 2.16
Freescale Semiconductor 15
Pin Assignments
62 50 PH2 KWH2 SCK1 RXD7
63 51 PH1 KWH1 MOSI1 TXD6
64 52 PH0 KWH0 MISO1 RXD6
65 PD0 DATA0
66 PD1 DATA1
67 PD2 DATA2
68 PD3 DATA3
69 53 37 PE3 LSTRB LDS EROMCTL
70 54 38 PE2 RW WE
71 55 39 PE1 IRQ
72 56 40 PE0 XIRQ
73 57 41 PA0 ADDR8
74 58 42 PA1 ADDR9
75 59 43 PA2 ADDR10
76 60 44 PA3 ADDR11
77 61 45 PA4 ADDR12
78 62 46 PA5 ADDR13
79 63 47 PA6 ADDR14
80 64 48 PA7 ADDR15
81 VDDX3
82 VDDX3
83 PD4 DATA4
84 PD5 DATA5
85 PD6 DATA6
86 PD7 DATA7
87 65 49 VDD2
88 66 50 VSS2
89 67 51 PAD00 AN0
90 68 PAD08 AN8
91 69 52 PAD01 AN1
92 70 PAD09 AN9
93 71 53 PAD02 AN2
94 72 PAD10 AN8
95 73 54 PAD03 AN3
96 74 PAD11 AN11
97 75 55 PAD04 AN4
98 76 PAD12 AN12
Table 5. Pin-Out Summary(1)
LQFP144
LQFP112
QFP80 Pin 2nd
Function3rd
Function4th
Function5th
Function
MC9S12XD Family, Rev. 2.16
16 Freescale Semiconductor
Pin Assignments
99 77 56 PAD05 AN5
100 78 PAD13 AN13
101 79 57 PAD06 AN6
102 80 PAD14 AN14
103 81 58 PAD07 AN7
104 82 PAD15 AN15
105 PAD16 AN16
106 PAD17 AN17
107 83 59 VDDA
108 84 60 VRH
109 85 61 VRL
110 86 62 VSSA
111 PAD18 AN18
112 PAD19 AN19
113 PAD20 AN20
114 PAD21 AN21
115 PAD22 AN22
116 PAD23 AN23
117 87 PM7 TXCAN3 TXCAN4 TXD3
118 88 PM6 RXCAN3 RXCAN4 RXD3
119 89 63 PS0 RXD0
120 90 64 PS1 TXD0
121 91 65 PS2 RXD1
122 92 66 PS3 TXD1
123 93 PS4 MISO0
124 94 PS5 MOSI0
125 95 PS6 SCK0
126 96 PS7 SS0
127 97 67 VREGEN
128 98 68 PJ7 KWJ7 TXCAN4 SCL0
129 99 69 PJ6 KWJ6 RXCAN4 SDA0
130 PJ5 KWJ5 SCL1 CS2
131 PJ4 KWJ4 SDA1 CS0
132 100 70 PM5 TXCAN2 TXCAN0 TXCAN4 SCK0
133 101 71 PM4 RXCAN2 RXCAN0 RXCAN4 MOSI0
134 102 72 PM3 TXCAN1 TXCAN0 SS0
135 103 73 PM2 RXCAN1 RXCAN0 MISO0
Table 5. Pin-Out Summary(1)
LQFP144
LQFP112
QFP80 Pin 2nd
Function3rd
Function4th
Function5th
Function
MC9S12XD Family, Rev. 2.16
Freescale Semiconductor 17
Pin Assignments
136 104 74 PM1 TXCAN0
137 105 75 PM0 RXCAN0
138 106 76 VSSX1
139 107 77 VDDX1
140 108 PK7 ROMCTL EWAIT
141 109 78 PP7 KWP7 PWM7 SCK2
142 110 PP6 KWP6 PWM6 SS2
143 111 79 PP5 KWP5 PWM5 MOSI2
144 112 80 PP4 KWP4 PWM4 MISO2
NOTES:1. Table shows a superset of pin functions. Not all functions are available on all derivatives
Table 5. Pin-Out Summary(1)
LQFP144
LQFP112
QFP80 Pin 2nd
Function3rd
Function4th
Function5th
Function
MC9S12XD Family, Rev. 2.16
18 Freescale Semiconductor
Pin Assignments
Figure 1. MC9S12XD Family Pin Assignments for 144-pin LQFP Package
SS1/PWM3/KWP3/PP3SCK1/PWM2/KWP2/PP2
MOSI1/PWM1/KWP1/PP1MISO1/PWM0/KWP0/PP0
CS1/KWJ2/PJ2NOACC/ADDR22/PK6
ADDR19/PK3IQSTAT2/ADDR18/PK2IQSTAT1/ADDR17/PK1IQSTAT0/ADDR16/PK0
IOC0/PT0IOC1/PT1IOC2/PT2IOC3/PT3
VDD1VSS1
IOC4/PT4IOC5/PT5IOC6/PT6IOC7/PT7
ADDR21/PK5ADDR20/PK4
TXD2/KWJ1/PJ1RXD2/KWJ0/PJ0
MODC/BKGDVDDX2VSSX2
DATA8/PC0DATA9/PC1
DATA10/PC2DATA11/PC3
UDS/ADDR0/PB0ADDR1/PB1ADDR2/PB2ADDR3/PB3ADDR4/PB4
ADD
R5/
PB5
ADD
R6/
PB6
ADD
R7/
PB7
DATA
12/P
C4DA
TA13
/PC5
DATA
14/P
C6DA
TA15
/PC7
TXD5
/ SS2
/KW
H7/P
H7RX
D5/S
CK2/
KWH6
/PH6
TXD4
/MO
SI2/
KWH5
/PH5
RXD4
/MIS
O2/
KWH4
/PH4
XCLK
S/EC
LK2X
/PE7
TAG
HI/M
OD
B/PE
6R
E/TA
GLO
/MO
DA/P
E5EC
LK/P
E4VS
SRVD
DR
RES
ETVD
DPL
LXF
CVS
SPLL
EXTA
LXT
ALTE
STSS
1/KW
H3/P
H3SC
K1/K
WH2
/PH2
MO
SI1/
KWH1
/PH1
MIS
O1/
KWH0
/PH0
PD0/
DATA
0PD
1/DA
TA1
PD2/
DATA
2PD
3/DA
TA3
ERO
MC
TL/ L
DS/
LSTR
B/PE
3W
E/RW
/PE2
IRQ
/PE1
XIR
Q/P
E0
VRHVDDAPAD17/AN17PAD16/AN16PAD15/AN15PAD07/AN07PAD14/AN14PAD06/AN06PAD13/AN13PAD05/AN05PAD12/AN12PAD04/AN04PAD11/AN11PAD03/AN03PAD10/AN10PAD02/AN02PAD09/AN09PAD01/AN01PAD08/AN08PAD00/AN00VSS2VDD2PD7/DATA7PD6/DATA6PD5/DATA5PD4/DATA4VDDX3VSSX3PA7/ADDR15PA6/ADDR14PA5/ADDR13PA4/ADDR12PA3/ADDR11PA2/ADDR10PA1/ADDR9PA0/ADDR8
PP4/
KWP4
/PW
M4/
MIS
O2
PP5/
KPW
5/PW
M5/
MO
SI2
PP6/
KWP6
/PW
M6/
SS2
PP7/
KWP7
/PW
M7/
SCK2
PK7/
ROM
CTL/
EWAI
TVD
DX1
VSSX
1PM
0/R
XCAN
0PM
1/TX
CAN
0PM
2/R
XCAN
1/R
XCAN
0/M
ISO
0PM
3/TX
CAN
1/TX
CAN
0/SS
0PM
4/R
XCAN
2/R
XCAN
0/R
XCAN
4/M
OSI
0PM
5/TX
CAN
2/TX
CAN
0/TX
CAN
4/SC
K0PJ
4/KW
J4/S
DA1/
CS0
PJ5/
KWJ5
/SCL
1/CS
2PJ
6/KW
J6/R
XCAN
4/SD
A0PJ
7/KW
J7/T
XCAN
4/SC
L0VR
EGEN
PS7/
SS0
PS6/
SCK0
PS5/
MO
SI0
PS4/
MIS
O0
PS3/
TXD
1PS
2/R
XD1
PS1/
TXD
0PS
0/R
XD0
PM6/
RXCA
N3/R
XCAN
4/RX
D3PM
7/TX
CAN3
/TXC
AN4/
TXD3
PAD2
3/AN
23PA
D22/
AN22
PAD2
1/AN
21PA
D20/
AN20
PAD1
9/AN
19PA
D18/
AN18
VSSA
VRL
MC9S12XD Family144 LQFP
Pins shown in BOLD are not available on the 80 QFP package
123456789101112131415161718192021222324252627282930313233343536
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
108107106105104103102101100999897969594939291908988878685848382818079787776757473
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
Pins shown in BOLD-ITALICS are bit available on the 112 LQFPnor on the 80 QFP Package Option
MC9S12XD Family, Rev. 2.16
Freescale Semiconductor 19
Pin Assignments
Figure 2. MC9S12XD Family Pin Assignments for 112-pin LQFP Package
VRHVDDAPAD15/AN15PAD07/AN07PAD14/AN14PAD06/AN06PAD13/AN13PAD05/AN05PAD12/AN12PAD04/AN04PAD11/AN11PAD03/AN03PAD10/AN10PAD02/AN02PAD09/AN09PAD01/AN01PAD08/AN08PAD00/AN00VSS2VDD2PA7PA6PA5PA4PA3PA2PA1PA0
PP4/
KWP4
/PW
M4/
MIS
O2
PP5/
KPW
5/PW
M5/
MO
SI2
PP6/
KWP6
/PW
M6/
SS2
PP7/
KWP7
/PW
M7/
SCK2
PK7
VDD
XVS
SXPM
0/R
XCAN
0PM
1/TX
CAN
0PM
2/R
XCAN
1/R
XCAN
0/M
ISO
0PM
3/TX
CAN
1/TX
CAN
0/SS
0PM
4/R
XCAN
2/R
XCAN
0/R
XCAN
4/M
OSI
0PM
5/TX
CAN
2/TX
CAN
0/TX
CAN
4/SC
K0PJ
6/KW
J6/R
XCAN
4/SD
A0PJ
7/KW
J7/T
XCAN
4/SC
L0VR
EGEN
PS7/
SS0
PS6/
SCK0
PS5/
MO
SI0
PS4/
MIS
O0
PS3/
TXD
1PS
2/R
XD1
PS1/
TXD
0PS
0/R
XD0
PM6/
RXCA
N3/R
XCAN
4PM
7/TX
CAN3
/TXC
AN4
VSSA
VRL
SS1/PWM3/KWP3/PP3SCK1/PWM2/KWP2/PP2
MOSI1/PWM1/KWP1/PP1MISO1/PWM0/KWP0/PP0
PK3PK2PK1PK0
IOC0/PT0IOC1/PT1IOC2/PT2IOC3/PT3
VDD1VSS1
IOC4/PT4IOC5/PT5IOC6/PT6IOC7/PT7
PK5PK4
TXD2/KWJ1/PJ1RXD2/KWJ0/PJ0
MODC/BKGDPB0PB1PB2PB3PB4
PB5
PB6
PB7
SS2/
KWH7
/PH7
SCK2
/KW
H6/P
H6TX
D4/M
OSI
2/KW
H5/P
H5RX
D4/M
ISO
2/KW
H4/P
H4EC
LK2X
/XC
LKS/
PE7
MO
DB/
PE6
MO
DA/P
E5EC
LK/P
E4VS
SRVD
DR
RES
ETVD
DPL
LXF
CVS
SPLL
EXTA
LXT
ALTE
STSS
1/KW
H3/P
H3SC
K1/K
WH2
/PH2
MO
SI1/
KWH1
/PH1
MIS
O1/
KWH0
/PH0 PE
3PE
2IR
Q/P
E1XI
RQ
/PE0
MC9S12XD Family112LQFP
112
111
110
109
108
107
106
105
104
103
102
101
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
12345678910111213141516171819202122232425262728
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
84838281807978777675747372717069686766656463626160595857
Pins shown in BOLD are not available on the 80 QFP package
MC9S12XD Family, Rev. 2.16
20 Freescale Semiconductor
Pin Assignments
Figure 3. MC9S12XD Family Pin Assignments for 80-pin QFP Package
1234567891011121314151617181920
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
MC9S12XD Family80-Pin QFP
VRHVDDAPAD07/AN07PAD06/AN06PAD05/AN05PAD04/AN04PAD03/AN03PAD02/AN02PAD01/AN01PAD00/AN00VSS2VDD2PA7PA6PA5PA4PA3PA2PA1PA0
PP4/
KWP4
/PW
M4/
MIS
O2
PP5/
KWP5
/PW
M5/
MO
SI2
PP7/
KWP7
/PW
M7/
SCK2
VDD
XVS
SXPM
0/R
XCAN
0/R
XBPM
1/TX
CAN
0/TX
BPM
2/R
XCAN
1/R
XCAN
0/M
ISO
0PM
3/TX
CAN
1/TX
CAN
0/SS
0PM
4/R
XCAN
2/R
XCAN
0/R
XCAN
4/M
OSI
0PM
5/TX
CAN
2/TX
CAN
0/TX
CAN
4/SC
K0PJ
6/KW
J6/R
XCAN
4/SD
A0/R
XCAN
0PJ
7/KW
J7/T
XCAN
4/SC
L0/T
XCAN
0VR
EGEN
PS3/
TXD
1PS
2/R
XD1
PS1/
TXD
0PS
0/R
XD0
VSSA
VRL
SS1/PWM3/KWP3/PP3SCK1/PWM2/KWP2/PP2
MOSI1/PWM1/KWP1/PP1MISO1/PWM0/KWP0/PP0
IOC0/PT0IOC1/PT1IOC2/PT2IOC3/PT3
VDD1VSS1
IOC4/PT4IOC5/PT5IOC6/PT6IOC7/PT7
MODC/BKGDPB0PB1PB2PB3PB4
PB5
PB6
PB7
XCLK
S/PE
7M
OD
B/PE
6M
ODA
/PE5
ECLK
/PE4
VSSR
1VD
DR
1R
ESET
VDD
PLL
XFC
VSSP
LLEX
TAL
XTAL
TEST PE
3PE
2IR
Q/P
E1XI
RQ
/PE0
6059585756555453525150494847464544434241
MC9S12XD Family, Rev. 2.16
Freescale Semiconductor 21
Memory Maps
Memory Maps
Figure 4. MC9S12XD-Family Memory Map1
1. The memory Map shows the memory sizes of DP512 part. For memory configuration of other parts see Table 1.
NORMALSINGLE CHIP
EXPANDED SPECIALSINGLE CHIP
VECTORS
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
16K Page Window32 * 16K Flash EEPROM Pages
16K Fixed Flash EEPROM
2K Register Space
32K Bytes RAM8 * 4K pages accessible through $1000 - $1FFF
4K Bytes EEPROM4 * 1K pages accessible through $0800 - $0BFF
VECTORS
Ext
erna
l
BDM
$0000
$FFFF
$C000
$8000
$4000
$0800
$1000
$FF00
$2000
$0C00
MC9S12XD Family, Rev. 2.16
22 Freescale Semiconductor
Memory Maps
Figure 5. MC9S12XD-Family Flash Configuration1, 2, 3, 4, 5
1. XGATE read access to Flash not possible on DG128/D128 and D642. Program Pages available on DT384 are $E0 - $E7 and $F0 - $FF3. Program Pages available on DQ256/D256 are $E0 - $E7 and $F8 - $FF4. Shared XGATE/CPU area on DP512/DT512/DT384 at global address $78_0800 to $78_FFFF (30Kbyte)5. Shared XGATE/CPU area on DQ256/D256 at global address $78_0800 to $79_3FFF (46Kbyte)
Shared XGATE/CPU area
Not implemented
$78_0000 (PPAGE $E0)
Global Address
$7A_0000 (PPAGE $E8)
$7C_0000 (PPAGE $F0)
$7E_0000 (PPAGE $F8)
128K
64K
128K 128K
128K128K128K
128K
128K
128K
128K
DP512/DT512
DT384 DQ256/D256
DG128/D128
D64
MC9S12XD Family, Rev. 2.16
Freescale Semiconductor 23
Mechanical Package Dimensions
Mechanical Package Dimensions
Figure 6. 144-pin LQFP Mechanical Dimensions (case no. 918-03)
N0.20 T L-M
144
GAGE PLANE
73
109
37
SEATING
1081
36
72
PLANE
4X 4X 36 TIPS
PIN 1IDENT
VIEW Y
B
B1 V1
A1
S1
V
P
G
A
S
0.1C2θ
VIEW AB
J1
J1
140X
4X
VIEW Y
PLATING
F AAJ
DBASEMETAL
SECTION J1-J1(ROTATED 90 )
144 PL°
N0.08 M T L-M
θ
DIMA
MIN MAX20.00 BSC
MILLIMETERS
A1 10.00 BSCB 20.00 BSCB1 10.00 BSCC 1.40 1.60C1 0.05 0.15C2 1.35 1.45D 0.17 0.27E 0.45 0.75F 0.17 0.23G 0.50 BSCJ 0.09 0.20K 0.50 REFP 0.25 BSC
R1 0.13 0.20R2 0.13 0.20S 22.00 BSCS1 11.00 BSCV 22.00 BSCV1 11.00 BSCY 0.25 REFZ 1.00 REF
AA 0.09 0.16θ 0θ 0 7θ 11 13
12
NOTES:1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.2. DIMENSIONS IN MILLIMETERS.3. DATUMS L, M, N TO BE DETERMINED AT THE
SEATING PLANE, DATUM T.4. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE, DATUM T.5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLEPROTRUSION IS 0.25 PER SIDE. DIMENSIONSA AND B DO INCLUDE MOLD MISMATCHAND ARE DETERMINED AT DATUM PLANE H.
6. DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL NOT CAUSE THE DDIMENSION TO EXCEED 0.35.
°°°
°°
0.05
CL
(Z)
R2
E
C2
(Y)
R1
(K)C1
1θ
0.25
VIEW AB
N0.20 T L-M
ML
N
2θ
T
T 144X
X
MC9S12XD Family, Rev. 2.16
24 Freescale Semiconductor
Mechanical Package Dimensions
Figure 7. 112-pin LQFP Mechanical Dimensions (case no. 987)
DIMA
MIN MAX20.000 BSC
MILLIMETERS
A1 10.000 BSCB 20.000 BSC
B1 10.000 BSCC --- 1.600
C1 0.050 0.150C2 1.350 1.450D 0.270 0.370E 0.450 0.750F 0.270 0.330G 0.650 BSCJ 0.090 0.170K 0.500 REFP 0.325 BSCR1 0.100 0.200R2 0.100 0.200S 22.000 BSC
S1 11.000 BSCV 22.000 BSC
V1 11.000 BSCY 0.250 REFZ 1.000 REF
AA 0.090 0.160θ
θθθ 11 °
11 °13 °
7 °13 °
VIEW Y
L-M0.20 NT4X 4X 28 TIPS
PIN 1DENT
1
112 85
84
28 57
29 56
B V
V1B1
A1
S1
A
S
VIEW AB
0.10
3
CC2
θ
2θ0.050
SEATINGPLANE
GAGE PLANE
1θ
θ
VIEW AB
C1
(Z)
(Y)E
(K)
R2
R1 0.25
J1
VIEW Y
J1
P
G108X
4X
SECTION J1-J1
BASE
ROTATED 90 COUNTERCLOCKWISE°
METAL
J AA
FD
L-MM0.13 NT
123
CL
L-M0.20 NT
L
N
M
T
T
112X
XX=L, M OR N
R
R
NOTES:1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.2. DIMENSIONS IN MILLIMETERS.3. DATUMS L, M AND N TO BE DETERMINED AT
SEATING PLANE, DATUM T.4. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLEPROTRUSION IS 0.25 PER SIDE. DIMENSIONSA AND B INCLUDE MOLD MISMATCH.
6. DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL NOT CAUSE THE DDIMENSION TO EXCEED 0.46.
8 °3 °0 °
MC9S12XD Family, Rev. 2.16
Freescale Semiconductor 25
Mechanical Package Dimensions
NOTES:1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THELEAD WHERE THE LEAD EXITS THE PLASTICBODY AT THE BOTTOM OF THE PARTING LINE.
4. DATUMS -A-, -B- AND -D- TO BEDETERMINED AT DATUM PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINEDAT SEATING PLANE -C-.
6. DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION. ALLOWABLEPROTRUSION IS 0.25 PER SIDE. DIMENSIONSA AND B DO INCLUDE MOLD MISMATCHAND ARE DETERMINED AT DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.08 TOTAL INEXCESS OF THE D DIMENSION AT MAXIMUMMATERIAL CONDITION. DAMBAR CANNOTBE LOCATED ON THE LOWER RADIUS ORTHE FOOT.
SECTION B-B
61
60
DETAIL A
41
40
80
-A-
L
-D-A
SA-BM0.20 D SH
0.05 A-B
S
1 20
21
-B-
B V
J
F
N
D
VIEW ROTATED 90 °
DETAIL A
B
BP
-A-,-B-,-D-
E
H
GM
MDETAIL C
SEATINGPLANE
-C-
C DATUMPLANE
0.10
-H-
DATUMPLANE -H-
U
T
R
QKW
XDETAIL C
DIM MIN MAXMILLIMETERS
A 13.90 14.10B 13.90 14.10C 2.15 2.45D 0.22 0.38E 2.00 2.40F 0.22 0.33G 0.65 BSCH --- 0.25J 0.13 0.23K 0.65 0.95L 12.35 REFM 5 10N 0.13 0.17P 0.325 BSCQ 0 7R 0.13 0.30S 16.95 17.45T 0.13 ---U 0 ---V 16.95 17.45W 0.35 0.45X 1.6 REF
° °
° °
°
SA-BM0.20 D SCS
A-B
M0.
20D
SH
0.05
D
SA
-BM
0.20
DS
C
SA-BM0.20 D SC
MC9S12XD Family, Rev. 2.16
26 Freescale Semiconductor
9S12XDFAMPPRev. 2.16, 27-May-2006
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