Automated Migration Of Standard Cell Library From 90nm to 45nm Technology And Comparison Of Characteristics

Akash , Akash M, Deepesh, Joseph

Presented To:

Prof. Sunil Kumar K.H

Prof. Sophiya Susan S

Prof. Amit Jain

OVERVIEW

• About Cadence

• Literature Survey

• Problem Formulation

• Solution Design

• Solution Implementation

• User Interface

• Migration

• Comparison

• Result

About

• Cadence Design Systems, Inc. is an American multinational electronic design automation (EDA) software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.

• Cadence products primarily target SoC design engineers, and are used to move a design into packaged silicon, with products for custom and analog design, digital design, mixed-signal design, verification, and package/PCB design, as well as a broad selection of IP, and also hardware for emulation and FPGA prototyping.

Literature Survey

• A computational geometry-based cell migration technique for VLSI placement problem:

The movement of preplaced cells among a prescribed existing placement to solve a set of worst designed placement related facts -for example, routing problems, timings, integrity of signals and distribution of heat. To solve this design related problems, one has toprefer to translate the design. The translation should be as small as possible while retaining the originality of the placement integrity.

Hierarchical analog migration :Despite all the research efforts, some areas of IC design are still mainly manual, such as analog layouts. The main assumption of this work is that when designing a circuit in a new flavor or technology node, expert analog designers start by reusing a topology from an already silicon-proven circuit. If the fabrication processes are similar, then only minor adjustments in the device sizes may be needed to achieve the required performance specifications

~Andrew Beeket Father of SKILL Scripting language

Problem Formulation

• Automation of analog design is considered as indispensable for the progress of mixed analog-digital VLSI circuits. Due to this factor, there is a demand for technology in a smaller form factor.

• One of the main problem is the generation of schematic for a design in different technologies as this design phase is very time consuming and prone to errors.

• As a result, there is a need for conversion of an existing circuit design to a design in different technology.

• Hence, automated migration of standard cell library from one technology to another (90nm to 45nm) is an effectivesolution.

Solution Design

• Using SKILL scripting language to automate the standard cell from 90nm to 45nm technology.

• SKILL has core level integration with design as well as script data base which makes it more efficient than any other scripting languages.

SKILL Scripting Language

• SKILL is a Lisp dialect used as a scripting language and Pcell

(parameterized cells) description language used in many EDA software suites by Cadence Design Systems like Virtuoso.

• All the routines in virtuoso are written in C. User cannot use the C

function as Cadence cannot give away its source code. Hence, SKILL works as an interface between the user and the database. SKILL function in-turn calls the C function which performs the required task.

Applications of Skill

• Interaction with the Schematic/Layout design Data Base

• User Interface Development/Customization

• Auto Schematic/Layout Generation

• Design Automation

• Design Of Pcell

Interaction with the Schematic/Layout design

Sample Code:cv=geGetEditCellView()db:0x198cdf9acv~>libName"example“cv~>cellName"inv"cv~>cellViewType"maskLayout“cv~>instances(db:0x198cda1a db:0x198cda1b)cv~>instances~>name("I2" "I1")cv~>shapes~>objType("rect" "rect" "rect" "path" "rect"

"path" "textDisplay" "path" "path" "path""path" "path" "rect" "textDisplay"

)

Solution Implementation

• Using SKILL IDE for scripting and modelling the design flow.

• Coding the UI(User Interface)

• Generating a comprehensive report for the selected Library

• Creating a copy of the existing Library with a new alias

• Migration of the circuit (From 90nm to 45nm)

Virtuoso Design Environment

Virtuoso Command Interpreter Window

SKILL Integrated Developer Environment(IDE)

SKILL IDE Use Model

User Interface Development/ Customization

someInt = hiCreateStringField(?name 'projectName?prompt "Name of project"?value "Automated Migration...")myCyclic = hiCreateCyclicField(?name 'names?prompt "Names"?value "-----"?choices list("-----""Akash Arun" "Akash C. Mathew""Deepesh S." "Joseph P. Lukose") )mytoggle = hiCreateToggleField(?name 'lecturers?prompt "Guides Present"?choices list('(g1 "Sunil Kumar K. H.")list( 'g2 "Sophiya Susan S.")list('g3 "Amith Jain"))

?value '(t t t)?numSelect 3 )aRadio = hiCreateRadioField(?name 'teamSize?prompt "Number of Members"?value "4"?defValue "4"?choices list("1" "2" "3" "4"))hiCreateAppForm( ?name 'firstReviewExampleForm?formTitle "Example"?callback "buildTeamSpirit()"?fields list( someInt mytoggle aRadio myCyclic )?help "Wenger" )status = hiDisplayForm( firstReviewExampleForm )

User Interface(UI)

User Interface(UI)

hiCreateCyclicField(?name 'abcd?prompt "Old Design Library"?choices cons(" ----" rt~>name)?callback "abc(cv->abcd->value rt)"

hiCreateButton(?name 'btf?callback "migrate(hiGetCurrentForm())"?buttonText "MIGRATE"?enabled t?invisible nil)

hiCreateStringField(?name 'sf?prompt "New Design Library"?value ""?defValue ""?callback "libcpy(hiGetCurrentForm())"?editable t?enabled t?invisible nil?nextField nil)

hiCreateAppForm( ?name 'tmig1?formTitle "CMRIT-Automated Migration"?callback nil?fields list( list(cyo 0:10 240:30 120) list(s 330:10 300:30 120)list(cyn 330:50 240:30 120)list(h 0:90 240:30 90)list(btn 240:150 200:30))?help "" )status = hiDisplayForm( tmig1 )

Report Generation For Selected Library

procedure(abc(x rt)

myport=outfile("/tmp/xqw.txt")

idx=inretr(x rt~>name)

a=nth(idx rt)

fprintf(myport "The List of cells in %s are:\n" x )

z=length(a~>cells)

for(i 0 z-1

fprintf(myport "\n")

fprintf(myport "%d. %s" i+1 nth(i a~>cells~>name))

fprintf(myport "\nList of views for %s are: \n" nth(i a~>cells~>name))

q=nth(i a~>cells)

l=length(q~>views)

for(j 0 l-1 fprintf(myport "--> %s\n" nth(j q~>views~>name))

cv=dbOpenCellViewByType(x nth(i a~>cells~>name) nth(j q~>views~>name))

g=length(cv~>instances)

fprintf(myport "\n instances in cellview are:\n")

for(r 0 g-1

fprintf(myport "\t\t <> %s <--> %s\n " nth(r cv~>instances~>name) nth(r cv~>instances~>cellName))

);end for r

);end for j

);end for i

close(myport)

view("/tmp/xqw.txt")

);end abc

Copying Library

Migration

• To Migrate to a different technology library, you must create a set of design libraries that are associated with the new technology library.

• Any Pcells in the source design must have implementations available in the target technology.

• Map all of the old libraries to a library using the new technology.

Before Migration: Opamp

After Migration: Opamp

Comparison Of Characteristics

RING OSCILLATOR

A ring oscillator is a device composed of an odd number of NOT gates in a ring, whose output oscillates between two voltage levels, representing true and false. The NOT gates, or

inverters, are attached in a chain and the output of the last inverter is fed back into the first.

Comparison Of Characteristics

Test Circuit Used-> RING OSCILLATOR

90nm 45nm

Output Waveform

90nm 45nm

Visualization and Analysis

Frequency

Rise Time

Fall Time

Comparison Of 90nm And 45nm

90nm

45nm

Optimized Output

Performance Characteristics

• Mobility related parameters

• Well proximity effect

• Gate dielectric tunneling current

• Capacitance parameters

• Sub threshold parameters

• Temperature coefficient parameters

• Stress effect

• Geometry range parameters