Final Technical Report

Atomic Layer Epitaxy of Group IV Materials: Surface Processes, Thin Films, Devices and

Their Characterization

Supported under Grant #N00014-91-J-1416 Office of the Chief of Naval Research Report for the period ending 9/30/96

R. F. Davis, S. Bedair*, N. A. El-Masry, and Z. Sitar c/o Materials Science and Engineering Department

and *Electrical and Computer Engineering Department North Carolina State University

Campus Box 7907 Raleigh, NC 27695-7907

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September, 1996

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Final Technical 4. TITLE AND SUBTITLE

Atomic Layer Epitaxy of Group IV Materials: Surface Processes, Thin Films, Devices and Their Characterization

C AUTHORfS)

Robert F. Davis

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414v001— 01 1114SS N00179 N66005 4B855

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North Carolina State University Hillsborough Street Raleigh, NC 27695

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IX ABSTRACT CMwdmun a» arona«;

The ALE technique has been employed to deposit monocrystalline 3C-SiC thin films at 860±10°C. Wafers containing heterojunction bipolar transistor structures have been completely processed and characterized. No transistor activity was detected in any of the HBT structures. Post growth oxidation anneals in argon followed orproceeded by oxygen environments improved both properties. However, the anneals in oxygen also resulted in the growth of a SiC«2 layer at the silicon interface which reduced the capacitance of the structure. An expression for the optimum oxidation time, t, was developed as a function of the initial thicknesses of the deposited film. The films have large MOS capacitance but also have larger leakage currents compared to those of epitaxial CeC«2 films on Si(l 11) substrates. However, improved leakage and breakdown characteristics were obtained with annealing in forming gas. The growth parameter, a, the ratio of the growth rates on {100} and {111} facets for diamond films deposited on Si and Ti by microwave plasma CVD has been studied using SEM micrographs. Different morphologies were generated on Si under different deposition conditions. The value of a increased with decreasing temperature and increasing methane concentration, as expected. A value of a for Ti was not obtained due to the heavily twinned particles. __^ m

»tlC QUALTTt INSPECTED 9

14. SUBJECT TERMS

ALE, atomic layer epitaxy, SiC, silicon carbide, HBTs, transistor activity, thin films, CeÜ2, oxidation, annealing, pulsed laser ablation, CVD, chemical vapor deposition, diamond, silicon, titanium, growth parameter

IS. NUMBER OF PAGES

34 1*. PHCECOOE

17. SECURITY CLASSIFICATION OF REPORT

UNCLAS

ML SECURITY CLASSIFICATION OF TH» PAGE

UNCLAS

1«. SECURITY CLASSIFICATION OF ABSTRACT

UNCLAS

20. UUTATION OF ABSTRACT

SAR NSN 754001-280-5500 Standard Form 298 (Rev. 2-80)

PtmatMi b» ANSI SW Z3S-1S

I. Introduction Atomic layer epitaxy (ALE) is the sequential chemisorption of one or more elemental

species or complexes within a time period or chemical environment in which only one

monolayer of each species is chemisorbed on the surface of the growing film in each period of

the sequence. The excess of a given reactant which is in the gas phase or only physisorbed is

purged from the substrate surface region before this surface is exposed to a subsequent

reactant This latter reactant chemisorbs and undergoes reaction with the first reactant on the

substrate surface resulting in the formation of a solid film. There are essentially two types of

ALE which, for convenience, shall be called Type I and Type EL

In its early development in Finland, the Type I growth scenario frequently involved the

deposition of more than one monolayer of the given species. However, at that time, ALE was

considered possible only in those materials wherein the bond energies between like metal

species and like nonmetal species were each less than that of the metal-nonmetal combination.

Thus, even if multiple monolayers of a given element were produced, the material in excess of

one monolayer could be sublimed by increasing the temperature and/or waiting for a sufficient

period of time under vacuum. Under these chemical constraints, materials such as GaAs were

initially thought to be improbable since the Ga-Ga bond strength exceeds that of the GaAs bond

strength. However, the self-limiting layer-by-layer deposition of this material proved to be an

early example of Type II ALE wherein the trimethylgallium (TMG) chemisorbed to the

growing surface and effectively prevented additional adsorption of the incoming metalorganic

molecules. The introduction of As, however caused an exchange with the chemisorbed TMG

such that a gaseous side product was removed from the growing surface. Two alternating

molecular species are also frequently used such that chemisorption of each species occurs

sequentially and is accompanied by extraction, abstraction and exchange reactions to produce

self-limiting layer-by-layer growth of an element, solid solution or a compound.

The Type II approach has been used primarily for growth of II-VI compounds [1-13];

however, recent studies have shown that it is also applicable for oxides [14-17], nitrides [18],

m-V GaAs-based semiconductors [19-32] and silicon [33-35]. The advantages of ALE

include monolayer thickness control, growth of abrupt interfaces, growth of uniform and

graded solid solutions with controlled composition, reduction in macroscopic defects and

uniform coverage over large areas. A commercial application which makes use of the last

attribute is large area electroluminescent displays produced from II-VI materials. Two

comprehensive reviews [36,6], one limited overview [37] and a book [38] devoted entirely to

the subject of ALE have been published.

In this reporting period, investigations concerned with (1) deposition via ALE of 3C-SiC

films and the fabrication and characterization of bipolar transistors on these films, (2) the

deposition, annealing and determination of the opitcal emission of CeC>2 epitaxial films on Si(100), (3) the determination of the growth parameter, a, for diamond films on Si and TL

The following sections introduce each topic, detail the experimental approaches, report the

results to date and provide a discussion and a conclusion for each materiaL Each major section

is self-contained with its own figures, tables and references.

References

1. T. Suntola and J. Antson, U.S. Patent 4,058,430, 1977. 2. M. Ahonen, M. Pessa and T. Suntola, Thin Solid Films 65, 301, 1980. 3. M. Pessa, R. Makela, and T. Suntola, Appl. Phys. Lett 38, 131, 1981. 4. T. Yao and T. Takeda, Appl. Phys. Lett 48, 160, 1986. 5. T. Yao, T. Takeda, and T. Watanuki, Appl. Phys. Lett 48, 1615, 1986. 6. T. Yao, Jpn. J. Appl. Phys. 25, L544, 1986. 7. T. Yao and T. Takeda, J. Cryst Growth 81, 43, 1987. 8. M. Pessa, P. Huttunen and M. A. Herman, J. Appl. Phys. 54, 6047, 1983. 9. C. H. L. Goodman and M. V. Pessa, J. Appl. Phys. 60, R65, 1986.

10. M. A. Herman, M. Valli and M. Pessa, J. Cryst Growth 73, 403, 1985. 11. V. P. Tanninen, M. Oikkonen and T. Tuomi, Phys. Status Solidi A67, 573,1981. 12. V. P. Tanninen, M. Oikkonen and T. Tuomi, Thin Solid Films 90,283,1983. 13. D. Theis, H. Oppolzer, G. Etchinghaus and S. Schild, J. Cryst Growth 63, 47, 1983. 14. S. Lin, J. Electrochm. Soc. 122, 1405, 1975. 15. H. Antson, M. Leskela, L. Niinisto, E. Nykanen and M. Tammenmaa, Kem.-Kemi 12,

11, 1985. 16. R. Tornqvist Ref. 57 in the bibliography of Chapt 1 of Ref. 38 of this report 17. M. Ylilammi, M. Sc. Thesis, Helsinki Univ. of Technology, Espoo, 1979. 18. I. Suni, Ref. 66 in the bibliography of Chapt 1 of Ref. 38 in this report 19. S. M. Bedair, M. A. Tischler, T. Katsuyama and N. A. El-Masry, Appl. Phys. Lett 47,

51, 1985. 20. M. A. Tischler and S. M. Bedair 48, 1681, 1986. 21. M. A. Tischler and S. M. Bedair, J. Cryst Growth 77, 89, 1986. 22. M. A. Tischler, N. G. Anderson and S. M. Bedair, Appl. Phys. Lett 49, 1199, 1986. 23. M. A. Tischler, N. G. Anderson, R. M. Kolbas and S. M. Bedair, Appl. Phys. Lett.

50, 1266, 1987. 24. B. T. McDermott, N. A. El-Masry, M. A. Tischler and S. M. Bedair, Appl. Phys. Lett.

51, 1830, 1987. 25. M. A. Tischler, N. G. Anderson, R. M. Kolbas and S. M. Bedair, SPIE Growth Comp.

Semicond. 796, 170, 1987. 26. S. M. Bedair in Compound Semiconductor Growth Processing and Devices for the

1990's, Gainesville, FL, 137, 1987. 27. J. Nishizawa, H. Abe and T. Kurabayashi, J. Electrochem. Soc. 132, 1197, 1985. 28. M. Nishizawa, T. Kurabayashi, H. Abe, N. Sakurai, J. Electrochm. Soc. 134,945,1987. 29. P. D. Dapkus in Ref. 27, in the bibliography of Chapt 1 of Ref. 38 in this report 30. S. P. Denbaars, C. A. Beyler, A. Hariz, P. D. Dapkus, Appl. Phys. Lett 51, 1530, 1987. 31. M. Razeghi, Ph. Maurel, F. Omnes and J. Nagle, Appl. Phys. Lett 51, 2216, 1987. 32. M. Ozeki, K. Mochizuki, N. Ohtsuka, K. Kodama, J. Vac. Sei. Technol. B5,1184,1987. 33. Y. Suda, D. Lubben, T. Motooka and J. Greene, J. Vac. Sei. Technol. B7, 1171,1989. 34. J. Nishizawa, K. Aoki, S. Suzuki and K. Kikuchi, J. Cryst Growth 99, 502, 1990. 35. T. Tanaka, T. Fukuda, Y. Nagasawa, S. Miyazaki and M. Hirose, Appl. Phys. Lett 56,

1445, 1990. 36. T. Suntola and J. Hyvarinen, Ann. Rev. Mater. Sei. 25, 177, 1985. 37. M. Simpson and P. Smith, Chem. Brit 23, 37, 1987. 38. T. Suntola and M Simpson, Atomic Layer Epitaxy, Chapman and Hall, New York, 1990.

II. Atomic Layer Epitaxy of Silicon Carbide Films and Their Application in the Development of Bipolar Transistors

A. Introduction The utilization of active ß-SiC components in semiconductor structures could dramatically

enhance the performance of integrated circuits and discrete devices. Two convenient, standard

criteria for comparing the relative merits and capabilities of semiconductor materials are the

Johnson's and Keye's figures of merit. The Johnson's figure of merit estimates the maximum

performance to be expected of a semiconductor material in discrete bipolar transistors[l] while

the Keye's rating assesses a material's suitability for high density integrated circuit applications[2]. ß-SiC ranks far above Si in both criteria, with ratings 33.9 and 5.82 times

higher than Si by the Johnson's and Keye's figures of merit, respectively. Although these ratings for ß-SiC demonstrate that both discrete devices and integrated circuitry employing

ß-SiC components should attain levels of performance unachievable with device technologies

based solely on Si, relatively few devices containing ß-SiC components have been

produced[4,5]. A significant barrier to the widespread exploitation of the capabilities of ß-SiC is the lack of

an advanced ß-SiC processing infrastructure. The most expeditious route to devices accessing

the performance increases possible with ß-SiC would be the development of a thin-film

deposition technique to allow the integration of ß-SiC into the existing Si device fabrication

infrastructure. Conventional chemical vapor deposition (CVD) techniques for producing heteroepitaxial ß-SiC films on Si wafers require a carbonizing pretreatment and high deposition

temperatures[6]. These requirements make ß-SiC CVD processes incompatible with existing Si

sub-micron architecture process routes. However, as shown in a previous report (June, 1994), atomic layer epitaxy offers the ability to deposit monocrystalline ß-SiC films on Si(100)

substrates at low temperatures without the carbonizing pretreatment and may serve as a vehicle to facilitate the introduction of ß-SiC into selected devices structures.

The objective of this research is to extend the state-of-the-art regarding SiC thin film deposition and application via the employment of atomic layer epitaxy to deposit ß-SiC films

on select substrates. During this reporting period, work has continued with the fabrication of

trenched heterojunction bipolar transistors (HBTs) employing a wide bandgap ß-SiC emitter.

The second batch of transistors has been completely processed. The following sections

describe the fabrication steps followed in this work and the results of characterization of the

resultant devices via electrical measurements and scanning electron microscopy (SEM).

B. Experimental Procedure

ALE Reactor. The ALE reactor employed in this research has not been significantly

modified since it was described in detail in a previous report (June, 1993). To prevent mixing

of process gases, flowing Ar "curtains" divide the reactor into four radial quadrants through

which isolated fluxes of Si2H£, C2H4, NH3 and triethylaluminum (A1(C2H5)3) may flow. The

quadrant containing NH3 also contains a W filament that may be heated to produce atomic

hydrogen or to crack NH3 depending on gas flow conditions. During deposition, heated

samples can be rotated alternately between quadrants and exposed to the species present to

form films in a layer-by-layer process. Due to the construction of the reactor, SiC films can be

deposited and doped n- and p-type with N and Al, respectively.

Fabrication of Trenched HBTs. The six level mask system designed to produce HBTs was

described in detail in a previous report (June, 1994). Each die contained four transistors: a

planar HBT, two HBTs in trench structures and one HBT with a corrugated or "waffle iron"

structure. The geometry of the latter devices were engineered to exploit the high degree of

conformality possible with layer-by-layer deposited SiC films. The procedures followed in

producing the devices are explained in detail in the last report (December, 1994).

Deposition. SiC films were deposited on partially processed wafers. Three samples,

HBT 6-HBT 8, were processed under the conditions listed in Table I. Prior to etching of the

SiC to define the emitters, the thickness of each film was determined via cross-sectional SEM

observation.

Table I . SiC Deposition Conditions for Second Batch of HBTs

Process parameter HBT 6 HBT 7 HBT 8

Sample temperature 850° C 870° C 850° C

Si2Hö flow/ H2 carrier 0.8 / 300 seem 0.8 seem/ 300 seem 2

C2H4 flow/ H2 carrier 2 / 200 seem 2 seem/ 200 seem 2

AT curtain flow 200 seem 200 seem Osccm

H2 across filament 100 seem 100 seem 3 seem

Filament temperature 1700°C 1700°C unheated

Pressure 1.5 Ton- 1.5 Ton- - IO-3 Ton

Rotational scheme rotate through Si2H6 and C2H4, wait under fil. 30 s. rpt. 1500 times.

rotate continuously to complete one Si-C-fil. cycle every 13 s. rpt. 3000 times

5 s. under Si2Hß, 5 s. under H2, 5 s. under C2H4, 5 s. under H2 rpt. 1100 times.

Film thickness 0.18 ^lm 0.32 ^m 0.2 urn

M Contacts (N-Type SiC). Ni contacts were sputtered onto the films using a

photolithography lift-off technique. The specifics of the lift-off technique were discussed in

detail in a previous report (June, 1994). Sputtering conditions were power = 100 watts

13.56 MHz R.F. and 20 mTorr Ar ambient. The Ni deposition rate was = 2000 Ä/Hr. Contacts

were then annealed in -\ Heatpulse rapid thermal annealer (RTA) with an Ar ambient at 1000° C

for 20 sec.

Al Contacts (P-type Si). Al contacts were vacuum evaporated from pure Al shot

(99.9999% pure). The deposited Al film was subsequendy processed using conventional

microelectronic fabrication techniques.

Electrical Characterization. I-V and Ic vs. VCE characterizations were performed with a

Hewlett Packard 4145A Semiconductor Parameter Analyzer. Ambient light was found to have

a significant effect on measured factors, therefore, all data was collected under dark conditions.

Typical contact points are indicated in Fig. 1. Emitter and base connections for testing were

made with W probes while the collector contact was made with a large area silver paint

electrode on the wafer backside after grinding.

+ SiC emitter p Si base

- Si collector

Backside collector contact

Figure 1. Testing contacts for electrical characterization of HBTs.

C. Results

The wafers in the second batch of HBT structures were denoted as: HBT 6, HBT 7 and

HBT 8. The conditions under which the SiC films were deposited on these samples are

tabulated in Table 1. In general, these SiC films were thinner than those produced in the first

batch of HBT structures in order to lessen the required accuracy of the SiC etch step.

5

Figure 2 is a SEM image of wafer HBT 6 taken after the SiC etch. The Al layer used to

mask the SiC is visible in the image. There was some over-etching of the p-type Si base region

on this wafer. The roughening of the Si surface is visible, although under-cutting of the emitter

region is visible, it is not as excessive as reported previously (December, 1994). The excess

etching in Fig. 2 is of the order of only 0.1 Jim and did not result in the total removal of the

base region which had an initial thickness of ~ 1.5 |im.

HBT Substrate

*~* NCSU 5 KV

Ü.25 urn

X60,000

m

14 mm 0

Figure 2. Wafer HBT 6 after etching of the SiC emitter layer.

6

Figures 3 and 4 are I-V curves generated across the emitter-base and the base-collector

junctions, respectively, of a typical corrugated interface transistor on wafer HBT 6. Both

junctions exhibited rectifying behavior. However, the emitter-base junction characterized in

Fig. 3 was very leaky in reverse bias. This device had an active area of 28,700 |im2, yielding a

IF

Figure 3.

Figure 4.

CuA)

143. 8

/

/

14. 38 /

/div

.0000

-5. 000 5.000 VF 1. 000/div (. V)

I-V characteristics of emitter-base junction of corrugated HBT on wafer HBT 6.

IF CuA)

630.0

70.00 /div

0 -70.00

-5. 000

1

/

1 /

/

/

/ /

1 VF

0 5. 000 1.000/div C V)

I-V characteristics of base-collector junction of corrugated HBT of wafer HBT 6.

reverse bias current density of 110 A cnr2 at -4.5 V. Good rectifying behavior across the base-

collector junction and rectifying, but leaky behavior across the emitter-base junction were

consistently observed on all three wafers of the second batch.

Figure 5 is a typical Ic vs. VCE performance plot for a corrugated interface HBT on wafer

HBT 6. In this plot Ic is determined as VCE is varied from 0 to 5V while Iß is increased in

1 mA increments from 0 mA to 4 mA, yielding five separate curves. From this plot, there is no

apparent gain in the transistors as Ic increases in each step by almost exactly the same value Iß

increases. This behavior is similar to that observed for the transistors produces in the first batch

of HBTs. Transistor activity was not observed in any of the devices produced in the second batch of HBTs.

IC GnA)

4. 217

'

»B- t nu\

—■

.4217 /div

Iß = 3 mA

IR = 2 mA

IB= 1 mA 1 1

0000 lB = 0mA 1 1

.0000 VCE 1.000/div C V)

9. 999

Figure 5. Typical Ic vs. VCE behavior of a typical corrugated surface HBT in the second HBT batch at several Iß values.

D. Discussion

No transistor activity was observed in the second batch of HBTs. Two possible causes for

the lack of performance were identified in the analysis of the first batch of HBTs: inaccurate

etching of the SiC film deposited to form the emitters and too wide a base region. Examination

of the wafers produced in the second batch after etching the SiC revealed that the etching was

performed accurately, removing all of the undesired SiC while only slightly etching the

underlying p-type Si base region. The most probable cause of the absence of transistor activity

was an excessive width of the base region.

Bipolar transistors usually operate by injecting minority carriers into the base region by

forward biasing the emitter-base junction. If the minority carrier diffusion distance in the base

is greater than the distance to the reverse biased base-collector junction, these carriers will

eventually reach the collector region to contribute to Ic- However, if the base region is too

wide for the carriers to transverse before recombining, the transistor becomes essentially two

diodes sharing a common terminal. This was apparently the root flaw of the HBT structures

developed in this work.

The collector and base regions of the HBT structures studied here were deposited by a

commercial contractor. A spreading resistance profile of the deposited layers is presented in

Fig. 6. Both the base region (p-type) and the collector region (lightly n-type) were much

thicker than ordered. This is due to the complication of carrier migration during deposition. As

these films were deposited at =1300°C, abrupt changes in carrier concentration are not possible

Carrier Concentration

(cm-3)

'.....;. |:

:: ^4Wf*Mnwi«i»*

:n ::

.: I: I " . I: I :: i:" il

;:;h;'';r

:-r

n-type collector n-type wafer

mm

< 5

DEPTH - microns

Figure 6. Spreading resistance profile of base and collector regions.

9

due to the diffusion of donors and acceptors. As a consequence, thicker films are necessary to

achieve a relatively constant dopant level.

E. Conclusions

The second batch of devices was processed with thinner SiC films, reducing the required

precision of the etching process. SEM examination of the second set of wafers indicated that

the SiC was etched appropriately. However, none of the wafers in this second batch contained

operational devices either. Electrical characterization of the latter devices revealed rectifying

behavior at both the emitter-base and the base-collector junction. An excessive base width is

hypothesized to be responsible for the lack of transistor behavior in the device structures. Due

to the base region width, injected carriers recombined before reaching the base-collector

junction. As a result, the transistors actually behaved as two independent p-n junctions that

shared a p-terminal contact. Although a batch of devices with a thinner base region may have

succeeded, this project was terminated.

F. Acknowledgements

The author would like to acknowledge John Palmour at CREE Research Inc., Durham, NC

for his diligent efforts in performing the etching of the SiC films in this research.

G. References

1. E. O. Johnson, RCA Rev. 26, 163, 1965. 2. R. W. Keyes, Proc. IEEE 60, 225, 1972. 3. Handbook of Chemistry and Physics , Editor-in-Chief D. R. Lide, CRC Press, 72M ed.,

1991-1992. 4. R. F. Davis, Physica B 185, 1, 1993. 5. R. F. Davis, J. W. Palmour and J. A. Edmond, Mat. Res. Soc. Symp. Proc. 162, 463,

1990. 6. H. P. Liaw and R. F. Davis, J. Electrochem. Soc. 131 3014, 1984.

10

III. Oxidation Process and the Prediction of the Optimum Oxidation Time of Ce02/cc-Ce02-x/Si02/Si(lll)

A. Introduction

Cerium oxide (CeC«2) is a crystalline insulator. It is a promising material to realize the

silicon-on-insulator (SOI) structure because it has a CaF2-type cubic structure which is nearly

lattice matched to Si with high dielectric constant (-26). The lattice misfit (Aa/a) is only

0.35%[1]. These values are considerably better than the respective values for other crystalline

insulators such as CaF2, sapphire, and spinel[2-4].

As previously reported, Ce02 on Si has two distinct amorphous regions at the interface and

the electrical properties of this structure can be improved by post-annealing in dry oxygen

ambient[5,6]. In other words, altering the film structure from CeC»2/a-Ce02-x/Si02/Si to

Ce02/Si02/Si greatly enhances the electrical properties. Unfortunately, this oxidation of the

as-grown films increases the thickness of SiC<2. It is desirable to keep the SiC»2 thickness as

thin as possible to maintain a large total capacitance.

In this report, oxidation models will be established for both Ce02/a-Ce02-x/Si02/Si and

Ce02/Si02/Si. The investigation will examine how to meet the optimum oxidation time in order to arrive at maximum capacitance without an a-CeC>2-x layer.

B. Experimental Procedure

CeC<2 thin films have been grown on Si substrates using a UHV laser ablation system[5,6].

The base pressure was kept 10"8 Torr during the growth. The growth temperature was ~700°C,

and post-annealing in dry oxygen ambient was applied. Both as-grown and annealed films

were evaluated by high resolution transmission electron microscopy (HRTEM), Rutherford

Back Scattering (RBS), and capacitance-voltage (C-V) measurements. The thickness of each

film was determined from the TEM images.

The post oxidation in dry oxygen was exactly the same procedure as the standard oxidation

of Si. The oxidation temperature was 900°C, and the oxidation times were 18 and 35

minutes[6]. Table I shows the thickness changes due to the oxidation as measured by TEM.

From the experimental data in Table I, the following was deduced:

i) Initially, the oxidation and the 02-diffusion processes were used mainly in converting

a-CeC»2-x to CeC«2, thus reducing xi to zero and increasing x0 to its maximum steady

value, i.e. Xo(final) = x0(initial)+xi(initial). This initial stage was expected to be carried out

in time t = x, where x in Table I was less than 18 minutes, as concluded from the TEM

microstructure observation.

11

Table I. Experimental Data of Each Layer Thickness Before and After Oxidation

Oxidation time [min]

Ce02 thickness x0[A]

cc-Ce02-x thickness xi [Ä]

Si02 thickness x2[Ä]

as-grown 181 37 26 18 218 0 70 35 218 0 192

ii) For t < x the thickness of Si02(x2) did not change much from its initial value X2(initial).

This assumption was based in the smaller relative increase in SK>2 layer thickness during

the first 18 minutes of oxidation time relative to the next 17 minutes of further oxidation.

C. Diffusion Model

The calculations used in this study were based on the Deal-Grove oxidation model of

Si02/Si structure[7]. This model was modified to study the O2 diffusion in the Ce02/Si02/Si

structure and determine an expression for X2 for t > x. The model was also expanded to

consider the more complicated Ce02/a-Ce02-x/Si02/Si structure.

Oxidation for CeOilSiO^Siilll). Figure 1 shows the O2 concentration profiles and the

fluxes considered in studying the O2 diffusion process in the Ce02/Si02/Si structure.

Si(lll)

Figure 1. Schematic oxidation model for Ce02/Si02/Si(l 11).

12

In this figure,

XQ: thickness of CeC>2,

X2'. thickness of SiÜ2,

Fi: oxygen flux in Ce02,

F3: oxygen flux in Si02,

F4: oxygen flux through the Si02/Si interface,

C0: oxygen concentration at the CeC>2 surface,

Cj2: oxygen concentration at the front surface of Ce02/Si02 interface,

Q3: oxygen concentration at the SiCtySi interface, and

1: segregation coefficient of oxygen at the Ce02/Si02 interface.

The oxygen fluxes, Fi - F4, were as follows:

C -C R=D. ° i2

F,=D,i^

where,

Do

D2

F =k C

diffusion constant of oxygen in CeC>2,

diffusion constant of oxygen in Si02, and

chemical reaction rate at SiC>2/Si interface.

Since the thickness of the Si substrate was too large compared with the other layers, the

oxygen flux in Si substrate was almost zero. In the steady state of oxidation conditions, all the

oxygen fluxes were equal, thus the oxygen concentration at Si02/Si, Q3, was deduced from

C:,= ic„

1 1 "C2Xo 1 ^2X2 (1) D„ D„

The SiC>2 growth rate was generally given as:

dXj _ r3 _ K2Li3

dt N, N, (2)

13

where,

N2: the number of oxygen atoms incorporated into a unit volume of SiC>2.

Since x0 was assumed to be constant based on the experimental results, the integration of

Eq. (2) with Eq. (1) led to the SiÜ2 thickness as a function of time.

21D2C0, . X2=J—^(t-T) + f T 1D2 D2^

2

V Do Kj

]D2,+ D1

D„ (3)

L2 J

The initial conditions used in Eq. (3) were as follows:

x: oxidation time for the film structure to change from Ce02/a-Ce02-x/Si02/Si to

Ce02/Si02/Si (optimum oxidation time), and

x2: thickness of SiÜ2 at t = x.

Equation (3) was valid for t > x. Using this solution and experimental data, the optimum

oxidation time x, i.e. the time required to recrystallize a-Ce02-x without increasing the SiC>2

layer thickness, was deduced.

Oxidation for Ce02lcc-Ce02-x/Si02lSi(Ul). Figure 2 shows the schematic oxidation model

for Ce02/cc-Ce02-x/Si02/Si with the same concept as the case above.

Si(lll)

Fii F4

Figure 2. Schematic oxidation model for Ce02/a-Ce02-x/Si02/Si( 111).

The following extra parameters were used:

xi: thickness of a-Ce02-x,

Fj 1: oxygen flux at Ce02/a-Ce02-x interface,

14

F2: oxygen flux in a-Ce02-x,

Qi: oxygen concentration at the Ce02/oc-Ce02-x interface,

nx segregation coefficient of oxygen at the Ce02/oc-Ce02-x interface, and

n: segregation coefficient of oxygen at the a-Ce02-x/Si02 interface.

The oxygen fluxes, Fi - F4, were as follows:

C.-C, 1 ~ *^o" F,=D„^ *-, (4)

F2 = = D: mC; 1 nCi2

xi

F3 = D nC 2 - ■c„

2 x2 »

Fu^kA. (5)

(6)

(7)

Fi2 = k2Ci3, (8)

where, Dj: diffusion constant of oxygen in a-Ce02-x, and

kj: chemical reaction rate at Ce02A*-Ce02-x interface.

In the steady state oxidation conditions, the oxygen fluxes satisfied the following equations:

Fi=Fii+F2, (9)

and F2 = F3 = F4. (10)

Substituting Eqs. (4)-(8) into Eqs. (9) and (10) gave

Cil " 1 + JEISL + nk2x0 / D0 ' (11}

D0 k2Xi/D1+n(l + k2x2/D2)

and

C = ™ ^ (12)

^ + n f, k^WM^ mk2x0/D0

1 + - V D2 J

D0 k^/D.+n^ + k^/D^

15

The growth rates of CeC>2 and SiÜ2 were as follows:

_5°. = _iL = £l_ii. (13) dt N, N,

and

^2 _ *3 _ ^2^-i3 (2)

dt N2 N2 '

where,

Ni: the number of oxygen atoms incorporated into a unit volume of Ce02-

Since the experimental data shown in Table I indicated that the sum of Ce02 and a-Ce02-x

thicknesses did not change with oxidation, the thickness of cc-Ce02-x was given simply as

__ mi . mi Xi —Xn T X, x0» i -*o + xi ~xo' (14)

where,

x™: initial thickness of Ce02, and

x™: initial thickness of a-CeC)2-x-

The differential Eqs. (13) and (2) had to be solved with Eqs. (11) and (12) in order to

obtain CeÜ2 and SiC>2 thicknesses as functions of time. However, the equations were too

complex to solve mathematically. This research relied on an earlier assumption based on the

data shown in Table I that most of the oxygen from the surface of CeÜ2 was consumed at Ce02/a-Ce02-x interface. For t<x, this assumption seemed reasonable since the SiC>2 growth

rate was much faster after the completion of a-Ce02-x recrystallization (t > x) than before the

completion (t < x). Using the oxidation models, this assumption was expressed as

Fii » F2 (15)

and modified with Eqs. (7) and (8) as

mk, V-; ( , „ v 05)'

D, 1 , ^2X2

V D2 j

Thus, Eqs. (11) and (12) were simplified as

Cu- ^ , ÖD' 11 l + klXo/D0

16

ci3«^ k2l + klXo/D0

and

k2Ci3«k1Lil. (12)'

The CeÜ2 thickness as a function of time was achieved by the integration of Eqs. (13) and

(11)':

x0 = ^^^t + (xf+D0/k1)2-D0/k1. (16)

Equation (12)' implied that the Si02 growth was negligible while CeC<2 was growing by

consuming the a-CeC«2-x- Thus,

X2 — X2 — X2 at t < x, (17)

where x™ was the initial thickness of SiC>2 in the as-grown material.

Equations (14), (16), and (17) were valid for t < x. The optimum oxidation time x was

obtained from Eq. (16) with x0 = x™ + xj™ as

T=- N,

2D0C0

xri(2x0üü + xri+2D0/k1). (18)

By using this value x, the optimum oxidation time for various initial thicknesses of CeC»2

and cc-Ce02-x was found. Since ki and C0 were unknown parameters, they were determined

based on the experimental data as shown below.

D. Results and Considerations

The following physical constants were used in the above equations:

D0 = 4.4 x 10-9 cm2/sec

Di = 9.0 x 10-8 cm2/sec

D2 = 2.8 x 10-9 cm2/sec

Ni=2.5 xl022/cm3

N2 = 2.2 xlO^/cm3

k2 = 2.2 x 1(H cm/sec

Diffusion constant of oxygen in Ce02[9],

Diffusion constant of oxygen in a-Ce02.x[9],

Diffusion constant of oxygen in SiO2[10],

Quantity of Oxidant incorporated into Ce02,

Quantity of Oxidant incorporated into Si02, and

Chemical reaction rate of oxide formation at Si02/Si[7].

17

First, Eq. (3) was used with the data shown in Table I to obtain 1, the segregation coefficient at the Ce02/SiC>2 interface. Since Eq. (3) was valid for any t > x, data shown in

Table I to obtain 1 was used and thus,

1 = 2.7

was obtained.

In this report, C0 = 6.0 x 1016 /cm3 was used which is oxygen concentration at the SiÜ2 surface[l 1]. Then, using Eqs. (3) and (17), x was obtained as

x = 11.6 min.

This was the average value of x calculated with t = 18 minutes and t = 35 minutes. Finally,

using Eq. (18) with this x resulted in

ki = 2.5 xl(Hem/sec.

Since this value was so close to the one of Si02/Si, it suggested that the approximation

which was applied was reasonable. Using these values, variation of thicknesses of each layer

with oxidation time was calculated and is shown in Fig. 3.

<D

u.

250

200

150

100

50

j 1— 1 l 1 j

Ce02

li '■ •

■ • J

,-:' Si02

*• *

(X-ueU2_x

,"' • Experimental Data

i i—^-4— 1 1 —i i 10 x 15 20 25

Oxidation Time [min]

30 35

Figure 3. Time dependence of each layer thickness with oxidation as calculated by the approximation used in this report.

18

Data in Fig. 3 was obtained based on the approximation previously mentioned. However,

the time dependence of thicknesses can also be obtained using fitting parameters by numerical

calculation on Eqs. (11) and (12). The numerical approach can calculate SiC>2 growth during

the recrystallization. Using the same parameters, the time dependence of thicknesses with

fitting parameters m and n was obtained which was the segregation coefficients at the interfaces

of Ce02/a-Ce02-x and a-Ce02-x/Si02, respectively. The results are shown in Fig. 4.

250

200 -

.5 o 2

o

m/n = 1.0 m/n = 0.5 m/n = 0.1 Experimental Date

0 10 x 15 20

Oxidation Time [min]

25 30 35

Figure 4. Si02 thickness changes with oxidation as calculated by the numerical calculation using m/n as fitting parameters.

From this figure, it was clear that if the ratio of m/n was close to zero, the calculation result

closely reached that of the approximation based on experimental data. The large value of n was

reasonable since a-Ce02-x was eliminated much faster than Si02 growth. Other iteration can

also be applied to the best fitting of data.

E. Conclusions

Oxidation models for Ce02/cx-Ce02-x/Si02/Si and Ce02/Si02/Si are proposed in order to

obtain optimum oxidation time T which gives the Ce02/SiO2/Si structure with the thinnest SiÜ2

thickness. An expression for x was developed as a function of the initial thickness of the

deposited film. The numerical calculation results also indicated the validity of the assumption.

19

F. Future Plans and Goals

It is planned to use the above calculations to predict the optimum oxidation time for

different initial CeÜ2 deposited films and the use of TEM, RBS and C-V to confirm the validity of the above model.

G. References

1. T. Inoue, Y. Yamamoto, S. Koyama, S. Suzuki, and Y. Ueda, Appl. Phys. Lett. 56, 1332, 1990.

2. T. Asano and H. Ishiwara, J. Appl. Phys. 55, 3566, 1984. 3. M. Ishida, I. Katakabe, and T. Nakamura, Appl. Phys. Lett. 52, 1326, 1988. 4. K. Egami, M. Mikami, and H. Tsuya, Appl. Phys. Lett. 43, 757, 1983. 5. T. Chikyow, L. Tye, N. A. El-Masry, and S. M. Bedair, Appl. Phys. Lett. 65, 1030,

1994. 6. L. Tye, T. Chikyow, N. A. El-Masry, and S. M. Bedair, Appl. Phys. Lett. 65, 3081,

1994. 7. B. E. Deal and A. S. Grove, J. Appl. Phys. 36, 3770, 1965. 8. Y. Takahashi, T. Ishiya, and M. Tabe, Appl. Phys. Lett. 65, 2987, 1994. 9. B. C. Steele and J. M. Floyd, Proc. Brit. Ceram. Soc. 19, 55, 1971.

10. S. M. Sze, VLSI Technology, McGraw Hill, 315, 1988. 11. F. J. Norton, Nature 171, 701, 1961.

20

IV. Properties of Ce02 Films on Si(100) Substrates

A. Introduction

Thin films of CeC>2 deposited on silicon substrates may have the potential of providing

MOS capacitor structures with a higher storage capacity compared to conventional Si02 films

because of the higher relative dielectric constant (~ 26) of Ce02 [1]. Epitaxial Ce02 films

deposited on Si(lll) substrates by pulsed laser ablation of a Ce02 target under UHV

conditions at relatively high substrate temperatures in the range 550 to 750°C and annealed in

different environments were previously investigated [2,3] and were shown to have improved

electrical properties after annealing in oxygen at high temperature (900°C). This annealing was

needed to reduce defects in the as-deposited films and retain their stoichiometry. This,

however, resulted in the growth of an intermediate Si02 layer which increased the effective

oxide thickness of MOS capacitors, and an optimization of the annealing time was generally

needed [3]. Unlike other amorphous materials such as Ta205 [4], amorphous Ce02 films have

not been investigated for use in capacitor applications. These films can be deposited at lower

temperatures which is expected to reduce oxygen deficiency and minimize the initial Si02 layer

thickness of the films. Crystallization of these films on Si(100) substrates would be very

interesting as a Silicon On Insulator (SOI) technology on Si(100) is preferred over a

technology on Si(l 11) substrates for the lower density of surface states on (100) surfaces. This

directly relates to a better performance of MOS devices fabricated on a (100) surface of an SOI substrate.

In this work, crystallization of Ce02 films grown at low temperatures on Si(100) substrates

was explored by rapid thermal annealing of a very thin film of Ce02 grown at room

temperature on an Si(100) substrate off-oriented by 4° in the <110> direction as enhanced

partial crystallization of Ce02 films grown by electron beam evaporation on such substrates

was reported in the literature [5]. MOS capacitors were fabricated on the CeC^ films deposited on silicon (100) substrates and characterized by C-V and I-V techniques.

B. Experimental Procedure

Five ohm-cm p-type Si(100) substrates off-oriented by 4° in the <110> direction were

cleaned and degassed under UHV as previously described [2]. A preheat to 750°C for 10

minutes was carried out to evaporate contaminants from the silicon surface. The substrate

temperature was then reduced to the growth temperature and pulsed laser ablation of a Ce02

target (99.999% purity) was carried out under pressures lower than 5xl0"8 Torr during the

ablation. The growth temperatures were 20, 40 and 200°C.

Samples of films grown at 20°C of about 50 Ä thickness were rapid thermally annealed in

argon at 1000°C for 5 and 10 minutes and reloaded into the vacuum system to be examined by

21

RHEED. Samples of the films grown at 20 and 40°C were ex situ annealed in forming gas for

30 minutes at 500°C, and rapid thermally annealed in argon at 1000°C for 5 minutes. MOS

capacitor structures were fabricated by evaporating aluminum dots onto the CeÜ2 surface and

the electrical properties of the films were investigated by C-V and I-V techniques. Films

deposited at 200°C were in situ annealed at 750°C for 30 minutes. TEM revealed that partial

coverage of the silicon surface took place at 200°C and no further work was done on these

samples.

C. Results

Figure 1 shows the RHEED patterns observed of films of about 50 Ä thickness grown at

20°C and rapid thermally annealed in argon at 1000°C for: (a) 5, and (b) 10 minutes. Figure 2

shows typical high frequency C-V characteristics obtained of as-grown, forming gas annealed

(N2 + H2 for 30 min. at 500°C) and rapid thermally annealed (Ar for 5 min. at 1000°C) films of

a thickness of about 300 Ä. The breakdown voltages of capacitors fabricated on the as-grown films ranged from 2 to 13 volts with leakage currents of the order of 100 |iA/cm2 just before

breakdown. For the forming gas annealed films, breakdown voltages between 8 and 14 volts

were observed with almost the same leakage level before breakdown. For the rapid thermally

annealed films lower breakdown voltages around 4 volts and higher leakage currents of about

500 |iA/cm2 were obtained.

D. Discussion

While the RHEED pattern in Fig.(a) indicates that the films were amorphous even after the

RTA for 5 minutes, fading streaks appear in the pattern of Fig.(b) which can indicate a partial

crystallization at the films surface after 10 minutes annealing. However, the patterns observed

in some spots of the 10 minutes annealed films had bright rings which suggests that another

technique is needed to achieve single-crystallization of the films on top of the Si(100) template.

As can be seen from Fig. 2(a), large accumulation capacitances were obtained from

as-deposited amorphous films of Ce02- The value of 2500 pF corresponds to an effective SiC«2

thickness of 8.5 nm of the MOS capacitors. The leakage level of these samples was, however,

excessively high resulting in inclined C-V curves in accumulation and deep depletion under

positive voltages as inversion charges had probably leaked through the films. Their breakdown

voltages varied largely depending probably on the presence of local defects in the films.

Forming gas annealing appears to improve the leakage characteristics. Leakage current effects

on the C-V curves were less pronounced as can be seen from Fig. 2(b). The films had

breakdown voltages which are larger and less scattered in value than those of as-grown films.

The capacitance obtained in accumulation was slightly less due probably to the formation of a

thin layer of SiC>2 by oxygen to the silicon surface. The annealing temperature which is 500°C

22

Figure 1(a). RHEED pattern observed of Ce02 films of about 50 Ä deposited at 20°C on Si(100) and rapid thermally annealed in argon at 1000°C for 5 minutes.

Figure 1(b). RHEED pattern observed of CeC>2 films of about 50 Ä deposited at 20°C on Si(100) and rapid thermally annealed in argon at 1000°C for 10 minutes.

is lower than values where the stoichiometry of the films would be affected by a low partial

pressure of oxygen in the annealing ambient [6,7]. However, still deep depletion of the silicon

surface under positive biases was observed. Films exposed to rapid thermal annealing in argon

at 1000°C for 5 minutes had degraded C-V characteristics as seen from Fig. 2(c). They did not

reach a maximum capacitance in accumulation up to -10 volts as accumulation charges could

have been leaking through the films. The leakage levels of these films were higher than those

23

-3 -2 -1 Voltage [V]

Fig. 2(a). High frequency C-V curves of MOS capacitors with 35 mils diameter fabricated on as-grown CeC>2 films with a thickness of about 300 Ä deposited on Si(100) at 40°C, at a frequency of 100 KHz.

-2 -1 0 Voltage [V]

Fig. 2(b). High frequency C-V curves of MOS capacitors with 35 mils diameter fabricated on CeÜ2 fihns with a thickness of about 300 Ä deposited on Si(lOO) at 40°C and annealed in forming gas (N2 + H2) for 30 min at 500°C, at frequency of 1MHz.

1320.0

1300.0

-10 I i I 1 J Voltage [V]

Fig. 2(c). High frequency C-V curves of MOS capacitors with 35 mils diameter fabricated on Ce02 films with a thickness of about 300 Ä deposited on Si(100) at 40°C and rapid thermally annealed in Ar for 5 min. at 1000°C, at a frequency of 100 KHz.

24

of as-deposited films and their breakdown voltages were lower than those of films annealed in

forming gas at 500°C. This can be a result of partial crystallization of the films into

polycrystalline CeÜ2 or an increase in oxygen deficiency of the films with annealing.

E. Conclusions

Films of CeC<2 were deposited at lower temperatures on Si(100) substrates. Crystallization

of very thin CeC>2 films deposited on 4° off-oriented Si(100) by rapid thermal annealing in an

argon environment at 1000°C for 5 and 10 minutes was investigated. The RHEED patterns

observed indicated partial crystallization at the films surface.

Samples of the deposited films were annealed in forming gas at 500°C for 30 minutes and

rapid thermally annealed in argon at 100°C for 5 minutes. The as-grown and annealed samples

were characterized by C-V and I-V techniques to explore their potential for use in MOS

memory devices. Relatively high accumulation capacitance and high leakage currents were

observed of as-grown films. Improved leakage and breakdown characteristics were obtained

with forming gas annealing while the rapid thermal annealing resulted in enhanced leakage through the films.

E. Future Research Plans and Goals

Crystallization of CeC>2 films on Si(100) surfaces for a SOI technology on Si(100)

substrates is very interesting and will be further investigated. Ways to reduce the leakage

currents of as-deposited amorphous CeC>2 films on silicon substrates are also to be

investigated. Characterization of MOS capacitors of epitaxial Ce02 films on Si(lll) substrates

with optimized oxygen annealing times is now in progress and will soon be reported.

F. References

1. T. Inoue, M. Osonoe, H. Tohda, M. Hiramatsu, Y. Yamamoto, A. Yamanaka and T. Nakayama, J. Appl. Phys. 69, 8313 (1991).

2. T. Chikyow, L. Tye, N. El-Masry and S. Bedair, Appl. Phys. Lett. 65, 1030 (1994). 3. A. H. Morshed, M. Tomita, P. McLarty, N. Parihk, N. El-Masry and S. Bedair,

Materials Research Society Meeting Fall 1994, Boston, MA. 4. S. O. Kim and H. J. Kim, Thin Solid Films 253, 435 (1994). 5. T. Inoue, H. Kudo, T. Fukusho, T. Ishihara, T. Ohsuna, Jpn. J. Appl. Phys. 33, LI39

(1994). y y

6. P. Kofstad, Non-Stoichiometry, Diffusion and Electrical Conductivity in Binary Metal Oxides, Wiley Interscience, 1972, p.277.

7. H. Tuller and A. Nowick, J. Electrochem. Soc. 126, 209 (1979).

25

V. Influence of Temperature and Methane Concentration on the Diamond Growth Parameter a on Silicon and Titanium Substrates

A. Introduction

Diamond has become an enticing candidate for high-power, high-frequency electronic device applications in high-temperature or chemically-harsh environments. However, to realize its true potential, single-crystal diamond films are needed. Although economically viable sizes and quantities of substrates for single-crystal diamond films are still not available, there has been significant progress on oriented diamond films [1-3]. Under certain growth conditions, strongly oriented diamond films can be obtained by taking advantage of the growth competition between differently oriented diamond grains [4]. In order to take advantage of the texture evolution process, it is essential to understand the growth parameter a which is given by the relative growth rates on {100} and {111} facets [5-7]. The growth parameter a can be represented by the simple formula, a = V3 (Vioo/Vm) where Viooand Vm are the growth rates on the {100} and {111} faces, respectively.

To gain the precise information about the growth parameter a on silicon and titanium in our

system, investigation of the dependence of the morphology of diamond films on methane concentration and deposition temperature was undertaken. After deposition, the morphology of each sample was examined by the scanning electron microscope (SEM). The values of a were

determined by comparing the surface morphologies with the idiomorphic crystal shapes for different values of a described by Wild [6]. While there have been some experimental results of the growth parameter a on silicon, understanding the growth parameter a on titanium remains elusive. Investigating the a parameter space on titanium is desirable because of its

potential application as an interlayer for diamond nucleation on otherwise "difficult to nucleate" materials, such as copper and steel. Also, comparison of "a maps" for silicon and titanium may elucidate some mechanisms of diamond growth.

B. Experimental Procedure

Substrate Preparation. The polycrystalline titanium samples were polished using progressively finer media. The polishing scheme started with 600 grit SiC, then 30nm and 6^m diamond powder and finished using a colloidal silica solution that polished by mechanical

and chemical means. Following the polishing, the sample was cleaned by acetone, methanol, and isopropanol. The silicon (100) substrates were etched in dilute HF acid prior to insertion into the chamber.

Four-step Deposition Process. The four-step deposition process consisted of a hydrogen plasma clean, surface carburization, biased enhanced nucleation (BEN), and growth. Hydrogen plasma clean was performed for 30 minutes to remove any carbonaceous residue on

26

the substrates. Following the hydrogen plasma clean, the carburization step was undertaken for 30 minutes at 2% methane/hydrogen concentration at 25 Torr. After the carburization step, the samples were subjected to a nucleation step. At the nucleation step, the chamber pressure was reduced to 20 Torr and methane/hydrogen ratio was increased to 5%. Then a negative DC voltage, about -240 V, was applied to the substrate for 8 minutes. At the end of the biasing step, the bias voltage was terminated and the pressure was raised to 25 Torr. In the growth stage, the substrate position and methane/hydrogen concentration was changed to the desired point Table I summarizes the system parameters for each step.

Table I. Summary of System Parameters

Parameters H2 Plasma Clean Carburization BEN Growth

Power 600W 600W 600W 600W Pressure 25 Torr 25 Torr 20 Torr 25 Torr CH4/H2 ratio - 2% 5% varied Bias Current - - 80 mA -

Bias Voltage - - -240V -

Temperature 700*C 800*C 850'C varied Duration 30 minutes 30 minutes 8 minutes 16-17 hours

Growth Conditions. From previous experience, the following upper and lower limits on methane concentration (0.1%-1.0%) and deposition temperature (700*C-900*C) were chosen. In order to have the best representative data points, a statistical experimental design software package (Strategy) was used to determine the different deposition conditions within the limits. The resulting deposition was observed by SEM and isolated diamond particles were examined to determine the a value. Approximate a values were assigned using the idiomorphic crystal

shapes described by Wild [6] and further discussed by Tamor [7]. Although a different chamber system and operating parameters were used, the diagram composed by both researchers gave a general gradient of cc The idiomorphic crystal shapes and a diagram composed by Wild is in Fig. 1. The value of a increased with decreasing deposition

temperature and increasing methane concentration. Table II summarizes the five different deposition conditions.

C. Results and Discussion

Deposition on Silicon. Well-defined facets were observed at all deposition conditions, except for the low methane concentration and low temperature sample (Sample 4). The

27

1.5 U

09®$$$$^

a=1.5 a =2.0

S 950

a=2.5

a=3.0

700 0 1.0 2.0 3.0 4.0

Methane concentration (%)

Figure 1. Idiomorphic crystal shapes and a diagram composed by Wild.

Table IL Deposition i Conditions for Each Sample

Sample Number CH4% Temperature

1 0.27 900±10 2 1.00 700±10 3 0.60 800±10 4 0.10 700±10 5 0.93 900±10

corresponding a value and SEM image of each sample is shown in Table HI and Figs. 2(a-d),

respectively. The diamond crystals on the Sample 1 showed cubo-octahedral shape

morphology as in Fig. 2(a). Since adjacent (111) faces and adjacent (100) faces were touching, the corresponding a value was about 1.5. Figure 2(b) shows the crystal morphology of

Sample 2 which had truncated-octahedral shaped crystals. Compared to the idiomorphic crystal

shape for a = 2, Sample 2 had slightly larger (100) faces. Thus, the a value for Sample 2 was

determined to be about 2.2. Sample 3 had a similar particle morphology to Sample 2 (Figs. 2c

and 2b, respectively), although the (100) faces appeared to cover more of the crystal surface

28

than in Sample 2. Therefore, the a value for Sample 3 should lie between 2.2 and 1.5 and a

value of 2.0 was assigned. Sample 5 had a similar morphology to Sample 1 (i.e. adjacent (111) and adjacent (100) faces intersected at a point), corresponding to a value of 1.5. As expected, the gradient of a followed the same trend as discussed by Wild [6] and Tamor [7]. Alpha

increased with decreasing deposition temperature and increasing methane concentration. Based on this preliminary evaluation, an initial a diagram for diamond growth on silicon is shown in

Fig. 3.

Table m. Corresponding a Values for Each Sample

Sample Number a Value on Si a Value on Ti

1 1.5±0.1 heavily twined particles 2 2.210.1 tt

3 2.0±0.1 it

4 heavily twined particles If

5 1.5±0.1 it

Figure 2(a). SEM image of Si Sample 1 (CH4% = 0.27%, T^ = 900°Q.

29

(b)

(c)

(d)

Figure 2 (b) SEM image of Si Sample 2 (CH4% = 0.1%, Tsub = 700°Q; (c) SEM image of Si Sample 3 (CH4% = 0.6%, Tsub = 800°C); (d) SEM image of Si Sample 5 (CH4% = 0.93%, T^ = 900°C).

30

1000-

950-

ü 1.5 1.5 °_ 900- o o 2 3 850-

S CD 800-

2 o

2.2 O

Q. § 750- 1-

700- o 650-

1 I i i ■ 1 ■ ■

0.0 0.2 0.4 0.6 0.8 Methane concentration

1.0

Figure 3. Alpha diagram for diamond growth on Si.

Deposition on Titanium. In the case of titanium, all of the samples had heavily twinned

"cauliflower-like" morphologies as shown in Fig. 4. The absence of diamond particles with well-defined facets made determination of a impossible. In order to examine the growth

parameter a on titanium, the twinning needed to be reduced as much as possible. There are

several factors which may have contributed to the twinning of diamond on titanium: i) surface

roughening after oxide removal, ii) hydride formation, iii) amorphous carbide formation, and

iv) high surface mobility of carbon species. The first possible explanation for the twinning of

diamond would be the surface roughening after oxide removal during the hydrogen plasma

cleaning. Because titanium is a strong oxide former, substantial amount of oxide was likely

formed during the substrate preparation stage. Since the interface between titanium and its

oxide was probably not as smooth as the polished original surface, a rough surface would have

resulted after etching by the hydrogen plasma. This rough surface may have contributed to the

formation of twins in diamond. Another possible reason for heavy twinning can be found from

its deposition environment Throughout the deposition steps, titanium substrates were exposed

to a hydrogen environment. Formation of a hydride could have occurred and would embrittle

the titanium surface. As the substrate was heated by the plasma, differences in the thermal

expansion coefficient may have caused cracking of the surface. These small cracks could have

served as nucleating sites for non-uniform diamond particles and might have been responsible

for heavily twined particles. The next factor may have been the formation of an amorphous

carbide during the carburization step. Since amorphous carbide does not have long range order,

it can easily contain defects that may contribute to the twinning. The last and more speculative

reason would be the effect of surface mobility of carbon species on the titanium surface.

Compared to silicon, titanium has much lower thermal conductivity; therefore, the surface

temperature of titanium may have been higher than silicon. Since titanium might have had a

31

higher substrate temperature, the carbon species on titanium could migrate more easily, leading to a higher local carbon concentration. The higher carbon concentration would lead to twinning of the diamond crystals. Among the four factors, surface roughening after etching the titanium oxide layer, during the hydrogen plasma clean stage, is probably the most dominant factor, although further investigation is needed.

Figure 4. SEM image of typical diamond crystals on TL

D. Conclusions

The growth parameter a has been studied on silicon and titanium by investigating the

dependence of films morphology on methane concentration and deposition temperature. On silicon, a range of a values was determined for diamond crystals deposited under a range of substrate temperature and methane concentration conditions. From this data, an initial a map was generated. The diagram confirmed the a gradient; the value of a increased with decreasing

deposition temperature and increasing methane concentration. Under the same conditions, only heavily-twined diamond particles were found on the titanium substrates. Possible mechanisms which may have contributed to the twinning of diamond include surface roughening after oxide removal, hydride formation, amorphous carbide formation, and high surface mobility of carbon species. The surface roughening of the titanium after oxide etching is probably the most dominant factor.

E. Future Research Plans and Goals

In order to have a more detailed diagram, more samples with different methane concentrations and deposition temperatures need to be examined. The goal of this research is to grow highly oriented (lOO)-faceted diamond film on a silicon (100) substrate. On titanium substrate, since well-faceted diamond particles could not obtained, non-twined diamond

32

particles need to be nucleated in order to study the growth parameter a. To reduce the effects of

surface oxide layer, it is planned to deposit a thin layer of titanium on silicon then transfer the

sample to microwave plasma chemical vapor deposition system to grow diamond. Since the

evaporation deposition system is connected to the microwave plasma chemical vapor deposition

system, the sample can be transferred between two chambers without exposing it to air.

F. References

1. B. A. Fox, B. R. Stoner, D. M. Malta and P. J. Ellis, Diamond and Related Materials 3, 382, 1994.

2. R. Beckman, W. Kulish, H. J. Frenk and R. Kassing, Diamond and Related Materials, 1, 164, 1992.

3. P. John, D. K. Milne and W. C. Vijayarajah, M. G. Jubber and J. I. B. Wilson, Diamond and Related Materials 3,388,1994.

4. C. Wild, N. Herres and P. Koidl, Journal of Applied Physics 68, 973, 1990. 5. C Wild, P. Koidl, W. Muller-Sebert, H. Walcher, R. Kohl, N. Heirs and R. Locher,

Diamond and Related Materials 2,158,1993. 6. C. Wild, R. Kohl, N. Herrs, W. Muller-Serbert and P. Koidl, Diamond and Related

Materials 3, 373,1994. 7. M. A. Tamor and M P. Everson, Journal of Materials Research 9 (7), 1839,1994.

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VI. Distribution List

Dr. Colin Wood Office of Naval Research Electronics Division, Code 312 Ballston Tower One 800 N. Quincy Street Arlington, VA 22217-5660

Administrative Contracting Officer Office of Naval Research Regional Office Atlanta 101 Marietta Tower, Suite 2805 101 Marietta Street Atlanta, GA 30323-0008

Director, Naval Research Laboratory ATTN: Code 2627 Washington, DC 20375

Defense Technical Information Center 8725 John J. Kingman Road, Suite 0944 Ft. Belvoir, VA 22060-6218

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