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8/3/2019 AtoD Timedomian2009!02!13 UCB Talk

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2009-02-13 11

A Bandpass Analog-to-Digital ConverterUsing Voltage-Controlled Oscillators

Young-Gyu Yoon & SeongHwan Cho

Communication Circuits and Systems Group, KAIST

http://ccs.kaist.ac.kr

Berkeley Wireless Research Center

CCS Group @ KAIST

Y.G. Yoon et al., Time-based Bandpass ADC using Time-Interleaved Voltage-Controlled

Oscillators, IEEE Trans. On Circuits & Systems I, Dec., 2008.


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2009-02-13

Motivation

Next-generation receivers require multi-mode multi-standardcommunication.

Programmableand digital-intensivereceiver is necessary.

ZigBee BluetoothWLAN

USNRFID

DECT

W-CDMA

UWB

GSM

GPS

2CCS Group @ KAIST
http://images.google.co.kr/imgres?imgurl=http://www.tele.ntnu.no/radio/newresearch/circuit/CMOS_chip.JPG&imgrefurl=http://www.tele.ntnu.no/radio/newresearch/circuit/RF-CMOS.htm&h=787&w=977&sz=137&tbnid=Xd7sAJ8npmUJ:&tbnh=119&tbnw=148&hl=ko&start=18&prev=/images?q=rf+chip&hl=ko&lr=&newwindow=1&rls=GGLD,GGLD:2004-46,GGLD:ko&sa=N


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2009-02-13

Receiver Architectures

3CCS Group @ KAIST

Large dynamic range

Many analog components

Low programmability

Highly digital

High programmability

Dynamic range is limited ( ADC)

High power consumption (

ADC)

A/D conversion at RFA/D conversion at IF

Low-power high-performance ADC is necessary.

ADCLNA DBBADCLNA IF Amp

LO

DBB


4/34

2009-02-13

Bandpass ADCs for Direct RF Sampling

Nyquist ADC Bandpass ADC

ff

4CCS Group @ KAIST

Bandpass ADC can be more efficient than a NyquistADC for a narrow-band communication receiver.


5/34

Conventional RF bandpass ADC

Mostly implemented in expensive processes due to highspeed requirement SiGe BiCMOS, InP HBT, etc

High power consumption due to high-speed analogcomponents (loop filter & DAC)

Filter is not programmable.

)(sH

DAC

+

AnalogInput

DigitalOutput

CLK

2009-02-13 CCS Group @ KAIST 5


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High Performance BP ADCs

A Low-Noise 40Gs/s Continuous-Time Bandpass

ADC Centered at 2GHz for Direct Sampling Receivers Continuous-time bandpass architecture using Gm-LC

LNA included in main path

Center frequency 2GHz

Sampling frequency 40GHz

SNR @ 10MHz BW 63dB (0dBm input)

Power consumption 1.6W

Supply Voltage 2.5V

Technology 0.13m SiGe BiCMOS

Active area 2.40mm2

Chalvatzis et al., A Low-Noise 40-GS/s Continuous-Time Bandpass ADC Centered at 2GHz for Direct Sampling Receivers,IEEE JSSC May, 2007.

2009-02-13 6CCS Group @ KAIST


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High Performance BP ADCs

Continuous-time bandpass architecture Passive L & C for band-pass filtering

Center frequency 950MHz

Sampling frequency 3.8GHz

SNR @ 1MHz BW 59dB

Power consumption 75mW

Supply Voltage 1.25V

Technology 0.25m SiGe BiCMOS

Active area 1.08mm2

Thandri and Martinez, "A 63 dB SNR, 75-mW Bandpass RF ADC at 950 MHz Using 3.8-GHz Clock in 0.25-umSiGe BiCMOS Technology," IEEE JSSC, Feb. 2007

2009-02-13 7CCS Group @ KAIST


8/342009-02-13 88

Previous Works on Direct RF Sampling

Ref fcarrier fsample BW SNDR Power Supply Process Mscl

JSSC2007

1.8~2.0GHz 40GHz 60MHz 55dB 1.6WVDD=2.5VVSS=0V

0.13um SiGeBiCMOS

4th2.40mm2

JSSC2007

950MHz 3.8GHz 1MHz 59dB 75mWVDD=1.25VVSS=-1.25V

0.25um SiGeBiCMOS

4th 1.08mm2

TCAS-II

2000 1GHz 4GHz 20MHz 37dB 450mW

VDD=5V

VSS=0V

0.5um SiGe

HBT

4th

1.36mm2

CICC2003

1.3GHz 4.3GHz 200MHz 39dB 6.2WVDD=5VVSS=-5V

InP HBT4th

5.28mm2

Goal800MHz ~

2.4GHz6.4GHz 20MHz 55dB ~ 15mW

VDD=1V

VSS=0V

65nm

CMOS

Time-basedADC

CCS Group @ KAIST

Conventional bandpass ADCs rely on fast devices (SiGe BiCMOS) and nonehave yet developed a CMOS RF sampling ADC.

Analog circuits are extensively used in conventional bandpass ADCs

Not compatible with future nanoscale CMOS devices.


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Contents

Motivation

Introduction to the VCO-based ADCTime-based ADC

Operation principle

Proposed VCO-based bandpass ADC

Implementation

Measurement results

Conclusion



10/342009-02-13 1010

Time-based Signal Processing

Time-based ADC is a promising candidate for direct RF samplingbandpass ADCs.

Conventional ADC Time-based ADC

In a deep-submicron CMOS process, time-domain resolution of a digital signal edge

transition is superior to voltage resolution of analog signals.[ Staszewski et al., All digital TX Frequency Synthesizer and Discrete-Time Receiver for Bluetooth Radio in 130-nm CMOS , IEEE JSSC, 2004 ]

CCS Group @ KAIST

Time domain

VDD

GND

GND

VDD

Faster transition

VDD

VDD

GNDGND

noise

Voltage domain

Lower SNR


11/342009-02-13 11

Operation Principle

VCO : Voltage-to-phase conversion

Counter: Phase quantization

Digital code generator: LUT

- Counting the edges of VCO output

ex) rising edge detection LSB = 2

ex) rising/falling edge detection LSB =

- Mapping circuit

Analoginput

Time

CLKs CLKs CLKs

Time

VCOoutputvoltage

VCOoutputphase

Time

VCO

Voltage tophase

domain

Rising edge

Counter out= 3

Rising edge

Counter out= 5

2

VCOAnalogInput

DigitalOutput

Digital CodeGenerator

Counter

clk

H. Burke, A survey of analog-to-digital converters, Proceedings of the IRE, 1954. A. Iwata et al., The Architecture of Delta Sigma Analog-to-Digital Converters Using a Voltage-Controlled Oscillator as a

Multibit Quantizer, IEEE Trans. Circuits Syst. II,, July 1999. A. Younis, H. Marwan, and R. Moises, Method and system for VCO-based analog-to-digital conversion (ADC), US pat.

# : 6,809,676 , 2004. E. Alon, et al, Circuits and Techniques for High-Resolution Measurement of On-Chip Power Supply Noise, IEEE Symp.

on VLSI Circuits, 2004

CCS Group @ KAIST


12/342009-02-13 12

Resolution of VCO-based ADC

fmax

fmin

9

2

t

Sampling period

(Conversion Window)

1LSB(2)

1LSB(2)

Number of

rising edges

max minV -V =81LSB

Resolution(N=3)

2

2

log1 ( )

log 1 ( )

MAX MIN

FS

V VResolution=

LSB V

V

LSB V

=

2

max min

2

2

log1 ( )

2 ( )log

1 ( )

2log

1 ( )

max min

VCO period

tune

sample

ResolutionLSB rad

K V V T

LSB rad

f

f LSB rad

=

=

=

1LSB

Vmax

Vmin

For high resolution ADC, a wide tuning range VCO is necessary.

CCS Group @ KAIST


13/342009-02-13 13

Operation Principles Revisit

Inherent 1-st order noise shaping property.

VCO Counter

Sampling Clock

x[n] Digital

outputS/H

input

Y[n]

{ }

{ }1

[ ] [ ]

2 [ ] [ ] [ ]

2 [ ] [ 1] [ ]

1[ ] [ ] [ ] [ 1]

2

1( ) ( ) (1 ) ( )

2

VCO

i

VCO

VCO

p n K x n

y n p n e n

y n e n e n

y n K x n e n e n

Y z K X z z E z

=

= +

= +

= +

=

VCO outputCounterOuputy[n] 4 3 ...

SampledInputx[n]

pi[n]

nn-1 n+1

Samplingclock

0

2

VCOphase shiftp[n]

e[n]

p[n]

time

4

6

8

10

e[n-1] e[n] pi[n+1]pi[n]

e[n-1]

CCS Group @ KAIST

A. Iwata et al. The architecture of delta sigma analog-to-digital converters using a voltage-controlled oscillator as amultibit quantizer," IEEE Trans. Circuits Syst. II, 1999.

1( 1) NTF z=


14/342009-02-13 14

SNR of VCO-based ADC

0 10 20 30 40 50 60 70 80 90 100-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

Frequency[MHz]

PSD[dB]

fsample = 200MHz

VCO Tuning Range : 50MHz~1GHz

Input frequency = 5MHz

ENOB = 8.48(bits)

Oversampling can be used to increase the resolution.

6.02 3.41 30log( )QSNR M OSR +2

/ 2

2log

1 ( )

sample in

tuneQ

sample

where OSR f f

fM

f LSB rad

=

=

Example)

CCS Group @ KAIST


15/342009-02-13 15

Past Work on VCO-based ADCs

A. Iwata et al., The Architecture of Delta Sigma Analog-to-Digital Converters Using a Voltage-Controlled Oscillator as a Multibit Quantizer, IEEE Trans. Circuits Syst. II, July 1999.

R. Naiknaware et al., Time-referenced single-path multi-bit ADC using a VCO-based quantizer,IEEE Trans. Circuits Syst. II, July 2000.

T.Watanabe, et al., An All-Digital Analog-to-Digital Converter With 12-uV/LSB Using Moving-AverageFiltering, IEEE JSSC, Jan. 2003.

J.Kim et al., A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator,ISCAS 2006

U. Wismar et al., A 0.2V 0.44W 20kHz Analog to Digital Modulator with 57fJ/conversion FoM,ESSCIRC, 2006.

Straayer et al., A 10-bit 20MHz 38mW 950MHz CT ADC with a 5-bit noise-shaping VCO-basedQuantizer and DEM circuit in 0.13um CMOS, VLSI 2007.

z-1DAC

CounterVCOAnalog

Integrator

Oversampling

Clock(fos)

Digital

output

Y(z)

Analog

input

X(z)VCO

Analog

InputDigital

Output

Digital Code

GeneratorCounter

clk

CCS Group @ KAIST


16/342009-02-13

n n+1Time (sample)

Sampling Clock

VCO Input 1

VCO phase 1

6

2

4]2[ ne

][ne

[ 2]i

p n +

CLK1

CLK2

VCO Input 2

VCO phase 2

6

2

4

0

0

n-1

]1[ ne

[ ]i

p n

[ 1]i

p n +

n+2

Analog Input

n+3

][n

[ 3]i

p n +

]1[ +ne

][nxGv

]1[ +n

]1[ +nxGv

AnalogInputx(t)

DigitalOutput

y[n]MUX

CounterVCOS/H

CLK1

CounterVCOS/H

CLK2

Reset(CLK2)

Analysis of Two-Channel Time Interleaved VCO-ADC

16CCS Group @ KAIST

2( ) 1 NTF z z

=

( )

( )

( )

( ){ }2

[ ] [ ] [ ]

1[ ] [ ] [ ]

2

1[ ] [ ] [ ]

2

1 [ ] [ 2 ] [ ]2

1( ) ( ) 1 ( )

2

v i

v i

v

v

n G x n p n

y n n e n

G x n p n e n

G x n e n e n

Y z G X z z E z

= +

=

= +

= +

= +


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SNR of the Two-channel T.I. VCO-ADC

Increase in |NTF| is canceled by the increased quantizer resolution.


2

2

2

1 1

8 8 / 2

14

8

tuneS FS

s

tune

s

fP V

f

f

f

= =

=

( )( )

( )

( )

1

2 1 1

1

2 1 , 1( ) 1 1 1

2 1 , 1

z z NTF z z z z

z z

= = +

+

210log 6.02log 3.41 30logS tune

e s

P fSNR OSR

P f

= = +

/

2

/

/

2

/

32

( ) | ( ) |

( ) 4 | 1|

436

OSR

e N

OSR

OSR

j

N

OSR

P S NTF d

S e d

OSR

=

=

=

/ 2(input referred quantization step)s

FS

tune

fV

f =


18/34

Proposed Nth-order ADC architecture

Analog

Input

x(t)

Digital

Output

y[n]

CounterVCOS/H

Reset

(CLK1)

CounterVCOS/H

Reset

(CLK2)

CounterVCOS/H

Reset

(CLK3)

CounterVCOS/H

Reset(CLKN)

CLK2

(fs/N)

CLK1

(fs/N)

CLK3

(fs/N)

CLKN(fs/N)

MUX

CCS Group @ KAIST2009-02-13 18

( )1( ) 1

1 , 1

N NTF z z

N z z

=


19/34

Comparison to a Conventional -ADC

Interleaving conventional DSM results in same NTF but quantizationnoise increases

Constant quantization noise level with time-interleaving is aunique property of VCO-based bandpass ADC.

0

|)(| fQN2nd

4th

8th16th

32th

0

|)(| fQN2nd

4th

8th16th

32th

TI VCO-based ADCs TI conventional ADCs



20/34

Behavioral Simulation Results

2009-02-13 20

N=2 N=4

N=16 N=128

Bandstop noise-shaping property is shown.

Increasing the number of channels results in more available bands.

SNR is nearly the same regardless of the number of channels.

CCS Group @ KAIST


21/34

Performance of the Proposed ADC architecture


N = 4

fs= 2GHz

8stage VCO (16phase) with tuningrange of 100MHz - 450MHz

Ideally, more than 10bits can be achieved with less than

10MHz of bandwidth.


22/34

Practical Issues: Effect of Non-Idealities

Issues in VCO-based ADCs

Non-linearity of VCO tuning curve Non-linearity of S/H circuit

Phase noise of sampling clock

Phase noise of VCO

Meta-stability of flip-flops

Backward coupling in VCO (output to input)

Issues in time-interleaved ADCs

Mismatch between sub-ADCs

Timing mismatch (input and clock skew)

Issues in time-interleaved VCO-based ADCs

Coupling between VCOs



23/34

Practical Issues: Non-linearity of S/H & VCO

Non-linearity results in harmonic spurious tones in the output.

Harmonic spurs limit SNDR performance.

Two-tone simulation with non-linearity



24/34

2009-02-13 24

Effect of VCO Phase Noise

0 100 200 300 400 500 600 700 800 900 1000-120

-100

-80

-60

-40

-20

0PSD from CppSim

Frequency [ MHz]

PSD

[dB]

0 100 200 300 400 500 600 700 800 900 1000-140

-120

-100

-80

-60

-40

-20

0PSD from CppSim

Frequency [MHz]

PSD[

dB]

-120 -115 -110 -105 -100 -95 -90 -85 -80 -75 -703

4

5

6

7

8

9

10

11

12

13

Phase noise @ 1MHz offset [dBc/Hz]

ENOB

for10MHzbandwidth[bit]

Assuming power consumption of ~ 1mW,phase noise of -100dBc @ 1MHz ,

fosc=500MHz results in -153dB of FOM.

Ideal VCO VCO with phase noise

Phase noise limits the timing accuracy and hence the resolution of the ADC.

FOM of ~ -150 is easily achievable in todays ring oscillators.

CCS Group @ KAIST


25/34

Effect of Clock Jitter

2009-02-13 25

< 0.1% clock jitter is required for > 10bit performance.

CCS Group @ KAIST


26/34

Metastability and Coupling

Meta-stability of flip-flops Not an issue if the resolution of flip-flops is better than

the time-resolution of VCOs.

Also first-order shaped.

Backward coupling in VCO

VCO output can corrupt its input.

Effect can be minimized if its tuning range of the VCOdoes not overlap with the input frequency range.



27/34

Practical Issues : Mismatch between sub-ADCs

Mismatch between sub-ADCs

One of the performance bottleneck in time-interleaved ADCs Simulated by giving random mismatch in the tuning curves of the VCOs

ENOB degradation due to mismatch

e.g.) 60dB 50dB with 1% mismatch



28/34

Conclusions

Time-interleaved VCO-based ADCs exploiting

time-based signal processing has beenintroduced. RF signals can be digitized in an energy & area efficient manner.

Limitations of the proposed ADC include Timing mismatch, non-linearity, supply noise, phase noise, etc.

Performance can improved with better measurement layout,measurement setup and already established calibrationtechniques.

Time-based signal processing will becomeincreasingly more prevalent in the future



29/34

29/44

References

[1] R. B. Staszewski et al., All-digital TX frequency synthesizer and discrete-time receiver forbluetooth radio in 130-nm CMOS, IEEE J. Solid-State Circuits, vol. 39, pp. 2278-2291, Dec2004.

[2] A. Iwata, N. Sakimura, M. Nagata, and T. Morie, The architecture of delta sigma analog-to-digital converters using a voltage-controlled oscillator as a multibit quan-tizer," IEEE Trans.Circuits Syst. II, vol. 46, pp. 941-945, July 1999.

[3] Y-.G. Yoon et al., A time-based bandpass ADC using time-interleaved voltage-controlledoscillators, IEEE Trans. Circuits Syst. I, vol. 55, no. 11, pp. 3571-3581, Dec 2008

[4] Y.-C. Jenq, Digital spectra of nonuniformly sampled signals : Fundamentals and high-speed

waveform digitizers," IEEE Trans. Instrum. Meas., vol. 37, pp. 245-251, June 1988.[5] J. Lee and B. Kim, "A low-noise fast-lock phase-locked loop with adaptive bandwidth control,"

IEEE J. Solid-State Circuits, vol. 35, pp. 1136-1145, Aug. 2000.

[6] H. Wang, "A 1.8V 3mW 16.8GHz frequency divider in 0.25um CMOS," in IEEE Int. Solid-StateCircuits Conference, Digest of Technical Papers, 2000.

[7] T. Chalvatzis et al., A low-noise 40-GS/s continuous-time bandpass ADC centered at 2 GHzfor direct sampling receivers, IEEE J. Solid-State Circuits, vol. 42, pp. 1065-1075, May 2007.

[8] B. K. Thandri and J. S. Martinez, A 63dB SNR, 75-mW bandpass RF ADC at 950MHz using3.8-GHz clock in 0.25-um SiGe BiCMOS technology, IEEE J. Solid-State Circuits, vol. 42, pp.269-279, Feb 2007.

[9] J. Rychaert et al., "A 2.4GHz 40mW 40dB SNDR/62dB SFDR 60MHz bandwidth mirrored-image RF bandpass ADC in 90nm CMOS," in Proc. of Asian Solid-State CircuitsConference.

2009-02-13 CCS Group @ KAIST


30/34


2005.3~ , 13 students

Research area of interest

PLL : Low-noise low-power frequency synthesis, clock generation& building blocks for wireless applications

ADC: Reconfigurable, ADCs for software radios

Bio-medical circuits: Health care and neuro-science

Communication Circuits & Systems (CCS) Group


31/34

Wireless Transceivers & PLLs

PLL-based transmitter for non-continuous modulation. [Lee, IEEE TCAS2007]


JSSC04

JSSC07

Thiswork

OptimalityTest

X X O

Cal Time 12.6 us 4 us 350 ns

Cycles toCalibrate2n Curves

20.5 n 5 2n n+2

BaseBand

FrequencySynthesizer

DI(t)

DQ(t)

/ 2

FrequencySynthesizer

[Lee, IEEE TCAS2, 07]

Divide-by-2Programmable

dividerDSM

PFD

Vmid

External loop filter

K

REF

2.4~2.5-GHz outputCharge recycling pathSignal

Decoupling

capacitorLevel

Shifter

[Park, Symp. on VLSI 08][Lee, A-SSCC 07]

800uW charge recycling frequency synthesizer [Park, VLSI08]

Low-jitter PLL with fast & accurate frequency calibration. [Lee, A-SSCC07]

Low-noise all digital PLLs


32/34

Building Blocks for PLLs: PVT Immune VCOs


VCO with wide tuning range & immunity to PVT variations [Park, IEEE MTT08]

Design techniques for robust low-voltage VCOs [Park, IEEE MTT09] Charge-recycling VCO & prescaler [Park, IEEE MWCL08]

VDD_digVoltage

BoostingCircuit

VDD

Vout_n Vout_p

VDD_dig

AmplitudeDetector

Vb

Vb

VDD_digboff

Vout_n Vout_p

Vout_n Vout_p

Vout_pVout_n

[Park, ESSCIRC06, IEEE MTT09, IEEE MWCL09]

JSSC 2005 This work

Tech 0. 18-um 0. 18-um

Frequency 3.8 GHz 2.41 GHz

TuningRange

3 % 20 %

Supply 0.5 V 0.5 V 0.43 V

Phase Noise@ 1-MHz

-119 -117.3 -115.6

FoM -193 -190 -191

FoMT -182.5 -196 -197

Area 0.23 mm2

0.31 mm2


33/34

Building Blocks for PLLs: Low Noise VCOs


[Ku, IEEE MWCL08]

N+ P+ N+ N+N+

P-Well

Deep N-Well

N-Well N-Well

P-Substrate

V-NPNC E B E C Vc

[Ku, IEEE MTT06]

Low-noise VCO using parasitic V-NPN [Ku, IEEE MTT06]

Optimum current mirror ratio for VCOs [Park, IEEE MTT09]


34/34

Building Blocks for PLLs: VCO, Divider & DCOs

Multi-modulus injection locked frequency divider [Lee, A-SSCC07]

High resolution DCO using complimentary varactors [Han, EL08]

Self-noise canceling VCO [Cho, EL08]

Input

Output

D1 D2 D3

M1D0

A BD4 D2n D2n+1

Programmable

delay cells

[Lee, A-SSCC07]

Cproposed = CNMOS CPMOS

[Han, EL08]

D

D

VCDL

PD

ICP

C0

vctrlICP

R

D

[Cho, EL08]

atod timedomian2009!02!13 ucb talk

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