28 July 2004

Firmware - Matt Warren 1ATLAS SCT/Pixel TIM FDR/PRR

Physics & AstronomyHEP Electronics

Matthew WarrenJohn Lane, Martin Postranecky

TIM Firmware

ATLAS SCT TIM FDR/PRR28 June 2004

28 July 2004

Firmware - Matt Warren 2ATLAS SCT/Pixel TIM FDR/PRR

General

• Firmware written in VHDL– Maintainable.– Support by almost all hardware.– Used by other collaborators.

• Tools:– Mentor Graphics FPGA Advantage 5.4 – Xilinx ISE 5.2i

• Firmware structured in blocks similar to the old PLD sub-divisions.

• Synchronous design principles followed.

28 July 2004

Firmware - Matt Warren 3ATLAS SCT/Pixel TIM FDR/PRR

FPGA/Code Structure

• FPGA1 is the ‘Manager’– VME Interface– Controls access to local bus– Manages resets– Can re-configure FPGA2’s PROM– Provides status information on FPGA2 etc.

• FPGA2 is the ‘TIM Function’– Front Panel Signals– J3 Backplane Signals– Sequencer RAM, ID FIFO’s are internal

28 July 2004

Firmware - Matt Warren 4ATLAS SCT/Pixel TIM FDR/PRR

TIM-3 Functional Layout

FPGA1

VMEInterface&

BoardManager

Address Bus

ConfigEEPROMFPGA2

Back-PlaneSignals

Front-PanelSignals

TTCrx

VME Control

Data Bus

Base Addr.Preset Switches

31 1532

32

fpga2_reset

spare_bus

Debug ModeSelect Switch

16

Clocks & Clk Control

vme_readvme_select

TriggerWindow

Board ID8 8

Front-PanelLEDs

Internal Trig, FER, ECR

vme_write

4 4

clk

JTAG

FP and POResets

ROD Busy16

ConfigEEPROMFPGA1

Addr(31:1)

Data(31:0)

Debug Header

16

ROD BusyLEDs

16

DebugLEDs

Debug Header

16

DebugLEDs

fpga2_ok

88

jtagx_en

FPGA2

TIMFunction

VMEI/O

MRMW v1.1 01-06-04

28 July 2004

Firmware - Matt Warren 5ATLAS SCT/Pixel TIM FDR/PRR

TIM Hardware for Firmware

• JTAG programmable PROMs used (Xilinx 18V)– FPGAs use Master Serial Mode for loading

• Lower VME Address Bus (15:1) on both FPGAs– Allows local address decoding

• Entire VME data-bus available to both FPGAs.– 32 bit registers if needed

• Debug Hardware (see next slide)

28 July 2004

Firmware - Matt Warren 6ATLAS SCT/Pixel TIM FDR/PRR

Debug/Expansion Features

• 16 line dedicated spare lines between FPGAs.

• 16 line dedicated debug lines per FPGA– Connected to header – logic-analyser access– 8 debug lines/FPGA connected to SMD LEDs

• Mode/Debug hex-switch connected to both

FPGAs– minor changes in operation without downloading

new code (e.g. LEDs map).

• ROD Busy LEDs on front-panel available to code.

• PCB version ID readable by FPGAs

• Enough resources to add extra functions– e.g. Fixed Frequency Veto (more later)

28 July 2004

Firmware - Matt Warren 7ATLAS SCT/Pixel TIM FDR/PRR

FPGA Resource Utilisation

From Xilinx ISE Place & Route Report:

• FPGA1– Number of External GCLKIOBs 1 out of 4 25%– Number of External IOBs 161 out of 285 56%– Number of BLOCKRAMs 4 out of 14 28%– Number of SLICEs 280 out of 2352 11%– Number of DLLs 1 out of 4 25%– Number of GCLKs 1 out of 4 25%– Number of TBUFs 128 out of 2464 5%

• FPGA2– Number of External GCLKIOBs 2 out of 4 50%– Number of External IOBs 244 out of 325 75%– Number of BLOCKRAMs 64 out of 72 88%– Number of SLICEs 1843 out of 6912 26%– Number of DLLs 1 out of 4 25%– Number of GCLKs 1 out of 4 25%– Number of TBUFs 160 out of 7104 2%

28 July 2004

Firmware - Matt Warren 8ATLAS SCT/Pixel TIM FDR/PRR

Outstanding code

• I2C interface to TTCrx– Works on TIM-2, so low priority

• System for re-configuring FPGA2 from

software– Firmware very ‘dumb’ – software will do the

work.

• Finalise Fixed Frequency Trigger Veto System– No big changes – just need iterate over best

style of operation with community.

28 July 2004

Firmware - Matt Warren 9ATLAS SCT/Pixel TIM FDR/PRR

Simulation

• Components Simulated using ModelSim

• Most simulation fast enough to be carried out on the whole FPGA level

• The VME interface was tested across both FPGAs including models of the external bus-transceivers.

• Simulations are controlled via the bus interface.

• Procedures have were written to do bus-like reads/writes. These allowed routines similar to those in the test software to be used.