atj209x program guide v1.4

Copyright 2005 Actions Semiconductor Co., Ltd. All rights reserved.

ATJ209X Product Program Guide

Version 1.4

ATJ209X PROGRAM GUIDE


Ver 1.4 Page 1 2006-10-11

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industrial or intellectual property rights. Actions Semiconductor Co., Ltd. is one of Licensee of Thomson Licensing S.A. and is approved to

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Ver 1.4 Page 2 2006-10-11

Table of Contents 1. Short Description ...................................................................................................................................................1

2. Block Diagram .......................................................................................................................................................2

3. Functions Block......................................................................................................................................................3

3.1 Clock /Bus Controller/DMA/IRQ/CTC .........................................................................................................3 3.1.1 Clock Control..............................................................................................................................................3 3.1.2 Bus Controller.............................................................................................................................................3 3.1.3 DMA Controller..........................................................................................................................................3 3.1.4 CTC Controller ...........................................................................................................................................3 3.1.5 IRQ Controller ............................................................................................................................................3

3.2 USB2.0 SIE .......................................................................................................................................................3 3.2.1 USB Control Registers.............................................................................................................................3 3.2.2 Endpoint Registers ...................................................................................................................................3

3.3 Nand Flash/SMC State Machine ....................................................................................................................4

3.4 MMC/SD Flash Card Controller....................................................................................................................4

3.5 ATA Interface ...................................................................................................................................................4

3.6 I2C Interface ....................................................................................................................................................4

3.7 SPI Interface.....................................................................................................................................................4

3.8 SDRAM Interface ............................................................................................................................................4

3.9 UART and IR Interface...................................................................................................................................5

3.10 Key Scan Interface.........................................................................................................................................5

3.11 SPDIF Interface..............................................................................................................................................5

3.12 ICON LCD 4*20.............................................................................................................................................5

3.13 GPIO and Multifunction Configuration......................................................................................................5

3.14 LOSC/RTC,HOSC/PLL,PMU/DC-DC........................................................................................................6 3.14.1 LOSC/RTC................................................................................................................................................6 3.14.2 HOSC/PLL................................................................................................................................................6 3.14.3 PMU/DC-DC ............................................................................................................................................6

3.15 ADC, DAC and Headphone Driver ..............................................................................................................6

3.16 CMOS Sensor Interface & GPIOK..............................................................................................................6



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4 Register Definition .............................................................................................................................................7

4.00 Register00-- MCU Clock Control Register (BackToFunctionsBlock)....................................................7 4.01 Register01--EM Low Page Register (BackToFunctionsBlock) ...............................................................8 4.02 Register02--EM High Page Register (BackToFunctionsBlock) ..............................................................8 4.03 Register03--EM Page Inc/Dec Register (Back).........................................................................................9 4.04 Register04-- MCU-A15 Control Register (BackToFunctionsBlock).......................................................9 4.05 Register05-- Internal SRAM Page Register (BackToFunctionsBlock).................................................10 4.06 Register06-- DMA1 Source Address 0 Register(Back) ..........................................................................14 4.07 Register07--DMA1 Source Address 1 Register (Back) ..........................................................................14 4.08 Register08--DMA1 Source Address 2 Register (Back) ..........................................................................14 4.09 Register09--DMA1 Source Address 3 Register (Back) ..........................................................................14 4.0A Register0A--DMA1 IPM/IDM/ZRAM2 SRC Address Register(Back) ...............................................14 4.0B Register0B--DMA1 Destination Address 0 Register (Back) .................................................................15 4.0C Register0C--DMA1 Destination Address 1 Register (Back).................................................................15 4.0D Register0D--DMA1 Destination Address 2 Register (Back).................................................................15 4.0E Register0E--DMA1 Destination Address 3 Register(Back) ..................................................................15 4.0F Register0F--DMA1 IPM/IDM/ZRAM2 DST Address Register (Back) ...............................................15 4.10 Register10--DMA1 Byte Counter low Register(Back)...........................................................................16 4.11 Register11--DMA1 Byte Counter High Register(Back).........................................................................16 4.12 Register12--DMA1 Mode Register (Back) ..............................................................................................16 4.13 Register13--DMA1 Command Register(Back).......................................................................................17 4.14 Register14--DMA2 Source Address 0 Register (Back) ..........................................................................18 4.15 Register15--DMA2 Source Address 1 Register (Back) ..........................................................................18 4.16 Register16--DMA2 Source Address 2 Register (Back) ..........................................................................18 4.17 Register17--DMA2 Source Address 3 Register (Back) ..........................................................................18 4.18 Register18--DMA2 IPM/IDM/ZRAM2 SRC Address Register (Back)................................................18 4.19 Register19--DMA2 Destination Address 0 Register(Back)....................................................................19 4.1A Register1A--DMA2 Destination Address 1 Register(Back) ..................................................................19 4.1B Register1B--DMA2 Destination Address 2 Register(Back) ..................................................................19



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4.1C Register1C--DMA2 Destination Address 3 Register(Back)..................................................................19 4.1D Register1D--DMA2 IPM/IDM/ZRAM2 DST Address Register(Back) ...............................................19 4.1E Register1E--DMA2 Byte Count low Register(Back) .............................................................................20 4.1F Register1F--DMA2 Byte Count High Register(Back) ...........................................................................20 4.20 Register20--DMA2 Mode Register(Back)...............................................................................................20 4.21 Register21--DMA2 Command Register(Back).......................................................................................21 4.22 Register22--CTC Prescale Register(Back)..............................................................................................22 4.23 Register23--CTC T Period Low Register(Back) ....................................................................................22 4.24 Register24--CTC T Period High Register(Back)....................................................................................22 4.25 Register25--DMA/CTC IRQ Status Register(Back) ..............................................................................22 4.26 Register26--Master Interrupt Status Register(Back).............................................................................23 4.27 Register27--Master Interrupt Enable Register(Back) ...........................................................................23 4.28 Register28--Flash Controller Nand Enable Register(Back)..................................................................24 4.29 Register29--Flash Controller Address/DMA5 Select Register(Back)...................................................24 4.2A Register2A--Flash COMMAND register(Back) ....................................................................................25 4.2B Register2B --Flash Controller ECC control Register(Back) ................................................................25 4.2C Register2C --User ECC Register0(Back) ...............................................................................................26 4.2D Register2D --User ECC Register1(Back) ...............................................................................................26 4.2E Register2E--DSP Control/Status Register(Back)...................................................................................27 4.2F Register2F--DSP Boot Mode Register(Back) .........................................................................................27 4.30 Register30--DSP HIP Register 0(DATA) (Back).....................................................................................27 4.31 Register31--DSP HIP Register 1(DATA) (Back).....................................................................................27 4.32 Register32--DSP HIP Register 2(DATA) (Back).....................................................................................28 4.33 Register33--DSP HIP Register 3(DATA) (Back).....................................................................................28 4.34 Register34--DSP HIP Register 4(DATA) (Back).....................................................................................28 4.35 Register35--DSP HIP Register 5(DATA) (Back).....................................................................................28 4.36 Register36--DSP HIP Register 6(STATUS) (Back).................................................................................28 4.37 Register37--DSP HIP Register 7(STATUS) (Back).................................................................................28 4.38 Register38--SPDIF Control Register(Back)............................................................................................28



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4.39 Register39--SPDIF Status Register(Back) ..............................................................................................31 4.3A Register3A--SPDIF FIFO DATA Register(Back) ..................................................................................32 4.3B Register3B--SPDIF Channel Status Register (Back).............................................................................32 4.3C Register3C --USB5V VCC Regulator Register (Back) .........................................................................33 4.3E Register3E --USB Internal Resistor Control Register (Back) ..............................................................33 4.3F Register3F --VDD & VCC voltage detect Control Register(Back).......................................................34 4.40 Register40--High frequency crystal control Register(Back) .................................................................35 4.41 Register41--PLL Performance tune Register (Back) .............................................................................35 4.42 Register42-- PLL Control Register (Back) .............................................................................................36 4.43 Register43--RTC Control Register (Back)..............................................................................................38 4.44 Register44--RTC IRQ Status Register (Back) ........................................................................................39 4.45 Register45--RTC Time Low Register (Back)..........................................................................................39 4.46 Register46--RTC Time Middle Register (Back) .....................................................................................39 4.47 Register47--RTC Time High Register (Back).........................................................................................39 4.48 Register48--RTC Alarm Low Register (Back)........................................................................................40 4.49 Register49--RTC Alarm Middle Register (Back)...................................................................................40 4.4A Register4A--RTC Alarm High Register (Back) .....................................................................................40 4.4B Register4B--Losc Divider Low Byte Register (Back) ............................................................................40 4.4C Register4C--Losc Divider Middle Byte Register (Back).......................................................................40 4.4D Register4D--Losc Divider High Byte Register (Back)...........................................................................40 4.4E Register4E--Watch Dog Register (Back) ................................................................................................40 4.4F Register4F --DC to DC Control Register (Back)....................................................................................41 4.50 Register50 --USB FIFO Control Register (Back)...................................................................................42 4.51 Register51USB DMA6 Control Register (Back) ................................................................................42 4.52 Register52USB Interrupt Status0 Register (Back).............................................................................43 4.53 Register53USB Interrupt Status1 Register (Back).............................................................................43 4.54 Register54USB Interrupt Enable0 Register(Back) ............................................................................44 4.55 Register55USB Interrupt Enable1 Register(Back) ............................................................................44 4.56 Register56--USB Control Register(Back) ...............................................................................................44



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4.57 Register57--USB Status Register(Back) ..................................................................................................45 4.58 Register58--Endpoint Index Register(Back) ..........................................................................................45 4.59 Register59--Endpoint Configuration Register(Back) ............................................................................46 4.5A Register5A--Endpoint Control Register(Back) .....................................................................................46 4.5B Register5B--Endpoint Status Register(Back) ........................................................................................47 4.5C Register5C --Endpoint Interrupt Request Register(Back)...................................................................48 4.5D Register5D --Endpoint Interrupt Enable Register (Back) ...................................................................48 4.5E Register5E --Endpoint MaxPacketSize0 Register(Back)......................................................................48 4.5F Register5F --Endpoint MaxPacketSize1 Register (Back)......................................................................49 4.60 Register60 --Endpoint Data Register (Back) ..........................................................................................49 4.61 Register61 --Endpoint Byte Count0 Register (Back) .............................................................................49 4.62 Register62 --Endpoint Byte Count1 Register (Back) .............................................................................49 4.63 Register63 --Endpoint Transfer Count0 Register (Back) ......................................................................49 4.64 Register64 --Endpoint Transfer Count1 Register (Back) ......................................................................50 4.65 Register65 --Endpoint Transfer Count2 Register (Back) ......................................................................50 4.66 Register66--USB Register Page Index (Back).........................................................................................50 4.67 Register67--Device Address Register (Back) ..........................................................................................51 4.68 Register68--USB Test Modes Register (Back) ........................................................................................51 4.69 Register69--Frame Number0 Register (Back)........................................................................................51 4.6A Register6A--Frame Number1 Register (Back) ......................................................................................51 4.70 Register70 --MCU & DMA Clock Control Register (Back) ..................................................................51 4.71 Register71 --I2C Address Register (Back) ..............................................................................................52 4.72 Register72 --UART2Sharp IR and SIR Baud Rate Register (Back) ................................................53 4.73 Register73--UART2 control Register(Back)...........................................................................................54 4.74 Register74--UART2/IR FIFO DATA Register(Back) ............................................................................55 4.75 Register75--IR Control Register(Back) ..................................................................................................55 4.77 Register77 --LRADC2 DATA Register(Back) ........................................................................................56 4.78 Register78--UART2 Mode & FIFO Status Register(Back) ...................................................................56 4.79 Register79--UART2 DRQ/IRQ Enable/Status Register(Back) .............................................................57



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4.7A Register7A-- I2C Control Register(Back) ..............................................................................................57 4.7B Register7B--I2C Status Register (Back) .................................................................................................59 4.7C Register7C --I2C Data Register(Back)...................................................................................................60 4.7D Register7D --SPI Control Register(Back) ..............................................................................................60 4.7E Register7E --SPI Clock Divide Control Register(Back) .......................................................................61 4.7F Register7F --SPI Data Register(Back) ....................................................................................................61 4.80 Register80 --DAC Control Register(Back) .............................................................................................61 4.81 Register81 --DAC Sample Rate Control Register(Back).......................................................................62 4.82 Register82 --Internal DAC PCM Out Lo Register(Back) .....................................................................63 4.83 Register83 --Internal DAC PCM Out Middle Register(Back)..............................................................63 4.84 Register84 --Internal DAC PCM Out High Register(Back) .................................................................63 4.85 Register85 --FIFO Status Register(Back) ...............................................................................................64 4.86 Register86 --Internal DAC Dither Control Register(Back) ..................................................................64 4.87 Register87--Internal DAC Analog Output Volume Control Register (Back) ......................................65 4.88 Register88--Internal DAC Analog Block Control Register (Back).......................................................65 4.89 Register89 USB DMA6 Address0 Register (Back) ...............................................................................65 4.8A Register8A USB DMA6 Address1 Register (Back)..............................................................................66 4.8B Register8B USB DMA6 Clock Register (Back) ...................................................................................66 4.8C Register8C --USB Global Control Register (Back) ...............................................................................66 4.8D Register8D--DMA4 Control and Status Register (Back) ......................................................................68 4.8E Register8E--GPIOK[7..0] Input and Output Enable (Back)................................................................68 4.8F Register8F--GPIOK[7..0] Data Register (Back) ....................................................................................69 4.90 Register90--ITU-R601 XY Data Register (Back) ...................................................................................69 4.91 Register91--DMA4 Destination Address high (Back) ............................................................................69 4.92 Register92--Cmos Sensor Control Register (Back)................................................................................69 4.93 Register93--Hsync Start Position Low(in pclk) (Back)..........................................................................70 4.94 Register94--Hsync Start & End Position High(in pclk) (Back) ............................................................70 4.95 Register95--Hsync End Position Low(in pclk) (Back) ...........................................................................70 4.96 Register96--Vsync Start Position Low(in Hsync) (Back).......................................................................70



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4.97 Register97--Vsync Start & End Position High(in Hsync) (Back) .........................................................70 4.98 Register98--Vsync End Position Low(in Hsync) (Back) ........................................................................71 4.99 Register99--DMA4 Destination Address Low (Back) ............................................................................71 4.9A Register9A--AUDIO ADC data register (Back).....................................................................................72 4.9B Register9B--Audio ADC Control Register 0 (Back)..............................................................................72 4.9C Register9C --BATTERY ADC DATA Register (Back) ..........................................................................72 4.9D Register9D --External input I2S DATA Register(Back) .......................................................................74 4.9F Register9F--Audio ADC modulator performance tuning register (Back) ...........................................74 4.A0 RegisterA0-A7 ATA Decode Registers (Back)........................................................................................75 4.A8 RegisterA8--DMA66 Destination/Source Address0(Back) ...................................................................76 4.A9 RegisterA9--DMA66 Destination/Source Address1(Back) ...................................................................76 4.AA RegisterAA--DMA66 Destination/Source Memory Select(Back)........................................................76 4.AB RegisterAB--DMA66 Byte Counter Low Register(Back) ....................................................................77 4.AC RegisterAC--DMA66 Byte Counter High Register(Back)...................................................................77 4.AD RegisterAD-- Serial LCM Control Register(Back) ..............................................................................79 4.AE RegisterAE--DMA3 Byte Counter Hi Register(Back) ......................................................................79 4.B0 RegisterB0 --SDRAM TYPE REGISTER (Back) .................................................................................79 4.B1 RegisterB1 --SDRAM COMMAND REGISTER (Back)................................................................79 4.B2 RegisterB2--SDRAM ADDRESS 2 (Back)..........................................................................................80 4.B3 RegisterB3--SDRAM ADDRESS 1 (Back)..........................................................................................80 4.B4 RegisterB4--SDRAM ADDRESS 0 (Back)..........................................................................................80 4.B5 RegisterB5--SDRAM Control Register (Back) ...................................................................................80 4.B6 RegisterB6--DMA3 SRAM ADDRESS LOW (Back) ........................................................................81 4.B7 RegisterB7--DMA3 SRAM ADDRESS HI (Back)..............................................................................81 4.B8 RegisterB8--DMA3 COUNTER LOW BYTE (Back) ........................................................................81 4.B9 RegisterB9--DMA3 MODE(Back) ..........................................................................................................81 4.BA RegisterBA--DMA3 Command Register(Back)....................................................................................82 4.BC RegisterBC-- DMA66 Control /Status Register (Back)........................................................................87 4.BD RegisterBD--ATA Config Register (Back) .............................................................................................88



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4.BE RegisterBE--Battery charger Control Register (Back) ........................................................................88 4.BF RegisterBF --Battery charger Status Register (Back)...........................................................................89 4.C0 RegisterC0--Key Scan Data Register (Back) .........................................................................................89 4.C1 RegisterC1--Key Scan Control Register (Back) ....................................................................................90 4.C2 RegisterC2--LCD Data0 Register(Back)................................................................................................91 4.C3 RegisterC3--LCD Data1 Register(Back)................................................................................................92 4.C4 RegisterC4--LCD Data2 Register(Back)................................................................................................92 4.C5 RegisterC5--LCD Data3 Register(Back)................................................................................................92 4.C6 RegisterC6--LCD Data4 Register(Back)................................................................................................92 4.C7 RegisterC7--LCD Data5 Register(Back)................................................................................................92 4.C8 RegisterC8--LCD Data6 Register(Back)................................................................................................92 4.C9 RegisterC9--LCD Data7 Register(Back)................................................................................................93 4.CA RegisterCA--LCD Data8 Register(Back) ..............................................................................................93 4.CB RegisterCB--LCD Data9 Register(Back) ..............................................................................................93 4.CC RegisterCC --Flash ECC Register0(Back)............................................................................................93 4.CD RegisterCD --Flash ECC Register1(Back)............................................................................................93 4.CE RegisterCE --Flash ECC Register2(Back) ............................................................................................94 4.CF RegisterCF --Flash ECC Register3(Back) .............................................................................................94 4.D0 RegisterD0 --BAT ADC and LRADC1/LRADC2 Control and Status Register (Back) .....................95 4.D1 RegisterD1--BATTERY ADC Control and Touch Panel Sense Period Select Register (Back) .........95 4.D2 RegisterD2--Touch Panel Enable and Scan Period Select Register (Back).........................................96 4.D3 RegisterD3--Audio ADC performance tuning register(Back)..............................................................96 4.D4 RegisterD4--Audio ADC First Control Register (Back) .......................................................................97 4.D5 RegisterD5--Audio ADC Second Control Register(Back) ....................................................................97 4.D6 RegisterD6--Analog Input Gain Control Register(Back) .....................................................................98 4.D7 RegisterD7--Audio ADC FIFO control register(Back) .........................................................................99 4.D8 RegisterD8--LRADC1 data Register (Back)..........................................................................................99 4.D9 RegisterD9--Touch Panel X Position Data Low Byte Register(Back) ...............................................100 4.DA RegisterDA--Touch Panel X Position Data High Byte Register(Back) .............................................100



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4.DB RegisterDB--Touch Panel Y Position Data Low Byte Register(Back) ..............................................100 4.DC RegisterDC--Touch Panel Y Position Data High Byte Register (Back) ............................................100 4.DE RegisterDE--Touch Panel ADC IRQ Control and Status Register (Back) .......................................100 4.DF RegisterDF --Power Control Register (Back)......................................................................................101 4.E0 RegisterE0 --SD control register1 (Back).............................................................................................102 4.E1 RegisterE1--SD control register2 (Back)..............................................................................................102 4.E2 RegisterE2--CMD/RSP register (Back) ................................................................................................103 4.E3 RegisterE3--CRC7 calculation result register (Back) .........................................................................103 4.E4 RegisterE4--Data in/out register (R/W) (E4h) (Back)......................................................................103 4.E5 RegisterE5--CRC16 calculation result register high (Back)...............................................................103 4.E6 RegisterE6--CRC16 calculation result register low (Back) ................................................................103 4.E7 RegisterE7--SD Status Register (Back) ................................................................................................104 4.E8 RegisterE8-- RS E(x) FIFO Register (Back) ........................................................................................104 4.E9 RegisterE9-- RS ECC Register(Parity Symbols FIFO) (Back) ..........................................................105 4.EA RegisterEA--ECC4 TEST(ECC4 TEST Register, 0EAh) (Back) ......................................................105 4.EB RegisterEB --R-S ECC Status/Control Register(Back) ......................................................................107 4.EC RegisterECUSB VBUS Control Register (Back) ............................................................................ 113 4.EE RegisterEE--MFP Select/GPO_A[2:0] Data Output Register (Back) ............................................... 113 4.EF RegisterEF--GPIO_B[7:0] and KEYI/O[3:0] Config Register(Back) ............................................... 116 4.F0 RegisterF0--GPIO_B[7:0] Output Enable Register (Back) ................................................................ 116 4.F1 RegisterF1--GPIO_B[7:0] Input Enable Register (Back) ................................................................... 117 4.F2 RegisterF2--GPIO_B[7:0] Data Output/Input Register (Back) ......................................................... 117 4.F3 RegisterF3--GPIO_C[3:0] Output/Input Enable Register (Back) ..................................................... 117 4.F4 RegisterF4--GPIO_C[3:0] Data Output/Input Register (Back) ......................................................... 118 4.F5 RegisterF5--GPIO_D[5:0] Output Enable Register (Back) ................................................................ 118 4.F6 RegisterF6--GPIO_D[5:0] Input Enable Register (Back)................................................................... 118 4.F7 RegisterF7--GPIO_D[5:0] Data Output/Input Register(Back) .......................................................... 119 4.F8 RegisterF8--GPIO_E[7:0] Output Enable Register(Back) ................................................................. 119 4.F9 RegisterF9--GPIO_E[7:0] Input Enable Register (Back) ................................................................... 119



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4.FA RegisterFA--GPIO_E[7:0] Data Output/Input Register (Back) ........................................................ 119 4.FB RegisterFB--GPIO_F[7:0] Output Enable Register (Back) ...............................................................120 4.FC RegisterFC--GPIO_F[7:0] Input Enable Register (Back)..................................................................120 4.FD RegisterFD--GPIO_F[7:0] Data Output/Input Register (Back)........................................................120 4.FE RegisterFE--GPIO_G[3:0] Output/Input Enable Register (Back)....................................................120 4.FF RegisterFF--GPIO_G[3:0] Data Output/Input Register(Back) .........................................................121

5. Abbreviation.......................................................................................................................................................122



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Revision History

Version Date Description

Ver1.0 Feb, 2005 1st version created Ver1.1 May, 2005 2nd version, file format modified Ver1.2 Jun, 2005 Battery adc typic value in different mode added Ver1.3 July, 2005 Some content modified Ver1.4 Oct2006 Some content modified



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1. Short Description

ATJ209X is a third generation single-chip highly-integrated digital music system solution for devices

such as dedicated audio players, PDAs, and cell phones. It includes an audio decoder with a high

performance DSP with embedded RAM and ROM, ADPCM record capabilities and USB interface for

downloading music and uploading voice recordings. ATJ209X also provides an interface to SPDIF, flash

memory, LED/LCD, button and switch inputs, headphones, microphone and FM radio input and control.

ATJ2095/2097/2099 contains a high performance DSP, which can easily be programmed to support many

kinds of digital audio standards such as MP3,WMA,ect. For devices like USB-Disk, ATJ209X can act as a

USB mass storage slave device to personal computer system. ATJ209X has low power consumption to

allow long battery life and an efficient flexible on-chip DC-DC converter that allows many different battery

configurations, including 1xAA, 1xAAA, 2xAA,2xAAA and Lilon. The built-in Sigma-Delta DAC include a

headphone driver to directly drive low impedance headphones. The ADC include inputs for both

Microphone and Analog Audio in to support voice recording and FM radio integration features. ATJ209X

provides a true ALL-IN-ONE solution that is ideally suited for highly optimized digital audio players.



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2. Block Diagram

ZRAM1 MCU

IO Register

(two bank)

IPM/IDM(24-bit)

DSP

PMU

(Power

Management

Unit)

USB

FLASH

ATA UDMA/66

SDRAM

ADC

DAC

I2C

SPI

GPIO

DMA Controller

&Arbiter

CMU(Clock)

Supply Monitor Charger

EM

NAND Chip MMC/SDC

ATA/SDRAM

Bridge

DMA BUS(Peripheral DMA path)

MCU BUS(include DMA1/2 path)

CMOS Sensor

480MHz

33MHz

66MHz

66MHz

Fs=48K

Fs=48K

400KHz

12MHz

100KHz

48MHz



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3. Functions Block

3.1 Clock /Bus Controller/DMA/IRQ/CTC 3.1.1 Clock Control Clock control includes Register00 , Register70

3.1.2 Bus Controller Bus Controller includes RegisterA0, Register01, Register02, Register03, Register04, Register05

six registers.

3.1.3 DMA Controller

DMA1 and DMA2 controller includes 16 registers from Register05 to Register21.

3.1.4 CTC Controller CTC controller includes Register22, Register23, Register24 3 registers.

3.1.5 IRQ Controller IRQ Controller includes Register25, Register26, Register27 3 registers.

3.2 USB2.0 SIE

3.2.1 USB Control Registers USB control registers include Register3E, RegisterEC, Register89~Register8C, Register50~

Register57, Register66~ Register69 , totally 18 registers.

3.2.2 Endpoint Registers Endpoint Registers include Register58~Register65 , totally 14 registers.



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3.3 Nand Flash/SMC State Machine Nand flash/Smc state machine registers include Register28 ~ Register2D, RegisterCC ~ RegisterCF,

RegisterEB, RegisterE8, RegisterE9, RegisterEA.

3.4 MMC/SD Flash Card Controller

MMC/SD flash card controller registers include SD status register RegisterE7, SD control

register1 RegisterE0, SD control register2 RegisterE1, CMD/RSP register RegisterE2, CRC7

calculation result register RegisterE3, Data in/out register RegisterE4, CRC16 calculation result

register RegisterE5 and RegisterE6.

3.5 ATA Interface

ATA interface includes registersATA cnfig register RegisterBD, DMA66 control /status register

RegisterBC, ATA decode registers RegisterA0~RegisterA7, DMA66m destination/source address

registers RegisterA8 and RegisterA9, DMA66 destination/source memory select register RegisterAA,

DMA66 byte counter register RegisterAB and RegisterAC.

3.6 I2C Interface

I2C Interface includes registers-- I2C control register Register7A, I2C status register Register7B,

I2C address register Register71, I2C data register Register7C.

3.7 SPI Interface

SPI Interface registers include SPI control register Register7D, SPI clock divide control

register Register7E, SPI data register Register7F.

3.8 SDRAM Interface

SDRAM Interface registers include SDRAM type register RegisterB0, SDRAM command



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register RegisterB1, SDRAM address registers RegisterB2, RegisterB3 and RegisterB4, SDRAM

control register RegisterB5, DMA3 SRAM address RegisterB6 and RegisterB7, DMA3 byte counter

low register RegisterB8, DMA3 byte counter high register RegisterAE, DMA3 command register

RegisterBA

3.9 UART and IR Interface

UART and IR interface includes registers UART2Sharp IR and SIR baud rate register,

Register72, UART2 control register Register73, UART2/IR FIFO data register Register74, UART2

Mode & FIFO status register Register78, UART2 DRQ/IRQ Enable/Status register register79, IR

Control Register register75.

3.10 Key Scan Interface

Key Scan Interface includes registers key scan data register RegisterC0, key scan control

register RegisterC1,

3.11 SPDIF Interface

SPDIF Interface includes registers SPDIF control register Register38, SPDIF status register

Register39, SPDIF FIFO data register Register3A, SPDIF channel status Register Register3B.

3.12 ICON LCD 4*20 ICON LCD 4*20 includes data registers RegisterC2~ RegisterC9.

3.13 GPIO and Multifunction Configuration GPIO and multifunction configuration includes registers MFP Select/GPO_A[2:0] data output register RegisterEE, GPIO_B[7:0] and KEYI/O[3:0] config register RegisterEF and other GPIO control/enable/data registers from RegisterF0 to RegisterFF.



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3.14 LOSC/RTC,HOSC/PLL,PMU/DC-DC

3.14.1 LOSC/RTC This block includes register Register43 ~ register4E.

3.14.2 HOSC/PLL This block include register Register40 ~ register42.

3.14.3 PMU/DC-DC This block includes battery charger control register RegisterBE, battery charger status register

RegisterBF, USB5V VCC regulator register Register3C, VDD & VCC voltage detect control register

Register3F, DC To DC Control Register Register4F, ADC control and status register RegisterD0, battery

ADC data register Register9C, LRADC2 data register Register77, power control register RegisterDF

3.15 ADC, DAC and Headphone Driver

This block includes DAC control register Register80, External I2S input data register Register9D,

DAC control register Register81 ~ Register88, AUDIO ADC data register register9A, Battery

ADC/LRADC1 control & touch panel sense period select register RegisterD1, touch panel enable and

scan period select register RegisterD2 , audio ADC performance tuning register RegisterD3, audio ADC

modulator performance tuning register Register9F, audio ADC first and second control register

RegisterD4 and RegisterD5, analog input gain control register RegisterD6, audio ADC FIFO control

registerD7, audio ADC fs control register Register9B, LRADC1 data register RegisterD8, touch panel

position data register RegisterD9 ~ RegisterDC, TPADC IRQ control and status register RegisterDE.

3.16 CMOS Sensor Interface & GPIOK

This block includes registers Register8D ~ Register99.



Ver 1.4 Page 7 2006-10-11

4 Register Definition

4.00 Register00-- MCU Clock Control Register (BackToFunctionsBlock) It may take a while before MCU Clock Changes. When the MCU clock is stopped (DC, or Standby

mode), there are several ways to recover the clock to non-divided LOSC clock source: 1. Push Reset button

2. POWER ON RESET

3. Key Board IRQ

4. Alarm IRQ

5. SIRQ

6. Touch Panel IRQ

7. USB wake up IRQ

Bits Description Access Reset

7:6

Number of Wait states for external memory access 0 0: 0, zero wait state (default) 0 1: 1, one wait state 1 0: 2, two wait states 1 1: 3, three wait states

R/W 00

5:4

MCU clock source select 0 0: LOSC (Low frequency oscillator) 0 1: HOSC (High frequency oscillator) 1 0: MCU PLL (Phase Locked Loop) 1 1: reserved

R/W 00



Ver 1.4 Page 8 2006-10-11

3

External Bus Width.0:8-bit, 1: 16-bit. If this bit is 1, the bus width is 16 bits when it operates external

hardware. It is used by MCU or DMA. When MCU/DMA writes or reads, it just needs writing to IOA0h or reading from IOA0h. When reading, read low byte first, then high byte. When writing, write low byte first, then high byte. These operations only send MRD-, MWR-, D[15..0], the external hardware chip enable signals need to be enabled by software. For example:

16Bit NAND Flash can use old-mode. 16Bit Color LCD can use GPIO port as chip enable signal.

RW 0

2:0

MCU clock division control 0 0 0 /1(default) 0 0 1 /2 0 1 0 /4 0 1 1 /8 1 0 0 /16 1 0 1 /32 1 1 0 /64 1 1 1 DC

R/W 000

4.01 Register01--EM Low Page Register (BackToFunctionsBlock) Bits Description Access Reset

7:0 Extended page address bits, for EMA22-15 R/W 0 NOTE: EM-External Memory

4.02 Register02--EM High Page Register (BackToFunctionsBlock) Bits Description Access Reset

7 Software reset. Write 1 to this bit will reset system, after resetting it will be cleared. its operation is equal to external reset- pin.

R/W 0

6 Software reset flag. 0: software reset not occured,1:software reset occurred. Writing 1 to this bit will clear it.

R/W 0



Ver 1.4 Page 9 2006-10-11

5:0

Extended page address bits, for EMA28-23 EMA28, 27,26=000B, decode to CE0-

001B, decode to CE1- 010B, decode to CE2- 011B, decode to CE3- 1XXB, reserved

R/W 000000

NOTE: CE0- is just for MROM/NorFlash/Sram, CE1/2/3- can be used for Nand Flash or others except MROM.

4.03 Register03--EM Page Inc/Dec Register (Back) Bits Description Access Reset

7:0 2s complement to add to page address NewReg02h*256+NewReg01h=OldReg02h*256+OldReg01h+Reg03h W 0

4.04 Register04-- MCU-A15 Control Register (BackToFunctionsBlock) Bits Description Access Reset

7 Watch Dog Flag, 1 means WD reset or irq ever occurred, writing 1 to this bit will clear it. R/W 0

6 External Reset flag, 1 means external reset had been asserted, writing 1 to this bit will clear the bit.

R/W 0

5

Low Bat NMI- pending. The LBNMI- voltage can be set by the regDF If LBNMI- occurred , this bit will be set . Writing 1 to this bit will clear it. if VbatMonLBD, circuit should release SysReset- and wake up MCU again.

R/W 0

4:3

DMA clock source select 0 0 LOSC 0 1 HOSC 1 0 MCU PLL 1 1 DC=Low level

R/W 00

2 SIRQ- enable. 0:disable, 1: enable. R/W 0

1 LBNMI- Enable. 0: disable , 1: enable. R/W 0



Ver 1.4 Page 10 2006-10-11

0

A15 control bit. 0 force MCUs A15 to be 1, execute program from CE0 memory

space 1 for normal operation. The boot code after power on reset must jump 800xh followed by an IO write to 04h to set this bit for normal operation.

R/W 0

4.05 Register05-- Internal SRAM Page Register (BackToFunctionsBlock)

16KB

ZRAM116KB-64

32KB

IPMM16KB

IPML16KB

IDMH16KB

IDMM16KB

IDML16KB

IPMH16KB

BANK0(32KB)BANK1(32KB)

BANK2(32KB)

BANK3(32KB)

......

BANK..(32KB)

EntendedMemorySpace

(MCU.A15=1)

InternalMemorySpace

(MCU.A15=0)

MCU 64KB Memory Space

0000H

8000H

FFFFH

ZRAM2(3+3)KB

Brom

Trom

URAM2k+256

If IA15=0 -> mapped to internal Memory

If IA14=0, mapped to internal ZRAM16K-64 ZRAM1

If IA14=1, mapped to internal DSP IPM/IDM when they are mapped into MCU memory space 3

extended address bits of a IO mapped register (Mapped at registered are used to decode the access to one of these memory blocks



Ver 1.4 Page 11 2006-10-11

Bit 2 1 0 Accessed Block

0 0 0 IPM low byte

0 0 1 IPM middle byte

0 1 0 IPM high byte

0 1 1 reserved

1 0 0 IDM low byte

1 0 1 IDM middle byte

1 1 0 IDM high byte

1 1 1 ZRAM2 B1+B2

Since IPM/IDM is mapped to MCU memory space per 8K block, IA13 is used to select low/high

block of 8K bytes in each 16K byte block.

If IA15=1 -> Extended address bits are IO mapped at 01h and 02h for EMA15-28. EMA15-25 are

output as address bus, while the EMA26-28 are used to decode CE0- ~ CE3-.

CE0- is used to access boot code from ROM/MASK/NOR- type Flash.

CE1- to CE3- can be configured to access ROM, or RAM or NAND-type Flash.

ATJ209Xs internal MCU MROM/SRAM memory mapping:

1) (16K-64) byte ZRAM1(IA15=0,IA14=0): 0000H-3FBFH 2) 6Kbyte ZRAM2 (IA15=0, IA14=1, IOReg05.[2:0]=111): 4000H-57FFH 3) (2K+256) byte URAM: 5800H-60FFH it has synchronization and asynchronism accessing

mode.

4) 12Kbyte BROM (IA15=1,Reg02=00h, Reg01=00h): 8000h-AFFFh 5) 21Kbyte g1 (IA15=1,Reg02=00h,Reg01=02h): 8000h-D3FFh 6) 17Kbyte TROM2 (IA15=1,Reg02=00h,Reg01=03h): 8000h-C400h

ATJ209Xs internal DSP IPM/IDM memory mapping:



Ver 1.4 Page 12 2006-10-11

1) 16K x24bit IPM SRAM: 0000H-3FFFH 2) 16K x24bit IDM SRAM : 0000H-3FFFH

ATJ209Xs internal DSP IPM/IDM memory mapping accessed by MCU:

1) 16K x3 byte IPM SRAM: 4000H-7FFFH 2) 16K x3 byte IDM SRAM : 4000H-7FFFH

(Hi/Mid/Low Byte Select and Mapping Mode controlled by IOReg05)

DMA Mode Notes:

1: When DMA1 and DMA2 are active, MCU will halt, and DMA1 and DMA2 have priority.

2: DMA3, DMA4, FLASHDMA or USB DMA is active, MCU will not halt.

ZRAM1 and ZRAM2 Notes:

Input: A[13:0], ID[7:0], ZRAMRD-, ZRAMWR- Output: RD[7:0] (Tri-state) Speed: max read time 30 ns from ZRAMRD- going low

Power consumption: stand by when both WR- and RD- are inactive, access current

as low as possible.

ZRAM2 is compose of B1 and B2 each of them is 2k*8 byte SRAM.B1 ,B2 and ZRAM1(B0) can be operated independently. It has the following modes:

1) MCU running at B0, while DMA[M] read B1 and DMA[N] write B2.B1 and B2 are vise versa. M=1, 2, 3, 4, 5, 6, 66; N=1, 2, 3, 4, 5, 6, 66; M!=N.

2) MCU running at B0+B1+B2 or B0+B1 or B0+B2. IPM and IDM Notes:

Power consumption: stand by when both WR- and RD- are inactive, access current is as low as possible.

PM/DM can be visited by MCU, DSP, DMA1, DMA2, DMA3, DMA4, DMA5 and DMA66 .When DSP visits

low or high bytes of 8Kbytes, MCU/DMA1~5/DMA66 can visit high or low bytes of 8Kbytes at the same



Ver 1.4 Page 13 2006-10-11

time.

ISRAMP (Internal SRAM Page Register, 05h) Bits Description Access Reset

7 0: low 8K block of IPM is mapped to DSP, 1: low 8K block of IPM is mapped to MCU/DMA[N] R/W 0

6 0: hi 8K block of IPM is mapped to DSP, 1: hi 8K block of IPM is mapped to MCU/DMA[N] R/W 0

5 0 low 8K block of IDM is mapped to DSP, 1 low 8K block of IDM is mapped to MCU/DMA[N] R/W 0

4 0 hi 8K block of IDM is mapped to DSP, 1 hi 8K block of IDM is mapped to MCU/DMA[N] R/W 0

3 Watchdog IRQ or Reset- Select.0:reset-,1:irq. 0when watchdog timeout, it send Reset- signal. 1when watchdog timeout, it send Irq signal.

R/W 0

2:0

Extended IPM/IDM page address bit. 0 0 0 IPM low byte 0 0 1 IPM middle byte 0 1 0 IPM high byte 0 1 1 reserved 1 0 0 IDM low byte 1 0 1 IDM middle byte 1 1 0 IDM high byte

1 1 1 B1+B2+URAM B1: 4000H-4BFFH B2: 4C00H-57FFH URAM: 5800H-60FFH

R/W 000

In DMA[N], N=1, 2, 3, 4, 5, 6, 66. The following list is register05 data in different condition.

WHEN DSP ACCESS WHEN MCU ACCESS Low 8k 0XXXX010B 1XXXX010B

IPMH High 8k X0XXX010B X1XXX010B Low 8k 0XXXX001B 1XXXX001B

IPMM High 8k X0XXX001B X1XXX001B Low 8k 0XXXX000B 1XXXX000B

IPML High 8k X0XXX000B X1XXX000B Low 8k XX0XX110B XX1XX110B

IDMH High 8k XXX0X110B XXX1X110B



Ver 1.4 Page 14 2006-10-11

Low 8k XX0XX101B XX1XX101B IDMM

High 8k XXX0X101B XXX1X101B Low 8k XX0XX100B XX1XX100B

IDML High 8k XXX0X100B XXX1X100B

4.06 Register06-- DMA1 Source Address 0 Register(Back) Bits Description Access Reset

7:0 DMA1SA[7:0] R/W X

4.07 Register07--DMA1 Source Address 1 Register (Back) Bits Description Access Reset

7:0 DMA1SA[15:8] R/W X


7 DMA1 Source DSP Mode Select. 0:normal, 1:DSP mode. R/W x

6:0 DMA1SA[22:16] R/W xxxxxxx


7 External Memory Select, 0 selects Int.Memory, 1 selects external memory R/W x

6 Int.Memory select, 0 selects ZRAM, 1 selects IPM/IDM/ZRAM2 R/W x

5 Reserved. / /

4:0 DMA1SA[28:24] R/W xxxxx

4.0A Register0A--DMA1 IPM/IDM/ZRAM2 SRC Address Register(Back) Bits Description Access Reset

7:3 Reserved / /

2:0 DMA1ISA[2:0] these bits should be set the same as R05h_2:0 if IPM/IDM/ZRAM2 is selected. R/W xxx

NOTE: SRCsource



Ver 1.4 Page 15 2006-10-11

4.0B Register0B--DMA1 Destination Address 0 Register (Back) Bits Description Access Reset

7:0 DMA1DA[7:0] R/W X

4.0C Register0C--DMA1 Destination Address 1 Register (Back) Bits Description Access Reset

7:0 DMA1DA[15:8] R/W X

4.0D Register0D--DMA1 Destination Address 2 Register (Back) Bits Description Access Reset

7:0 DMA1DA[23:16] R/W X

4.0E Register0E--DMA1 Destination Address 3 Register(Back) Bits Description Access Reset

7 External Memory Select, 0: Int.Memory, 1: external memory R/W x

6 Int.Memory select, 0: ZRAM, 1: IPM/IDM/ZRAM2 R/W x

5 Reserved / /

4:0 DMA1DA[28:24] R/W xxxxx

4.0F Register0F--DMA1 IPM/IDM/ZRAM2 DST Address Register (Back) Bits Description Access Reset

7:3 Reserved / /



Ver 1.4 Page 16 2006-10-11

2:0

DMA1IDA[2:0]. 0 0 0 IPML 0 0 1 IPMM 0 1 0 IPMH 0 1 1 reserved 1 0 0 IDML 1 0 1 IDMM 1 1 0 IDMH 1 1 1 ZRAM2(B1+B2+URAM)

R/W xxx

NOTE: DST-- Destination

4.10 Register10--DMA1 Byte Counter Low Register (Back) Bits Description Access Reset

7:0 DMA1IDA[7:0] R/W X

4.11 Register11--DMA1 Byte Counter High Register (Back) Bits Description Access Reset

7 Reserved / /

6:0 DMA1BC[14:8] Maximum byte transferred is 32Kbytes R/W xxxxxxx

4.12 Register12--DMA1 Mode Register (Back) Bits Description Access Reset

7:6

DMA1 wait state select 0 0 0 wait state 0 1 1 wait state 1 0 2 wait states 1 1 3 wait states

R/W 00

5 DMA1 Destination DSP transfer mode 0: linear mode, 1: DSP mode, it is used when transmitting DSP code or data.

R/W 0

4 DMA1 DST down count, 0: up count (default), 1: down count R/W 0

3 DMA1 SRC down count, 0: up count(default), 1: down count R/W 0



Ver 1.4 Page 17 2006-10-11

2 DMA1 for DSP BOOT, 0: normal, 1: DSP BOOT R/W 0

1 DMA1 DST is IO. 0 : Memory 1: IO .When DMA DST is IO, usually the IO is a FIFO or other array, the IO address will not increase or decrease. R/W 0

0 DMA1 SRC is IO. 0 : Memory 1: IO .When DMA SRC is IO, usually the IO is a FIFO or other array, the IO address will not increase or decrease. R/W 0

4.13 Register13--DMA1 Command Register (Back) Bits Description Access Reset

7

DMA1 TC IRQ enable. 0 disables IRQ. 1 enables IRQ when DMA1 finishes the whole block transfer. TC: Transmit complete.

R/W 0

6 DMA1 Half Transfer IRQ enable. 0 disables IRQ. 1 enables IRQ when DMA1 finishes half of the defined block transfer.

R/W 0

5

DMA1 Continue Block Transfer enable. 0 disables the continuous block transfer mode and Bit 1 of this register will be cleared when the last byte of the block is transferred. 1 enables the continuous block transfer mode and Bit 1 of this register will not be cleared and SRC address counter/DST address counter/byte length counter will be reloaded with their corresponding registers when DMA1 finishes the block transfer.

R/W 0

4

DMA1 Priority, 0 DMA1 low priority, 1: DMA1 high priority When both DMA1 Priority and DMA2 Priority are set or cleared simultaneously, the priority is in the style of the first start one which is also the first end one.

R/W 0

3:2

External Trigger 0 0 DRQ1A, UART2 TX DRQ 0 1 DRQ1B, reserved 1 0 DRQ1C, reserved 1 1 DRQ1D, SPDIF TX DRQ

R/W 00

1 External DRQ trigger enable, 0: disable external DRQ trigger. 1: enable R/W 0

0

DMA1 Start. After TC, the bit will be cleared. The low-go-high edge of this bit will load SRC start address, DST start address, byte count into the current working counters.

R/W 0



Ver 1.4 Page 18 2006-10-11


7:0 DMA2SA[7:0] R/W X


7:0 DMA2SA[15:8] R/W X


7 DMA2 Source DSP Mode Select. 0:linear, 1: DSP Mode. R/W x

6:0 DMA2SA[22:16] R/W xxxxxxx


7 External Memory Select, 0: Int.Memory,1: external memory RW x

6 Int.Memory select, 0: ZRAM, 1: IPM/IDM/ZRAM2 RW x

5 Reserved / /

4:0 DMA2SA[28:24] R/W xxxxx

4.18 Register18--DMA2 IPM/IDM/ZRAM2 SRC Address Register (Back) Bits Description Access Reset

7:3 Reserved / /



Ver 1.4 Page 19 2006-10-11

2:0

DMA2ISA[2:0] 0 0 0 IPML 0 0 1 IPMM 0 1 0 IPMH 0 1 1 reserved 1 0 0 IDML 1 0 1 IDMM 1 1 0 IDMH 1 1 1 ZRAM2(B1+B2+URAM)

R/W xxx

4.19 Register19--DMA2 Destination Address 0 Register(Back) Bits Description Access Reset

7:0 DMA2DA[7:0] R/W X

4.1A Register1A--DMA2 Destination Address 1 Register(Back) Bits Description Access Reset

7:0 DMA2DA[15:8] R/W X

4.1B Register1B--DMA2 Destination Address 2 Register(Back) Bits Description Access Reset

7:0 DMA2DA[23:16] R/W X

4.1C Register1C--DMA2 Destination Address 3 Register(Back) Bits Description Access Reset

7 External Memory Select, 0: Int.Memory, 1: external memory R/W x

6 Int.Memory select, 0: ZRAM, 1: IPM/IDM/ZRAM2 R/W x

5 Reserved / /

4:0 DMA2DA[28:24] R/W xxxx

4.1D Register1D--DMA2 IPM/IDM/ZRAM2 DST Address Register (Back) Bits Description Access Reset

7:3 Reserved / /



Ver 1.4 Page 20 2006-10-11

2:0

DMA2IDA[2:0] 0 0 0 IPML 0 0 1 IPMM 0 1 0 IPMH 0 1 1 reserved 1 0 0 IDML 1 0 1 IDMM 1 1 0 IDMH 1 1 1 ZRAM2

R/W xxx

4.1E Register1E--DMA2 Byte Count Low Register (Back) Bits Description Access Reset

7:0 DMA2BC[7:0] R/W X

4.1F Register1F--DMA2 Byte Count High Register (Back) Bits Description Access Reset

7 Reserved / /

6:0 DMA2BC[14:8] R/W xxxxxxx

4.20 Register20--DMA2 Mode Register (Back) Bits Description Access Reset

7:6

DMA2 wait state select 0 0 0 wait state 0 1 1 wait state 1 0 2 wait states 1 1 3 wait states

RW 00

5 DMA2 Destination DSP transfer mode, 0: linear mode, 1: DSP mode, it is used when transmit DSP code or data.

R/W 0

4 DMA2 DST down count. 0: up count, 1: down count R/W 0

3 DMA2 SRC down count. 0: up count, 1: down count R/W 0

2 DMA2 for DSP for DSP BOOT, 0: normal, 1 : DSP BOOT R/W 0



Ver 1.4 Page 21 2006-10-11

1 DMA2 DST is IO. 0 : Memory 1: IO. When DMA DST is IO, usually the IO is a FIFO or other array, the IO address will not increase or decrease. R/W 0

0 DMA2 SRC is IO. 0 : Memory 1: IO. When DMA SRC is IO, usually the IO is a FIFO or other array, the IO address will not increase or decrease. R/W 0

4.21 Register21--DMA2 Command Register (Back) Bits Description Access Reset

7 DMA2 TC IRQ enable. 0 disable IRQ. 1 enables IRQ when DMA2 finishes the whole block transfer.

RW 0

6 DMA2 Half Transfer IRQ enable. 0 disable IRQ. 1 enables IRQ when DMA2 finishes half of defined block transfer.

R/W 0

5

DMA2 Continue Block Transfer enable. 0 disables the continuous block transfer mode and Bit 1 of this register will be cleared when the last byte of the block is transferred. 1 enables the continuous block transfer mode and Bit 1 of this register will not be cleared and SRC Address Counter/DST Address Counter/Byte Length Counter will be reloaded with their corresponding registers when DMA2 finishes the block transfer.

R/W 0

4

DMA2 Priority, 0: DMA2 low priority, 1: DMA2 high priority When both DMA1 Priority and DMA2 Priority are set or cleared simultaneously, the priority is in the style of the first start one which is also the first end one.

R/W 0

3:2

External DRQ trigger select 0 0 DRQ2A, UART2 RX DRQ 0 1 DRQ2B, ADCFIFO RX DRQ 1 0 DRQ2C, external input I2S DRQ

1 1 DRQ2D, SPDIF RX DRQ If ADC FIFO DRQ is selected ,the DMA Clock should be a quarter of MCU clock. If I2S DRQ is selected, the DMA Clock should be HOSC and there is no wait in DMA2.

R/W 00

1 External DRQ trigger enable, 0: disable external DRQ trigger, 1: enable R/W 0



Ver 1.4 Page 22 2006-10-11

0

DMA2 Start. After TC the bit will be cleared. The low-go-high edge of this bit will load SRC start address, DST start address, byte count into current working counters.

R/W 0

4.22 Register22--CTC Prescale Register(Back) Bits Description Access Reset

7 CTC1 enable, 0 disable(default), 1 enable RW 0

6:0 pre-scale, /1, /2 /3 /4 .. /128. Clock source of CTC is from HOSC. R/W xxxxxxx

4.23 Register23--CTC T Period Low Register(Back) Bits Description Access Reset

7:0 TPERIOD[7:0], period low byte register of CTC RW X

4.24 Register24--CTC T Period High Register(Back) Bits Description Access Reset

7:0 TPERIOD[15:8], period register of CTC RW X

4.25 Register25--DMA/CTC IRQ Status Register(Back) Bits Description Access Reset

7 CTC IRQ pending RW 0

6 DMA2 Half Transfer IRQ pending RW 0

5 DMA2 End Transfer IRQ pending RW 0 4 DMA1 Half Transfer IRQ pending RW 0

3 DMA1 End Transfer IRQ pending RW 0

2 SIRQ- pending,writing 1 to this bit will clear it. RW 0 1 Reserved. / /



Ver 1.4 Page 23 2006-10-11

0

software controlled DMA1/DMA2 reset signal, The low-go-high edge of this bit will generate a pulse to reset DMA1/DMA2 state machine, bytes counter, and clear H.W DRQ status etc. After the pulse the bit will be cleared to 0.

RW 0

4.26 Register26--Master Interrupt Status Register(Back) Bits Description Access Reset

7 ADC interrupt(3), READ ONLY R 0

6 KeyBoard(1), Writing 1 to this bit will clear the bit, otherwise the bit is unchanged RW 0

5 RTC interrupt(3), READ ONLY R 0 4 DMA/CTC/SDRAM/Cmos sensor interrupt(3), READ ONLY R 0 3 SIRQ/ATAIRQ/I2C/SPI/RB interrupt(3), READ ONLY R 0 2 USB interrupt(5), READ ONLY R 0 1 UART/IR/SPDIF interrupt(2), READ ONLY R 0

0 DSP interrupt(1) pending, when dspirq disable, if the DSP irq occurs, this bit will still be set to 1. Writing 1 to this bit will clear the bit, otherwise unchanged

RW 0

4.27 Register27--Master Interrupt Enable Register(Back) Bits Description Access Reset

7 ADC interrupt Enable, 0 disable, 1 enable RW 0

6 Key Board IRQ Enable, 0 disable, 1 enable RW 0 5 RTC interrupt Enable, 0 disable, 1 enable RW 0

4 DMA/CTC/SDRAM/Cmos sensor interrupt Enable. 0: disable, 1: enable RW 0

3 SIRQ/ATAIRQ/I2C/SPI/RB interrupt enable. 0: disable, 1: enable RW 0

2 USB interrupt Enable, 0 disable, 1 enable RW 0

1 UART/IR/SPDIF interrupt Enable, 0 disable, 1 enable RW 0

0 DSP interrupt Enable, 0 disable, 1 enable RW 0



Ver 1.4 Page 24 2006-10-11

4.28 Register28--Flash Controller Nand Enable Register(Back) Bits Description Access Reset

7 Reserved. RW 0

6 Data Ready IRQ Enable.0:disable, 1:enable. RW 0

5 Reserved. / /

4 enable Nand Flash access on Bank 3,ie. CE3-. 1 enable. RW 0

3 enable Nand Flash access on Bank 2,ie. CE2-. 1 enable. RW 0

2 enable Nabd Flash access on Bank 1,ie. CE1-. 1 enable. RW 0

1 Flash Mode select, 0 old mode, 1 new mode If 2 or more Nand Flash are used, only one can be enabled at one time. RW 0

0

Nand Flash State Machine Status, Read Only, 0: the state machine is in its idle state. 1: the state machine is busy. When CE1- or CE2- enables, enable the ALE and CLE output. CE1-, CE2- should be controlled separately, each of them can use 1.8v or 3.3v.

R 0

Note: 1.8V power requirements: 1.65V1.95V.

3.3V power requirements: 2.70V3.60V.

4.29 Register29--Flash Controller Address/DMA5 Select Register(Back) Bits Description Access Reset

7 Data Ready IRQ pending, the bit will be set to 1 when low-go-high edge of the R/B- signal occur, writing 1 to this bit will clear it.

RW 0

6 Ready/Busy Status bit. It indicates that the flash current status. R /

5

DMA5 End Transfer or 16Bytes Spare End flag, the bit will be set to 1 when DMA5 finishes DATA or Spare transfer, writing 1 to this bit will clear the bit. Hardware will automatically clear this bit when MCU sends the next command.

RW 0

4:3

DMA5 wait state Select, Bit4 3 wait state

0 0 0 wait state 0 1 1 wait state 1 0 2 wait states 1 1 3 wait states

RW 00



Ver 1.4 Page 25 2006-10-11

2 DMA5 Waits H/L Level Select. 1:flash R-/W- low Level, 0: flash R-/W- high Level. RW 0

1:0

Address Cycle Mode Select Bit 1 0 Address Cycle Mode

0 0 5 Cycle Mode 0 1 4 Cycle Mode 1 0 3 Cycle Mode 1 1 reserved

Cycle mode Erase (Row) W/R

(Col+Row) LB

(Col) SB

(Col) 5 cycle mode 3 5 2 -

4 cycle mode 3 4 2 -

3 cycle mode 2 3 - -

RW 00

DMA5 Buffer Registers are memory (zram) mapping registers. see register 2bh for the details.

4.2A Register2A--Flash COMMAND register(Back) Bits Description Access Reset

7:0 Flash COMMAND [7..0] x 0

4.2B Register2B --Flash Controller ECC control Register(Back) if ECC Enable bit0the ECC generated after writing 256 bytes data or read back will be stored in ECC[13..0] and ECC[13..0]. ECC is only for Hamming Code. 1bit correction & 2bit detection.

Bits Description Access Reset

7:6

Memory MAP Address Select, Bit 7 6 Memory MAP

0 0 [3fc0-3fcfh] 0 1 [3fd0-3fdfh] 1 0 [3fe0-3fefh] 1 1 [3ff0-3fffh]

RW 00

5 Reserved to 0. RW 0

4

User ECC storage control bit. 0:normal, The twelfth and The 13th byte will store ECC3. 1: The twelfth and The 13th byte will store the seventh and the eighth byte of user data.

RW 0



Ver 1.4 Page 26 2006-10-11

3:2

Bit[3-2] : ECC type Bit 3 2 ECC Type

0 0 128 bytes ( 20 bits ECC ) 0 1 256 bytes ( 22 bits ECC )(default) 1 0 512 bytes ( 24 bits ECC ) 1 1 2k bytes ( 28 bits ECC )

RW 01

1 ECC Storage Select, 0: Flash ECC Register storage ECC1, 1: Flash ECC Register storage ECC2 RW 0

0 1 BIT ECC Enable. 1: enable, 0: disable. RW 0

4.2C Register2C --User ECC Register0 (Back) Bits Description Access Reset

7 ECC 5 R 0

6 ECC5 R 0

5 ECC 4 R 0

4 ECC 4 R 0

3 ECC 3 R 0

2 ECC3 R 0

1 ECC 2 R 0

0 ECC2 R 0

4.2D Register2D --User ECC Register1(Back) Bits Description Access Reset

7 ECC 1 R 0

6 ECC1 R 0

5 ECC 0 R 0

4 ECC0 R 0

3:0 Reserved / /



Ver 1.4 Page 27 2006-10-11

4.2E Register2E--DSP Control/Status Register (Back) Bits Description Access Reset

7 DSP Reset. 0: DSP reset, 1: normal operation RW 0

6:4 IDM/IPM option select, DUMMYS[0:2] RW 000

3 DSP phase timing control. 0: normal phase, 1: extended IPM/IDM Read RW 0

2 DSP clock select, 0 from PLL, 1 from HOSC RW 0

1 DSPCKEN. 0: DSP CLK=DC(LOW), 1: enable CLK toggle to DSP. RW 0

0 IRQ2DSP-. 0: asserts IRQ2- to DSP core to interrupt DSP by MCU RW 1

4.2F Register2F--DSP Boot Mode Register (Back) Bits Description Access Reset

7:4 Chip Version 1001B ( read only ) R 1001 3 Reserved. / /

2 CE3- Multiplexed Select. 0: normal as CE3-, if SD Card is enabled, CE3- is used as MMC_DAT, 1: MAP to GPO_A3.

RW 0

1:0

BMODE MMAP DSP BOOT 0 0 reserved 0 1 reserved 1 0 HIP boot 1 1 No boot, start at 0x000h from internal IPM

RW 11

4.30 Register30--DSP HIP Register 0(DATA) (Back) Bits Description Access Reset

7:0 HIP DATA Register 0 [7..0] RW X

4.31 Register31--DSP HIP Register 1(DATA) (Back) Bits Description Access Reset




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4.32 Register32--DSP HIP Register 2 (DATA) (Back) Bits Description Access Reset








4.36 Register36--DSP HIP Register 6 (STATUS) (Back) Bits Description Access Reset

7:0 HIP Status Register 6 [7..0] RW X

4.37 Register37--DSP HIP Register 7 (STATUS) (Back) Bits Description Access Reset

7:0 HIP Status Register 7 [7..0] RW X

4.38 Register38--SPDIF Control Register (Back) Bits Description Access Reset

7 SPDIF enable. 0:disable,1:enable. RW 0

6:5 reserved. / /

4 this bit should be set to 1. RW 0

3 SPDIF DRQ enable. 0:disable, 1:enable. RW 0



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2 SPDIF FIFO reset. 0: FIFO reset valid, 1: FIFO reset invalid. RW 0

1 SPDIF Block In IRQ enable.0: disable, 1: enable. RW 0

0 SPDIF Data In IRQ enable.0: disable, 1: enable. RW 0 NOTES:

1. Frames, sub-frames and blocks

An audio sample is placed in a structure known as a sub-frame. The sub-frame, shown in Figure 1,

consists of 4 bits of preamble, 4 bits of auxiliary data, and 20 bits of audio data, 3 bits called validity,

user, channel status, and a parity bit. The preamble contains bi-phase coding violations and identifies the start of a sub-frame. The audio sample word length can vary up to 24 bits and the LSB

is transmitted first. If the word length is greater than 20 bits, the sample occupies both the audio and

auxiliary data fields. If it is 20 bits or less, the auxiliary field can be used for other applications such

as voice. The parity bit generates even parity and can detect an odd number of transmission errors

in the sub-frame. When the validity bit is low, it indicates the audio sample is fit for the conversion to

analog. The user and channel status bits are sent once per sample, and when it is accumulated over a number of samples, then define a block of data. The user bit channel is undefined and

available to the user for any purpose. The channel status bit conveys, over an entire block, the

important information about the audio data and transmission link. Each of the two audio channels

has its own channel status data with a block structure that repeats every 192 samples.

Figure 2 the consecutive sub-frames are defined as a frame, containing channels A and B, and 192

frames define a block. The preambles that identify the start of a sub-frame are different for each of

the two channels with another unique one identifying the beginning of a channel status block.

2. Modulation and Preambles

The data is transmitted with bi-phase-mark encoding to minimize the DS component and to allow

clock recovery from the data. As illustrated in Figure 3, the 1s in the data has transitions in the center, and the 0s does not have after bi-phase-mark encoding.

Also, the bi-phase-mark data switches polarity at every data bit boundary. Since the value of the data bit is determined by whether there is a transition in the center of the bit, the actual polarity of

the signal is irrelevant. Each sub-frame starts with a preamble. This allows a receiver to lock on to

the data within one sub-frame. There are three defined preambles: one for each channel and one to



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indicate the beginning of a channel status block (which is also channel A). To distinguish the preambles from arbitrary data patterns, the preambles contain two bi-phase-mark violations.

Bi-phase-mark data is required to transition at every bit period, but each preamble violates that

requirement twice. In Figure 3 each bit boundary, indicated by the dashed lines, contains a transition in the bi-phase data; Each preamble shown in Figure 4 has two bit boundaries with no

transition, which enables the receiver to recognize the data as a preamble. Since bi-phase-mark

encoding is not polarity conscious, both phases are shown in the table. Preambles X and Y indicate a sub-frame containing channels A and B respectively. Preamble Z replaces preamble X

once every 192 frames to indicate the start of a channel status block. There are two channel status

blocks, one for channel A and one for channel B .Since there are 192 frames in a block, each channel has a channel status block of 192 bits long. These 192 channel status bits in a block can be

arranged as 24 bytes. The blocks have one of the two formats, professional or consumer. The first

bit of the channel status block defines the format with 0 indicating consumer and 1 indicating professional.

Figure 1



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Figure 2

Figure 3

Figure 4

28-level by 8 bits FIFO are used to buffer data for TX and RX. After receiving 192 frame- four bytes of

channel status is appended into the RX FIFO. When TX FIFO is empty and SPDIF is enabled, 0 is to

send out for all frames.

4.39 Register39--SPDIF Status Register (Back) Bits Description Access Reset

7 SPDIF TX FIFO Full (read only). 1: full. R 0 6 SPDIF RX FIFO Empty (read only). 1: empty. R 1



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5 SPDIF Block in IRQ pending, writing 1 to this bit will clear it, while 0 unchanged. RW 0

4 SPDIF Data in IRQ pending,writing 1 to this bit will clear it, while 0 unchanged. RW 0

3 SPDIF TX FIFO error Pending. Writing 1 to this bit will clear it , otherwise unchanged. RW 0

2 SPDIF RX FIFO error Pending. Writing 1 to this bit will clear it , otherwise unchanged. RW 0

1 SPDIF Receive error Pending. Writing 1 to this bit will clear it, otherwise unchanged. RW 0

0 Reserved. / /

4.3A Register3A--SPDIF FIFO DATA Register (Back) Bits Description Access Reset

7:0 SPDIF FIFO DATA, Write : SPDIF TX FIFO . Read : SPDIF RX FIFO.

RW X

4.3B Register3B--SPDIF Channel Status Register (Back) For RX:

There are 32 bits status per 192 frames transfer. All these 4-byte status bits are mapped into this register.

An internal read pointer is used to point to the current byte from which data will be returned at the next

read. The internal read pointer will increase after read from this register. When SPDIF receives all 192

frames of a block, SPDIF IRQ will be issued to notify MCU to read channel status. The internal pointer will

be cleared when SPDIF is issued.

For TX:

Another 4 bytes status are also implemented for transmit, which are mapped into this register also. An

internal write pointer is used to point to the byte position for the next write. When read from this register,

the internal write pointer will be cleared to point to the first byte of TX channel status. The write pointer will

move to the next byte after write to this register.

SPDIFCH(SPDIF Channel Status Register, 03Bh)



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Bits Description Access Reset 7:0 SPDIF Channel status RW x

4.3C Register3C--USB5V VCC Regulator Register (Back) Bits Description Access Reset

7 Reserved. / /

6 1.8V Regulator Output Enable.0:disable,1:enable. This regulator is used only for 1.8V Nand Flash and the corresponding pins.

RW 1

5 Reserved. RW 0

4 Reserved.. RW 0

3 Reserved. . RW 0

2:0

USB 5V VCC(Regulator) voltage control 000 2.6V 001 2.7V 010 2.8V 011 2.9V 100 3.0V

**101 3.1V 110 3.2V 111 3.3V

RW 101

4.3E Register3E --USB Internal Resistor Control Register (Back) Bits Description Access Reset

7 Internal Pull Up Enable. Set this bit to enable internal 1500 pull up resistor on the D+.

R/W 0

6 Internal Resistor Enable. Set this bit to enable internal 45 precise resistors on the D+ and D- respectively.

R/W 0

5 Internal Resistors Calibration. Set this bit to one to trig the internal resistors calibration process which will adjust the internal precise resistors to 45.

R/W 0

4 Plugged In Enable. Set this bit to one to enable the plugged in detector and to switch in the two 500K pull-up resistors. R/W 1



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3 Plugged In. When Plugged In Enable bit is set, this read only bit returns a zero if both D+ and D- are high. Otherwise this bit returns a one. When Plugged In Enable bit is zero, this bit will always return a zero. The Plugged In Enable bit must be set to one for enough time (at least 1ms) before the state of this bit becomes reliable. Note: A debounce mechanism of D+ and D- should be implemented to filter temporary SE1 when data lines of D+ and D- transition in data transfer.

R 0

2:0 Value of Internal Pull Up Resistor. 0 0 0 1.1k 0 0 1 1.2k 0 1 0 1.3k 0 1 1 1.4k 1 0 0 1.5k 1 0 1 1.6k 1 1 0 1.7k 1 1 1 1.8k

R/W 100

4.3F Register3F --VDD & VCC voltage detect Control Register (Back) Bits Description Access Reset

7 VDD voltage detect enable; 0: disable; 1: enable RW 0

6 VCC voltage detect enable; 0: disable; 1: enable RW 0

5:3

VCC voltage detect level select **000 2.4V

001 2.5V 010 2.6V 011 2.7V 100 2.8V 101 2.9V 110 3.0V 111 3.1V

RW 000



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2:0

VDD voltage detect level select **000 1.4V

001 1.5V 010 1.6V 011 1.7V 100 1.8V 101 1.9V 110 2.0V 111 2.1V

RW 000

4.40 Register40--High Frequency Crystal Control Register (Back) The ATJ209X supports 24Mhz crystal, and it is the system clock source.

A low jitter PLL referenced to 24MHz is used to generat

atj209x program guide v1.4

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