ate boards designs
DESCRIPTION
quick design and routing support services to ATE designers involved in designing of loadboards,BiBs,probecards,handler and probe interface boards , motherboards and characterization boards. MLO/MLC substrate designing.TRANSCRIPT
2010.10
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Since 2000
Contact : Caliber Interconnect Solution (Pvt) LtdNo 6 ,1st Street, Kavundampalayam,Coimbatore-30 Indiawww.caliberinterconnect.com
Design for perfection
ATE hardware Design/Routing and SI Analysis services(Exclusive service to ATE Designers)
ATE Design Service EnvironmentATE Design Service Environment
Layout ToolsCadence AllegroMentor ExpeditionMentor PadsZuken CadstarProtel DXPPcad
Schematic ToolsConcept HDLMentor Capture CISDxdesignerOrcad capturePowerlogic
Testers Advantest CredenceLTXNextestVerigyTeradyneYokogawa
Service Introduction
Design/Routing/SI analysis support services to ATE test interface board designing from 2000.Designers are well versed with ATE test system instrumentation and follows hardware design guidelines recommended by test system vendors.
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“Provide the best solutions to the society by reaping the benefits of advanced technologies.”
“Provide dependable services to the satisfaction of the customers through innovation and commitment.”
Vision Vision
Mission Mission
Caliber is a design supplier to
ATE Test system vendorsTest interface board vendors and design
housesTest houses and socket manufacturersProbecard assembly and design housesIC packaging design, manufacturing and
assembly houses
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HistoryHistory
2000 Feb Caliber was registered
2004 Caliber licensed to Cadence tools and Signal integrity team formed.
Caliber become an ISO 9001:2000 certified design house.
2005 Caliber consolidated itself as a strong technological service provider in ATE
domain with 100 plus designers and customers around the globe
2006 Caliber developed test program conversion tools. Caliber formed 50 member
component library and data capturing team
2007 Caliber formed ATE test program development division
2010 Caliber licensed to Cadence PCB SI
Caliber qualified by Teradyne as a design service provider and a service
provider to another major test system vendor.
2001 Caliber developed EDA conversion and design tools for PCB designing .
ATE design team formed and started serving for major ATE vendors
2002 High speed design and component assembly team was formed
2003 Caliber entered into IC Package design service
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Engineering Service Capabilities
Divisions
Design/Routing support for ATE test hardware ,handles partial/full design and routing alone services
ATE Design
MLO/MLC
SI Analysis
SiP
Library
HSD High speed application boards
Designing Substrates for vertical probecards
Signal and power integrity analysis services for PCBs and Packages
IC Packaging BGA packages for ICs
System in Package designing
Component Library development and maintenance
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Caliber is a ISO 9000 certified design house with 70 plus design and electrical simulation analysts
Caliber serving to the ATE industry for 10 years and designed over 6000 plus ATE interface boards
Designers with excellent knowledge about ATE tester configuration , instrumentation and handler
Proven test board design process for mixed and RF signals
In house SI team to resolve signal integrity issues to design boards free from signal distortions.
Familiar with the DFM rules of leading ATE board manufacturers
Capability to design on all EDA layout and schematic tools
Expertise to extend the capability of the EDA tools through customization
ATE Design Capabilities
Caliber design team has the legacy of servicing to major test board and test system vendors from 2000
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ATE Design
Our ATE design services are exclusive for test interface
board vendors ,designers and ATE test system manufacturers.
We have experience in designing of
Universal, Speciality and Blade Probe cards
Load boards Handler Interface Boards & Probe interface boards
Bench Boards & Evaluation Boards
Characterization Boards & Reference Boards
Adapter Cards & Burn in Boards
Hast Boards, ESD and Latch up boards
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Space Transformers (MLO/MLC)
Caliber can design
MLO/MLCs for Wafer Test Boards
Partial and full design of test Boards
HDI technology with blind, buried via
Electrical Simulation Services
Electrical Integrity Analysis
The following electrical analysis are carried out in the pre and post layout analysis:
Signal Integrity AnalysisTiming Analysis Power Integrity AnalysisS-parameter Analysis
The test boards operating at high frequency and fast switching rates demand SI analysis for the right design for first pass success. Our SI engineers are having strong knowledge in SI theory and expertise in simulation tools to analyze various SI issues.
Simulation of probcard PCB with MLO/MLC
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Simulation Ability for ATE
Expertise in Simulation Tools
Allegro PCB SIAllegro PCB PIAllegro Package SIHyperlynxHSpice
Controlled Impedance CalculationInsertion and Return Loss Calculation Interconnect Bandwidth verification Reflection Analysis Crosstalk AnalysisPower Plane IR-Drop Analysis Power Plane Impedance Profile AnalysisChannel Analysis
What we simulate
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Controlled Impedance Calculation
The Trace Width is calculated for Single ended signals and TraceWidth/Spacing for Differential Pairs to achieve controlled impedance of 50 ohms & 100 ohms respectively
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Service HighlightsService Highlights
Get your test boards designed at Caliber
Caliber reduces your risk of investment on design infrastructure and resourcesHigh quality boards designed at short duration for a low costPool of experienced designers having experience in multiple EDA tools and ATE Testers systems
Reduce your design time and increases the profit marginTranslator available for German ,French and Japanese.Proven design process and quality assurance system
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Controlled Impedance Calculation
The Trace Width is calculated for Single ended signals and TraceWidth/Spacing for Differential Pairs to achieve controlled impedance of 50 ohms & 100 ohms respectively
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Insertion and Return Loss Calculation
The trace is modeled with a ground coupled via
Insertion loss @ 800 MHz = -0.787 dB (up to -1dB is good value)Return loss @ 800 MHz = -16.003 dB (below -15dB is good value)
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Interconnect Bandwidth verification
The band width (BW) of the interconnect is calculated
BW = 0.35/RT (This is thump rule from signal integrity theory) RT = rise time for 10% to 90% signal level
RT =197 ps
BW = 0.35 / 197 ps= 1.77 GHz
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Reflection Analysis
The receiver waveform is not crossing the threshold levels and not good
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Reflection Analysis
The receiver waveform is crossing the threshold levels and the waveform is good
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Crosstalk Analysis
After Optimization :
HSEvenXtalk = 58.68 mV LSOddXtalk = 64.71 mV
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Crosstalk Analysis (Frequency domain)
The NEXT and FEXT analysis is carried out for Crosstalk analysis
1%
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IRIR--Drop AnalysisDrop Analysis
The maximum voltage drop observed is 1.7 mV for 1.5V supply
The IR-Drop analysis of power plane
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Power Plane Impedance AnalysisPower Plane Impedance Analysis
From 112 MHz (Actual) to 237 MHz (optimized)
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Channel AnalysisChannel Analysis
6.25 Gbps Serial Data Transfer :From eye height 0V (actual) to 269 mV(optimized)
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Short DeliveryShort Delivery
Our team can route 1500-2000 traces in a day
Low complex designs 1-2 DaysMedium complex 2-4 DaysHigh Complex design 4-6 Days
We offer Signal and Power integrity simulation for test boards
