ata6565 dual high-speed can transceiver with...

ATA6565Dual High-Speed CAN Transceiver with Standby Mode

Features

• Fully ISO 11898-2, ISO 11898-5, ISO 11898-2: 2016 and SAE J2962-2 Compliant

• CAN FD Ready

• Communication Speed up to 5 Mbps

• Low Electromagnetic Emission (EME) and High Electromagnetic Immunity (EMI)

• Differential Receiver with Wide Common-Mode Range

• Remote Wake-up Capability via CAN Bus – Wake-up on Pattern (WUP) as Specified in ISO 11898-2: 2016, 3.8 µs Activity Filter Time

• Functional Behavior Predictable Under All Supply Conditions

• Transceiver Disengages from the Bus when Not Powered Up

• RXD Recessive Clamping Detection

• High Electrostatic Discharge (ESD) Handling Capability on the Bus Pins

• Bus Pins Protected Against Transients in Automotive Environments

• Transmit Data (TXD) Dominant Time-out Function

• Undervoltage Detection on VCC Pin

• Bus Pins Short-Circuit and Overtemperature Protected

• Fulfills the OEM “Hardware Requirements for LIN, CAN and FlexRay™ Interfaces in Automotive Applications”, Rev. 1.3

• Qualified According to AEC-Q100

• Two Ambient Temperature Grades Available:

- ATA6565-GCQW1 and ATA6565-GNQW1 up to Tamb = +125°C

- ATA6565-GCQW0 and ATA6565-GNQW0 up to Tamb = +150°C

• 14-Lead SOIC Package and 14-Lead VDFN Package with Wettable Flanks (Moisture Sensitivity Level 1)

Applications

Classical CAN and CAN FD networks in Automotive,Industrial, Aerospace, Medical and Consumerapplications.

General Description

The ATA6565 is a fully integrated, dual high-speed CANtransceiver with two completely independent andseparated high-speed CAN transceivers integrated inone package (only the GND pins, GND1 and GND2, areinternally connected). Each of the two identicaltransceivers provides an interface between a ControllerArea Network (CAN) protocol controller and a physicaltwo-wire CAN bus.

The device is designed for high-speed (up to 5 Mbps)CAN applications in the automotive industry, providingdifferential transmit and receive capability to (a micro-controller with) a CAN protocol controller. It offersimproved Electromagnetic Compatibility (EMC) andElectrostatic Discharge (ESD) performance, as well asfeatures such as:

• Ideal passive behavior to the CAN bus when the supply voltage is off

• Very low current consumption in Standby mode with bus wake-up capability

Two operating modes, together with the dedicatedfail-safe features, make the ATA6565 an excellent choicefor all types of high-speed CAN networks. The ATA6565includes more than one high-speed CAN interface whichrequires a Low-Power mode with wake-up capability viathe CAN bus. These features are especially valuable forbody control units and gateways.

Package Types

1

2

3

4

5

6

7

TXD

GND

VCC

RXD

VIO

MISO

INH

NCS

CANH

CANL

MOSI

VS

WAKE

SCK

14

13

12

11

10

9

8

ATA6565

ATA6565 14-Pin SOIC

ATA6565 3 x 4.5 mm

14-Pin VDFN

1

2

3

4

5

6

7

14

13

12

11

10

9

8

ATA6565

TXD1

GND1

VCC1

RXD1

TXD2

GND2

VCC2

STBY1

CANH1

CANL1

STBY2

CANH2

CANL2

RXD2

TXD1

GND1

VCC1

RXD1

TXD2

GND2

VCC2

STBY1

CANH1

CANL1

STBY2

CANH2

CANL2

RXD2

2017 Microchip Technology Inc. DS20005782B-page 1

ATA6565

ATA6565 Family Members

Block Diagram

Device Grade 0 Grade 1 SOIC14 VDFN14

ATA6565-GNQW1 X X

ATA6565-GNQW0 X X

ATA6565-GCQW1 X X

ATA6565-GCQW0 X X

Note: For ordering information, see the “Product Identification System” section.

TemperatureProtection

ControlUnit

Wake-upFilter

SlopeControl

andDriver

TXDTime-out

Timer

VHSC(1)

WUC(2)

V

V

V

MUX

1 TXD1

STBY1

CANH1

RXD1

14

13

4

GND1(3)

Transceiver 1

2

CANL112

TemperatureProtection

ControlUnit

Wake-upFilter

SlopeControl

andDriver

TXDTime-out

Timer

VCC2HSC(1)

WUC(2)

VCC2

VCC2

VCC2

MUX

5TXD2

STBY2

CANH2

RXD2

11

10

8

GND2(3)

Transceiver 2

6

CANL29

V7

Note 1: HSC: High-Speed Comparator.2: WUC: Wake-up Comparator.3: GND1 and GND2 are internally connected.

DS20005782B-page 2 2017 Microchip Technology Inc.

ATA6565

1.0 FUNCTIONAL DESCRIPTION

The ATA6565 is a stand-alone, dual high-speed CANtransceiver, compliant with the ISO 11898-2, ISO11898-5, ISO 11898-2: 2016 and SAE J2962-2 stan-dards. Each of the two transceivers provides a very lowcurrent consumption in Standby mode and wake-upcapability via the CAN bus.

The functions described in the following text apply toeach of the two identical high-speed CAN transceiversintegrated in the ATA6565. Therefore, if for example,the CANH pin is stated, this applies to each of the twotransceivers, meaning CANH1 and CANH2. The twotransceivers are identical and there is no internal

connection between them (with the exception of theGND pins, GND1 and GND2), so they work completelyindependently.

1.1 Operating Modes

Each of the transceivers supports three operatingmodes: Unpowered, Standby and Normal. Additionally,there is the internal Silent mode, which is not externallyaccessible. This mode is a Receive Only mode, whichmeans the CAN drivers are deactivated and only datafrom the bus can be received.

The operating modes can be selected via the STBYpins (STBY1 and STBY2). See Figure 1-1 andTable 1-1 for a description of the operating modes.

FIGURE 1-1: OPERATING MODES

STBY = 0 andTXD = 0

VCC < Vuvd(VCC)

STBY = 1

STBY = 0 andTXD = 1 and

Error = 0 andTXD = 1

*

Error = 1

Error = 0

VCC < Vuvd(V )

VCC < Vuvd VCC > Vuvd

UnpoweredMode

StandbyMode

SilentMode

NormalMode

STBY = 1

* Silent mode is externally not accessible. In this mode, the transceiver can only receive data from the bus, but the transmitter is disabled.

TABLE 1-1: OPERATING MODES

ModeInputs Outputs

STBY Pin TXD CAN Driver Pin RXD

Unpowered X(1) X(1) Recessive Recessive

Standby High X(1) Recessive Active(2)

Normal Low Low Dominant Low

Low High Recessive High

Note 1: Irrelevant.

2: Reflects the bus only for wake-up.


ATA6565

1.1.1 NORMAL MODE

A low level on the STBY pin, together with a high level onthe TXD pin, selects the Normal mode. In this mode, thetransceiver is able to transmit and receive data via theCANH and CANL bus lines (see the Block Diagram).The output driver stage is active and drives data from theTXD input to the CAN bus. The High-Speed Comparator(HSC) converts the analog data on the bus lines intodigital data, which is output to pin RXD. The bus biasingis set to VVCC/2 and the undervoltage monitoring of VVCCis active.

The slope of the output signals on the bus lines is con-trolled and optimized in a way that ensures the lowestpossible Electromagnetic Emission (EME).

To switch the device to Normal Operating mode, set theSTBY pin to low and the TXD pin to high (see Table 1-1and Figure 1-2). The STBY pin provides a pull-upresistor to VCC, thus ensuring a defined level if the pinis open.

Please note that the device cannot enter Normal modeas long as TXD is at ground level.

The switching into Normal mode is depicted inFigure 1-2.

FIGURE 1-2: SWITCHING FROM STANDBY MODE TO NORMAL MODE

STBY

TXD

Standby Mode

tdel(stby-norm) =

47 μs max

Normal Mode

t

t

t

OperationMode


ATA6565

1.1.2 STANDBY MODE

A high level on the STBY pin selects Standby mode. Inthis mode, the transceiver is not able to transmit orcorrectly receive data via the bus lines. The transmitterand the High-Speed Comparator (HSC) are switched offto reduce current consumption.

1.1.2.1 Remote Wake-up via the CAN Bus

In Standby mode, the bus lines are biased to ground toreduce current consumption to a minimum. The devicemonitors the bus lines for a valid wake-up pattern, asspecified in the ISO 11898-2: 2016. This filtering helpsto avoid spurious wake-up events which would betriggered by scenarios, such as a dominant clampedbus or by a dominant phase due to noise, spikes on thebus, automotive transients or EMI.

The wake-up pattern consists of at least two consecu-tive dominant bus levels for a duration of at least tFilter,each separated by a recessive bus level with a durationof at least tFilter. Dominant or recessive bus levelsshorter than tFilter are always ignored. The completedominant-recessive-dominant pattern, as shown inFigure 1-3, must be received within the bus wake-uptime-out time, tWake, to be recognized as a validwake-up pattern. Otherwise, the internal wake-up logicis reset and then the complete wake-up pattern mustbe retransmitted to trigger a wake-up event. The RXDpin remains at a high level until a valid wake-up eventhas been detected.

During Normal mode, at a VCC undervoltage conditionor when the complete wake-up pattern is not receivedwithin tWake, no wake-up is signaled at the RXD pin.

FIGURE 1-3: TIMING OF THE BUS WAKE-UP PATTERN (WUP) IN STANDBY MODE

When a valid CAN wake-up pattern is detected on thebus, the RXD pin switches to low to signal a wake-uprequest. A transition to Normal mode is not triggereduntil the STBY pin is forced back to low by themicrocontroller.

1.2 Fail-Safe Features

1.2.1 TXD DOMINANT TIME-OUT FUNCTION

A TXD dominant time-out timer is started when the TXDpin is set to low. If the low state on the TXD pin persistsfor longer than tto(dom)TXD, the transmitter is disabled,releasing the bus lines to the recessive state. This func-tion prevents a hardware and/or software applicationfailure from driving the bus lines to a permanent domi-nant state (blocking all network communications). TheTXD dominant time-out timer is reset when the TXD pin

is set to high. If the low state on the TXD pin was longerthan tto(dom)TXD, then the TXD pin has to be set to high≥ 4 µs in order to reset the TXD dominant time-out timer.

1.2.2 INTERNAL PULL-UP STRUCTURE AT THE TXD AND STBY INPUT PINS

The TXD and STBY pins have an internal pull-up toVCC. This ensures a safe, defined state in case one orboth pins are left floating. Pull-up currents flow in thesepins in all states, meaning all pins should be in a highstate during Standby mode to minimize the currentconsumption.

1.2.3 UNDERVOLTAGE DETECTION ON PIN VCC

If VVCC drops below its undervoltage detection level,Vuvd(VCC) (see Section 2.0 “Electrical Characteris-tics”), the transceiver switches off and disengages fromthe bus until VVCC has recovered. The low-power

tdom = t

VDiff

tdom = ttrec = t

dominant recessive

Bus Wake-upis Signaled

CANH

CANL

RXD

dominant


ATA6565

wake-up comparator is only switched off during a VCCundervoltage. The logic state of the STBY pin is ignoreduntil the VCC voltage has recovered.

1.2.4 BUS WAKE-UP ONLY AT DEDICATED WAKE-UP PATTERN

Due to the implementation of the wake-up filtering, thetransceiver does not wake-up when the bus is in a longdominant phase; it only wakes up at a dedicated wake-uppattern, as specified in the ISO 11898-2: 2016. Thismeans for a valid wake-up, at least two consecutivedominant bus levels for a duration of at least, tFilter, eachseparated by a recessive bus level with a duration of atleast, tFilter, must be received via the bus. Dominant orrecessive bus levels shorter than tFilter are alwaysignored. The complete dominant-recessive-dominant

pattern, as shown in Figure 1-3, must be received withinthe bus wake-up time-out time, tWake, to be recognizedas a valid wake-up pattern. This filtering leads to a higherrobustness against EMI and transients, and therefore,significantly reduces the risk of an unwanted buswake-up.

1.2.5 OVERTEMPERATURE PROTECTION

The output drivers are protected against overtemperatureconditions. If the junction temperature exceeds the shut-down junction temperature, TJsd, the output drivers aredisabled until the junction temperature drops below TJsdand pin TXD is at a high level again. This TXD conditionensures that output driver oscillations, due to temperaturedrift, are avoided.

FIGURE 1-4: RELEASE OF TRANSMISSION AFTER OVERTEMPERATURE CONDITION

FailureOvertemp

GND

TXD

Overtemperature

R D R

t

t

t

OT

BUS VDIFF(CANH-CANL)

VVCC

R DD

t

RXDVVCC

GND


ATA6565

1.2.6 SHORT-CIRCUIT PROTECTION OF THE BUS PINS

The CANH and CANL bus outputs are short-circuitprotected, either against GND or a positive supply volt-age. A current-limiting circuit protects the transceiveragainst damage. If the device is heating up due to acontinuous short on CANH or CANL, the internalovertemperature protection switches the bus transmitteroff.

1.2.7 RXD RECESSIVE CLAMPING

This fail-safe feature prevents the controller from sendingdata on the bus if its RXD is clamped to high (e.g., reces-sive). That is, if the RXD pin cannot signalize a dominant

bus condition (e.g., because it is shorted to VCC), thetransmitter is disabled to avoid possible data collisions onthe bus. In Normal mode, the device permanently com-pares the state of the High-Speed Comparator (HSC)with the state of the RXD pin. If the HSC indicates adominant bus state for more than tRC_det, without theRXD pin doing the same, a recessive clamping situationis detected and the transceiver is forced into Silent mode.This Fail-Safe mode is released by either enteringStandby or Unpowered mode, or if the RXD pin isshowing a dominant (e.g., low) level again.

FIGURE 1-5: RXD RECESSIVE CLAMPING DETECTION

CAN

TXD

RXD

OperationMode Normal NormalSilent

If the clamping condition is removed and adominant bus is detected, the transceivergoes back to normal mode.

If the clamping condition is removed and adominant bus is detected, the transceivergoes back to Normal mode.


ATA6565

1.3 Pin Description

The descriptions of the pins are listed in Table 1-2.

TABLE 1-2: PIN FUNCTION TABLE

Pin Number Pin Name Description

1 TXD1 Transmit Data Input 1

2 GND1 Ground 1, Internally Connected to GND2

3 VCC1 Supply Voltage of Transceiver 1

4 RXD1 Receive Data Output 1; Reads out Data from the Bus Lines of Transceiver 1

5 TXD2 Transmit Data Input 2

6 GND2 Ground 2, Internally Connected to GND1

7 VCC2 Supply Voltage of Transceiver 2

8 RXD2 Receive Data Output 2; Reads out Data from the Bus Lines of Transceiver 2

9 CANL2 Low-Level CAN Bus Line 2

10 CANH2 High-Level CAN Bus Line 2

11 STBY2 Standby Mode Control Input of Transceiver 2

12 CANL1 Low-Level CAN Bus Line 1

13 CANH1 High-Level CAN Bus Line 1

14 STBY1 Standby Mode Control Input of Transceiver 1

15 EP(1) Exposed Thermal Pad: Heat Slug, Internally Connected to the GND Pins

Note 1: Only for the VDFN package


ATA6565

Typical Application

1314

1

11

2

3

6

CANH1

V

7

VCC2

100 nF 22 μF(1)

VDD

Microcontroller

GND

ATA6565

CANH1STBY1

TXD1

4

5

8

RXD1

RXD2

TXD2

STBY2 CANL1

VBAT+

12

10

9

CANL1

GND1(2) GND2(2)

CANH2CANH2

CANL2CANL2

GND

5V12V


ATA6565

NOTES:


ATA6565

2.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

DC Voltage at CANH1, CANL1, CANH2, CANL2 (VCANH, VCANL) ................................................................–27 to +42V

Transient Voltage at CANH, CANL (according to ISO 7637, Part 2) (VCANH, VCANL)................................–150 to +100V

Max. Differential Bus Voltage (VDiff) .................................................................................................................–5 to +18V

DC Voltage on All Other Pins (VX) ...............................................................................................................–0.3 to +5.5V

ESD according to IBEE CAN EMC – Test Specification following IEC 61000-4-2 – Pins CANH1, CANL1, CANH2, CANL2 .......................................................................................±8 kV

ESD (HBM following STM5.1 with 1.5 kΩ/100 pF) – Pins CANH1, CANL1, CANH2, CANL2 to GND ....................±6 kV

Component Level ESD (HBM according to ANSI/ESD STM5.1, JESD22-A114, AEC-Q100 (002) ........................ ±4 kV

CDM ESD STM 5.3.1..............................................................................................................................................±750V

ESD Machine Model AEC-Q100-RevF(003)...........................................................................................................±200V

Virtual Junction Temperature (TvJ) ............................................................................................................. –40 to +175°C

Storage Temperature Range (Tstg) ........................................................................................................ –55°C to +150°C

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This isa stress rating only and functional operation of the device at those or any other conditions above those indicated in theoperation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods mayaffect device reliability.

TABLE 2-1: ELECTRICAL CHARACTERISTICS

Electrical Specifications: The values below are valid for each of the two identical integrated CAN transceivers.

Grade 1: Tamb = -40°C to +125°C and Grade 0: Tamb = –40°C to +150°C; VVCC = 4.5V to 5.5V; RL = 60Ω, CL = 100 pFunless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the IC.

Parameters Sym. Min. Typ. Max. Units Conditions

Supply, Pin VCC

Supply Voltage VVCC 4.5 — 5.5 V

Supply Current in Silent Mode

IVCC_sil 1.9 2.5 3.0 mA Silent mode, VTXD = VVCC

Supply Current in Normal Mode

IVCC_rec 2 — 5 mA Recessive, VTXD = VVCC

IVCC_dom 30 50 70 mA Dominant, VTXD = 0V

IVCC_short — — 85 mA Short between CANH and CANL (Note 1)

Supply Current in Standby Mode

IVCC_STBY — — 12 µA VTXD = VVCC

IVCC_STBY — 7 — µA Tamb = +25°C (Note 3)

Undervoltage Detection Threshold on Pin VCC

Vuvd(VCC) 2.75 — 4.5 V

Mode Control Input, Pin STBY

High-Level Input Voltage VIH 0.7 VVCC — VVCC + 0.3 V

Low-Level Input Voltage VIL –0.3 — 0.3 VVCC V

Pull-up Resistor to VCC Rpu 75 125 175 kΩ VSTBY = 0V

High-Level Leakage Current IL –2 — +2 µA VSTBY = VVCC

Note 1: 100% correlation tested.

2: Characterized on samples.

3: Design parameter.


ATA6565

CAN Transmit Data Input, Pin TXD

High-Level Input Voltage VIH 0.7 VVCC — VVCC + 0.3 V

Low-Level Input Voltage VIL –0.3 — 0.3 VVCC V

Pull-up Resistor to VCC RTXD 20 35 50 kΩ VTXD = 0V

High-Level Leakage Current ITXD –2 — +2 µA Normal mode, VTXD = VVCC

Input Capacitance CTXD — 5 10 pF (Note 3)

CAN Receive Data Output, Pin RXD

High-Level Output Current IOH –8 — -1 mA Normal mode, VRXD = VVCC – 0.4V

Low-Level Output Current, Bus Dominant

IOL 2 — 12 mA Normal mode, VRXD = 0.4V

Bus Lines, Pins CANH and CANL

Single-Ended Dominant Output Voltage

VO(dom) 2.75 3.5 4.5 V VTXD = 0V, t < tto(dom)TXD,RL = 50W to 65W,CANH pin (Note 1)

0.5 1.5 2.25 V VTXD = 0V, t < tto(dom)TXD,RL = 50W to 65W,CANL pin (Note 1)

Transmitter Voltage Symmetry

VSym 0.9 1.0 1.1 — VSym = (VCANH + VCANL)/VVCC (Note 3)

Bus Differential Output Voltage

VDiff 1.5 — 3 V VTXD = 0V, t < tto(dom)TXD,RL = 45Ω to 65Ω

1.5 — 3.3 V RL = 70Ω (Note 3)

1.5 — 5 V RL = 2240Ω (Note 3)

–50 — +50 mV VVCC = 4.75V to 5.25V,VTXD = VVCC, receive, no load

Recessive Output Voltage VO(rec) 2 0.5 * VVCC 3 V Normal and Silent mode,VTXD = VVCC, no load

VO(rec) –0.1 — +0.1 V Standby mode,VTXD = VVCC, no load

Differential Receiver Threshold Voltage

Vth(RX)dif 0.5 0.7 0.9 V Normal and Silent mode (HSC), Vcm(CAN) = -27V to +27V

Vth(RX)dif 0.4 0.7 1.1 V Standby mode (WUC),Vcm(CAN) = -27V to +27V (Note 1)

Differential Receiver Hysteresis Voltage

Vhys(RX)dif 50 120 200 mV Normal and Silent mode (HSC), Vcm(CAN) = -27V to +27V

Dominant Output Current IIO(dom) –75 — -35 mA VTXD = 0V, t < tto(dom)TXD,VVCC = 5V, CANH pin, VCANH = -5V

35 — 75 mA VTXD = 0V, t < tto(dom)TXD,VVCC = 5V, CANL pin, VCANL = +40V

TABLE 2-1: ELECTRICAL CHARACTERISTICS (CONTINUED)








ATA6565

Recessive Output Current IIO(rec) –5 — +5 mA Normal and Silent mode,VTXD = VVCC, no load,VCANH = VCANL = –27V to +32V

Leakage Current IIO(leak) –5 0 +5 µA VVCC = 0V,VCANH = VCANL = 5V

IIO(leak) –5 0 +5 µA VCC is connected to GND with R = 47kΩ,VCANH = VCANL = 5V (Note 3)

Input Resistance Ri 9 15 28 kΩ VCANH = VCANL = 4V

Ri 9 15 28 kΩ –2V ≤ VCANH ≤ +7V, –2V ≤ VCANL ≤ +7V (Note 3)

Input Resistance Deviation ∆Ri –1 0 +1 % Between CANH and CANL,VCANH = VCANL = 4V

∆Ri –1 0 +1 % Between CANH and CANL,–2V ≤ VCANH ≤ +7V, –2V ≤ VCANL ≤ +7V (Note 3)

Differential Input Resistance Ri(dif) 18 30 56 kΩ VCANH = VCANL = 4V

Ri(dif) 18 30 56 kΩ –2V ≤ VCANH ≤ +7V, –2V ≤ VCANL ≤ +7V (Note 3)

Common-Mode Input Capacitance

Ci(cm) — — 20 pF (Note 3)

Differential Input Capacitance Ci(dif) — — 10 pF (Note 3)

Differential Bus Voltage Range for Recessive State Detection

VDiff_rec –3 — +0.5 V Normal and Silent mode (HSC),–27V ≤ VCANH ≤ +27V, –27V ≤ VCANL ≤ +27V (Note 3)

VDiff_rec –3 — +0.4 V Standby mode (WUC) –27V ≤ VCANH ≤ +27V, –27V ≤ VCANL ≤ +27V (Note 3)

Differential Bus Voltage Range for Dominant State Detection

VDiff_dom 0.9 — 8.0 V Normal and Silent mode (HSC),–27V ≤ VCANH ≤ +27V,–27V ≤ VCANL ≤ +27V (Note 3)

VDiff_dom 1.15 — 8.0 V Standby mode (WUC),–27V ≤ VCANH ≤ +27V,–27V ≤ VCANL ≤ +27V (Note 3)









ATA6565

Transceiver Timing, Pins CANH, CANL, TXD and RXD (see Figure 2-1 and Figure 2-3)

Delay Time from TXD to Bus Dominant

td(TXD-busdom) 40 — 130 ns Normal mode (Note 2)

Delay Time from TXD to Bus Recessive

td(TXD-busrec) 40 — 130 ns Normal mode (Note 2)

Delay Time from Bus Dominant to RXD

td(busdom-RXD) 20 — 100 ns Normal mode (Note 2)

Delay Time from Bus Recessive to RXD

td(busrec-RXD) 20 — 100 ns Normal mode (Note 2)

Propagation Delay from TXD to RXD

tPD(TXD-RXD) 40 — 210 ns Normal mode, rising edge at TXD pin, RL = 60Ω, CL = 100 pF

40 — 200 ns Normal mode, falling edge at TXD pin, RL = 60Ω, CL = 100 pF

tPD(TXD-RXD) — — 300 ns Normal mode, rising edge at TXD pin, RL = 150Ω, CL = 100 pF (Note 3)

— — 300 ns Normal mode, falling edge at TXD pin, RL = 150Ω, CL = 100pF (Note 3)

TXD Dominant Time-out Time

tto(dom)TXD 0.8 — 3 ms VTXD = 0V, Normal mode

Bus Wake-up Time-out Time tWake 0.8 — 3 ms Standby mode

Min. Dominant/Recessive Bus Wake-up Time

tFilter 0.5 3 3.8 µs Standby mode

Delay Time for Standby Mode to Normal Mode Transition

tdel(stby-norm) — — 47 µs Falling edge at STBY pin

Delay Time for Normal Mode to Standby Mode Transition

tdel(norm-stby) — — 5 µs Rising edge at STBY pin (Note 3)









ATA6565

Transceiver Timing for Higher Bit Rates, Pins CANH, CANL, TXD and RXD (see Figure 2-1 and Figure 2-3), External Capacitor on the RXD Pin, CRXD ≤ 20 pF

Debouncing Time for Recessive Clamping State Detection

tRC_det — — 90 ns V(CANH-CANL) > 900 mV, RXD = high (Note 3)

Recessive Bit Time on RXD tBit(RXD) 400 — 550 ns Normal mode, tBit(TXD) = 500 ns (Note 1)

120 — 220 ns Normal mode, tBit(TXD) = 200 ns

Recessive Bit Time on the Bus

tBit(Bus) 435 — 530 ns Normal mode, tBit(TXD) = 500 ns (Note 1)

155 — 210 ns Normal mode, tBit(TXD) = 200 ns

Receiver Timing Symmetry ∆tRec -65 — +40 ns Normal mode, tBit(TXD) = 500 ns,∆tRec = tBit(RXD) – tBit(Bus) (Note 1)

–45 — +15 ns Normal mode, tBit(TXD) = 200 ns,∆tRec = tBit(RXD) – tBit(Bus)

TABLE 2-2: TEMPERATURE SPECIFICATIONS

Parameters Sym. Min. Typ. Max. Units

14-Lead SOIC

Thermal Shutdown of the Bus Drivers for ATA6565-GNQW1 (Grade 1)

TJsd 150 175 190 °C

Thermal Shutdown of the Bus Drivers for ATA6565-GNQW0 (Grade 0)

TJsd 160 175 190 °C

Thermal Resistance Virtual Junction to Ambient, where IC is soldered to PCB according to JEDEC

RthvJA — 110 — K/W

14-Lead VDFN

Thermal Shutdown of the Bus Drivers for ATA6565-GCQW1 (Grade 1)

TJsd 150 175 195 °C

Thermal Shutdown of the Bus Drivers for ATA6565-GCQW0 (Grade 0)

TJsd 160 175 195 °C

Thermal Resistance Virtual Junction to Heat Slug RthvJC — 8 — K/W

Thermal Resistance Virtual Junction to Ambient, where Heat Slug is Soldered to PCB according to JEDEC

RthvJA — 45 — K/W









ATA6565

FIGURE 2-1: TIMING TEST CIRCUIT FOR THE ATA6565 CAN TRANSCEIVER

FIGURE 2-2: CAN TRANSCEIVER TIMING DIAGRAM 1

1314

1

11

2

3

6

CANH1

VCC1

7

VCC2

100 nF22 μF

ATA6565

STBY

+5V

TXD1

RL CL

RL CL

4

5

8

RXD1

RXD2

TXD2

STBY2

+

15 pF

15 pF

12

10

9

CANL1

GND1 GND2

CANH2

CANL2

TXD

CANH

HIGH

LOW

HIGH

recessive

LOW

dominant

0.9V

0.5V

CANL

RXD

VDiff

td(TXD-busdom) td(TXD-busrec)

td(busdom-RXD)

tPD(TXD-RXD) tPD(TXD-RXD)

td(busrec-RXD)

0.7 VVCC0.3 VVCC


ATA6565

FIGURE 2-3: CAN TRANSCEIVER TIMING DIAGRAM 2

70%

30%

30%

70%

500 mV

900 mV

5 x tBit(TXD) tBit(TXD)

tBit(Bus)

tBit(RXD)

TXD

RXD

VDiff


ATA6565

3.0 PACKAGING INFORMATION

3.1 Package Marking Information

Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.

3e

3e

14-Lead SOIC

ZZZZZZZ

YWW ATA6565H

ZZZZZZZ

YWW ATA6565

Example, Grade 1

Example, Grade 0

14-Lead 4.5 x 3 mm VDFN Example, Grade 1

YWW

ZZZZZZZATA6565

Example, Grade 0

YWW

ZZZZZZZATA6565H


ATA6565

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging


ATA6565

!"#$%!&!!'#*$+::%%%:#


ATA6565

BA

0.10 C

0.10 C

0.10 C A B0.05 C

(DATUM B)

CSEATING

PLANE

1 2

N

2XTOP VIEW

SIDE VIEW

BOTTOM VIEW

0.10 C A B

0.10 C A B

0.10 C

0.08 C

Microchip Technology Drawing C04-21361 Rev A Sheet 1 of 2

2X

14X

For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packaging

Note:

14-Lead Very Thin Plastic Dual Flat, No Lead Package (QBB) - 4.5x3 mm Body [VDFN]With 1.6x4.2 mm Exposed Pad and Stepped Wettable Flanks

D

E

NOTE 1

(A3)

1 2

N

D2

E2

NOTE 1

L

K

e

A

A

(DATUM A)

AA1

14X b


ATA6565

Microchip Technology Drawing C04-21361 Rev A Sheet 2 of 2

Number of Terminals

Overall Height

Terminal Width

Overall Width

Terminal Length

Exposed Pad Width

Terminal Thickness

Pitch

Standoff

UnitsDimension Limits

A1A

bE2

A3

e

L

E

N0.65 BSC

0.203 REF

1.55

0.350.27

0.800.00

0.320.40

1.60

0.850.03

3.00 BSC

MILLIMETERSMIN NOM

14

1.65

0.450.37

0.900.05

MAX

K -0.20 -

REF: Reference Dimension, usually without tolerance, for information purposes only.BSC: Basic Dimension. Theoretically exact value shown without tolerances.

1.2.3.

Notes:

Pin 1 visual index feature may vary, but must be located within the hatched area.Package is saw singulatedDimensioning and tolerancing per ASME Y14.5M

Terminal-to-Exposed-Pad

14-Lead Very Thin Plastic Dual Flat, No Lead Package (QBB) - 4.5x3 mm Body [VDFN]


Note:

With 1.6x4.2 mm Exposed Pad and Stepped Wettable Flanks

Overall LengthExposed Pad Length

DD2 4.15

4.50 BSC4.20 4.25

A4

E3

SECTION A–A

Wettable Flank Step Cut Depth A4 0.10 0.13 0.15E3 -- 0.04Wettable Flank Step Cut Width

PARTIALLYPLATED


ATA6565

RECOMMENDED LAND PATTERN

Dimension LimitsUnits

Optional Center Pad WidthOptional Center Pad Length

Contact Pitch

Y2X2

4.251.65

MILLIMETERS

0.65 BSCMIN

EMAX

Contact Pad Length (X14)Contact Pad Width (X14)

Y1X1

0.850.35

Microchip Technology Drawing C04-23361 Rev A

NOM

14-Lead Very Thin Plastic Dual Flat, No Lead Package (QBB) - 4.5x3 mm Body [VDFN]

1 2

14

CContact Pad Spacing 2.90

Contact Pad to Center Pad (X14) G1 0.20

Thermal Via Diameter VThermal Via Pitch EV

0.301.00

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:Dimensioning and tolerancing per ASME Y14.5M

For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss duringreflow process

1.

2.


Note:

With 1.6x4.2 mm Exposed Pad and Stepped Wettable Flanks

C

E

X1

Y2

ØV

Y1

G1

EV

SILK SCREEN

G2

Contact Pad to Center Pad (X12) G2 0.20

Pin 1 Index Chamfer CH

X2 EV

0.30

CH


ATA6565

APPENDIX A: REVISION HISTORY

Revision B (September 2017)

The following is the list of modifications:

• Added the new devices ATA6565-GNQW0 and ATA656- GNQW1 and updated the related information across the document.

• Updated Package Types section.

• Updated ATA6565 Family Members section.

• Modified Figure 1-3.

• Updated Section 1.3, Pin Description.

• Updated Temperature Specifications.

• Updated Section 3.0, Packaging Information.

• Updated the Product Identification System.

• Fixed minor typographical errors.

Revision A (June 2017)

• Original Release of this Document.

• This document replaces Atmel - 9364G-11/16.


ATA6565

NOTES:


ATA6565

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

a) ATA6565-GCQW0: ATA6565, 14-Lead VDFN,Tape and Reel, Packageaccording to RoHS,Temperature Grade 0

b) ATA6565-GCQW1: ATA6565, 14-Lead VDFN,Tape and Reel, Package according to RoHS, Temperature Grade 1

c) ATA6565-GNQW1: ATA6565, 14-Lead SOIC,Tape and Reel, Packageaccording to RoHS,Temperature Grade 1

b) ATA6565-GNQW0: ATA6565, 14-Lead SOIC,Tape and Reel, Package according to RoHS, Temperature Grade 0

PART NO. X

Package DirectivesDevice

Device: ATA6565: Dual High-Speed CAN Transceiver with Standby Mode

Package: GC = 14-Lead VDFN

GN = 14-Lead SOIC

Tape and Reel Option:

Q = 330 mm diameter Tape and Reel

Package Directives Classification:

W = Package according to RoHS(2)

Temperature Range:

0 = Temperature Grade 0 (-40°C to +150°C)1 = Temperature Grade 1 (-40°C to +125°C)

XX

Package

X

TemperatureRange

[X](1)

Tape and ReelOption Classification

Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.

2: RoHS compliant, maximum concentration value of 0.09% (900 ppm) for Bromine (Br) and Chlorine (Cl), and less than 0.15% (1500 ppm) total Bromine (Br) and Chlorine (Cl) in any homogeneous material. Maximum concentration value of 0.09% (900 ppm) for Antimony (Sb) in any homogeneous material.


ATA6565

NOTES:


Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights unless otherwise stated.

2017 Microchip Technology Inc.

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

QUALITYMANAGEMENTSYSTEMCERTIFIEDBYDNV

== ISO/TS16949==

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

© 2017, Microchip Technology Incorporated, All Rights Reserved.

ISBN: 978-1-5224-2188-7

DS20005782B-page 29


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