assembly, packaging, and testing (apt) of microsystems

8/20/2019 Assembly, Packaging, And Testing (APT) of Microsystems

1/85

Lecture on Microsystems Design and Manufacture

Chapter 11

Assembly, Packaging, and Testing (APT)

of Microsystems

● Like ICs, no MEMS or microsystem is made by only one single component.They are almost all made of multi-components that need to be assembledand packaged to make the microdevices

• Thus, packaging of microsystems involves: assembly, joining, interconnecting,encapsulation of minute parts and components into a microsystem product

● Packaging also includes performance and reliability testing of the finishedproducts

● Packaging is the most critical factor of successful commercialization of micro-scale products. Packaging cost can be as high as 95% of the overall cost of the production. On average, packaging cost is about 30% of the totalproduction cost. Cost-effective and reliable packaging technique is thus the

key to the competitiveness of the microsystem product in the marketplace


2/85

Content

Overview of Assembly, Packaging and Testing (APT)

of MEMS and Microsystems

Part 1: Microassembly

Part 2: Packaging of Microsystems

Part 3: Reliability and Testing of Microsystems


3/85

High Cost in APT of MEMS and Microsystems

￭

MEMS and microsystems involve complex structural geometry anda variety materials

￭ They are expected to perform multi-functions involving biological, chemical,electrical, mechanical, and optical performances

￭ There is no standard in materials and process to follow in APT:

￭ Every microdevice requires special design, component fabrication and APT

1990 1995 2000 2005 2010 2015 2020

Materials

Equipment

Design & Modeling; TestingInterconnect

Process

Packaging

Standards Timeline

C a t e g o r

i e s

High development cost No sharing in technical information

Every new device development requires APT from fresh startHigh overall costs in APT


4/85

APT of a Microdevice Component


5/85

Top View

Elevation(Cross-Section)

S i l icon D ie

P y r e x G l a s s

C o n s t r a i n t B a s e

Silicon Wafer

Pyrex Glass Wafer

A Micro Pressure Sensor Die


6/85

A Flow Chart for Integrated Assembly, Packaging and Testingfor mass production of micro pressure sensors

Wafers

Incoming wafer inspection

Wafer bonding

Microfabrication

on wafers

Wafer dicing

Lift-off

Surface

coating

Partsorting

( P

a r

t s

) Sub-group

assemblies:

Die attach and/or Bonding

Surface

bonding

Wire

bonding

Die or parts

passivation

Electricalinspection

Curing of

passivation

materials

Electrical

inspection

Systemassembly

System

encapsulation

(Sealing)

Testing for

sealing

Testing for

electrical and performance

functions

Product packaging

Shipping

( P a c k a g e d

s u b - g r o u p s )

(1)

(2)

(3)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

(14)

(15)

(16)

(17)

Assembly: Steps (6) and (12)Packaging: Steps (3), (7), (9) and (16)Testing: Steps (2), (8), (11), (14) and (15) -fabrication: Steps (4), (5), (10), (13)


7/85

Part 1

Microassembly

Microassembly = the assembly of objects with microscale and/or

mesoscale features under microscale tolerances.


8/85

The High Costs in Microassembly

￭ We have defined microcomponents of MEMS and microsystems to be in the dimensionsranging from 1 µm to 1 mm

￭ Thus, most of them cannot be seen by naked human eyes

￭ Almost all assembly of microcomponents have to be performed under microscopes

￭ There are huge number of microcomponents to be assembled by MEMS industry:

MST

Products

1996 Units

(millions)

1996 Revenue

($millions)

2002 Units

(millions)

2002

Revenue($millions

)

2006 Units

(millions)

2006

Revenue($million)

Established

Products

1595 13033 6807 34290 10282 48461

Emerging

Products

33 107 1045 4205 1720 6937

Total 1628 13140 7852 38495 12002 55398

Source: NEXUS , hhtp://www.wtec.org/loyala/mcc/mes.eu/pages/chapter-6.html


9/85

The Needs for Cost-Effective Assembly of Microsystems

● By reliable estimate, there are 12 billion units worth $50 billion of microscaledproducts to be in the marketplace in 2006.

● Among them, there are 2+ billion units are “read-write heads” for hard disk drives,“inkjet printer heads” and “inertia sensors” that are automatically assembled.

● The remaining 10 billion units would be assembled with some degree of automation, or entirely assembled by human effort.

● Manual assembly of MST products is prohibitively expensive, tiresome and

time consuming. Often, the products would not meet the extremely stringent

requirements in precision and thus the necessary quality and reliability of

the finished products.

● Awkward assembly and packaging techniques used by the MST industry are

the major stumbling blocks to successful marketing, and thus capitalizing the

enormous full potential benefits of microsystems technology.


10/85

Main reasons for lack of automated microassembly technology:

●There is lack of standard procedures and rules for such assemblies:Products are assembled according to the specific procedures based either on

individual customer requirements, or on the personal experience of the design

engineer

● There is lack of effective tools for micro assemblies:Tools such as micro grippers, manipulators and robots are still being developed

● Micro assemblies require reliable visual and alignment equipment:

Such as stereo electron microscopes, electron-beam, UV stimulated beam or

ion beam imaging systems specially design for microsystems assembly

● Lack of established methodology in setting proper tolerances:

The strategies for setting tolerances in parts feeder , grasp surface to mating surface,

fixtured surface to mating surface, etc. have not been established for micro assembly

● Micro assemblies are physical-chemical processes related withstrong material-dependence:Traditional assembly techniques are not suitable for micro devices because of the

minute size of the components and the close tolerances in the orders of sub-microns.

Moreover, chemical and electrostatic forces dominate in micro assembly, whereas

gravity and physics are primary consideration in macro assemblies. There is littletheory or methodology developed to deal with these problems in micro assemblies.


11/85

Four Reasons for High Cost of Microassembly

￭ No standard procedure for microassembly

￭ Lack of effective tools for:

● Microgripping● Manipulating● Reliable visual and alignment

● Stereo imaging

￭ Lack of established methodologies in setting tolerances in:

● Insertion and assembly

￭ Lack of understanding in the influences of non-conventional forces,e.g., the interface electrostatic and atomic/chemical forces during

microassembly


12/85

Microassembly Processes

￭ Parts feeding

￭ Part grasping by microgrippers, manipulators and robots

￭ Part mating by specially designed tools

￭ Part bonding and fastening

● Wire bonding●

Special surface bonding

￭ Encapsulation and passivation

● Mechanical and physical/chemical encapsulation● Vacuum packaging

￭ Sensing and verification

● Visual inspection for structural integrity● Performance testing


13/85

Major Technical Problems in Microassembly

- setting proper tolerances￭ Dimensional tolerances inherited from microfabrication:

0.30.2 µm/10x10 or larger Ni, PMMA, Au,ceramics

LIGA process

0.1Sub- µm-wafer sizeSi crystalSilicon-on-insulators

0.5Sub- µm-wafer sizePoly-Si, Al, TiPoly-siliconsurfacemicromachining

0.1Sub- µm-wafer sizeSi, GaAs, quartz,

SiC, InP

Dry etching

1.0Few µm – wafer sizeSi, GaAs, quartz,

SiC, InP

Wet anisotropic

etching

Dimensional

Tolerance (µm)

Minimum/Maximum

Sizes

MaterialsFabrication Processes


14/85

Major Technical Problems in Microassembly - setting proper tolerances (Cont’d)

￭ Geometric Tolerances:

● Relating to the discrepancy of the geometry of microcomponents produced bymicrofabrication processes and the intended application of the microsystem.

● Improperly setting of this tolerance may cause serious misfit in assembly:

V

Fixed Electrodes Moving

Electrodes

w d

L

L = length

w = width

d = gap

with “fingers”

W=2 µm

L = 4 0

µ m

2o

4.8 µm

W=2 µm

2o

4.8 µm

3 6 µ m

4 0 µ m

dt = 1.74 µm

db = 3 µm

(a) Resonator actuated by comb-drive (b) An electrode finger with 2o tapered edges

(c) Variation in gaps

Figure 11.5


15/85

Major Technical Problems in Microassembly - setting proper tolerances (Cont’d)

￭ Alignment Tolerances:

● Proper setting is necessary in “inserting” and “placing” of parts

● This tolerance relates to specific applications, e.g., bioMEMS and OptoMEMS

● In most cases, these tolerances < 1 µm

￭ Other Tolerances:

● Part feeders

● Grasping surface to mating parts

● Fixture surface to mating surfaces


16/85

Tools and Fixtures for Microassembly

Major problem in microassembly is the minute size of microcomponents to be assembled

Many components can only be viewed under microscopeswith magnification at 300X - 500X

For typical optical microscope, the working distance

(the gap between the objective lens and the microcomponent) dis inversely proportional to the magnification:

d y

Y X

1∝=

Y

y

WorkingDistance

d

Ocular Lens(Eyepiece)

Objective Lens

The small d for large X means very small working space formicroassembly tools, e.g., microgrippers, or other fixtures→ tools and fixtures with very low aspect ratios

(aspect ratio = dimension in height to length)

Tools with high aspect ratios may not have sufficient rigidityto provide high precision pick-n-place operations →difficult in precision control without feedback tactile sensor feedback

Microgripper with LONG arms


17/85

Contact Problems in Microassembly Tools

● “Pick-n-Place” by microgrippers or micro robotic end-effectors are common

and necessary practice in microasdsembly

● This practice requires the tool surface to be in contact with that of the micro-components to be “picked” from one location and “placed” at another location.

● Adhesive forces on the contacting surfaces of minute pieces develop, e.g.,

in the effort to peel of thin light-weight piece of paper from a transparency

● These adhesive forces likely developed between the surface of the tools

and that of the microcomponents – due to electrostatic and chemical

(atomic or van der Waals) forces.

● In the Pick-n-Place operations in microassembly, there is no problem in “Pick”

but often cannot “release” for the “Place” part of the operation because ofthese adhesive forces compounded by insignificant gravity (weight) effect


18/85

d F l a t G r i p p e r A

r m s

d

δ

GrippingForce

Gravitation(insignificant)

AdhesiveForce

Gravitation

Grasping: Releasing:

● Gravitation of minute objects is insignificant in pick-n-place operations.

As such, induced adhesive forces may dominate in this operation.

● These adhesive forces cause great difficulty in releasing the object at the

end of the operation:

Adhesive Forces in Micrograsping


19/85

Adhesive Forces in Micrograsping

● There are two principal contributing sources for the adhesive

forces:

● Van der Waals force, and● Electrostatic force.

● In wet assemble, or assembly in humid environment, the

“surface tension” of the fluid between the contacting surfacesbecome the 3rd adhesive force component.

● Exact quantification of these forces is not possible.

● Use a case involving Pick-n-Placing a sphere by a pair of

flat plate gripping arms for assessing the adhesive forces:


20/85

212 δ η

d AF v =

Adhesive forces in Pick-n-Placing of a sphere by a pair of flat

plate gripping arms:

(1) Van der Waals force (d < 100 nm, or 0.1 µm):

where A = Hamaker constant = 10-20 to 10-19 J

δ = atomic separation between the contacting surfaces

typically at 4 to 10

η = correction factor for rough surfaces (≈ 0.01)

(2) Electrostatic force (10 µm < d < 1 mm):Induced in picking portion of the process due to

charge-generation, or charge- transfer during the contact.

2

2

4 d

qF e

ε π =

where q = electrostatic charge, ≈ 1.6x10-6 C/m2 in microgripping

ε = permittivity of the dielectric, = 8.85x10-12 C2 /N-m2

d = diameter of the sphere (10 µm to 1 mm)

(3) Surface Tension:

d

δ

Adhesive

Force, F

Gravitation(insignificant)

F l a t

g r i p p i n g a r m

o

A

Total adhesive force in assembly: F = Fv + Fe + Fs

γ sF s =where s = perimeter of microvoid in contacting area

γ = coefficient of surface tension


21/85

● An integrated micropositioner:

● Linear movement with step sizes: 0.3 µm in X-Y and 0.07 µm in the Z-axis● Rotation about both X & Y axes at 0.0028o /step.

● Resolution in linear movements: 40 nm.

● Microscope optics and imaging unit.

Require long working distance to 30 mm with 1 µm resolution.

● Micromanipulator unit:

● Microgripper with special end-effector, or micro tweezers.● Provide proper gripping forces, and be able to overcome the induced

adhesive forces in releasing the object.

● A high precision transfer tool.

For transporting dies in wafers, or trays with discrete parts.

● A real-time computer with vision for precision alignment:

● Controls movements of transfer tools, micro positioner and micro manipulator.● Implement assembly strategy, process monitoring, diagnosis and error recovery.

● A portable class 100 clean room.

Essential Elements of an Automatic Microassembly Work Cell

Microassembly Work Cells


22/85

Integrated

Micro-positioner

with Micro ServoActuator:

(Linear in X & Y

+

Rotations about x-Y)

Microtweezers

or manipulator

S t e r e o M i c

r o s c o p

e

& c a m

e r a

S t e r e o M i c r o s c o p e

& C a m e r a

Vertical Microscope

& Camera

Portable Clean Room (class 100)

PC

Micro-controller

cards + operationsoftware

Optics

A Typical Automatic Microassembly Work Cell


23/85

An Experimental Microassembly Work Cell at Sandia National Laboratory

Grasping a ring by a

micro tweezers


24/85

An Experimental Automatic Microassembly Work Cell

at University of New Mexico


25/85

An Experimental Automatic Microassembly Work Cell

at University of Minnesota

Micro positioner

Micro manipulator


26/85

Part 2

Packaging of Microsystems


27/85

Overview of Mechanical Packaging of Microelectronics

● To provide support and protection to the IC, the associate wire bonds and

the printed circuit board from mechanical or environmentally induced

damages.

•To dissipate excessive heat generated by electric heating of the IC.

Objectives of mechanical packaging of microelectronics:

Chip (L0)

Module (L1)

Card (L2)

Board (L3)

Gate (L4)

Level 1

Level 2

Level 3

Level 4The 4 levels of microelectronics packaging:

Level 1: Silicon chip into a module.

Level 2: Card level.

Level 3: Cards to boards

Level 4: Boards to system

Level 1 and 2 are of primaryinterest to mechanical engineers.


28/85

Overview of Mechanical Packaging of Microelectronics – Cont’d

Level 1 & 2 packaging:

Wire bondSi die

Die pad

Interconnect

J-Lead

Interconnect

Gull-wing Lead

Solder joint Solder joint

Printed Circuit Board (or Wirebound) Board

Die attach

Silicon die

with ICEpoxy

encapsulant

Die pad and

die attach Wire bond

I n t e r

c o n n

e c t s

S o l d e

r j o i n

t s

Printed circuit board

P r i n t e d

c i r c u i t

Principal components in a chip: Plastic encapsulated chip:

Reliability issues:

● Die and passivation cracking.

● Delamination between the die, die attach, die pad and plastic passivation.

● The fatigue failure of interconnects.

● Fatigue-fracture of solder joints.

● The warping of printed circuit board.

Failure mechanisms:

● Mismatch of coefficients of thermal expansion between the attached materials.

● Fatigue-fracture of materials due to thermal cycling and mechanical vibration.

● Deterioration of material strength due to environmental effects such as moisture.

● Intrinsic stresses and strains from fabrication processes as described in Chapter 8.


29/85

There is no standards in packaging materials and methodologies adopted by

the industry at the present time.

MEMS and Microsystems Packaging

• Most MEMS and microsystems packaging have been carried out on thebasis of specific applications by the industry.

Little has been reported in the public domain on the strategies,

methodologies, and materials used in packaging of MEMS and

microsystem products.

Current state:

1990 1995 2000 2005 2010 2015 2020

Materials

Equipment

Design & modeling;

Testing

Interconnect

Process

Packaging

C a t e g o r i e s

Standards Timeline


30/85

Objectives of microsystems packaging:

• To provide support and protection to the delicate core elements (e.g. dies),the associate wire bonds and transduction units from mechanical or

environmentally induced damages (e.g. heat and humidity).

• Most of these elements requiring protection are required to interface withworking media, which may be environmentally hostile to these elements.

Interface is thus a major concern in microsystems packaging.

Diverse signal transduction in mcirosystems:

YesYesOptical

YesYesMechanical

YesMagnetic

YesYesFluid/hydraulic

YesYesElectrical

YesYesChemical

OutputInputSignals

MEMS and Microsystems Packaging – Cont’d


31/85


General considerations:

● The required costs in manufacturing, assemblies and packaging of the components.

● The expected environmental effects, such as temperature, humidity, chemical

toxicity, etc. that the product is designed for.

● Adequate over capacity in the packaging design for mishandling and accidents.

● Proper choice of materials for the reliability of the package.

● Achieving minimum electrical feed-through and bonds in order to minimize theprobability of wire breakage and malfunctioning.

The scope of this chapter:

● On silicon-based microsystems only.

● Packaging of microsystems produced by LIGA processes are not covered inthis chapter.


32/85

Level 1: The “die level”,Level 2: The “device level”, andLevel 3: The “system level”.

Sensing

Element

Actuating

Element

Die Packaging:

Signal Mapping

& Transduction

Signal

Conditioning &

Processing

Power

Supply

Device packaging:

System Packaging:

Output

Motion

Input

Action

Output

Signals


The 3 levels of microsystems packaging


33/85


Die-level packaging:Dies in most microsystems are the most delicate components, which requireadequate protection. Thus the objectives of this level packaging are:

● To protect the die or other core elements from plastic deformation and cracking,● To protect the active circuitry for signal transduction of the system,● To provide necessary mechanical isolation of these elements, and● To ensure the system functioning at both normal operating and over-load

conditions.Die-level packaging often involves wire bonding:

Silicon

Diaphragm

Pyrex Glass

Constraining

Base

Metal

Casing

Passage for

Pressurized

Medium

Silicon gel

Wire bond

Metal filmDielectric layer

Piezoresistor

Die

Attach

Interconnect

Si die

Die attach

Wire bond(Si gel)

Plastic encapsulant

Metal coverInterconnect

Pressurized

medium inlet

Pressure sensor with metal casing:Pressure sensor with plastic encapsulation:


34/85


Device-level packaging:

Sensingelement

Actuating

element

Signal mapping

& transduction

Signal

conditioning

& processing

Inputaction

Output

motion

Output

signals

Power

supply

● electric bridges

● signal conditioning circuits

● Proper regulation

of input power Major technical problems:

● The interfaces of delicate dies and core elements with other parts of thepackaged products at radically different sizes, and

● The interfaces of these delicate elements with environmental factors, such astemperature, pressure and toxicity of the working and the contacting media.


35/85

MEMS and Microsystems Packaging – Ends

System-level packaging:

● This level packaging involves the packaging of primary signal circuitry withthe package of the die or core element unit.

● Major tasks involve proper mechanical and thermal isolation as well as

electromagnetic shielding of the circuitry.

● Metal housings usually give excellent protection for mechanical andelectromagnetic influences.

● MEMS devices or microsystems at the end of this packaging level are readyto be “plug-in” to the existing engineering systems:

Packaged inertia

Sensor for airbag

Deployment system


36/85

The packaged systems need to be biologically compatible with humansystems and they are expected to function for a specified lifetime.

Every micro biosystem must be built to satisfy the following requirements

that are related to interface:

• It is inert to chemical attack during the useful lifetime of the unit.• It follows mixing with biological materials in a well-controlled manner

if it is used as biosensors.

• It causes no damage or harm to the surrounding biological cells in thecases of instrumented catheters such as pace makers.

• It causes no unwanted chemical reactions such as corrosion between thepackaged device and the contacting human body fluids, tissue and cells.

All biomedical devices and systems are subject to FDA regulations.

Interfaces in Microsystems Packaging

● Various parts, in particular, the delicate dies of microsystems are expected to be incontact with various working media, e.g. chemicals, optical, corrosive gases, etc.

● Interface between these parts with working media becomes a major design issue in

packaging.

Biomedical interfaces


37/85

Optical interfaces

There are two principal types of optical MEMS:

• The devices that direct lights, e.g. micro switches involvingmirrors and reflectors.

• Optical sensors.

Optical MEMS require:

• Proper passages for light beams to be received and reflected.Fiber-optics are common light conduits in optical MEMS.

• Proper surface coating for receiving and reflect lights.• The quality of the coating must be enduring during the lifetime of the device.• The surfaces must be free of contamination of foreign substance.• The enclosure must be free of moisture. The presence of moisture may

cause stiction of the enclosed components.

Interfaces in Microsystems Packaging – Cont’d


38/85

Electromechanical interface

Electrical insulation, grounding and shielding are typical problemsto be dealt with in MEMS and microsystems packaging.

Interfaces in microfluidics

• Precise fluid delivery.• Thermal and environmental isolation and mixing.•

Material compatibility between the fluid and the containing walls.• Interface of the fluid and containment wall, e.g. corrosion, friction, etc.• Another major interface problem is in sealing

Interfaces in Microsystems Packaging – Ends


39/85

Die preparation

• Dies, or substrates in MEMS, are normally cut(sliced) from single wafers using thin diamond

saw blades.

Enabling Packaging Technologies

Spacing between dies: ≈ 50 µm with saw blade thickness of 20 µm.Cutting wheel: 75 – 100 mm diameterCutting speed: 30,000 – 40,000 rpm.

E bli P k i T h l i


40/85

Surface bonding

There are four (4) techniques available for surface bonding in MEMSand microsystems:

(1) Adhesives(2) Eutectic soldering(3) Anodic bonding(4) Silicon fusion bonding (SFB)

Enabling Packaging Technologies – Cont’d

Bonding by adhesives:

● Epoxy resin and silicone rubbers are two

commonly used adhesives.

● Good bonding by epoxy resin rely on

surface treatments and curing process

control. Avoid glass transition temperature

at 150-175

o

C.

● Soft silicone rubbers are used for bonding

parts require “flexibility.” It is vulnerable

to chemicals and air. A typical micro dispenser ofepoxy resins (Courtesy of

Asymtek Co., Carlsbad, CA

E bli P k i T h l i C ’d


41/85

Surface bonding – Cont’d


Eutectic bonding:

● Eutectic bonding involves the diffusion of atoms of eutectic alloys into theatomic structures of the materials to be bonded together.

● Must first select a candidate material that will form a eutectic alloy with thematerials to be bonded.

● A common material to form eutectic alloywith silicon is thin films made of goldor alloys that involve gold.

● Gold-tin (80% Au+20% Sn) films around 25 µmthick is commonly used.

● Bonding takes place at about 300oC.

● Offers much solid bonding than adhesives.

Si Substrate

Doped Si

Weight

Heat

Au/Sn Film

Enabling Packaging Technologies C t’d


42/85



Anodic bonding:

● Bonding wafers of different materials.

● Also called “electrostatic bonding” or “Field-assisted thermal bonding.”

● It is popular because of simple set-up and inexpensive equipment.

● Bonding temperature is relatively low in the range: 180-500oC.

● Possible to bond wafers of:● Glass-to-glass● Glass-to-silicon● Glass-to-silicon compounds● Glass-to-metals● Silicon-to-silicon

● Most common application is for Glass-to-silicon wafer bonding.

Enabling Packaging Technologies Cont’d


43/85



Anodic bonding-Ends

The working principle of Glass-to-silicon wafer bonding:

Weight for contacting pressure (Cathode)

Glass wafer

Silicon wafer

Heated mechanical support (Anode)

Applied DC voltage:

200-1000 volts

SiliconSi+

Si+

Si+

Si+

Si+Na+←

Na+←Na+←Na+←Na+←

O2-

O2-

O2-

O2-

O2- S i O 2 l a y

e r

Glass

Hot Plate (Anode)Weight for contact

Pressure (Cathode) ≈ 20 nm

Bonding interface

Na Depletion

Layer ≈ 1 µm

Enabling Packaging Technologies Cont’d


44/85


Enabling Packaging Technologies – Cont d

Silicon Fusion bonding

● Silicon fusion bonding is like “welding” a silicon wafer to another silicon wafer.● It is relatively simple and inexpensive bonding method.● Silicon fusion bonding (SFB) has been used to bond:

● Silicon-to-silicon● Silicon with oxide-to-silicon● Silicon with oxide-to silicon with oxide● GaAs-to-silicon● Quartz-to-silicon

● Silicon-to-glass● It is the induced chemical forces that bond the pieces together.● Wafer surfaces need to be extremely flat (at 4 nm) to be bonded.● Bonding strength between silicon wafers can be as high as 20 MPa.● The SFB process begins with thorough cleaning of the bonding surfaces.

These surfaces must be polished, then make them hydrophilic by exposingthem in boiling nitric acid.

● These two surfaces are naturally bonded even at room temperature.● Strong bonding occurs at high temperature in the neighborhood of

1100oC to 1400oC.

Wire Bonding


45/85

● The three (3) wire bonding techniquesused in IC industry are adopted forMEMS and microsystems:● Thermocompression wire bonding

● Wedge-wedge ultrasonic bonding● Thermosonic bonding.

● Common wire materials are Au, Ag, Al,Cu and Pt with diameters at 20-80 µm.

● Wire bonding is fully automatic.

Silicon

Diaphragm

Pyrex Glass

Constraining

Base

Metal

Casing

Passage forPressurized

Medium

Silicon gel

Wire bond

Metal filmDielectric layer

Piezoresistor

Die

Attach

Interconnect

Si dieDie attach

Wire bond(Si gel)

Plastic encapsulant

Metal coverInterconnect

Pressurized

medium inlet

Wire Bonding

● Wire bonding techniques developed for microelectronics are applicable for

bonding electric lead wires in MEMS and microsystems.

Wire Bonding C t’d


46/85

Wire Bonding – Cont’d

Thermocompression wire bonding

● Wire bonding is accomplished with mechanical compression at elevatedtemperatures at about 400oC.

● The bonding process is illustrated as:

Capillary

Tool

Metal Wire

(HEAT)

Substrate

Metal Pad

Substrate

Substrate

● Heat the wire to form a bead

● Feed the bead to the pad by

pulling down the capillary tool:

● Compress the bead topad mechanically:

● Retract the capillary tool

after the bead is bondedto the pad:

Wi B di E d


47/85

Wire Bonding – Ends

Wedge-wedge ultrasonic bonding

● This bonding process takes place at room temperature.● The energy supply to the bonding is from ultrasonic vibration of the tool

at 20 – 60 kHz.●

The process is illustrated as:

Wedge

Bonding

Tool

Wire

Tool Direction

Metal PadsMetal pad

Substrate

Wedge

Bond

WireWedge

Bonding

Tool

Metal Pads

Thermosonic bonding

● This process uses ultrasonic energy with thermocompression.● As such, wire bonding can take place at 100-150oC.● Joints can be in either ball-wedge or wedge-wedge form.

With mechanical

compression

Sealing


48/85

Sealing

• Sealing is a key requirement in MEMS and microsystems packaging.

• Hermetic sealing is essential in devices or systems such as: microfluidic,optoMEMS, bioMEMS, pressure sensors, etc.

• There are generally 3 sealing techniques available for MEMS and microsystems:(1) Mechanical sealing technique:

• Epoxy for microfluidics. It is flexible but ages with time.● Eutectic soldering for hermetic seals.

(2) Sealing by microfabrication processes - Sealing by micro shells:

Doped silicon PSG sacrificial

layer

Die

Constraint base Constraint base

Doped silicon

micro shell

(a) With sacrificial layer (b) After the removal of sacrificial layer

S li E d


49/85

Sealing(3) Sealing by chemical reactions:

• Sealing is accomplished by “growing” the sealant using chemical reactions.

• Example is the production of SiO2 as the sealant for sealing a delicate die

with a silicon shell.

• The growth of SiO2 from the silicon encapsulant to the constraint baseprovides reliable and hermetic seal for the die.

Si Constraint base

Silicon shell

Si Constraint base

SiO2seals

SiO2seals

Die Die

SiO2 film

(a) Unsealed encapsulant (b) Sealed encapsulation by oxide

grown from silicon shell

Sealing – Ends

3-Dimensional Packaging


50/85

3-Dimensional Packaging

● 3-dimensional packaging is a popular R&D topic in microelectronics

packaging.

● Principal reasons for 3-D packaging are:

● Provides high volumetric efficiency,● Provides high-capacity layer-to-layer signal transport.

● Has the ability to accommodate wide range of variation of layer types.● Has the ability to isolate and access a fundamental stackable

element for repair, maintenance or upgrading.● Has the ability to accommodate multiple modalities, e.g. analog,

digital, RF power, etc.

● Provides adequate heat removal among the package layers.● Allows for high pin-count delivery to the next level of packaging with

high electrical efficiency.

3-D microelectronics packaging

3-Dimensional Packaging Ends


51/85

3-Dimensional Packaging - Ends

3-D MEMS and microsystems packaging

● Package MEMS and microsystems with distinct functions stacked upwith signal processing units in compact configurations

● Shielding of electromagnetic and thermal effect, and hermetic sealing of movingfluids are the critical issues in 3-D packaging.

x

y

Accelerometer

for x-direction

Accelerometer

for y-direction

Signal conditioning

and processing

Acceleration

in x-direction

Acceleration

in y-direction

Signal conditioning

and processing

x

y

Planar (2-D) packaging

3-D packaging

V S li d E l ti


52/85

Vacuum Sealing and Encapsulation

Many MEMS and microsystems can perform better, or can only performin vacuum.

It is a very important requirement for many MEMS and microsystems.

Examples such as microgyroscopes and micromirrors in micro fiber optical switchesrequire vacuum to provide free air-resistance and a moisture-free environment.

High vacuum in the MEMS devices must be maintained while the system

is packaged.

Hermetic and enduring sealing is required to maintain vacuum in the system.

Two vacuum sealing techniques will be introduced here:

(1) Vacuum sealing by RTP bonding process, and

(2) Vacuum sealing by localized CVD process.

V S li d E l ti


53/85

Vacuum Sealing and Encapsulation

Many MEMS and microsystems can perform better, or can only performin vacuum.

It is a very important requirement for many MEMS and microsystems.

Examples such as microgyroscopes and micromirrors in micro fiber optical switchesrequire vacuum to provide free air-resistance and a moisture-free environment.

High vacuum in the MEMS devices must be maintained while the system

is packaged.

Hermetic and enduring sealing is required to maintain vacuum in the system.

Two vacuum sealing techniques will be introduced here:

(1) Vacuum sealing by RTP bonding process, and

(2) Vacuum sealing by localized CVD process.

Vacuum Sealing – Cont’d


54/85

Cap wafer

Al-to-nitride bond

Device wafer

Heating Elements

Quartz Tube

To vacuum pump

Example of Sealing by RTP bonding

RTP = Rapid Thermal Processing, a process that is commonly used in IC packaging

Two wafers:

Cap wafer = the wafer with cavity for passivation of the deviceDevice wafer = the wafer with microcompenents

Both the device and cap wafers are pre-baked in vacuum at 300oC for 4 hours in a vacuum

quartz tube to drive out and entrapped gas from microfabrication processes.

The two wafers are assembled and loaded into a sample holder and placed in the vacuum

heating tube again.The set is then placed inside of the RTP equipment and the base pressure was pumpeddown to about 1 mTorr .

The vacuum was held steady for about 4 hours to drive out entrapped gas inside the cavity.

The sealing is completed by RTP heating in 10 s at 750o

C.

Vacuum Sealing – Cont’d


55/85

Example of Sealing by localized CVD process

Glass cap

Microheater

Vent

Silicon substrate

MicrostructureCVD

Deposition

Vacuum Cavity

The set is put into a vacuum chamber at about 250 mTorr with the flow of silane gas.

The microcomponent is assembled to the silicon substrate.

The silicon substrate with assembled microcomponent is anodically bonded to a glass cap.

A vent hole is created in the assembly.

There is a small heater at the vent hole made by electrically conducting polysilicon

The intense heat release by the microheater decomposes silane for localized polysilicondeposition to seal the venting hole as shown in the right of the Figure.

The CVD deposition process provide the necessary seal for the microdevice

Selection of Packaging Materials


56/85

g g

● There are a broad range of materials used in packaging MEMS and microsystems.● Commonly used materials for various parts of MEMS and microsystems are:

Refer to Chapter 7 and

Section 10.2.2 for selection.

Materials are in order of

Increasing quality and cost.

Pyrex and alumina are more

commonly used materials

Solder for better seal, silicone

rubber for better die isolation.

Gold and aluminum are popular choices.

Silicon, polycrystalline silicon, GaAs,

ceramics, quartz, polymers

SiO2, Si3 N4, quartz, polymers

Glass (Pyrex), quartz, alumina, silicon

carbide

Solder alloys, epoxy resins, silicone

rubber

Gold, silver, copper, aluminum andtungsten

Copper and aluminum

Plastic, aluminum and stainless steel

Die

Insulators

Constraint base

Die bonding

Wire bonds

Interconnect pins

Headers and casings

Remarks Available MaterialsMicrosystem Components

Selection of Packaging Materials – Cont’d


57/85

Summary of die packaging material properties:

2.33

6.0-7.0 (25-300oC)

26

63 below 126oC

140 above 126oC

370

0.29

0.27

0.44

0.49

190,000

344,830-408,990 (20oC)

344,830-395,010 (500oC)

31,000

4,100

1.2

Silicon

Alumina

Solder (60Sn40Pb)

Epoxy

(Ablebond 789-3)

Silicone rubber

(Dow Corning 730)

Thermal Expansion

Coefficient ppm/oK)

Poisson’s ratioYoung’s Modulus (MPa)Materials

Selection of Packaging Materials – Ends


58/85

Temperature-dependent properties of epoxy resin (Ablebond 789-3):

55

601.5

Same as above

Same as above

Same as above

0.42

0.420.49

Same as above

Same as above

Same as above

at –40oC: 7,990

at 25oC: 5,930at 125oC: 200

at –40oC: 4,680

at 25oC : 4,360

at 125o

C: 110

at –40oC: 3,830

at 25oC: 3,620

at 125oC: 60

at –40oC: 3,610at 25oC: 2,650

at 125oC: 40

at 25oC: 1,790

at 125oC: 30

0 – 500

500 – 2,000

2,000 –10,000

10,000 – 20,000

20,000 – 30,000

Fracture strength

(MPa)

Poisson’s ratioYoung’s modulus (MPa)Strain range (10-6)

Signal Mapping and Transduction


59/85

Signal Mapping:

Develop and establish strategies in selecting both the type and positions

of the transducers for the MEMS device of microsystem.

Transducers Electric signals Input or Output Typical applications

Piezoresistors

Piezoelectric

Capacitors

Electro-resistantheating/Shapememory alloys

Resistance, R

Voltage, V

Capacitance, C

Current, i

Output

Input or Output

Input or Output

Input

Pressure sensors

Actuators,accelerometersActuators byelectrostatic forces,

Pressure sensorsActuators

Common Transducers for MEMS and Microsystems

Signal Mapping and Transduction

Signal Mapping and Transduction – Cont’d


60/85

Signal mapping for a micro pressure sensor:Piezoresistors are used to sense the change of electrical resistance relating to theInduced stresses at the location.

Three locations are chosen for these piezoresistors in the following 3 cases:

Outline of diaphragm

Piezoresistors

Outline of silicon die

4 5 o

Case 1: Square die/square diaphragm:

Case 2: Rectangular die/rectangular diaphragm

Case 3: For shear deformation in square diaphragm



61/85

VoVin

R1=Rg

R2

R3

R4

+

-a

b

Signal transduction by Wheatstone bridge:

● 4 gages involved in the bridge.● R1= Rg – the variable resistance

R2, R3 and R4 have fixed resistance.

■ For static conditions:

The voltage Vo is adjusted to zero:

R

R R Rg

2

43= (11.6)

■ For dynamic conditions:The voltage Vo changes with time, and the changesare recorded.

The change of the measured resistance is:

1

132

32

3

1

4

1 3

−

+−∆

−

⎟ ⎠ ⎞⎜

⎝ ⎛

++∆

=∆

R R R

V

V

R R R

V V

R R

R

R

in

o

in

o

g(11.8)

where R1 = the original value of Rg



62/85

Signal transduction bridge for capacitance measurements:

Vo Vin

C C

CVariablecapacitor

● 4 capacitors are involved in the bridge.

● There are 3 identical capacitors with

capacitance C.● The 4th capacitor with varying capacitance,

e.g. with gap change between two plate

electrodes.

● The bridge is subjected to a constant input

voltage, Vin.● The variation of capacitance, ∆C in this

capacitor may be obtained from the

measured output voltage, Vo:

V V V

C C

oin

o

2

4

−=∆(11.9)

Design case: Packaging of Micro Pressure Sensor Dies


63/85

Primary packaging considerations

● The die in a pressure sensor is to support the thin diaphragm that sensesthe medium pressure by the induced stresses.

● For accurate sensing the medium pressure, the stresses that the diaphragmhas sensed should be those stresses induced by the medium pressure ONLY.

● Unfortunately, there could be stresses induced in the diaphragm by sourcesother than the medium pressure – the “parasite stresses”.

● A major source of parasite stress is from the thermal stresses induced bysignificantly different CTE of various components attached to the diaphragm:

Constraint base (Pyrex): : 7 ppm/ oC

Die attach

(60Sn40Pbsolder):

: 26 ppm/ oC

Silicon die:

: 2.33 ppm/ oCSilicon diaphragm

Dielectric film

● How to ISOLATE the die/diaphragm from these sources of parasite stressesbecome a primary consideration in the packaging design.

Design case: Packaging of Micro Pressure Sensor Dies – Cont’d


64/85

Die down

● It is a process to bond the die to the constraint base with “die attach”.

● Three commonly used bonding techniques:

● Anodic bonding● Eutectic soldering

● Adhesive

Constraint base

Die attach

Silicon dieSilicon diaphragm

Height

H

Constraint base

Die attach

Silicon dieSilicon diaphragm

Height

H

Spacer

L

Normal die down Die down with “spacer” for die isolation:

The extension of the height by the spacerincreases the flexibility and thereby reducesthe parasite thermal stress.Disadvantage: takes up extra space.



65/85

Die protection

● The delicate die in a pressure sensor needs to be protected from possibledamage by the contact pressurized medium.

● There are three (3) ways to do this:

(1) By vapor-deposited organic on the die surface:

The deposited organic coating will insulate the die surface from the contactmedium. Unfortunately the deposited organic also serve as a “reinforcement”

and make the diaphragm undesirably stiff.

Silicon die

Thin organic protective layer

Glass constraint base



66/85

Die protection –Cont’d

(2) By coating with silicone gel:

● Silicone gel containing one or two

parts of siloxanes has very lowYoung’s modulus. So, it is very soft.

● Being soft, it would not addunwanted stiffness to the diaphragm.

● A few mm thick coating givessufficient protection to the die.

● The only problem is aging and

become contaminated withimpurities from the contact medium.



67/85

Die protection –Cont’d

Diaphragm in contact with

pressurized medium

Ball seal

Oil fill

HeaderTIG weld

Stainless

casing

Ceramic volume

compensator

(3) Indirect pressure transmission:

● This method is used in situation in

which the pressurized medium is soenvironmentally hostile that directcontact of the die and medium isnot possible.

● A special arrangement is made for

a special case that involved:● P = 70 kPa – 350 MPa● Impact force = 10-20,000 g● T = 5,000oF in milliseconds● Media contain high-velocity dusts

● Die and wirebonds are submerged in silicone oil.● Pressure from the media was transmitted to the diaphragm through silicon oil.● The stainless steel diaphragm has compliance is 100 times less than that of

silicon diaphragm.● Minimum volume of silicone oil in order to mitigate thermal expansion.


68/85

Part 3

Reliability and Testing of Microsystems

Reliability Testing for ICs and Microelectronics


69/85

y g

These routine tests are performed before the products are shipped tothe customers:

Thermal Shock Tests

-60oC

+100oC

∆t according to specification Time, t T e m p e

r a t u r e ,

T ( t )

Thermal Cycling Tests

-60oC

+100oC

Time, t T e m p e r a t u r e , T

( t )

∆t1 ∆t2

∆t3

Burn-in Tests Products are placed in autoclaves at specified temperaturesand humidity for hundreds of hours for endurance tests.

Reliability of MEMS and Microsystems

R li bilit f IC d i l t i t t l t d


70/85

Reliability of ICs and microelectronics are more structure-related.

Reliability of MEMS and microsystems have all the issues as in ICs and

microelectronics +

Failure mechanisms for microsystems are much more complicated than thosein microelectronics for the following reasons:

● Microsystem components are designed to interact with various substances(e.g., optical, chemical and biological fluids) at various environmentalconditions (temperatures and pressures).

● Microsystem components are hermatically sealed and are expected toperform in immediate and long-terms.

● Example of the damage of stiction of delicate components in sealed plasticpackage by slow release of moisture (de-gassing) of plastic encapsulating

materials – impossible to predict and prevent.Unlike IC and microelectronics, NO standard is available for reliability testing forMEMS & microsystems.

New testing procedures and criteria need to be developed for every new product.

many more issues related to their performances both uponshipping and in the subsequent in-service in the designedlife span.

Failure Mechanisms in MEMS and Microsystems


71/85

HighTemperature, humidity, dusts and toxic gasEnvironmental effects

HighImproper bonding and sealing, poor dieprotection and isolation

Packaging

HighResidual stresses and molecular forces

inherent from microfabrication.

Excessive intrinsic

stresses

Moderate Aging and degassing of plastic and polymers.Corrosion and erosion of materials

Deterioration of

materials

HighCollapse of electrodes due to excessive

deformation.

Electromechanical

break-down

Low

Moderate

Low in silicon,moderate in plasticModerate to high

High

▪ Local stress concentration due tosurface roughness.

▪ Improper assembly tolerances▪ Vibration-induced high cycle fatigue

failure.▪ Delamination of thin layers.▪ Thermal stresses by mismatch of CTE.

Mechanical

ProbabilityCausesFailure Mode

Testing for Reliability of MEMS and Microsystems

Reference: “MEMS Packaging,” ed. T.R. Hsu, IEE, United Kingdom, 2004.


72/85

Following major tasks are involved:

● Design for testing:● Set the testing strategy, e.g., identifying testing points.

● Parametric testing

● Testing during assembly

● Burn-in and final testing

● Self testing

● Testing during use

Chapter 1 Fundamentals of MEMS Packaging by T.R. Hsu & J. Custer;Chapter 6 Testing and Design for Test by A. Oliver & J. Custer.

Design for Test is an important responsibility of design engineers for MEMS and microsystems

● Establish Range of Acceptable Device Performance:● Proper PASS/FAIL limits for test results●

a proper balance between Quality (being too lenient)and Waste (being too stringent)

● Performing tests:

Testing for Reliability of MEMS and Microsystems – Cont’d


73/85

Parametric testing

● For inspecting key components during and after the fabrication.

● Requires the definition of parameters, e.g., film resistances, surface stress/strainfor such testing.

● Requires proper selection of test points on the workpiece.

● Parametric test structures are attached to the workpiece for the testing.

Example 1: The van der Pauw sheet resistance test structure.

Pass current to Pad 2 & 3

Measure voltage acrossPad 1 & 4

The surface resistancein the area is:

3,2

4,1

I

V Rc =



74/85

Parametric testing - Cont’d

Example 2: Parametric test structure for measuring tensile strain.

I nd uc ed t ensi on

B u c k l i n g o f t h i n b e a m

ε

π

3

22t Lc =

The compressive strain ε responsible for the buckling of the thin beam is:

where Lc = length of the beam, t = thickness



75/85


Example 3: Parametric test structure for measuring both tensile andcompressive strains.

Beam electrodes are connected and anchored on the workpiece at shallow angles.

Tension gap change in A & B

Compression Gap change in A & C

Associated tensile or compressive strains can be correlated to the measuredcapacitances from these beam electrodes.



76/85


Example 4: Parametric test structure using resonator for monitoringsurface stresses.

Comb Drives

Springs

Vibrating

Mass

● Change of stiffness of springsdue to change of stresses inattached workpiece leads tochange of resonant frequencies.

● Resonant frequency of the resonator can be generated by electricalstimulator.

●

Shifting of resonant frequencies inthe resonator can be related to thesurface stresses in the workpiece.


Testing During Assembly


77/85

For two (2) purposes:● To determine which device components are good enough for further

packaging into devices.

● To monitor the yield of the packaging process.

Example 1: Texas Instrument’s digital micromirror device with 0.5 to 1.5 million electro-statically actuated mirrors at 16 µm x 16 µm

Micromirrors

Dies

● Mirrors offer 0 or 1 signals on its reflectedintensities.

● The open center in the array shows the CMOSbeneath that supplies voltage to rotate themirrors for reflecting lights.

● Mirrors are tested for reflecting lights atincreasing voltage supplies by the CMOS.

● Dies with mirror fails to perform are rejected.

● Further inspection on mirror functions after dies are assembled.



78/85

Testing During Assembly - Cont’d

Example 2: infrared detectors by Dexter Research Center Inc. of Dexter, Michigan

The particular device is thermopile-based single element bulk micromachined infrareddetector for home security, tympanic thermometers, fire detection, and remote temperature

measurement.

● Final assembly of device only after passing all these tests.

Series of tests during assembly:

● Electric parametric tests on wafers on:e.g., sheet and contact resistances.

● Same tests after bulk manufacturing by wet etching.

● Further Testing on:● die with infrared black coating● wafer dicing● mounting● wire bonding

● Partially packaged device exposed to calibratedblackbody infrared source, with further testing on:coating, wirebond, tilting & mounting.



79/85

Burn-in Tests for MEMS and Microsystems

● These are the tests conducted after all components are assembled into a device.

● Some microdevices can only be tested after the assembly.

● “Burn-in” tests are necessary b/c many microdevices can fail to perform due toinvasion of unwanted foreign substances, e.g., air to some packaged infrareddetectors, or dust particles and moisture to the packaged micromirrors.

● A typical failure rate history for a product – a “Bath-tub” curve:

F a i l u r e R a t e

Time (in logarithmic scale)

Useful Life

InfantMortality

Wear-out

● The GOAL of “Burn-in” tests is to have the “Infant mortality” failure of thedevice occurs in the factory, but not in the field.



80/85

Burn-in Tests for MEMS and Microsystems - Cont’d

● Requirements for proper design of Burn-in tests:

● Identify possible failure modes of the particular device.

● Identify factors that can accelerate the failure rates of the device.

● Possible factors for accelerating failure rates:

● Mechanical and thermal loading.

● Humidity.

● Shifting of applied threshold voltage.

● Arrhenius model can be used to identify accelerating loading for Burn-in tests.This model states: “device failure is dependent of the energy barrier surmountedfor failure to occur. “

● This model can relate failure rate of a device at one temperature to the failurerate at another temperature.

● We may thus accelerate the failure of a device at a higher temperature usingthis model.



81/85

Self Testing

● For MEMS and microsystems, it involves using electric stimuli that mimicsthe real input loads.

● Self testing is important to many electronics devices and computers to ensureproper functioning of various components in the device before actually usingthe device.

Cavity Cavity

Silicon Die

with

Diaphragm

Constraint

Base

Measurand

Fluid Inlet

MeasurandFluid Inlet

(a) Back side pressurized (b) Front side pressurized

● Self test device, e.g., a pair of electrodes can mimic mechanical load tomicro pressure sensors:



82/85

Self Testing - Cont’d

A self testing device for a thermopile-based infrared detector:



83/85

Self Testing - Cont’d

Stimuli other than electrical means:

Ambient air for micro pressure sensors.Earth gravitation for microaccelerometers.Oxygen content in air for gas sensors.

Testing During Use

It is used for calibrations of microsensors in the designed life span.

Input for these tests usually involve the natural loads as in self testing.

Testing during use ensures the proper functioning of devices for the intendedapplications.

Summary on Testing and Reliability of Microsystems


84/85

● Failure mechanisms in ICs and microelectronics are primarily attrobuted tomechanical means, e.g., over-stressing or over-heating.

● Failure mechanisms in MEMS and microsystems attribute to many morecauses:

● Improper interfacing of delicate core components and the workingmedia can also result in failure of MEMS and microsystems.

● Improper sealing and encapsulation in packaging may cause failure of microsystems such as by undesired dusts and moisture to delicate corecomponents.

● Fabrication induced means such as intrinsic and residual stressesand strains.

● Fault-proof design for reliability for MEMS and microsystems appear unrealistic.Intelligent testing is a practical approach to insure reliability of these products.

Summary on Testing and Reliability of Microsystems – cont’d


85/85

1990 1995 2000 2005 2010 2015 2020

Materials

Equipment

Design & modeling;Testing

Interconnect

Process

Packaging

C a t e g o r i e s

Standards Timeline

● While testing is viewed to be a practical solution to reliability assuranceof MEMS and microsystems, cost for developing effective and reliabletesting remain high – mainly because of lack of standard to follow:

Likely extension

assembly, packaging, and testing (apt) of microsystems

Documents