assembly language for intel-based computers, 5 edition€¦•2.2.4 how programs run. irvine, kip r....

Assembly Language for Intel-BasedComputers, 5th Edition

Chapter 2: IA-32 ProcessorArchitecture

(c) Pearson Education, 2006-2007. All rights reserved. You may modify and copy this slide show for your personal use,or for use in the classroom, as long as this copyright statement, the author's name, and the title are not changed.

Slides prepared by the authorRevision date: June 4, 2006

Kip Irvine

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 2

Chapter 2 Outline

• 2.1 General Concepts• 2.2 IA-32 Processor Architecture• 2.3 IA-32 Memory Management• 2.4 Components of an IA-32 Microcomputer• 2.5 Input-Output System


2.1 General Concepts

•2.1.1 Basic microcomputer design•2.2.2 Instruction execution cycle•2.2.3 Reading from memory•2.2.4 How programs run


2.1.1 Basic Microcomputer Design

• The central processor unit (CPU): where all the calculations and logicoperations take place•Clock: synchronizes internal CPU operations with other

components•Control unit (CU): coordinates sequence of execution steps•Arithmetic logic Unit (ALU): performs arithmetic and bitwise

processing

Central Processor Unit(CPU)

Memory StorageUnit

registers

ALU clock

I/ODevice

#1

I/ODevice

#2

data bus

control bus

address bus

CU


Basic Microcomputer Design (Cont.)

•The memory storage unit: where instructions anddata are held while a computer program is running.

•A bus: a group of parallel wires that transfer datafrom one part of the computer to another.•Data bus

•Transfer instruction and data

•Address bus•Hold the address of instruction and data

•Control bus•Synchronize the actions of all devices


Clock

•Clock: repeatedly pulses at a constant time•Synchronizes all CPU and BUS operations•Machine cycle (clock cycle time): the most basic unit of

time for machine instruction•A machine instruction requires at least one clock cycle

to execute.•A few instructions (e.g., the multiply instruction) require in

excess of 50 clocks

one cycle

1

0


Clock (Cont.)

•The duration of a clock cycle is the reciprocal of theclock’s speed•1 GHz ( 1 billion oscillations per second)

=> clock cycle time = 1 ns (nanosecond)

•Synchronous operation: need a clock•Clock is used to trigger events

•Asynchronous operation: does not require a systemclock


2.1.2 Instruction Execution Cycle

• The execution of a single machine instruction can bedivided into a sequence of individual operations.

• Three primary operations: fetch, decode and execute.

• Two more steps are required when the instruction uses amemory operand: fetch operand and store outputoperand


2.1.2 Instruction Execution Cycle (cont.)

• Fetch• Decode• Fetch operands• Execute• Store output

I-1 I-2 I-3 I-4

PC program

I-1instructionregister

op1op2

memory fetch

ALU

registers

writ

e

decode

execute

read

writ

e

(output)

registers

flags


Instruction Execution Cycle (Cont.)

• Fetch•Fetch the instruction indexed by PC (program counter)•Copy it from memory into the CPU• Increment the PC

• Decode•The control unit (CU) determine the type of instruction and

tell the ALU• Fetch operand

• If a memory operand is needed, the CPU retrieve theoperand from memory

• Execute• Store output operand

• If the output operand is in memory, write it back• p.s.

•Each step takes at least one clock cycle•Each processor has its own steps, e.g, IA-32 has six stages


Multi-Stage Pipeline• Pipelining makes it possible for processor to execute instructions in

parallel• Instruction execution divided into discrete stages

S1 S2 S3 S4 S51

Cyc

les

Stages

S6

23456789

101112

I-1

I-2

I-1

I-2

I-1

I-2

I-1

I-2

I-1

I-2

I-1

I-2

Example of a non-pipelined processor.Many wasted cycles.

For k states and n instructions, the number of required cycles is:n * k


Pipelined Execution

• More efficient use of cycles, greater throughput of instructions:

S 1 S 2 S 3 S 4 S 51

Cyc

les

S ta g e s

S 6

2

34567

I - 1I - 2 I - 1

I - 2 I - 1I - 2 I - 1

I - 2 I - 1I - 2 I - 1

I - 2

For k states and n instructions, the number of required cycles is:k + (n –1)


Wasted Cycles (pipelined)

• When one of the stages requires two or more clock cycles, clockcycles are again wasted.

S 1 S 2 S 3 S 4 S 51

Cyc

les

S t a g e s

S 6

234567

I - 1I - 2I - 3

I - 1I - 2I - 3

I - 1I - 2I - 3

I - 1

I - 2 I - 1I - 1

89

I - 3 I - 2I - 2

e x e

1 01 1

I - 3I - 3

I - 1

I - 2

I - 3

For k states and n instructions, the number of required cycles is: k + (2n –1)


Superscalar

A superscalar processor has multiple execution pipelines. In thefollowing, note that Stage S4 has left and right pipelines (u and v).

S 1 S 2 S 3 u S 51

Cyc

les

S ta g e s

S 6

234567

I -1I - 2I - 3I - 4

I - 1I - 2I - 3I - 4

I - 1I - 2I - 3I - 4

I - 1

I - 3 I - 1I - 2 I - 1

v

I- 2

I - 4

S 4

89

I -3I - 4

I - 2I - 3

1 0 I -4

I- 2

I - 4

I - 1

I - 3

For k states and n instructions, the number of required cycles is: k + n


2.1.3 Reading from Memory• Memory access is a bottleneck and multiple machine cycles are

required when reading from memory• It responds much more slowly than the CPU.

• The steps are:• Address placed on address bus• Read Line (RD) set low to notify memory that a value is to be read• CPU waits one cycle for memory to respond• Read Line (RD) goes to 1, indicating that the data is on the data

bus

Cycle 1 Cycle 2 Cycle 3 Cycle 4

Data

Address

CLK

ADDR

RD

DATA


Cache Memory

•High-speed expensive static RAM both inside andoutside the CPU.•Level-1 cache: inside the CPU•Level-2 cache: outside the CPU

•Cache hit: when data to be read is already in cachememory

•Cache miss: when data to be read is not in cachememory.


How a Program Runs

Operatingsystem

User

Currentdirectory

Systempath

Directoryentry

sends programname to

gets startingcluster from

searches forprogram in

loads andstarts

Program

returns to


How a Program Runs (Cont.)

•The user issues a command to run a certain program.•The OS searches for the program’s filename (in the

current directory or predetermined list of directories)• If found, the OS retrieves basic information, like file

size, physical location, about the program’s file fromthe disk directory.

•The OS loads the program file into memory.•The CPU begins to execute the program (process) by

jumping to the first instruction of the program•Now, the program is called a process

•The process runs by itself•When the process ends, OS removes its handle and

memory


Multitasking

•OS can run multiple programs at the same time.•A process may optionally contains multiple threads of

execution.•Scheduler assigns a given amount of CPU time to

each running program.•Rapid switching of tasks

•Gives illusion that all programs are running at once•The processor must support task switching.

•The processor saves the state (e.g., registers, variables,program counter) of each task before switching to a newone

•OS can assign varying priorities to tasks


Chapter 2: What's Next



2.2 IA-32 Processor Architecture

•2.2.1 Modes of operation•2.2.2 Basic execution environment•2.2.3 Floating-point unit•2.2.4 Intel Microprocessor history


2.2.1 Modes of Operation•Protected mode

•The native mode of the processor and all instructions andfeatures are available

•Used by Windows and Linux•Programs are given separate memory areas (called

segments) with proper protection

•Real-address mode•Native MS-DOS• Implements the programming environment of the Intel 8086

processor•All Intel processors boot in Real-address mode

•Then the OS may switch to another mode


Modes of Operation (cont.)

•System management mode•Provides an operating system with a mechanism for

implementing•power management, system security, diagnostics

• Implemented by computer manufactures

•Virtual-8086 mode•While in Protected mode, the processor can directly execute

Real-address mode program in a safe multitasking environment.•Each program has its own 8086 computer•A special case of Protected Mode, so it is called Virtual


2.2.2 Basic Execution Environment

•Addressable memory•General-purpose registers• Index and base registers•Specialized register uses•Status flags•Floating-point, MMX, XMM registers


Addressable Memory

•Protected mode•4 GB•32-bit address

•Real-address and Virtual-8086 modes•1 MB space•20-bit address

•Protected mode while running program in Virtual-8086 mode•Each program can access its own separate 1MB

memory


Registers• Registers are high-speed storage locations directly inside the CPU

• Intel registers•8 general-purpose registers•6 segment registers•EFLAGS: processor status flag•EIP: instruction pointer

CS

SS

DS

ES

EIP

EFLAGS

16-bit Segment Registers

EAX

EBX

ECX

EDX

32-bit General-Purpose Registers

FS

GS

EBP

ESP

ESI

EDI


General-Purpose Registers

• Used for arithmetic and data movement•EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP

• Use 8-bit name, 16-bit name, or 32-bit name• Applies to EAX, EBX, ECX, and EDX

AH AL

16 bits

8

AX

EAX

8

32 bits

8 bits + 8 bits


Accessing Parts of Registers

•Use 8-bit name, 16-bit name, or 32-bit name•Applies to EAX, EBX, ECX, and EDX

AH AL

16 bits

8

AX

EAX

8

32 bits

8 bits + 8 bits


Index and Base Registers

•Some registers have only a 16-bit name for theirlower half:


Some Specialized Register Uses (1 of 3)

•EAX –extended accumulator register•Used by multiplication and division instructions)

•ECX –loop counter•ESP –stack pointer, extended stack pointer

register•ESI, EDI –index registers

•Extended source/destination index registers

•EBP –extended frame pointer (stack)•Used by high-level languages to reference function

parameters and local variables



• Segment register: as base locations for pre-assigned memory areas•CS –code segment

•Hold instruction

•DS –data segment•Hold variables

•SS –stack segment•Hold local variables and function parameters

•ES, FS, GS - additional segments

• EIP –instruction pointer•Containing the address of the next instruction to be executed



• EFLAGS•Status and control flags•Each flag is a single binary bit•Control Flag

•Control the operation of the CPU•Example, IF Flag (interrupt flag)

•Status Flag•Reflect the outcome of some CPU operations•Example

–Carry Flag (CF)–Overflow Flag (OF)–Sign Flag–Zero Flag–Auxiliary Carry Flag–Parity Flag


Flags•Control Flags

•Direction• Interrupt

•Status Flags•Carry

•unsigned arithmetic out of range•Overflow

•signed arithmetic out of range•Sign

•result is negative•Zero

•result is zero•Auxiliary Carry

•carry from bit 3 to bit 4•Parity

•sum of 1 bits is an even number


System Registers

•System registers•Only permit access by programs running at the highest

privilege level (level 0), e.g., the Window XP•IDTR (Interrupt Descriptor Table Register)•GDTR (Global Descriptor Table Register)•LDTR (Local Descriptor Table Register)•Task Registers•Control Registers: CR0, CR2, CR3, CR4•Model-Specific Registers


2.2.3 Floating-Point, MMX, XMM Registers

• Floating-point unit: eight 80-bit floating-point data registers• ST(0), ST(1), . . . , ST(7)

• arranged in a stack

• used for all floating-point arithmetic

• Registers for multimedia programming• Eight 64-bit MMX registers

• Eight 128-bit XMM registers for single-instruction multiple-data (SIMD) operations

ST(0)

ST(1)

ST(2)

ST(3)

ST(4)

ST(5)

ST(6)

ST(7)


2.2.4 Intel Microprocessor History

• Intel 8086, 80286• IA-32 processor family•P6 processor family•CISC and RISC


Early Intel Microprocessors

• Intel 8080•64K addressable RAM•8-bit registers•CP/M operating system•S-100 BUS architecture•8-inch floppy disks!

• Intel 8086/8088•Mark the beginning of the modern Intel Architecture

family• IBM-PC Used 8088•1 MB addressable RAM•16-bit registers•16-bit data bus (8-bit for 8088)•separate floating-point unit (8087)


The IBM-AT

• Intel 80286•16 MB addressable RAM•Protected memory•several times faster than 8086•introduced IDE bus architecture•80287 floating point unit


Intel IA-32 Family

•Intel386•4 GB addressable RAM, 32-bit registers,

paging (virtual memory)

•Intel486•instruction pipelining

•Pentium•superscalar, 32-bit address bus, 64-bit

internal data path


Intel P6 Family

•Pentium Pro•advanced optimization techniques in microcode

•Pentium II•MMX (multimedia) instruction set

•Pentium III•SIMD (streaming extensions) instructions

•Pentium 4 and Xeon•Intel NetBurst micro-architecture, tuned for

multimedia


CISC and RISC

• CISC –complex instruction set• large instruction set•high-level operations•High-level language compilers would have less work• requires microcode interpreter•Complex instructions require a long time for the

processor to decode and execute•examples: Intel 80x86 family

• RISC –reduced instruction set•simple, atomic instructions•small instruction set•directly executed by hardware•examples:

•ARM (Advanced RISC Machines)•DEC Alpha (now Compaq)


Chapter 2 Outline: What's Next



2.3 IA-32 Memory Management

•2.3.1 Real-address mode•2.3.2 Calculating linear addresses•2.3.3 Protected mode•2.3.4 Multi-segment model•2.3.5 Paging


IA-32 Memory Management• Real-address mode

•Processor can run only one program at a time•Each program can address up to 1MB

•1 MB RAM maximum addressable•(00000~FFFFFh)

•Application programs can access any area of memory•Single tasking•Supported by MS-DOS operating system

• Protected mode•Processor can run multiple program at the same time with

each process a total of 4GB memory•MS-Windows and Linux

• Virtual-8086 mode•Simulate an 80x86 running in real-address mode while in

protected mode•Command windows in MS-Windows


Real-Address Mode Real-address mode can address up to 1MB memory

(20-bit address) However, the original 8086 processor had only 16-bit

registers, which can not directly represent a 20-bit address

Solution: segmented memory addressing Memory is divided into 64KB (16-bit address) units called

segment Segment-offset address: use two 16-bit numbers to calculate

20-bit address A 16-bit segment value stored in segment register A 16-bit offset value

Thus, absolute (linear) address is a combination of a 16-bitsegment value added to a 16-bit offset


Segmented Memory Map, Real-address Mode

00000

10000

20000

30000

40000

50000

60000

70000

80000

90000

A0000

B0000

C0000

D0000

E0000

F0000

8000:0000

8000:FFFF

seg ofs

8000:0250

0250

linea

ra d

dre s

ses

one segment


Calculating Linear Addresses

•Given a segment address, multiply it by 16 (add ahexadecimal zero), and add it to the offset

•Example: convert 08F1:0100 to a linear address

Adjusted Segment value: 0 8 F 1 0

Add the offset: 0 1 0 0

Linear address: 0 9 0 1 0


Your turn . . .

What linear address corresponds to the segment/offsetaddress 028F:0030?

028F0 + 0030 = 02920

Always use hexadecimal notation for addresses.


Your turn . . .

What segment addresses correspond to the linear address28F30h?

Many different segment-offset addresses can produce thelinear address 28F30h. For example:

28F0:0030, 28F3:0000, 28B0:0430, . . .


Protected Mode (1 of 2)

•4 GB addressable RAM•(00000000 to FFFFFFFFh)

•Each program assigned a memory partition whichis protected from other programs•Described by segment descriptor tables

•Designed for multitasking

•Supported by Linux & MS-Windows


Protected Mode (2 of 2)

•Program structure•code, data, and stack areas•CS, DS, SS segment descriptors•global descriptor table (GDT)

•Has two memory model•Flat segmentation model•Multi-segment model


Flat Segmentation Model•All segments are mapped to the entire 32-bit physical

address space of the computer.•At least two segments: one for program code and one

for data•Each segment is defined by a segment descriptor,

a 64-bit value stored in a table known as the globaldescriptor table (GDT)


Multi-Segment Model• Each program has a local descriptor table (LDT)

•Holds descriptor for each segment used by the program

3 0 0 0

R A M

0 0 0 0 3 0 0 0

L o c a l D e s c rip to r T a b le

0 0 0 20 0 0 0 8 0 0 0 0 0 0 A0 0 0 2 6 0 0 0 0 0 1 0

b a s e lim it a c c e s s

8 0 0 0

2 6 0 0 0


Paging

•Supported directly by the CPU•A segment is further divided into 4096-byte (4KB)

blocks of memory called pages•Allow the memory used by programs can be larger

than the computer’s actual memory•Virtual memory v.s. physical memory•Part of running program is in memory, part is on disk

•Virtual memory manager (VMM) –OS utility thatmanages the loading and unloading of pages

•Page fault –issued by CPU when a page must beloaded from disk•Page in: bring a requested page into memory•Page out: evict an unused page to the disk


2.4 Components of an IA-32 Microcomputer

•2.4.1 Motherboard•2.4.2 Video output•2.4.3 Memory•2.4.4 Input-output ports


2.4.1 Motherboard

•CPU socket•External cache memory slots•Main memory slots•BIOS chips•Sound synthesizer chip (optional)•Video controller chip (optional)• IDE, parallel, serial, USB, video, keyboard, joystick,

network, and mouse connectors•PCI bus connectors (expansion cards)


Intel D850MD Motherboard

dynamic RAM

Pentium 4 socket

Speaker

IDE drive connectors

mouse, keyboard,parallel, serial, and USBconnectors

AGP slot

Battery

Video

Power connector

memory controller hub

Diskette connector

PCI slots

I/O Controller

Firmware hub

Audio chip

Source: Intel® Desktop Board D850MD/D850MV Technical ProductSpecification


2.4.2 Video Output

•Video controller•on motherboard, or on expansion card•AGP (accelerated graphics port technology)*

•Video memory (VRAM)•Video CRT Display

•uses raster scanning•horizontal retrace•vertical retrace

•Direct digital LCD monitors•no raster scanning required

* This link may change over time.


Sample Video Controller (ATI Corp.)

•128-bit 3D graphicsperformance powered byRAGE™ 128 PRO

•3D graphics performance

• Intelligent TV-Tuner withDigital VCR

•TV-ON-DEMAND™

• Interactive Program Guide

•Still image and MPEG-2 motionvideo capture

•Video editing

•Hardware DVD video playback

•Video output to TV or VCR


2.4.3 Memory• ROM

• read-only memory• EPROM

•erasable programmable read-only memory• Dynamic RAM (DRAM)

• inexpensive; must be refreshed constantly• Static RAM (SRAM)

•expensive; used for cache memory; no refresh required• Video RAM (VRAM)

•dual ported; optimized for constant video refresh• CMOS RAM

•complimentary metal-oxide semiconductor•system setup information


2.4.4 Input-Output Ports and Device Interfaces

•USB (universal serial bus)•intelligent high-speed connection to devices•up to 12 megabits/second•USB hub connects multiple devices•enumeration: computer queries devices•supports hot connections

•Parallel•short cable, high speed•common for printers•bidirectional, parallel data transfer•Intel 8255 controller chip


2.4.4 Input-Output Ports and Device Interfaces(cont)

•Serial•RS-232 serial port•one bit at a time•uses long cables and modems•16550 UART (universal asynchronous receiver

transmitter)•programmable in assembly language


2.5.1 Levels of Input-Output

• Level 3: Call a library function (C++, Java)•easy to do; abstracted from hardware; details hidden•slowest performance

• Level 2: Call an operating system function•specific to one OS; device-independent

•E.g., writing entire strings to files, reading string from thekeyboard, allocating blocks of memory for application programs

•medium performance• Level 1: Call a BIOS (basic input-output system) function

•may produce different results on different systems•knowledge of hardware required•usually good performance

• Level 0: Communicate directly with the hardware• May not be allowed by some operating systems


Displaying a String of Characters

• When a HLL program displays a string ofcharacters, the following steps take place:

1. Application program writes the string tostandard output.

2. The library function calls OS, passing astring pointer.

3. OS passes the ASCII code and color ofeach character to BIOS. OS also callsBIOS function to control the cursor.

4. BIOS maps each character to a particularsystem font and sends it to a hardwareport attached to the video controller card.

5. The video controller card generateshardware signals to the video display.

Application Program

OS Function

BIOS Function

Hardware Level 0

Level 1

Level 2

Level 3


ASM Programming levels

ASM Program

OS Function

BIOS Function

Hardware Level 0

Level 1

Level 2

ASM programs can perform input-output ateach of the following levels:


Playing a WAV File

•At the OS level, you do not have to know what type ofdevice was installed and the card’s features

•At the BIOS level, you would query the sound card andfind out whether it belongs to a certain class of soundcards

•At the hardware level, you would fine-tune the programfor certain brands of audio cards, to take advantage ofeach card’s special features•Not all operating system permit user programs to directly

access system hardware


Tradeoff

•Tradeoff•Control (efficiency) v.s. portability

•However, some OSs, like Windows and Linux, do notpermit user programs to directly access systemhardware


Summary

•Central Processing Unit (CPU)•Arithmetic Logic Unit (ALU)• Instruction execution cycle•Multitasking•Floating Point Unit (FPU)•Complex Instruction Set•Real mode and Protected mode•Motherboard components•Memory types• Input/Output and access levels

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