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1ITEC 1000 Introduction to Information Technologies

Outline of todays lecture Time, location and coverage for midterm

Summary of last weeks class

Case study: two examples

Computer instructions

ITEC 1000 Introduction to Information Technologies

ITEC 1000A Midterm

Midterm time: Tuesday (June 27): 18:00pm - 21:00pm

Class location: TEL 0001

Coverage: Chapter 1, 2, 3 , 4 and 6


Format of Midterm 4 LMC questions

similar in style to those in the book and the slides.

you should know how to write a short program.

3 short answer questions for definitions 7 questions about number representation,

conversion and operations. These questions will be similar in format to the questions in

the assignment#1. Additionally 10's and 2's complement representation will be

included. ITEC 1000 Introduction to Information Technologies

LMC Counterparts

05

123123500199500399

123

000102030405

9596979899

456

789

ALU

Control unit

Program counter

Input/outputinterface

p. 167


Registers A register is a single permanent storage location

within the CPU used for a particular purpose. Unlike memory, which is outside the CPU Examples of registers:

Program counter (PC) Instruction register (IR) Memory address register (MAR) Memory data register (MDR) Accumulator (ACC) Status register

General purpose registers (R0, R1, ) Included on some CPUs Used for high-speed temporary storage


A dedicated register in the CPU.

Contains the address in memory of the current instruction being executed.

Incremented automatically after each instruction.

May be forced to change: eg jump instruction.Usually initialize to zero when machine starts, or is reset.

Program Counter ( PC )


A dedicated register in the CPU which contains the actual current instruction.

Op Code + Address

What To Do Location of Data

Simple 16-bit example: 1101 101101100100

Instruction Register ( IR )


Memory Address Register (MAR)Contains Address in memory to find or place data.

Memory Data Register (MDR)Contains Actual Data to be placed in location given in MAR, or which has been retrieved from location given in MAR.

Memory registers


Memory Unit

Mem

ory

ad

dres

s re

gist

er

Add

ress

de

code

r

bit n - 1

bit 0

bit 101234

2n-1

Memory data register

Memory celln bits

m bits0 1 2 m - 1

p. 160

MAR

MDRITEC 1000 Introduction to Information Technologies

A dedicated register (or set of registers) in the CPU used for the actual manipulation of data.

Default source (or destination) register.

Usually contains results of arithmetic or logical operations.

AccumulatorCalculator in LMC


Accumulator ( A or Acc )

Instruction Register ( IR )

Memory Address Register ( MAR )

Memory Data Register ( MDR )

Program Counter ( PC )

Memory

Generic CPU With Registers


Fetch-Execute Cycle

Two steps, or cycles, in the execution of every instruction Fetch fetch the code for the instruction from

memory and place it in the IR (instruction register)

Execute execute the instruction

Fetch Executetime


The LOAD Instruction

PC MAR

MDR IR

IR[address] MARMDR A

PC + 1 PC

Fetch

Execute

time

Text: Page 177, Revised.ITEC 1000 Introduction to Information Technologies

The Add Instruction

PC MAR

MDR IR

IR[address] MARA + MDR A

PC + 1 PC

Fetch

Execute

time

Text: Page 177, Revised.


Fetch-Execute Example: Load Accumulator

Assume: Simple Eight bit system.Thirty-two memory locations (0 to 31).Load instruction is 010.Value in location 15 is ten (ie: binary 00001010)PC is at 5, about to increment.The instruction, 01001111, is in location 6.

Then ...


PC: 00101

IR: (previous)

A: (previous)

MAR: (previous)

MDR: (previous)

CPU Before PC increments

Location 31

15: 00001010

06: 01001111

Location 0


PC: 00110

IR: (previous)

A: (previous)

MAR: (previous)

MDR: (previous)

Increment PC: PC = PC + 1

Location 31

15: 00001010

06: 01001111

Location 0


PC: 00110

IR: (previous)

A: (previous)

MAR: 00110

MDR: (previous)

MAR loaded with PC: PC -> MAR

Location 31

15: 00001010

06: 01001111

Location 0


PC: 00110

IR: (previous)

A: (previous)

MAR: 00110

MDR: (previous)

Memory Location 00110 Accessedand Contents Placed in MDR:

Location 31

15: 00001010

06: 01001111

Location 0


PC: 00110

IR: (previous)

A: (previous)

MAR: 00110

MDR: 01001111

Memory Location 00110 Accessedand Contents Placed in MDR:

Location 31

15: 00001010

06: 01001111

Location 0


PC: 00110

IR: 01001111

A: (previous)

MAR: 00110

MDR: 01001111

MDR copied to IR: MDR -> IR

Location 31

15: 00001010

06: 01001111

Location 0


PC: 00110

IR: 01001111

A: (previous)

MAR: 01111

MDR: 01001111

IR [ address part ] -> MAR

Location 31

15: 00001010

06: 01001111

Location 0


PC: 00110

IR: 01001111

A: (previous)

MAR: 01111

MDR: 01001111

Location in MAR (01111) Accessed

Location 31

15: 00001010

06: 01001111

Location 0


PC: 00110

IR: 01001111

A: (previous)

MAR: 01111

MDR: 00001010

Contents of 01111 loaded into MDR

Location 31

15: 00001010

06: 01001111

Location 0


PC: 00110

IR: 01001111

A: 00001010

MAR: 01111

MDR: 00001010

IR [op code] executed: MDR -> A

Location 31

15: 00001010

06: 01001111

Location 0


PC: 00110

IR: 01001111

A: 00001010

MAR: 01111

MDR: 00001010

Finished !

Location 31

15: 00001010

06: 01001111

Location 0


Now: Assume: Value in location 7 is 10110010.

Add instruction is 101.Value in location 18 is seventy-one

(i.e.: binary 01000111)Everything else is as we left it!

Then ...


PC: 00111

IR: 01001111

A: 00001010

MAR: 01111

MDR: 00001010

PC = PC + 1

Location 31

18: 01000111

15: 00001010

07: 1011001006: 01001111

Location 0


PC: 00111

IR: 01001111

A: 00001010

MAR: 00111

MDR: 00001010

PC -> MAR

Location 31

18: 01000111

15: 00001010

07: 1011001006: 01001111

Location 0


PC: 00111

IR: 01001111

A: 00001010

MAR: 00111

MDR: 00001010

MAR Accesses Location 00111

Location 31

18: 01000111

15: 00001010

07: 1011001006: 01001111

Location 0


PC: 00111

IR: 01001111

A: 00001010

MAR: 00111

MDR: 10110010

Contents of 00111 -> MDR

Location 31

18: 01000111

15: 00001010

07: 1011001006: 01001111

Location 0


PC: 00111

IR: 10110010

A: 00001010

MAR: 00111

MDR: 10110010

MDR -> IR

Location 31

18: 01000111

15: 00001010

07: 1011001006: 01001111

Location 0


PC: 00111

IR: 10110010

A: 00001010

MAR: 10010

MDR: 10110010

IR [address] -> MAR

Location 31

18: 01000111

15: 00001010

07: 1011001006: 01001111

Location 0


PC: 00111

IR: 10110010

A: 00001010

MAR: 10010

MDR: 10110010

Location 10010 [MAR] Accessed

Location 31

18: 01000111

15: 00001010

07: 1011001006: 01001111

Location 0


PC: 00111

IR: 10110010

A: 00001010

MAR: 10010

MDR: 01000111

Contents of [10010] -> MDR

Location 31

18: 01000111

15: 00001010

07: 1011001006: 01001111

Location 0


PC: 00111

IR: 10110010

A: 01010001

MAR: 10010

MDR: 01000111

IR [opcode] executed: A = A + MDR

Location 31

18: 01000111

15: 00001010

07: 1011001006: 01001111

Location 0


To Continue:

If the next instruction were to load the Accumulator contents into an area of memory reserved for screen output (for example), then the number 81 should appear on the screen.

The process continues in the same fashion, more or less, until astop or halt instruction is encountered.


All communication between the LMC and the outside world takes place using three-digit numbers

Instruction (Op Code )+ mailbox address (address field)

What To Do Location of Data

3 25

LMC Instruction word format


LMC address field Unused (HALT- 000) Extension of the op code (INPUT-901, OUTPUT-

902) Contain the 2-digits address where data for the

instruction could be found ( LOAD-599) or was to be placed (STORE -398)

To hold the location of the next instruction to be executed (BR-614, BRZ-714, BRP-814)

ITEC 1000 Introduction to Information TechnologiesFigure 7.14 A simple 32-bit instruction format

A Simple 32-bit instruction format


Data manipulation computer instructions

Require the specification of at least 2 locations for the data :

One or more source locations One destination location

Locations may be expressed : Explicitly as address fields in the instruction

word Implicitly as part of the definition of the

instruction itself.


Operands

The sources and destinations of data for an instruction whether implicit or explicit are also known as operands

Explicit address fields are known as operand fields


Classification of instructions Data movement instructions (LOAD, STORE, and

others)Most frequently used, include instruction to move data

from memory to general registers, from general registers to memory, between different general registers

Arithmetic instructionsThere may be several different integer arithmetic

instruction formats providing various combinations of register and memory access in different addressing modes


Boolean logic instructions Example: NOT, AND , OR instructions

Single operand manipulation instructionsMost of them operate on the value in the register, but

some of them operate on memory values as wellExample: increment a value, decrement a value or

resetting a value. Bit manipulation instructions

Provide setting and resetting of individual bits in a data word.

Classification of instructions


Shift and rotate instructions Logical shift simply shift the data as you would expect,

and zeros are shifted in to replace the bit spaces that has been vacated.

Arithmetic shift used to multiply or divide the original value by a power of 2. The leftmost bit is not shift.

Rotate shift take the bits as they exit and rotate them back into the other end of the register.

Program control instructions control the flow of a program, include jumps, branches and subroutine CALL and RETURN instructions.

Classification of instructions

ITEC 1000 Introduction to Information TechnologiesFigure 7.17 Typical register shifts and rotates

Shift and Rotate instructions

Page 192


Shift and Rotate instructions

10011001 -103

11001100 -52

11100110 -26

11110011 -13


Stack instructions

Stack instructions Stack data storage used to store data when

the most recently used data will be the first needed. LIFO last-in, first-out structures.Stacks are an efficient way of storing intermediate data values during complex calculations. Example: PUSH and POP instructions

others


Figure 7.19 Using a stack

Using a Stack


Figure 7.22 Using a block of memory as a stack


Figure 7.18 Operation of CALL and RETURN instructions

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