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ASIC:Status of resubmission/ List of changes/Left to do

A. Klyuev et all ASIC designers for the AGIPD collaboration

AGIPD Collaboration meeting 11-13 November 2015

Textmasterformat bearbeitenList of patches applied:Top level

1. AOUT RC reduction: E1 instead of M2 in vertical direction, M3 instead of M1 at the bottom, better grounding of separation anti-crosstalk lines

2. Power_right changed: VDDA from E1 to MA3. Improved vias (M2_M3) connecting the biasing and the AOUT input

signals to the offchip driver4. New power-up reset pad5. New offchip driver with a buffered vref_chipbuf to suppress channel

signal crosstalks through the biasing6. New pixel layout (mostly MQ and up, improved contacts)7. Added VDDA MA metal clamps from the right power group to the pixel

matrix8. Added vdda clamps from the right power group to the outmux9. Added ground clamps from the pixel matrix to the output signal

separators10. Added M1 parallel to M2 VDDA bus in the outmux with corresponding via

sets11. Doubled mux clock and tokens buffers, new routing from the periphery

Textmasterformat bearbeitenList of patches applied:Pixel

1. pixel_ma changed to have wider (and trough) vdd_pa vdd_pix and vss lines (MA, E1)2. (D)MIM caps (e.g. pixelPowDecoupCap(1), filter_caps opa_ds..) layout and position changed3. Orientation and connection (now via MA) of test pulse cap changed4. MG: Rearranged bias (now over active part) control (no longer under preamp FB cap)and power (widened) lines5. Increased # of vias for power (esp. FY FT F1)6. Added MQ lines for power, filled MG crOssings with VGss7. Added LY Shield under input pad8. Increased # of vnwell_pix vias to wells9. aux_calibr, preamp_3gain_highGain layout changes

Textmasterformat bearbeitenPixel improvements

Crosstalk between address lines and analog circuitry nodes AGIPD 1.0

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Coupling table

AGIPD10 vs AGIPD11 - Crosstalks

Parasitic Coupling AGIPD10 AGIPD11

Row_SELA_0/pix_in 5.35 fF < 1 fF

Col_SELA_3/Vrefcds 11 fF 1.2 fF

Row_SELA_3/test_curr 20 fF < 1 fF

Col_SELA_29/Vrefpxb 12.5 fF 9.2 fF

Textmasterformat bearbeitenPixel improvements

AGIPD 1.0 AGIPD 1.1

Textmasterformat bearbeitenOutput signal speed issue

t10to90

measured:

21 ns

27 ns

41 ns

56 ns

Textmasterformat bearbeitenOutput signal speed issue

AGIPD 1.0 AGIPD 1.1

Textmasterformat bearbeitenGhosting

Textmasterformat bearbeitenPower mesh improvements

first port second port value1 {Layout Port vdd_preamp} {Layout Port vddpa_cb} 0.2511012 {Layout Port vdd_preamp} {Layout Port vddpa_cc} 0.2415663 {Layout Port vdd_preamp} {Layout Port vddpa_ct} 0.2636594 {Layout Port vdd_preamp} {Layout Port vddpa_lb} 0.2934765 {Layout Port vdd_preamp} {Layout Port vddpa_lc} 0.2677316 {Layout Port vdd_preamp} {Layout Port vddpa_lt} 0.3015367 {Layout Port vdd_preamp} {Layout Port vddpa_mq_cb} 0.6082618 {Layout Port vdd_preamp} {Layout Port vddpa_mq_cc} 0.5988159 {Layout Port vdd_preamp} {Layout Port vddpa_mq_ct} 0.64446710 {Layout Port vdd_preamp} {Layout Port vddpa_mq_lb} 0.66614411 {Layout Port vdd_preamp} {Layout Port vddpa_mq_lc} 0.64785412 {Layout Port vdd_preamp} {Layout Port vddpa_mq_lt} 0.74153713 {Layout Port vdd_preamp} {Layout Port vddpa_mq_rb} 0.59292814 {Layout Port vdd_preamp} {Layout Port vddpa_mq_rc} 0.61536715 {Layout Port vdd_preamp} {Layout Port vddpa_mq_rt} 0.69568216 {Layout Port vdd_preamp} {Layout Port vddpa_rb} 0.27550217 {Layout Port vdd_preamp} {Layout Port vddpa_rc} 0.29245118 {Layout Port vdd_preamp} {Layout Port vddpa_rt} 0.340166

1 {Layout Port vdd_analog_PAD} {Layout Port vdd_muxb} 1.199612 {Layout Port vdd_analog_PAD} {Layout Port vdd_muxc} 0.5331683 {Layout Port vdd_analog_PAD} {Layout Port vdd_muxt} 0.7572124 {Layout Port vdd_analog_PAD} {Layout Port vdda_cb} 0.1546635 {Layout Port vdd_analog_PAD} {Layout Port vdda_cc} 0.1543246 {Layout Port vdd_analog_PAD} {Layout Port vdda_ct} 0.1911427 {Layout Port vdd_analog_PAD} {Layout Port vdda_lb} 0.1982858 {Layout Port vdd_analog_PAD} {Layout Port vdda_lc} 0.1783079 {Layout Port vdd_analog_PAD} {Layout Port vdda_lt} 0.22604910 {Layout Port vdd_analog_PAD} {Layout Port vdda_mq_cb} 0.48295211 {Layout Port vdd_analog_PAD} {Layout Port vdda_mq_cc} 0.47300712 {Layout Port vdd_analog_PAD} {Layout Port vdda_mq_ct} 0.51648313 {Layout Port vdd_analog_PAD} {Layout Port vdda_mq_lb} 0.53207314 {Layout Port vdd_analog_PAD} {Layout Port vdda_mq_lc} 0.50124215 {Layout Port vdd_analog_PAD} {Layout Port vdda_mq_lt} 0.56725816 {Layout Port vdd_analog_PAD} {Layout Port vdda_mq_rb} 0.44111617 {Layout Port vdd_analog_PAD} {Layout Port vdda_mq_rc} 0.47833318 {Layout Port vdd_analog_PAD} {Layout Port vdda_mq_rt} 0.55222719 {Layout Port vdd_analog_PAD} {Layout Port vdda_rb} 0.10832520 {Layout Port vdd_analog_PAD} {Layout Port vdda_rc} 0.15060921 {Layout Port vdd_analog_PAD} {Layout Port vdda_rt} 0.210877

first port second port1 {Layout Port vdd_preamp} {Layout Port vddpa_cb} 0.2648202 {Layout Port vdd_preamp} {Layout Port vddpa_cc} 0.2548163 {Layout Port vdd_preamp} {Layout Port vddpa_ct} 0.2843834 {Layout Port vdd_preamp} {Layout Port vddpa_lb} 0.3307875 {Layout Port vdd_preamp} {Layout Port vddpa_lc} 0.2986856 {Layout Port vdd_preamp} {Layout Port vddpa_lt} 0.3444547 {Layout Port vdd_preamp} {Layout Port vddpa_mq_cb} 0.8752778 {Layout Port vdd_preamp} {Layout Port vddpa_mq_cc} 0.8818059 {Layout Port vdd_preamp} {Layout Port vddpa_mq_ct} 1.0054210 {Layout Port vdd_preamp} {Layout Port vddpa_mq_lb} 0.95428611 {Layout Port vdd_preamp} {Layout Port vddpa_mq_lc} 0.94745312 {Layout Port vdd_preamp} {Layout Port vddpa_mq_lt} 1.0288813 {Layout Port vdd_preamp} {Layout Port vddpa_mq_rb} 0.84787514 {Layout Port vdd_preamp} {Layout Port vddpa_mq_rc} 0.88460115 {Layout Port vdd_preamp} {Layout Port vddpa_mq_rt} 1.0505116 {Layout Port vdd_preamp} {Layout Port vddpa_rb} 0.24298517 {Layout Port vdd_preamp} {Layout Port vddpa_rc} 0.26846918 {Layout Port vdd_preamp} {Layout Port vddpa_rt} 0.328556

1 {Layout Port vdd_analog_PAD} {Layout Port vdd_muxb} 4.502912 {Layout Port vdd_analog_PAD} {Layout Port vdd_muxc} 3.168353 {Layout Port vdd_analog_PAD} {Layout Port vdd_muxt} 6.174914 {Layout Port vdd_analog_PAD} {Layout Port vdda_cb} 0.1695965 {Layout Port vdd_analog_PAD} {Layout Port vdda_cc} 0.1725216 {Layout Port vdd_analog_PAD} {Layout Port vdda_ct} 0.2178457 {Layout Port vdd_analog_PAD} {Layout Port vdda_lb} 0.2195688 {Layout Port vdd_analog_PAD} {Layout Port vdda_lc} 0.1991129 {Layout Port vdd_analog_PAD} {Layout Port vdda_lt} 0.25387410 {Layout Port vdd_analog_PAD} {Layout Port vdda_mq_cb} 0.73485711 {Layout Port vdd_analog_PAD} {Layout Port vdda_mq_cc} 0.73145512 {Layout Port vdd_analog_PAD} {Layout Port vdda_mq_ct} 0.94381213 {Layout Port vdd_analog_PAD} {Layout Port vdda_mq_lb} 0.84700914 {Layout Port vdd_analog_PAD} {Layout Port vdda_mq_lc} 0.77961715 {Layout Port vdd_analog_PAD} {Layout Port vdda_mq_lt} 1.0192916 {Layout Port vdd_analog_PAD} {Layout Port vdda_mq_rb} 0.72086917 {Layout Port vdd_analog_PAD} {Layout Port vdda_mq_rc} 0.74568118 {Layout Port vdd_analog_PAD} {Layout Port vdda_mq_rt} 0.97752719 {Layout Port vdd_analog_PAD} {Layout Port vdda_rb} 0.12750120 {Layout Port vdd_analog_PAD} {Layout Port vdda_rc} 0.20265321 {Layout Port vdd_analog_PAD} {Layout Port vdda_rt} 0.248594

AGIPD 1.0 AGIPD 1.1

~1 Ohm

~0.8 Ohm ~0.45 Ohm

~0.65 Ohm

Textmasterformat bearbeitenAMS functional simulation

Textmasterformat bearbeitenTo-do list of changes

● DGN caps inside the outmux● GND contacts from outmux to the pixel● Discuss IBM test structures placement → supertop

layout placement● Place blocking DGN caps in the bottom and on the

right side of the ASIC● Put monitoring bump bonds for VDDA VDDPA GND

on the top (right) of the ASIC● Add cutting mark● Discuss bump bonding mark

Textmasterformat bearbeitenAGIPD 1.1 Submission

Expected improvements and patches for the AGIPD 1.1 version:

● Better and stable level separation of the gain bits by implementing different

powering schemes and revised operation timings ● Easier and faster calibration of the system due to:

● Removing the ghosting crosstalk by adding a buffer

in the off-chip driver circuitry● Removing the cross talk between the address lines

and the analog nodes● Improved internal calibration structures

● Faster readout up to 33 MHz with new output lines

and power distribution layout● New stable Power-On-Reset circuitry

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