asic flow
TRANSCRIPT
Asic Flow
Asic Design Flow
Step 1: Prepare an Requirement SpecificationStep 2: Create an Micro-Architecture Document.Step 3: RTL Design & Development of IP'sStep 4: Functional verification all the IP's/Check whether the RTL is free from Linting Errors/Analyze whether the RTL is Synthesis friendly.
Step 4a: Perform Cycle-based verification(Functional) to verify the protocol behaviour of the RTL
Step 4b: Perform Property Checking , to verify the RTL implementation and the specification understanding is matching.
Step 5: Prepare the Design Constraints file (clock definitions(frequency/uncertainity/jitter),I/O delay definitions, Output pad load definition, Design False/Multicycle-paths) to perform Synthesis, usually called as an SDC synopsys_constraints, specific to synopsys synthesis Tool (design-compiler)
Step 6: To Perform Synthesis for the IP, the inputs to the tool are (library file(for which synthesis needs to be targeted for, which has the functional/timing information available for the standard-cell library and the wire-load models for the wires based on the fanout length of the connectivity), RTL files and the Design Constraint files, So that the Synthesis tool can perform the synthesis of the RTL files and map and optimize to meet the design-constraints requirements. After performing synthesis, as a part of the synthesis flow, need to build scan-chain connectivity based on the DFT(Design for Test) requirement, the synthesis tool (Test-compiler), builds the scan-chain.
Step 7: Check whether the Design is meeting the requirements (Functional/Timing/Area/Power/DFT) after synthesis.
Step 7a: Perform the Netlist-level Power Analysis, to know whether the design is meeting the power targets.
Step 7b: Perform Gate-level Simulation with the Synthesized Netlist to check whether the design is meeting the functional requirements.
Step 7c: Perform Formal-verification between RTL vs Synthesized Netlist to confirm that the synthesis Tool has not altered the functionality.( Tool: Formality )
Step 7d: Perform STA(Static Timing Analysis) with the SDF(Standard Delay Format) file and synthesized netlist file, to check whether the Design is meeting the timing-requirements.( Tool: PrimeTime)
Step 7e: Perform Scan-Tracing , in the DFT tool, to check whether the scan-chain is built based on the DFT requirement.
Step 8: Once the synthesis is performed the synthesized netlist file(VHDL/Verilog format) and the SDC (constraints file) is passed as input files to the Placement and Routing Tool to perform the back-end Actitivities.
Step 9: The next step is the Floor-planning, which means placing the IP's based on the connectivity,placing the memories, Create the Pad-ring, placing the Pads(Signal/power/transfer-cells(to switch voltage domains/Corner pads(proper accessibility for Package routing), meeting the SSN requirements(Simultaneous Switching Noise) that when the high-speed bus is switching that it doesn't create any noise related acitivities, creating an optimised floorplan, where the design meets the utilization targets of the chip.
Step 9a : Release the floor-planned information to the package team, to perform the package feasibility analysis for the pad-ring .
Step 9b: To the placement tool, rows are cut, blockages are created where the tool is prevented from placing the cells, then the physical placement of the cells is performed based on the timing/area requirements.The power-grid is built to meet the power-target's of the Chip .
Step 10: The next step is to perform the Routing., at first the Global routing and Detailed routing, meeting the DRC(Design Rule Check) requirement as per the fabrication requirement.
Step 11: After performing Routing then the routed Verilog netlist, standard-cells LEF/DEF file is taken to the Extraction tool (to extract the parasitics(RLC) values of the chip in the SPEF format(Standard parasitics Exchange Format), and the SPEF file is generated. ( Tool: STARRC )
Step 12: Check whether the Design is meeting the requirements (Functional/Timing/Area/Power/DFT/DRC/LVS/ERC/ESD/SI/IR-Drop) after Placement and Routing step.
Step 12a: Perform the Routed Netlist-level Power Analysis, to know whether the design has met the power targets.
Step 12b: Perform Gate-level Simulation with the routed Netlist to check whether the design is meeting the functional requirement .
Step 12c: Perform Formal-verification between RTL vs routed Netlist to confirm that the place & route Tool has not altered the functionality.
Step 12d: Perform STA(Static Timing Analysis) with the SPEF file and routed netlist file, to check whether the Design is meeting the timing-requirements.
Step 12e: Perform Scan-Tracing , in the DFT tool, to check whether the scan-chain is built based on the DFT requirement, Peform the Fault-coverage with the DFT tool and Generate the ATPG test-vectors.
Step 12f: Convert the ATPG test-vector to a tester understandable format(WGL)
Step 12g: Perform DRC(Design Rule Check) verfication called as Physical-verification, to confirm that the design is meeting the Fabrication requirements.
Step 12h: Perform LVS(layout vs Spice) check, a part of the verification which takes a routed netlist converts to spice (call it SPICE-R) and convert the Synthesized netlist(call it SPICE-S) and compare that the two are matching.
Step 12i : Perform the ERC(Electrical Rule Checking) check, to know that the design is meeting the ERC requirement.
Step 12j: Perform the ESD Check, so that the proper back-to-back diodes are placed and proper guarding is there in case if we have both analog and digital portions in our Chip. We have seperate Power and Grounds for both Digital and Analog Portions, to reduce the Substrate-noise.
Step 12k: Perform seperate STA(Static Timing Analysis) , to verify that the Signal-integrity of our Chip. To perform this to the STA tool, the routed netlist and SPEF file(parasitics including coupling capacitances values), are fed to the tool. This check is important as the signal-integrity effect can cause cross-talk delay and cross-talk noise effects, and hinder in the functionality/timing aspects of the design.
Step 12l: Perform IR Drop analysis, that the Power-grid is so robust enough to with-stand the static and dynamic power-drops with in the design and the IR-drop is with-in the target limits.
Step 13: Once the routed design is verified for the design constraints, then now the next step is chip-finishing activities (like metal-slotting, placing de-coupling caps).
Step 14: Now the Chip Design is ready to go to the Fabrication unit, release files which the fab can understand, GDS file.
Step 15: After the GDS file is released , perform the LAPO check so that the database released to the fab is correct.
Step 16: Perform the Package wire-bonding, which connects the chip to the Package.
Prime Time Questions
1) What's PrimeTime?
Answer:PrimeTime is a full chip static analysis tool that can fully analyze a multimillion gate ASIC in a shortamount of time.
2) What files are required for PrimeTime to run?
Answer:PrimeTime needs four types of files before you can run it:1. Netlist file: Verilog, VHDL, EDIF2. Delay file: SPEF(standard parasitic format, it's from STARRC or place&route tool), SPF, SDF(standard delay format) 3. Library file: DB ( From library vendors)4. Constrains file: Synopsys Design Constraints(SDC) include 3 min requirement, clock, input delay and output delay
3) Can I use script in PrimeTime?
Answer: Yes, you should use tcl( Tool command language) whenever possible.
4) What PrimeTime check?
Answer:PrimeTime will check the following violations:1. Setup violations: The logic is too slow compare to the clock. With that in mind there are several things a designer can do to fix the setup violations.
Reduce the amount of buffering in the path. Replace buffers with 2 inverters place farther apart
Reduce larger than normal capacitance on a book’s output pin
Increase the size of books to decrease the delay through the book.
Make sure clock uncertainty is not to large for the technology library that youare using.
Reduce clock speed. This is a poor design technique and should be used as alast resort.
2. hold time violations: the logic is too fast. To fix hold violations in the design, the designer needs to simply add more delayto the data path. This can be done by
Adding buffers/inverter pairs/delay cells to the data path. Decreasing the size of certain books in the data path. It is better to reduce the books
closer to the capture flip flop because there is less likely hood of affecting other paths and causing new errors.
Add more capacitance to the output pin of books with light capacitance.
Fix the setup time violation first, and then hold time violation. If hold violations are not fixed beforethe chip is made, more there is nothing that can be done post fabrication to fix hold problems
unlike setup violation where the clock speed can be reduced.
3. Transition Violations: When a signal takes too long transiting from one logic level to another, a transition violation is reported. The violation is a function of the node resistance and capacitance.
The designer has two simple solutions to fix the transitions violations. Increase the drive capacity of the book to increase the voltage swing or decrease the
capacitance and resistance by moving the source gate closer to sink gate.
Increase the width of the route at the violation instance pin. This will decrease the resistance of the route and fix the transition violation
4. Capacitance Violations: The capacitance on a node is a combination of the fan-out of the output pin andthe capacitance of the net. This check ensures that the device does not drive morecapacitance than the device is characterized for.
The violation can be removed by increasing the drive strength of the book By buffering the some of the fan-out paths to reduce the capacitance seen by the output
pin.
5) What conditions are used to check setup violation?
Answer:
WorstCase => setup violations BestCase => hold violations We use the worst case delay when testing for setup violations and then we use the best case delay when testing for hold violations.
6) How to run PrimeTime in the unix?
[Linux] user@gmu>> pt_shell –f pt_script.tcl |& tee pt.log
Here are the sample PrimeTime script :
A total of three scripts must be created, one for each timing corner.# ------------------------------------------------------------# Library Declarations.# ------------------------------------------------------------set search_path ". /proj/timing/etc"set link_path "*"lappend link_path "stdCell_tt.db"# ------------------------------------------------------------
# Read in Design# ------------------------------------------------------------# Read in netlistread_file -f verilog top_level.v# Define top level in the hierarchycurrent_design "top_level"# Combine verilog and db files and identify any errors.link_design# Read in SPEF fileread_parasitics -quiet -format SPEF top_level.spef.gz# ------------------------------------------------------------# Apply Constraints# ------------------------------------------------------------# Read in timing constraitsread_sdc -echo top_level.sdc# Propagate clocks and add uncertainty to setup/hold calculationsset_propagated_clock [all_clocks]set_clock_uncertainty 0.2 [all_clocks]21# ------------------------------------------------------------# Time# ------------------------------------------------------------set_operating_conditions -min WORST -max WORST# Register to Registerreport_timing -from [all_registers -clock_pins] \-to [all_registers -data_pins] -delay_type max \-path_type full_clock –nosplit \-max_paths 1 -nworst 1 \-trans -cap -net > tc_reg2reg_setup.rptreport_timing -from [all_registers -clock_pins] \-to [all_registers -data_pins] -delay_type min \-path_type full_clock –nosplit \-max_paths 1 -nworst 1 \-trans -cap -net > tc_reg2reg_hold.rpt# Register to Outreport_timing -from [all_registers -clock_pins] \-to [all_outputs] -delay_type max \-path_type full_clock –nosplit \-max_paths 1 -nworst 1 \-trans -cap -net > tc_reg2out_setup.rptreport_timing -from [all_registers -clock_pins] \-to [all_outputs] -delay_type min \-path_type full_clock –nosplit \-max_paths 1 -nworst 1 \-trans -cap -net > tc_reg2out_hold.rpt# In to Register
report_timing -from [all_inputs]-to [all_registers -data_pins] \-delay_type max \-path_type full_clock –nosplit \-max_paths 1 -nworst 1 -trans \–cap -net > tc_in2reg_setup.rptreport_timing -from [all_inputs] \-to [all_registers -data_pins] \-delay_type min -path_type full_clock \-nosplit -max_paths 1 -nworst 1 \-trans -cap -net > tc_in2reg_hold.rpt# All Violators – Find Cap/Tran Violations# Summary of Setup/Hold Violationsreport_constraints -all_violators > tc_all_viol.rpt# Clock Skewreport_clock_timing -type skew -verbose > tc_clockSkew.rptexit
Design Constraints and Synthesis Questions
What are the various Design constraints used while performing Synthesis for a design?
Ans:Synopsys Design Constraints (SDC) is a standard time file format for the synthesis and prime time.
They are 3 basic requirements for the SDC files:Clock, input delay and output delays.
There are 4 timing path: Register to register input to register register to output input and output
1. Create the clocks (frequency, duty-cycle). e.g. create_clock -period 100 clk create_clock -period 100 -waveform {0 50} [get_ports {clk}]
2. Define the transition-time requirements for the input-ports e.g. set_max_path_delay delay_value
3. Specify the load values for the output ports
set_load [expr 5 * [load_of $REFLIB/$DFFCELL/$DFFCELL_IN_PIN]] [all_outputs]
4. For the inputs and the output specify the delay values(input delay and ouput delay), which are already consumed by the neighbour chip.
e.g.
set_output_delay [-add_delay] -clock [-clock_fall] [-fall] [-max] [-min][-reference_pin ] [-rise] [-source_latency_included]
set_output_delay -clock clk 0.5 [all_outputs]
set_input_delay [-add_delay] -clock [-clock_fall] [-fall] [-max] [-min][-reference_pin ] [-rise] [-source_latency_included] set_input_delay -clock clk 1.5 [get_ports myin*]
set_input_to_register_delay [-from inp_port];
set_input_to_register_delay 22 -from I*;
set_register_to_output_delay -to out_port;
5. Specify the case-setting (in case of a mux) to report the timing to a specific paths.
6. Specify the false-paths in the design e.g. set_false_path [-from from_port] [-through any_port] [-to to_port]; set_false_path -from resetd -through const2/*;
7. Specify the multi-cycle paths in the design. e.g. set_multicycle_path -from reg_port [-through_ any_port] [-to_port];
set_multicycle_path 2 -from /us/u1/dff*.q -to /u4/mem1/*.D";
8. Specify the clock-uncertainity values(w.r.t jitter and the margin values for setup/hold).
e.g. set_clock_uncertainty [-add] [-fall_from ] [-fall_to ][-from ] [-hold] [-rise_from ] [-rise_to ][-setup] [-to ]
set_clock_uncertainty -setup -rise_from clk1 -fall_to clk2 200ps set_clock_uncertainty 0.3 [get_clocks clk]
9. Specify few verilog constructs which are not supported by the synthesis tool.
Sample Sdc files mips32.s0.tcl: (constraints) echo "** LOG(mips32.s0.tcl): SCENARIO (S0)" set PERIOD 10 ;# 10 ns clock period -> 100 MHz max set INPUT_DELAY 1.0 set OUTPUT_DELAY 1.0 set CLOCK_LATENCY 1.5 set MIN_TO_DELAY 1.0 set MAX_TRANSITION 0.5
# Preserve all heirarchy (set to true when RTL is in development) set NO_UNGROUP false
echo "** LOG(mips32.s0.tcl): S0 PERIOD: ${PERIOD}"
# Clock basics # Set clk period create_clock -name "clk" -period $PERIOD [get_port clk] # Set clk latency: time it takes for clk signal to get from source to FF sync pin. set_clock_latency $CLOCK_LATENCY [get_clocks clk] # Set clk uncertainity (jitter/skew): maximum time difference between two pins on # a chip receiving the same clk signal set_clock_uncertainty 0.3 [get_clocks clk] # Set clk transition: time for clk to go 0->1 or 1->0 set_clock_transition 0.4 [get_clocks clk]
# Grouping clk/inputs/outputs for better optimization group_path -name CLK -to clk group_path -name INPUTS -through [all_inputs] group_path -name OUTPUTS -to [all_outputs]
# Set I/O names
set INPUTPORTS [remove_from_collection [all_inputs] [get_ports clk]] set OUTPUTPORTS [all_outputs]
# Set delay constraints on I/O boundaries set_input_delay -clock "clk" -max $INPUT_DELAY $INPUTPORTS set_input_delay -clock "clk" -min $MIN_TO_DELAY $INPUTPORTS
set_output_delay -clock "clk" -max $OUTPUT_DELAY $OUTPUTPORTS set_output_delay -clock "clk" -min $MIN_TO_DELAY $OUTPUTPORTS
# Set the load and driving cell set REFLIB [file rootname $TARGET_LIBRARY_FILES] set DFFCELL "DFFARX1" set DFFCELL_IN_PIN "D" set DFFCELL_OUT_PIN "Q"
# Set maximum load to be 5X the input capacitance of a DFFARX1 cell set_load [expr 5 * [load_of $REFLIB/$DFFCELL/$DFFCELL_IN_PIN]] [all_outputs]
# Set a DFF flip flop as the driving cell for all inputs (pipelined stages) set_driving_cell -library $REFLIB -lib_cell $DFFCELL -pin $DFFCELL_OUT_PIN [all_inputs]
# Driving cell does not drive clk so remove it remove_driving_cell [get_ports clk]
# Set maximum transition time of any net in design to be 1 ns. set_max_transition $MAX_TRANSITION [current_design]
# Set the maximum capacitance on any net in the design to be 1 pF. set_max_capacitance 1.0 [current_design]
# Set maximum fanout of any net in the design set_max_fanout 20 [current_design]
# Minimize the area set_max_area 0 Sample Design Compiler Synthesis script common-setup.tcl: Name of top-level design set DESIGN_NAME "mips32"
# Set Design Path set DESIGN_PATH [file normalize ~/cad/mips32]
# Aboslute path prefix variable for library/design data. Use this variable to # prefix the common absolute path to the common variables defined # below. Absolute paths are mandatory are mandary for heirarchical RM flow. set DESIGN_REF_DATA_PATH "${DESIGN_PATH}/ref"
# List of hierarchical block design names "DesignA DesignB" ... set HIERARCHICAL_DESIGNS ""
# List of hierarchical block cell instance names "u_DesignA u_DesignB" ... set HIERARCHICAL_CELLS ""
# Additional search path to be added to the default search path set ADDITIONAL_SEARCH_PATH "${DESIGN_PATH} \ ${DESIGN_REF_DATA_PATH}/icons \ ${DESIGN_REF_DATA_PATH}/itf \ ${DESIGN_REF_DATA_PATH}/models \ ${DESIGN_REF_DATA_PATH}/plib \ ${DESIGN_REF_DATA_PATH}/tech \ ${DESIGN_REF_DATA_PATH}/tluplus"
# Target libraries set TARGET_LIBRARY_FILES "saed90nm_typ.db"
# Symbol library set SYMBOL_LIBRARY_FILES "saed90nm.sdb"
# Extra link logical libraries not included in TARGET_LIBRARY_FILES set ADDITIONAL_LINK_LIB_FILES ""
# List of max/min library pairs set MIN_LIBRARY_FILES "saed90nm_max.db saed90nm_min.db"
# Milkyway refere libraries (include IC compiler ILMs here) set MW_REFERENCE_LIB_DIRS "${DESIGN_REF_DATA_PATH}/saed90nm_fr"
# Reference control file to define the MW reference libraries set MW_REFERENCE_CONTROL_FILE ""
# Milkyway technology file set TECH_FILE "${DESIGN_REF_DATA_PATH}/tech/saed90nm.tf"
# Mapping file for TLUplus set MAP_FILE "saed90nm.map"
# Max/Min TLUplus file set TLUPLUS_MAX_FILE "saed90nm_1p9m_1t_Cmax.tluplus"
set TLUPLUS_MIN_FILE "saed90nm_1p9m_1t_Cmin.tluplus"
# Names for power/ground nets set MW_POWER_NET "VDD" set MW_POWER_PORT "VDD" set MW_GROUND_NET "VSS" set MW_GROUND_PORT "VSS"
# Min/Max routing layer set MIN_ROUTING_LAYER "" set MAX_ROUTING_LAYER ""
# Tcl file with library modificatiosn for don't use set LIBRARY_DONT_USE_FILE ""
# Multi-Voltage Common Variables # # Define the following MV common variables for the RM scripts for multi-voltage # flows. Use as few or as many of the following definitions as needed by your # design. set PD1 "" ;# Name of power domain/voltage area 1 set PD1_CELLS "" ;# Instances to include in power domain/voltage area 1 set VA1_COORDINATES {} ;# Coordinates for voltage area 1 set MW_POWER_NET1 "VDD1" ;# Power net for voltage area 1 set MW_POWER_PORT1 "VDD" ;# Power port for voltage area 1
set PD2 "" ;# Name of power domain/voltage area 2 set PD2_CELLS "" ;# Instances to include in power domain/voltage area 2 set VA2_COORDINATES {} ;# Coordinates for voltage area 2 set MW_POWER_NET2 "VDD2" ;# Power net for voltage area 2 set MW_POWER_PORT2 "VDD" ;# Power port for voltage area 2
# Timestamp sh date
# Apply the dc-setup.tcl to setup libraries, paths, variables, etc source ./dc/dc-setup.tcl
# Design Compiler Reference Methodology Script for Top-Down Flow
# Add any additional variables here
# No additional flow variables are being recommended
# Setup for Formality verification: SVF should always be written to allow # Formality verification for advanced optimizations set_svf ${RESULTS_DIR}/${DESIGN_NAME}.mapped.svf
# Setup SAIF name mapping database: Include an RTL SAIF for better power # optimizaiton and analysis saif_map -start
# Read in the RTL design: read in either RTL source files or an elaborated # design (DDC) define_design_lib WORK -path ./work analyze -format verilog ${RTL_SOURCE_FILES} elaborate ${DESIGN_NAME} write -hierarchy -format ddc -output ${RESULTS_DIR}/${DESIGN_NAME}.elab.ddc
# OR read an elaborated design from the same release. Using an elaborated design # from an older release will not give best results. # # read_ddc ${DESIGN_NAME}.elab.ddc # current_design ${DESIGN_NAME}
# Resolve design/modules references by linking design to logical libraries link
# Apply logical design constraints source ${DESIGN_NAME}.s0.tcl # We can enable analysis and optimization for multiple clocks per register. To # use this, we must constrain to remove false interactions between mutually # exclusive clocks. This is needed to prevent unnecesasry analysis that can result # in a significant runtime incrase with this feature enabled. # # For mips32, it is unnecessary since we have a single clock. # set_clock_groups -physically_exlucive | -logically_exclusive | -asynchronous \ # -group {CLKA, CLKB} -group {CLKC, CLKD} # # set timing_enable_multiple_clocks_per_reg true
# Apply operating conditions on top level. Set min/max for delay analysis and # typical for normal usage. set_operating_conditions -max WORST \ -max_library [file rootname $max_library] \ -min BEST -min_library [file rootname $min_library] set_operating_conditions TYPICAL
# Create default path groups: separating these paths can help improve optimization. # Remove these path group settings if user path graoups have already been defined. set ports_clock_root [get_ports [all_fanout -flat -clock_tree -level 0]] group_path -name REGOUT -to [all_outputs] group_path -name REGIN -from [remove_from_collection [all_inputs] $ports_clock_root] group_path -name FEEDTHROUGH -from [remove_from_collection [all_inputs] $ports_clock_root] -to [all_outputs]
# Power optimization
# Clock gating setup # Default clock_gating_style suits most designs. Change only if necessary. # set_clock_gating_style ...
# Clock gate insertion is now performed during compile_ultra -gate_clock # so insert_clock_gating is no longer recommended at this step.
# For better timing optimization of enable logic, clock latency for # clock gating cells can be optionally specified.
# set_clock_gate_latency -clock -stage \ # -fanout_latency {fo_range1 latency_val1 fo_range2 latency_val2 ...}
# Apply power optimization constraints # Include a SAIF file, if possible, for power optimization. If a SAIF file # is not provided, the default toggle rate of 0.1 will be used for propagating # switching activity. # read_saif -auto_map_names -input ${DESIGN_NAME}.saif -instance < DESIGN_INSTANCE > -verbose
# Remove set_max_total_power power optimization constraint from scripts in 2008.09 # Enable both of the following settings for total power optimization set_max_leakage_power 0 # set_max_dynamic_power 0
if {[shell_is_in_topographical_mode]} { # Setting power constraints will automatically enable power prediction using clock tree estimation. # If you are not setting any power constraints and you still want to report # correlated power, you can use the following command to turn on power prediction. set_power_prediction true }
if {[shell_is_in_topographical_mode]} {
# Apply physical desigin constraints # Optional: Floorplan information can be read in here if available. # This is highly recommended for irregular floorplans. # # Floorplan constraints can be extracted from DEF files using # extract_physical_constraints OR provided from Tcl commands. # # DEF is the recommended input format to maximize the use of the latest # floorplan read capabilities of Design Compiler topographical mode.
# Specify ignored layers for routing to improve correlation # Use the same ignored layers that will be used during place and route if {${MIN_ROUTING_LAYER} != ""} { set_ignored_layers -min_routing_layer ${MIN_ROUTING_LAYER} } if {${MAX_ROUTING_LAYER} != ""} { set_ignored_layers -max_routing_layer ${MAX_ROUTING_LAYER} } report_ignored_layers
# If the macro names change after mapping and writing out the design due to # ungrouping or Verilog change_names renaming, it may be necessary to translate # the names to correspond to the cell names that exist before compile.
# During DEF constraint extraction, extract_physical_constraints automatically # matches DEF names back to precompile names in memory using standard matching rules.
# Modify fuzzy_query_options if other characters are used for hierarchy separators # or bus names.
# set_fuzzy_query_options -hierarchical_separators {/ _ .} \ # -bus_name_notations {[] __ ()} \ # -class {cell pin port net} \ # -show
# Note: The -site_row or -pre_route options are not needed to extract this info # from the DEF file. These are extracted automatically and saved in DDC. # Only use these options if you want this info to be included in the # ASCII output from "extract_physical_constraints -output". if {[file exists [which ${DESIGN_NAME}.def]]} { extract_physical_constraints ${DESIGN_NAME}.def }
# OR
# For Tcl constraints, the name matching feature must be explicitly enabled
# and will also use the set_fuzzy_query_options setttings. This should # be turned off after the constraint read in order to minimize runtime.
# set fuzzy_matching_enabled true # source -echo -verbose ${DESIGN_NAME}.physical_constraints.tcl # set fuzzy_matching_enabled false
# Note: Include the -site_row or -pre_route options with either # write_physical_constraints or report_physical_constraints if you also # want to include these in the ASCII output files. Site rows and pre-routes # are automatically extracted from the DEF and saved in the DDC even if these # options are not specified.
# You can save the extracted constraints for fast loading next time. # write_physical_constraints -output ${DESIGN_NAME}.physical_constraints.tcl
# Verify that all the desired physical constraints have been applied report_physical_constraints > ${REPORTS_DIR}/${DESIGN_NAME}.physical_constraints.rpt
}
# Apply additional optimization constraints # Prevent assignment statment in the Verilog netlist set_fix_multiple_port_nets -all -buffer_constants
# Insert level-shifters on all clocks set auto_insert_evel_shifters_on_clocks all
# Preserve subdesign interfaces # NOTE; when design is matured, we can turn this off so it does heirarchical # optimization by pushing subdesign constants (pins connected to logic 0/1) to # the external environment and optimizing that. #set compile_preserve_subdesign_interfaces true
# Write out all unconnected pins in verilog netlist set verilogout_show_unconnected_pins true
# Fix hold-time violations on clock by slowing down data signals set_fix_hold [get_clocks clk]
# Fix timing violations if not in topographical mode if {![shell_is_in_topographical_mode]} { set compile_top_all_paths true } # Compile the Design
# # Recommended Options: # # -scan # -gate_clock # -retime # -timing_high_effort_script # -area_high_effort_script # -congestion # -num_cpus # # Use compile_ultra as your starting point. For test-ready compile, include # the -scan option with the first compile and any subsequent compiles. # # Use -gate_clock to insert clock-gating logic during optimization. This # is now the recommended methodology for clock gating. # # Use -retime to enable adapative retiming optimization for further timing # benefit without any runtime or memory overhead. # # The -timing_high_effort_script or the -area_high_effort_script option # may also be used to try and improve the optimization results at the tradeoff # of some additional runtime. # # The -congestion option (topographical mode only) enables specialized optimizations that # reduce routing related congestion during synthesis and scan compression insertion # with DFT Compiler. Only enable congestion optimization if required. # This option requires a license for Design Compiler Graphical. # # Use -num_cpus to enable multi-core optimization to improve runtime. Note # that this feature has special usage and license requirements. See the following # article for more info: https://solvnet.synopsys.com/retrieve/024947.html
if {[shell_is_in_topographical_mode]} { # Use the "-check_only" option of "compile_ultra" to verify that your # libraries and design are complete and that optimization will not fail # in topographical mode. Use the same options as will be used in compile_ultra. compile_ultra -check_only }
if {$NO_UNGROUP} { compile_ultra -gate_clock -area_high_effort_script -no_autoungroup -retime } else { compile_ultra -gate_clock -area_high_effort_script -retime }
# Write Out Final Design and Reports # # .ddc: Recommended binary format used for subsequent Design Compiler sessions # Milkyway: Recommended binary format for IC Compiler # .v : Verilog netlist for ASCII flow (Formality, PrimeTime, VCS) # .spef: Topographical mode parasitics for PrimeTime # .sdf: SDF backannotated topographical mode timing for PrimeTime # .sdc: SDC constraints for ASCII flow # change_names -rules verilog -hierarchy
# Check the design for consistency check_design
# Write and close SVF file and make it available for immediate use set_svf off
# Write out design write -format ddc -hierarchy -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.ddc write -f verilog -hierarchy -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.v
# Write out design data if {[shell_is_in_topographical_mode]} { # Note: Include the -site_row or -pre_route options with write_physical_constraints # if you also want to include these in the ASCII output files. Site rows and pre-routes # are automatically extracted from the DEF and saved in the DDC even if these # options are not specified. write_physical_constraints -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.physical_constraints.tcl
# Write parasitics data for static timing analysis write_parasitics -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.spef
# Write SDF back annotation data from DCT placment for static timing analysis write_sdf ${RESULTS_DIR}/${DESIGN_NAME}.mapped.sdf
# Do not write out net RC info onto SDC set write_sdc_output_lumped_net_capacitance false set write_sdc_output_net_resistance false }
write_sdc -nosplit ${RESULTS_DIR}/${DESIGN_NAME}.mapped.sdc
# If SAIF is used, write out SAIF name mapping file for PrimeTime-PX saif_map -type ptpx -write_map ${RESULTS_DIR}/${DESIGN_NAME}.mapped.SAIF.namemap
# Generate final reports - qor, timing, area, congestion, power, clock gating report_qor > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.qor.rpt report_timing -nworst 10 -transition_time -nets -attributes -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.timing.rpt
report_hierarchy -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.hierarchy.rpt report_resources -nosplit -hierarchy > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.resources.rpt report_constraint > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.constraints.rpt
if {[shell_is_in_topographical_mode]} { report_area -physical -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.area.rpt
# report_congestion (topographical mode only) reports estimated routing related # congestion after topographical mode synthesis. This command requires a # license for Design Compiler Graphical. # report_congestion > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.congestion.rpt } else { report_area -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.area.rpt }
# Use SAIF file for power analysis #read_saif -auto_map_names -input ${DESIGN_NAME}.saif -instance < DESIGN_INSTANCE > -verbose
report_power -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.power.rpt report_clock_gating -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.clock_gating.rpt
# Write the shell command script to save current settings write_script -out ${RESULTS_DIR}/${DESIGN_NAME}.script
# Write out Milkyway Design for Top-Down Flow # NOTE: This should be the last step in the script if {[shell_is_in_topographical_mode]} { write_milkyway -overwrite -output ${DESIGN_NAME}_DCT }
# Timestamp sh date
# Terminate exit
dc-setup.tcl
# Source the file that is common to ALL Synopsys tools to setup commmon variables source common-setup.tcl
# Setup variables: Portions of the dc_setup.tcl may be used by other tools, so # do check for DC only commands if {$synopsys_program_name == "dc_shell"} { # Change alib_library_analysis_path to point to a centeral cache of analyzed # libraries to save some runtime and disk space. The following setting only # reflects the default value and shoudl be changed to a central location for # best results. set alib_library_analysis_path . # Add any other DC variables here }
# List of source files to read if reading from RTL set RTL_SOURCE_FILES "${DESIGN_PATH}/src/mips32.v";
# The following directories are created and used by DC scripts to direct the # location of the output files set REPORTS_DIR "syn-reports" set RESULTS_DIR "syn-results" set LOG "syn-log" file mkdir ${REPORTS_DIR} file mkdir ${RESULTS_DIR} file mkdir ${LOG}
# Library Setup: Define all the library variables shared by all the front-end # tools. It is designed to work with the settings in common-setup.tcl without # any additional modification. set search_path ". ${DESIGN_PATH}/synopsys/syn \ ${DESIGN_PATH}/synopsys/syn/dc \ ${ADDITIONAL_SEARCH_PATH} $search_path"
# Milkyway variable settings: make sure to define the variables mw_logic1_net, # mw_logic0_net and mw_design_library as they are need by write_milkway command. set mw_logic1_net ${MW_POWER_NET} set mw_logic0_net ${MW_GROUND_NET}
set mw_reference_library ${MW_REFERENCE_LIB_DIRS} set mw_design_library ${DESIGN_NAME}_lib
set mw_site_name_mapping [list CORE unit Core unit core unit]
# The remainder of the seutp should only be performed in Design Compiler if {$synopsys_program_name == "dc_shell"} {
# Include all libraries for multi-Vth leakage power optimization set target_library ${TARGET_LIBRARY_FILES} set symbol_library ${SYMBOL_LIBRARY_FILES} set synthetic_library dw_foundation.sldb set link_library "* $target_library $ADDITIONAL_LINK_LIB_FILES $synthetic_library"
# Set min libraries if they exist foreach {max_library min_library} $MIN_LIBRARY_FILES { set_min_library $max_library -min_version $min_library }
# If in topological mode, create/open milkway library and setup TLU+ files for # RC extraction if {[shell_is_in_topographical_mode]} {
# Only create new Milkyway design library if it doesn't already exist if {![file isdirectory $mw_design_library]} { create_mw_lib -technology $TECH_FILE \ -mw_reference_library $mw_reference_library $mw_design_library \ -hier_separator {/} } else { # If Milkyway design library already exists, ensure that is consistent with # specified Milkyway reference libraries set_mw_lib_reference $mw_design_library -mw_reference_library $mw_reference_library }
open_mw_lib $mw_design_library check_library
set_tlu_plus_file -max_tluplus $TLUPLUS_MAX_FILE \ -min_tluplus $TLUPLUS_MIN_FILE \ -tech2itf_map $MAP_FILE check_tlu_plus_files }
# Library modifications: Apply library modifications here after the # libraries are loaded. if {[file exists [which ${LIBRARY_DONT_USE_FILE}]]} { source -echo ${LIBRARY_DONT_USE_FILE} } }
dc.tcl:
# Timestamp sh date
# Apply the dc-setup.tcl to setup libraries, paths, variables, etc source ./dc/dc-setup.tcl
# Synopsys auto setup mode set synopsys_auto_setup true
# Note: The Synopsys Auto Setup mode is less conservative than the Formality # default mode, and is more likely to result in a successful verification # out-of-the-box. # # Using the Setting this variable will change the default values of the variables # listed here below. You may change any of these variables back to their default # settings to be more conservative. Uncomment the appropriate lines below to # revert back to their default settings: # set hdlin_ignore_parallel_case true # set hdlin_ignore_full_case true # set verification_verify_directly_undriven_output true # set hdlin_ignore_embedded_configuration false # set svf_ignore_unqualified_fsm_information true
# Other variables with changed default values are described in the next few sections.
# The Synopsys Auto Setup mode sets undriven signals in the reference design to "0" similar to DC. # Undriven signals in the implementation design are set to "X". # Uncomment the next line to revert back to the more conservative default setting: set verification_set_undriven_signals BINARY:X
# The Synopsys Auto Setup mode will produce warning messages, not error messages, # when Formality encounters potential differences between simulation and synthesis. # Uncomment the next line to revert back to the more conservative default setting: set hdlin_error_on_mismatch_message true
# The Synopsys Auto Setup mode, along with the SVF file, will appropriately # set the clock-gating variable. Otherwise, the user will need to notify # Formality of clock-gating by uncommenting the next line: # set verification_clock_gate_hold_mode any
# Set this variable ONLY if your design contains instantiated DW or function-inferred DW # set hdlin_dwroot "" ;# Enter the pathname to the top-level of the DC tree
# If the design has missing blocks or missing components in both the # reference and implementation designs, uncomment the following variable # so that Formality can complete linking each design: # set hdlin_unresolved_modules black_box
# Set SVF file to read set_svf ${RESULTS_DIR}/${DESIGN_NAME}.mapped.svf
# Read in libraries foreach tech_lib "${TARGET_LIBRARY_FILES} ${ADDITIONAL_LINK_LIB_FILES}" { read_db -technology_library $tech_lib }
# Read in the reference (original) design as verilog/vhdl source read_verilog -r ${RTL_SOURCE_FILES} -work_library WORK # Set reference design set_top r:/WORK/${DESIGN_NAME}
# Read in the mapped design # For verilog # read_verilog -i ${RESULTS_DIR}/${DESIGN_NAME}.mapped.v
# For DDC read_ddc -i ${RESULTS_DIR}/${DESIGN_NAME}.mapped.ddc
# Or Milkyway # read_milkyway -i -libname ${mw_design_library} -cell_name ${DESIGN_NAME}_DCT ${mw_reference_library}
# Set implementation design set_top i:/WORK/${DESIGN_NAME} # Or for Milkyway # set_top i:/${mw_design_library}/${DESIGN_NAME}
# Configure constant ports. When using the Synopsys Auto Setup mode, # the SVF file will convey information automatically to Formality about # how to disable scan. # # Otherwise, manually define those ports whose inputs should be assumed constant # during verification. # # Example command format: # # set_constant -type port i:/WORK/$DESIGN_NAME/
# Match compare points and report unmatched points match report_unmatched_points > ${REPORTS_DIR}/${DESIGN_NAME}.fmv_unmatched_points.rpt
# Verify and report if {![verify]} { save_session -replace ${REPORTS_DIR}/${DESIGN_NAME} report_failing_points > ${REPORTS_DIR}/${DESIGN_NAME}.fmv_failing_points.rpt report_aborted > ${REPORTS_DIR}/${DESIGN_NAME}.fmv_aborted_points.rpt }
# Timestamp sh date
# Terminate exit
CAM related Questions
1) What is CAM?
Content-addressable memory (CAM) is a special type of computer memory used in certain very high speed searching applications. It is also known as associative memory, associative storage, or associative array.A CAM is designed such that the user supplies a data word and the CAM searches its entire memory to see if that data word is stored anywhere in it. If the data word is found, the CAM returns a list of one or more storage addresses where the word was found (and in some architectures, it also returns the data word, or other associated pieces of data). Thus, a CAM is the hardware embodiment of what in software terms would be called an associative array.
2) What is difference between TCAM and Binary CAM ?
Binary CAM is the simplest type of CAM which uses data search words comprised entirely of 1s and 0s. Ternary CAM allows a third matching state of "X" or "Don't Care" for one or more bits in the stored dataword, thus adding flexibility to the search. For example, a ternary CAM might have a stored word of "10XX0" which will match any of the four search words "10000", "10010", "10100", or "10110". The added search flexibility comes at an additional cost over binary CAM as the internal memory cell must now encode three possible states instead of the two of binary CAM. This additional state is typically implemented by adding a mask bit ("care" or "don't care" bit) to every memory cell.
3) What is associative array?
An associative array (also associative container, map, mapping, dictionary, finite map, and in query-processing an index or index file) is an abstract data type composed of a collection of unique keys and a collection of values, where each key is associated with one value (or set of values). The operation of finding the value associated with a key is called a lookup or indexing, and this is the most important operation supported by an associative array. The relationship between a key and its value is sometimes called a mapping or binding. For example, if the value
associated with the key "bob" is 7, we say that our array maps "bob" to 7. Associative arrays are very closely related to the mathematical concept of a function with a finite domain. As a consequence, a common and important use of associative arrays is in memoization.
Clock Domain Crossing Timing Q&A
1) What are the major issues for Clock Domain Crossing ?
Answers:
They are 3 major problems for clock domain crossing:
A. Metastability - the transaction of data violated the setup or hold time of the destination FF. It caused the ouput may oscillate for an indefinite amount time. The Metastability may lead to the high current or even burn out of the chip. It also caused functional issue and timing issue.
B. Data Loss - whenever a new source data is generated, it may not be captured by the destination domain in the very first cycle of the destination clock because of metastability. Plus the different clock frequency of source and destination may also caused the data loss.
C. Data Incoherency - whenever new data is generated in the source clock domain, it may take 1 or more destination clock cycles to capture it, depending on the arrival time of active clock edges.
ASIC Gate Interview Questions Part #1
Here are the basic interview questions and answer from my previous experience and other source.
1) What is the difference between a latch and a flip lop. For the same input, how would the output look for a latch and for a flip-flop.
Latch is a level-sensitive "sequential" element. The output captures the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes.
It's faster than Flip-flop, it takes less gates to implemented ( less area). But it's sensitive to glitches on enable pin. It also can be clocked or clock less.
Flip-flop is a edge sensitive "sequential" element. Flip flop will store the input only when there is a rising or falling edge of the clock.
FF is immune to glitches. D-FF is built from two latches. They are in master slave configuration.
2) What's finite state machines?
A finite state machine(FSM), is a model of behavior composed of a finite number of states, transitions between those states, and actions. It is similar to a "flow graph" where we can inspect the way in which the logic runs when certain conditions are met.They are two types of FSM. Mealy Machine and Moore Machine:
Moore Machines uses only entry actions and output depends on the state.
Mealy Machines uses only input actions and output depends on the input and the state.
For more detail, please check this link
3) Explain the differences between "direct Mapped", "fully Associative" and "Set Associative" caches.
Answer:If each block has only one place it can appear in the cache, the cacheis said to be direct mapped . The mapping is usually (block-frame address) modulo (number of blocks in cache).
If a block can be placed anywhere in the cache, the cache is said to befully associative .
If a block can be placed in a restricted set of places in the cache, the cacheis said to be set associative . A set is a group of two or more blocks in the cache. A block is first mapped onto a set, and then the blockcan be placed anywhere within the set. The set is usually chosen by bitselection; that is, (block-frame address) modulo (number of sets in cache). If there are n blocks in a set, the cache placement is called n-way set associative .
4) Design a four-input NAND gate using only two-input NAND gates.
Answer:
Tie the inputs of NAND gate together to get an inverter. The result is as following:
Verilog Interview Questions Part #1
1) How re blocking and non-blocking statements executed?
Answer:In the blocking statement, the RHS will be evaluated and the LHS will be then updated without any interruptions.
In the non-blocking statement, RHS will be evaluated at the beginning of the time step. Then the LHS will be updated at the end of the time step. Within the whole period, the other process can run in parallel.
2) How do you model a synchronous and asynchronous reset in Verilog?
Answer:Synchronous reset:
always @(posedge clk)begin----if (reset)begin-----endend
Asynchronous reset:
always @(posedge clk or negedge reset)begin-----if (!reset)begin-----end
end
In asynchronous reset, the always block will invoked at the negative edge of the reset signal, irrespective of clock's value.
3) What happens if there is connecting wires width mismatch?
Answer:
For examples:RHS[7:0] = LHS[15:0]
The end result is LHS[7:0] = RHS[7:0];The assignments starts from LSBs of the signals, and ends at the MSB of smaller width signal.
4) What are different options that can be used with $display statement in Verilog?
%b - binary%c - ASCII character%d - Decimal%h - Hexadecimal%m - Hierarchical name%o - Octal%s - Steing%t - Time%v - Net signal strength
5) Give the precedence order of the operators in Verilog.
Answer:
Precedence rules for operators
+ - ! ~ (unary) highest precedence
* / %
+ - (binary)
<< >>
< <= > >=
== != === !==
& ~&
^ ^~
| ~|
&&
||
?: (conditional operator) lowest precedence
6) Should we include all the inputs of a combinational circuit in the sensitivity lists? Give reason.
Answer:
Yes, in combinational circuit all inputs should be included in the sensitivity lists, otherwise, it will result in a synthesis error.
7) What is the difference between a task and a function in verilog?
Answer:
Function Task
Time-Control statementsNo, shall execute in one simulation time unit
Yes
Call function or tasks Cannot call tasks Can call both tasks and functions
input type argumentat least 1 input type argument and shall not have an output or inout type argument
can have 0 or more arguments of any type
return value return a single value shall not return a value
P
Verilog Interview Questions Part #2
1) Given the following Verilog Code, what value of a "a" is displayed?
always @(clk) begina = 0;a <= 1; $display(a); end Answer: Verilog scheduling semantics basically imply a 4 level deep queue for the current simulation time: 1: Active Evens ( blocking statements) 2: Inactive Events ( #0 delays, etc) 3: Non-Blocking Assign updates ( non-blocking statements ) 4: Monitor Events ($display, $monitor, etc ). Since the "a=0" is an active event, it's scheduled into the 1st "queue". The "a<= 1" is a non-blocking event, so it's placed into the 3rd queue. Finally, the display statement is placed into the 4th queue. Only events in the active queue are completed this sim cycle: 1st sim cycle: a=0, display show a=0; 2nd sim cycle: display a =1; 2)
Show the waveform of the following code:
always @(a)begin#10 ( same as blocking statement )b1 =a;end
always@(a)beginb2 = #10 a; ( #10 as the delay )end
Answer:
always @(a)begin#10 ( same as blocking statement )b1 =a;end
always@(a)beginb2 = #10 a; ( #10 as the delay )end
a ====____________________b1 _______________________t =0, t=10nsat t=10ns, b1 = a;
a ===_____________________b1 ______________===______t =0, t=10nsRead a at time t=0, assign the b2 =a at 10ns
2) Given the following snipet of Verilog code, draw out the waveforms for clk and a
always @(clk)begina=0;#5 a=1;end
Answer:
You should add the always@(posedge clk), otherwise, the result will be unstable.
10 30 50 70 90clk ___===___===___===___===___===___
a __________________===__________
Verilog Interview Questions Part #4
1) Write code for 2:1 MUX using different coding methods?
Use assign statement:
7 module mux_using_assign(8 din_0 , // Mux first input9 din_1 , // Mux Second input10 sel , // Select input11 mux_out // Mux output12 );13 //-----------Input Ports---------------14 input din_0, din_1, sel ;15 //-----------Output Ports---------------16 output mux_out;17 //------------Internal Variables--------18 wire mux_out;19 //-------------Code Start-----------------20 assign mux_out = (sel) ? din_1 : din_0;2122 endmodule //End Of Module mux
Use if statement7 module mux_using_if(8 din_0 , // Mux first input9 din_1 , // Mux Second input10 sel , // Select input11 mux_out // Mux output12 );13 //-----------Input Ports---------------14 input din_0, din_1, sel ;15 //-----------Output Ports---------------16 output mux_out;17 //------------Internal Variables--------18 reg mux_out;19 //-------------Code Starts Here---------20 always @ (sel or din_0 or din_1)21 begin : MUX22 if (sel == 1'b0) begin23 mux_out = din_0;24 end else begin25 mux_out = din_1 ;26 end27 end2829 endmodule //End Of Module mux
Use Case statement7 module mux_using_case(8 din_0 , // Mux first input9 din_1 , // Mux Second input10 sel , // Select input11 mux_out // Mux output12 );13 //-----------Input Ports---------------14 input din_0, din_1, sel ;15 //-----------Output Ports---------------16 output mux_out;17 //------------Internal Variables--------18 reg mux_out;19 //-------------Code Starts Here---------20 always @ (sel or din_0 or din_1)21 begin : MUX22 case(sel )23 1'b0 : mux_out = din_0;24 1'b1 : mux_out = din_1;25 endcase26 end2728 endmodule //End Of Module mux
2) What's the difference between === and ==?
Answer:"a===b" a equal to b, including x and z (Case equality)"a==b" a equal to b, result may be unknown (logical equality)The equality operators ( = = , ! = ) will yield an x if either operandhas x or z in its bits. Where as the case equality operators ( = = = ,! = = ) compare both operands bit by bit and compare all bits,including x and z.
3) Write code for a parallel encoder and a priority encoder?
module pri_encoder_using_assign (8 binary_out , // 4 bit binary output9 encoder_in , // 16-bit input
10 enable // Enable for the encoder11 );1213 output [3:0] binary_out ;14 input enable ;15 input [15:0] encoder_in ;1617 wire [3:0] binary_out ;18 19 assign binary_out = ( ! enable) ? 0 : (20 (encoder_in == 16'bxxxx_xxxx_xxxx_xxx1) ? 0 : 21 (encoder_in == 16'bxxxx_xxxx_xxxx_xx10) ? 1 : 22 (encoder_in == 16'bxxxx_xxxx_xxxx_x100) ? 2 : 23 (encoder_in == 16'bxxxx_xxxx_xxxx_1000) ? 3 : 24 (encoder_in == 16'bxxxx_xxxx_xxx1_0000) ? 4 : 25 (encoder_in == 16'bxxxx_xxxx_xx10_0000) ? 5 : 26 (encoder_in == 16'bxxxx_xxxx_x100_0000) ? 6 : 27 (encoder_in == 16'bxxxx_xxxx_1000_0000) ? 7 : 28 (encoder_in == 16'bxxxx_xxx1_0000_0000) ? 8 : 29 (encoder_in == 16'bxxxx_xx10_0000_0000) ? 9 : 30 (encoder_in == 16'bxxxx_x100_0000_0000) ? 10 : 31 (encoder_in == 16'bxxxx_1000_0000_0000) ? 11 : 32 (encoder_in == 16'bxxx1_0000_0000_0000) ? 12 : 33 (encoder_in == 16'bxx10_0000_0000_0000) ? 13 : 34 (encoder_in == 16'bx100_0000_0000_0000) ? 14 : 15);3536 endmodule
module encoder_using_case(8 binary_out , // 4 bit binary Output9 encoder_in , // 16-bit Input10 enable // Enable for the encoder11 );12 output [3:0] binary_out ;13 input enable ;14 input [15:0] encoder_in ;15 16 reg [3:0] binary_out ;17 18 always @ (enable or encoder_in)19 begin20 binary_out = 0;21 if (enable) begin22 case (encoder_in)23 16'h0002 : binary_out = 1;24 16'h0004 : binary_out = 2;
25 16'h0008 : binary_out = 3;26 16'h0010 : binary_out = 4;27 16'h0020 : binary_out = 5;28 16'h0040 : binary_out = 6;29 16'h0080 : binary_out = 7;30 16'h0100 : binary_out = 8;31 16'h0200 : binary_out = 9;32 16'h0400 : binary_out = 10;33 16'h0800 : binary_out = 11;34 16'h1000 : binary_out = 12;35 16'h2000 : binary_out = 13;36 16'h4000 : binary_out = 14;37 16'h8000 : binary_out = 15;38 endcase39 end40 end4142 endmodule
Verilog Interview Questions Part #3
1) What is the difference between the following two lines of verilog code?
#5 a=b;a= #5 b;
Answer:#5 a=b; Wait 5 time units before doing the action for "a=b".
a= #5 b; The value of b is calculated and stored in an internal temp register. After 5 time units, assign this stored value to a.
2) What is the difference between
c foo ? a:b;
and
if(foo) c=a; else c=b;
Answer:
The ? merges answers if the condition is "x", so for instance if foo = 1'bx, a=2'b10 and b=2'b11,you'd get c=2'b1x.
On the other hand, if treats Xs and Zs as FALSE, so you'd always get c=b.
3) what's difference between $monitor and $display?
Answer:
$monitor: display every time one of it's parameters change.$display : display once every time they are executed.$strobe: display only at the end of the current simulation time
4) What's the different between casex, casez and case statements?
Answer:
casez treats all z as "Don't care".casex treat all z or x as "Don't care".case pass all z or x to the result.
Example:Driving 0Normal : Logic 0 on selCASEX : Logic 0 on selCASEZ : Logic 0 on sel
Driving 1Normal : Logic 1 on selCASEX : Logic 1 on selCASEZ : Logic 1 on sel
Driving xNormal : Logic x on selCASEX : Logic 0 on selCASEZ : Logic x on sel
Driving zNormal : Logic z on selCASEX : Logic 0 on selCASEZ : Logic 0 on sel
5) What's the differenece between wire and reg data type?
Answer:
Wire is a net data type, represents connections between hardware elements. It's default value is z.Reg is a register data type, which represent data storage elements. Registers retain value until
another value is placed onto them. It's default value is x.e reg.
6) What is defparam used for?
Answer:
Defparam is used to pass a new set of parameters during instantiation
For example:
1 module secret_number;2 parameter my_secret = 0;34 initial begin5 $display("My secret number is %d", my_secret);6 end7 8 endmodule910 module defparam_example();11 12 defparam U0.my_secret = 11;13 defparam U1.my_secret = 22;14 15 secret_number U0();16 secret_number U1();17 18 endmodule
Verilog Interview Question Part # 5
1) What is the difference between unary and logical operators?
Answer:Unary operators have only one operand, where as logical operators are of two operands.
2) What is the difference between transport delay and inertial delay?
Answer:
Transport delay is the delay caused by the wires connecting the gates. Wire do delay the signal they carry, this is due to the wire resistance, capacitance, and inductance. Simply transport delay is propagation delay on a wire. In verilog transport delay is modeled as follows:
a <= #10 b; Inertial delay is the time taken by a gate to change its output. It is the gate delay. In verilog inertial delay is modeled as follows: assign #10 a = b;
ASIC Logic Interview Questions Part # 1
1) Draw the gate level diagram of the NAMD and list the table with four different inputs [ 0, 1, z, x]?
Answer:
The inputs are only four different types [0, 1, z, x]. Assume inputs are A and B, C as output. The truth table are as following:
Input A Input B Output C Comments
0 0 1
0 1 1
1 0 1
1 1 0
0 Z 1The p-gate turn on with "0" input, the "z" input has no effect on n-gate.
Z 0 1The p-gate turn on with "0" input, the "z" input has no effect on n-gate.
1 Z X
The p-gate is off with "1" input, but the "z"
input has no effect on n-gate. The result is
unknown.
Z 1 X
The p-gate is off with "1" input, but the "z"
input has no effect on n-gate. The result is
unknown.
Z Z X
The "z" input has no effect on both p-gate
and n-gate. The result is unknown.
0 X X
The p-gate turn on with "0" input, the "X" input has unknown effect on
n-gate. The result is unknown.
X 0 X
The p-gate turn on with "0" input, the "X" input has unknown effect on
n-gate. The result is unknown.
Can we put Z on the output C?
Answer:
For this circuit, it's impossible. Both inputs A and B are tied with p-gate and n-gate. There's no way to put both "0" and "1" in the same input A or input B.
2) Write the verilog code to create the following patterns: 000->001->010->100->000->001....... Answer:
reg [0:2] result; reg [0:3] temp;
always@(posedge clk or reset)
begin if(!reset) begin temp= 4'b0001; result = 3'b000; end else begin result <= temp[2:0]; temp << 1; // shift 1 bit to the left temp[3] = temp[0]; // make the chain connected end end
3) Given the following FIFO and rules, how deep does the FIFO need to be to prevent underflowing or overflowing?
c
RULES: 1) frequency(clk_A) = frequency(clk_B) / 4 2) period(en_B) = period(clk_A) * 100 3) duty_cycle(en_B) = 25%
Answer:
Assume clk_B is 100Mhz ( 10ns )
From rule 1, clk_A = clk_B/4 = 25MHz ( 40ns )
From rule 2, period (en_B) = clk_A*100 = 40ns * 100 = 4000ns
From rule 3, duty_cycle(en_B) is 25%, so it's only 1000ns. 3000ns does not output anything.
Therefore, the FIFO size = 3000ns/40ns = 75 entries.
4) Draw a state diagram to detect the sequence "0110" ( the leading 0s cannot be used in more than one sequence).
Answer:
State machine
always (@posedge clk or reset_n)begin if(!reset_n) begin reset statement end else begin case(state) S0:
S1: default: endend
ASIC Logic Interview Questions Part # 2
1)
Draw the state diagram for a circuit that outputs a "1" if the aggregate serial binary input is divisible by 5. For instance, if the input stream is 1, 0, 1, we output a "1" (since 101 is 5). If we then get a "0", the aggregate total is 10, sowe output another "1" (and so on).
Answer: The number is divided by 5 , it doesn't matter if it's 25 or 0. We need to keep tracks of "0" to "4"
2) How to design a divided by 2 clock and divided by 3 clock with 50% duty cycles? Answer: The divided by 2 clock is as following:
The divided by 3 clock with 50% duty cycle is as following
ASIC Logic Interview Questions Part # 3
1) Create "AND" Gate using a 2:1 multiplexer. ( Create all other gates too)
Answer:
Z = XS + Y/S
If X=0, Y=1, Z = /S ( Inverter gate)
If X=1, Y=0, Z = XS ( AND gate )
With AND gate and inverter, it's a basic building gate NAND.
2) What is the minimum logic gates required to generate any boolean function?
Answer:
NAND and NOR are the universal gates. They can created any gates as following:
Use NAND to create an inverter
Use NAND to create a NOR gate
Use NAND to create a XOR gate
XNOR can be created with additional inverte
ASIC Logic Interview Questions Part #4
1) Design a Gray counter to count 6.
The reflected binary code, also known as Gray code after Frank Gray, is a binary numeral system where two successive values differ in only one bit.
Dec Gray Binary0 000 0001 001 0012 011 0103 010 0114 110 1005 111 1016 101 1107 100 111
module gray_counter (out , // counter outenable , // enable for counter
clk , // clockrst // active hight reset);
//------------Input Ports--------------input clk, rst, enable; //----------Output Ports----------------output [ 2:0] out;//------------Internal Variables--------wire [2:0] out;reg [2:0] count;//-------------Code Starts Here---------always @ (posedge clk) if (rst) count <= 0; else if (enable) begin if(count < 3'b101) count <= count + 1; elsecount <= 0;
endassign out = { count[2], (count[2] ^ count[1]),(count[1] ^ count[0]) };
endmodule
ASIC Gate Interview Questions Part #2
1) Deriving the vectors for the stuck at 0 and stuck at 1 faults.
A line l is stuck at a fixed logic value v (v {0,1}), denoted by l/v;
(we say also: a line has a fault stuck-at-1 (s-a-1) or stuck-at-0 (s-a-0);
examples:
a short between ground (s-a-0) or power (s-a-1) and a signal line; an open on a unidirectional signal line;
any internal fault in the component driving its output that it keeps a constant value;
The detectable error can be tested by applying different vectors to the circuit. The combination logic will pass the errors if there's any stack-at-1 or stack-at-0 errors.
Some errors could not be detectable because the error could not passed to the result logic. It need additional tests to catch this errors.
The testing based on stuck at fault model is aided by several things:1) A test developed for a single stuck at fault often finds a large number of other stuck at faults.2) A series of tests for stuck at faults will often, purely by serendipity, find a large number of other faults, like the stuck-open faults. This is sometimes called "windfall" fault coverage.3) Another type of testing called IDDQ testing measures the way the power supply current of a CMOS integrated circuit changes, when a small number of slowly changing test vectors are applied. Since CMOS draws a very low current when its inputs are static, any increase in that current indicates a potential problem.
2) minimize a boolean expression:
Use Karnaugh Maps to minimize the logic.
For example:
3) What's the latchup effect?
Latchup is a term used in the realm of integrated circuits (ICs) to describe a particular type of short circuit which can occur in an improperly designed circuit. More specifically it is the inadvertent creation of a low-impedance path between the power supply rails of a MOSFET circuit, triggering a parasitic structure which disrupts proper functioning of the part and possibly
even leading to its destruction due to overcurrent. A power cycle is required to correct this situation.
Preventing latchupFab/Design Approaches
1. Reduce the gain product b1 x b1o move n-well and n+ source/drain farther apart increases width of the base of Q2
and reduces gain beta2 > also reduces circuit density
o buried n+ layer in well reduces gain of Q1
2. Reduce the well and substrate resistances, producing lower voltage drops
o higher substrate doping level reduces Rsub
o reduce Rwell by making low resistance contact to GND
o guard rings around p- and/or n-well, with frequent contacts to the rings, reduces the parasitic resistances.
Systems Approaches1. Make sure power supplies are off before plugging a board. A "hot plug in" of an
unpowered circuit board or module may cause signal pins to see surge voltages greater than 0.7 V higher than Vdd, which rises more slowly to is peak value. When the chip comes up to full power, sections of it could be latched.
2. Carefully protect electrostatic protection devices associated with I/O pads with guard rings. Electrostatic discharge can trigger latchup. ESD enters the circuit through an I/O pad, where it is clamped to one of the rails by the ESD protection circuit. Devices in the protection circuit can inject minority carriers in the substrate or well, potentially triggering latchup.
3. Radiation, including x-rays, cosmic, or alpha rays, can generate electron-hole pairs as they penetrate the chip. These carriers can contribute to well or substrate currents.
4. Sudden transients on the power or ground bus, which may occur if large numbers of transistors switch simultaneously, can drive the circuit into latchup. Whether this is possible should be checked through simulation.
ASIC Timing Interview Questions
1)
The digital circuit is shown with logic delay (dly3) and two clock buffer delays (dly1, dly2).
How will you fix setup timing viloations occuring at pin B?
Answer:
Use the following formula:
Tc2q + Tdly3 <= Tsk + Tp - Tsu
Since Tp ( clock frequency is fixed 1/Tp = f ), Tc2q (clock to Q) and Tsu (setup time) are fixed, the setup timing violations are caused by Tdly3. In order to fix the setup violations, we can reduce Tdly3.
How will you fix the hold violations occuring at pin B?
Answer:
Use the following formula:
Tc2q + Tdly3 >= Tsk + ThdTc2q + Tdly3 - Tsk >= Thd
Since Tc2q (clock to Q) and Thd (hold time) are fixed, the hold time violations are caused by the Tdly3. We can increase the Tdly3. For example, add buffer to the path. We should not mess up with the clock skew. It would affect too many paths.
2) If there's a timing violation in the chip, how could you verify it as setup violation or hold time?
Answer: If the test engineer slow the clock speed, the chip passed the tested. It's a setup time problem. If the problem did not changes, it could be hold time issue.
Setup violations occurs when the data path is too slow compared to the clock speed. The designer can fix the setup violations by reducing the delay in the data path. Designer can also reduce the clock speed to fix the setup violation, but it is going to be a poor design technique.
Hold violations occurs when data is too fast when compared to the clock speed. If hold violations are not fixed before the chip is made, lot of problem occurs unlike setup violation where the clock speed can be reduced. To fix hold violations, designer can add more delay to the data path.
3) what's timing constraint?
Timing Constraints:
Timing constraints are how the designer tells the STA tool about the timing behavior of the ASIC. The three minimum constraints are defining the clock, input delay, and output delay. There are four types of timing paths are available. They are :
Input to Register (Sync),
Register to Register (Sync),
Register to Output (Sync) and
Input to Output(Async). Each path has a start and endpoint
When the clocks are defined, all Register to Register paths are assumed to be constrained in one clock cycle. A path originates from either an Input port or a Register clock pin, while an end point is either an Output port or a Register data pin. All start and end point must be timing constrained.
Systemverilog Interview Questions 3
1) What is the difference between mailbox and queue?
Answer:
A queue is a variable-size, ordered collection of homogeneous elements. A Queue is analogous to one dimensional unpacked array that grows and shrinks automatically. Queues can be used to model a last in, first out buffer or first in, first out buffer.
// Other data type as reference// int q[]; dynamic array// int q[5]; fixed array// int q[string]; associate array // include <// List#(integer) List1; //
int q[$] = { 2, 4, 8 };int p[$];int e, pos;e = q[0]; // read the first (leftmost) iteme = q[$]; // read the last (rightmost) itemq[0] = e; // write the first itemp = q; // read and write entire queue (copy)
A mailbox is a communication mechanism that allows messages to be exchanged between processes. Data can be sent to a mailbox by one process and retrieved by another.
2) What data structure you used to build scoreboard?
Answer:
In SV, we use mailbox to get data from different modules and compare the result.
class Scoreboard;
mailbox drvr2sb;mailbox rcvr2sb;
function new(mailbox drvr2sb,mailbox rcvr2sb); this.drvr2sb = drvr2sb; this.rcvr2sb = rcvr2sb;endfunction:new
task start(); packet pkt_rcv,pkt_exp; forever begin rcvr2sb.get(pkt_rcv); $display(" %0d : Scorebooard : Scoreboard received a packet from receiver ",$time); drvr2sb.get(pkt_exp); if(pkt_rcv.compare(pkt_exp)) $display(" %0d : Scoreboardd :Packet Matched ",$time); else $root.error++; endendtask : start
endclass
In VMM, we use channels to connect all the modules and compare the result.
class Scoreboard extends vmm_xactor;
Packet_channel drvr2sb_chan; Packet_channel rcvr2sb_chan;
function new(string inst = "class", int unsigned stream_id = -1, Packet_channel drvr2sb_chan = null, Packet_channel rcvr2sb_chan = null);
super.new("sb",inst,stream_id);
if(drvr2sb_chan == null) `vmm_fatal(this.log,"drvr2sb_channel is not constructed"); else this.drvr2sb_chan = drvr2sb_chan; if(rcvr2sb_chan == null) `vmm_fatal(this.log,"rcvr2sb_channel is not constructed"); else this.rcvr2sb_chan = rcvr2sb_chan; `vmm_note(log,"Scoreboard created ");
endfunction:new
task main(); Packet pkt_rcv,pkt_exp; string msg; super.main(); forever begin rcvr2sb_chan.get(pkt_rcv); $display(" %0d : Scoreboard : Scoreboard received a packet from receiver ",$time); drvr2sb_chan.get(pkt_exp); if(pkt_rcv.compare(pkt_exp,msg)) $display(" %0d : Scoreboard :Packet Matched ",$time); else `vmm_error(this.log,$psprintf(" Packet MissMatched \n %s ",msg)); endendtask : main
endclass
3) What are the advantages of linkedlist over the queue ? Answer:
Queue has a certain order. It's hard to insert the data within the queue. But Linkedlist can easily insert the data in any location.
4) What is the use of $cast?
Using Casting one can assign values to variables that might not ordinarily be valid because of differing data type. SystemVerilog adds 2 types of casting. Static casting and dynamic casting.
e.g. i = int '(10.0-0.1); // static cast convert real to integer
// Dynamic castingfunction int $cast( singular dest_var, singular source_exp );ortask $cast( singular dest_var, singular source_exp );
SystemVerilog interview Questions 4
1) How to call the task which is defined in parent object into derived class ?
Answer:The super keyword is used from within a derived class to refer to members of the parent class. It is necessary to use super to access members of a parent class when those members are overridden by the derived class.
EXAMPLE: class parent; task printf(); $display(" THIS IS PARENT CLASS "); endtask endclass class subclass extends parent; task printf(); super.printf(); endtask endclass program main; initial begin subclass s; s = new(); s.printf();
end endprogram
RESULT
THIS IS PARENT CLASS
2) What is the difference between rand and randc?
Answer:rand are standard random variables. When there are no other control on distrubution, these variables are uniformly distributed across valid values.
randc are random cyclic that randomly iterates over all the values in the range and no value is repeated with in an iteration until every possible value has been assigned. 3) What is solve...before constraint ?
Answer:constraint order { solve a before b ;}This guides the solver to give highest priority to a than b while picking the solution from solution space.
Answer: 4) What is the difference between fork/joins, fork/join_none fork/join_any ?
Fork Join None: The parent process continues to execute concurrently with all the processes spawned by the fork. The spawned processes do not start executing until the parent thread executes a blocking statement.
Fork Join Any: The parent process blocks until any one of the processes spawned by this fork completes.
For Join All: The parent process blocks until all the processes spawned by this fork complete.
SystemVerilog Interview Question 5
1) What is the use of modports ?
Answer:Modport restrict interface access within a module based on the direction declared. Directions of signals are specified as seen from the module.
e.g.interface intf (input clk);
logic read, enable, logic [7:0] addr,data; modport dut (input read,enable,addr,output data); modport tb (output read,enable,addr,input data); endinterface :intf
2) How parallel case and full cases problems are avoided in SV?
The full_case and parallel_case directives are dangerous because they tell the synthesis toolsomething different about the design than what is told to the simulator.
To the Verilog simulator, full_case and parallel_case are buried inside of Verilogcomments and are completely ignored. To the synthesis tool, full_case and parallel_caseare command-directives that instruct the synthesis tools to potentially take certain actions orperform certain optimizations that are unknown to the simulator.
A full case statement is a case statement in which all possible case-expression binary patternscan be matched to a case item or to a case default.
e.g. Full case, sel=2'b11 will be covered by default statement. The x-assignment will also be treated as a don'tcare for synthesis, which may allow the synthesis tool to further optimize the synthesized design. It's the potentially causing a mismatch to occur between simulation and synthesis. To insure that the pre-synthesis and post-synthesis simulations match, the case default could assign the y-output to either apredetermined constant value, or to one of the other multiplexer input values
module mux3c(output reg y,input [1:0] sel,input a, b, c);always @*case (sel)2'b00: y = a;2'b01: y = b;2'b10: y = c;default: y = 1'bx;endcaseendmodule
// Use synopsys full_case statement to create the full case , but it treated differently in simulation and synthesis.module mux3b (y, a, b, c, sel);(output reg y,
input [1:0] sel,input a, b, c);always @*case (sel) // synopsys full_case2'b00: y = a;2'b01: y = b;2'b10: y = c;endcaseendmodule
SystemVerilog use priority modified case statement to solve the full case problem. The biggest difference between a full_case directive and a priority modified case statementis that the priority keyword is part of the SystemVerilog syntax that will be interpreted thesame by simulators, synthesis tools and formal verification tools. In essence, the priority casestatement is a "safe" full_case case statement.
e.g.priority case (...)...endcase
A parallel case statement is a case statement in which it is only possible to match any caseexpression to one and only one case item.
e.g. A parallel case statement
module intctl1b(output reg int2, int1, int0,input [2:0] irq );always @* begin{int2, int1, int0} = 3'b0;casez (irq) // synopsys parallel_case3'b1??: int2 = 1'b1;3'b?1?: int1 = 1'b1;3'b??1: int0 = 1'b1;endcaseendendmodule
This is an example that demonstrates that adding the parallel_case directive makes the designsmaller and faster, but in the process it also adversely changes the functionality of the design.
SystemVerilog adds the new case statement modifier called "unique."The unique keyword shall cause the simulator to report a run-time error if a case expression isever found to match more than one of the case items. In essence, the uniquecase statement is a "safe" parallel_case case statement.
unique case (...)...default: ...endcase
Guideline: Code all intentional priority encoders using if-else-if statements. It is easier forthe typical design engineer to recognize a priority encoder when it is coded as an if-else-ifstatement.
SystemVerilog Interview Questions 6
1) What is the difference between $random and $urandom?
Answer:
The functionality of the seed arguments are different for $random and $urandom. The seed argument to $random is an inout. It updates its seed argument after each call to $random. This means the internal random number generator (RNG) state variable is a 32-bit number.
The seed argument to $urandom is an input. This seed is used to set the internal RNG to a value that is over 32-bits (typically 96-bits or greater).
In SystemVerilog, each thread has its own RNG, so only use the the seed argument on the first call to $urandom in each thread. There is also a way to set the seed without generated a random value by using the built-in process class and using the srandom() method.
class packet;rand bit [7:0] header;
function new(int seed);this.srandom(seed);endfunctionendclass
initial beginpacket p=new;p.new(33);end
2) How do we get seed or use single seed in the VMM ?
Method 1: Let it random by itself In VMM , VCS usually prints it to log file. Recently it added a system task to get the seed,
something like: $get_initial_random_seed() Use the following command to put seed back to get the same result "+nbt_random_seed=".
Method: Fix the seed. The better approach is to use srandom task/function to fix the seed. We can increase the seed by 1 or use other script to generate the seed. The start seed is only start the regression. It has enough randomize with the test environment. EXAMPLE:class Rand_seed; rand integer Var; function new (int seed); srandom(seed); $display(" SEED is initised to %0d ",seed); endfunction
function void post_randomize(); $display(": %0d :",Var); endfunctionendclass
program Rand_seed_p_80; Rand_seed rs; initial begin rs = new(20); repeat(5) void'(rs.randomize()); rs = new(1); repeat(5) void'(rs.randomize()); rs = new(20); repeat(5) void'(rs.randomize()); endendprogram
SystemVerilog Interview Question 9
1) How to kill a process in fork/join?
The kill() task terminates the given process and all its sub-processes, that is, processes spawned using fork statements by the process being killed. If the process to be terminated is not blocked
waiting on some other condition, such as an event, wait expression, or a delay then the process shall be terminated at some unspecified time in the current time step.
2) What is cross coverage ?
Cross allows keeping track of information which is received simultaneous on more than one cover point. Cross coverage is specified using the cross construct.
program main; bit [0:1] y; bit [0:1] y_values[$]= '{1,3}; bit [0:1] z; bit [0:1] z_values[$]= '{1,2}; covergroup cg; cover_point_y : coverpoint y ; cover_point_z : coverpoint z ; cross_yz : cross cover_point_y,cover_point_z ; endgroup cg cg_inst = new(); initial foreach(y_values[i]) begin y = y_values[i]; z = z_values[i]; cg_inst.sample(); end endprogram
3) Why always block is not allowed in program block?
The program block does not allow always block. Only initial and methods are allowed, which are more controllable.
4) What is final block ?
SystemVerilog final blocks execute in an arbitrary but deterministic sequential order. This is possible because final blocks are limited to the legal set of statements allowed for functions.
EXAMPLE : module fini; initial #100 $finish; final $display(" END OF SIMULATION at %d ",$time); endmodule
SystemVerilog Interview Questions 7
1) Difference between Associative array and Dynamic array ?
Answer:
Dynamic arrays are useful for dealing with contiguous collections of variables whose number changes dynamically. e.g. int array[]; When the size of the collection is unknown or the data space is sparse, an associative array is a better option. In associative array, it uses the transaction names as the keys in associative array. e.g. int array[string];
2) What are the advantages of SystemVerilog DPI?
SystemVerilog introduces a new foreign language interface called the Direct Programming Interface (DPI). The DPI provides a very simple, straightforward, and efficient way to connect SystemVerilog and foreign language code unlike PLI or VPI.
3) What is bin?
A coverage-point bin associates a name and a count with a set of values or a sequence of value transitions. If the bin designates a set of values, the count is incremented every time the coverage point matches one of the values in the set. If the bin designates a sequence of value transitions, the count is incremented every time the coverage point matches the entire sequence of value transitions.
e.g. program main; bit [0:2] y; bit [0:2] values[$]= '{3,5,6}; covergroup cg; cover_point_y : coverpoint y { option.auto_bin_max = 4 ; } endgroup cg cg_inst = new(); initial foreach(values[i]) begin y = values[i]; cg_inst.sample(); end endprogram
4) What are void functions ?
The function does not have return value
5) What is coverage driven verification?
Coverage Driven Verification is a result oriented approach to functional verification. The manager and verification terms define functional coverage points, and then work on the detail of process.
Used effectively coverage driven verification focuses the Verification team on measurable progress toward an agreed and comprehensive goal.
6) Explain about pass by ref and pass by value?Pass by value is the default method through which arguments are passed into functions and tasks. Each subroutine retains a local copy of the argument. If the arguments are changed within the subroutine declaration, the changes do not affect the caller.
In pass by reference functions and tasks directly access the specified variables passed as arguments.Its like passing pointer of the variable.
example:task pass(int i) // task pass(var int i) pass by reference {delay(10);i = 1;printf(" i is changed to %d at %d\n",i,get_time(LO) );delay(10);i = 2;printf(" i is changed to %d at %d\n",i,get_time(LO) );}
7) What is the difference between program block and module ?
The module is the basic building block in Verilog which works well for Design. However, for the testbench, a lot of effort is spent getting the environment properly initialized and synchronized, avoiding races between the design and the testbench, automating the generation of input stimuli, and reusing existing models and other infrastructure.
Systemverilog adds a new type of block called program block. Systemverilog adds a new type of block called program block. The program construct serves as a clear separator between design and testbench, and, more importantly, it specifies specialized execution semantics in the Reactive region for all elements declared within the program. Together with clocking blocks, the program construct provides for race-free interaction between the design and the testbench, and enables cycle and transaction level abstractions.
8) Describe the difference between Code Coverage and Functional Coverage Which is more important and Why we need them.
Code Coverage indicates the how much of RTL has been exercised. The Functional Coverage indicates which features or functions has been executed. Both of them are very important. With only Code Coverage, it may not present the real features coverage. On the other hand, the functional coverage may miss some unused RTL coverage.