Proceedings of the 2003 ASEE Gulf-Southwest Annual Conference

The University of Texas at Arlington Copyright © 2003, American Society of Engineering Education

Calculations of Lead Diffusion due to Threshold Voltage Shift in NMOS IGFETs

Harold Smith, undergraduate student

Southern University, College of Engineering, Baton Rouge, LA 70813

Madan Dubey, mentor Army Research Laboratory, Microelectronics Division, Adelphi, MY 20783

Pradeep Bhattacharya, Southern University Research Mentor

Southern University, College of Engineering, Baton Rouge, LA 70813

Abstract

PZT or Lead Zirconium Titanate sensor has a possibility of lead diffusion into the substrate where lead is injected onto a n-type metal-oxide semiconductor processed silicon wafer while annealing. This research shows effect of the diffusion process from start to finish and it contains photo images of the NMOS insulated gate field effect transistor changes through each phase. The IGFET was first covered with silicon dioxide or an insulating oxide layer and then annealed in air for 30 seconds. The metals, titanium and silicon, were added to the NMOS IGFET as barrier layers in the bottom of PZT sensors. PZT material was deposited onto the IGFET through four sol-gel spins each with a different color change. The lead diffusion process ended with a photo-resist mask used to pattern the sensor and anneal it. Measurements were taken on a 4145B semiconductor parameter analyzer and a 3-point probe station. These I-V curve measurements began to show p-type properties of the NMOS IGFET. This change in data measurements can be observed, from a viewer’s point of view that the lead has diffused to a different area on the NMOS IGFET, therefore, causing the p-type characteristics. The amount of lead that was diffused into the IGFET can be determined from the threshold voltage shift (∆VT) between the n-type and p-type curves. The relationships for the shift ∆VT = (qφImplant)/εox/tox

where, q is electronic charge, φImplant is the number density of the impurity and εox is the electrical permittivity of the oxide. These threshold voltage shifts give the concentration of diffused lead into the Si/SiO2 interface of the NMOS IGFETs studied.

Introduction NMOS IGFETs are defined as n-channel metal oxide semiconductor insulated gate field effect transistors. This research deals with the study of PZT sensor material deposited on a NMOS processed wafer. The sample contained two metals, Platinum and Titanium, which served as barrier and contact layers for the PZT sensors. Lead Zirconate Titanate or PZT was patterned

Proceedings of the 2003 ASEE Gulf-Southwest Annual Conference

The University of Texas at Arlington Copyright © 2003, American Society of Engineering Education

with a photo-resist mask and annealed. Studies were made to describe the patterning and the diffused lead. The sample consisted of a 0.1Ω-cm silicon wafer processed by a NMOS process.

The lowest layer is a gate oxide of 225Å covered with a poly-silicon (poly-Si) gate electrode of 3500Å and a capping layer of Low Temperature CVD Oxide (LTO) of ~3500Å. A Titanium contact is given to the gate, source and drain over which the contact metal Aluminum – Silicon-Copper is laid. If one looks at the structure using digital imaging methods and profilometry by a KLA-Tencor P15 instrument, the average mesa-height of the metal contact on the wafer surrounding the chips is approximately 1.4µm. As the top contact metal used was different, a sol-gel PZT (Lead-Zirconate-Titanate) MEMS process was combined with the NMOS process. It has a limitation that the maximum temperature to which these MOS structures can be annealed will be 500°C. The following is the process flow for a generic low-temperature (pyraclore phase) PZT device to be incorporated with the existing NMOS process:

1. SiO2 Deposition (1µm) 2. RTA 500°C, 60 seconds N2 3. LAM oxide RIE etch – SF6 plasma 300W(2000 Å) 4. PECVD SiO2 Deposition (0.2µm) 5. RTA 500°C, 60 seconds N2 6. Ti (200-400 Å)/Pt (1200-1400 Å) Deposition (~300°C) (~1600 Å) 7. RTA 500°C, 60 seconds, compressed dry air 8. PZT (~0.25µm) pyrolized 350°C, 2 minutes after each deposition, total of 4 9. RTA 500°C, 30 seconds, compressed dry air 10. Photolithography for ion-mill 11. Ion-mill (PZT/Ti/Pt-oxide) - give access to Al contacts

• The Fig.1 shows the digital image of the chips after 1µm PECVD and 500 °C anneal –

before the oxide etch. This process was a test experiment to see if the chip would survive 500°C annealing with 1µm. There was a blistering effect that symbolized how the sample’s chips were burning out. The 1µm SiO2 deposition was not a good adhesion of the oxide over layer.

Fig. 1 After 1um of PECVD Oxide and 500° C Anneal – Prior to Lam Oxide Etch

Proceedings of the 2003 ASEE Gulf-Southwest Annual Conference

The University of Texas at Arlington Copyright © 2003, American Society of Engineering Education

• The Fig.2 describes the LAM oxide RIE etch completed in 3 minutes and 37 seconds using a 2-step oxide program. The oxide was completely removed – as established via (VASE) Ellipsometer comparison with standard. This etch was completed with an annealing process in ultra pure dry nitrogen.

Fig.2 Post 3:37 (2-Step Oxide Etch Program) oxide etch in LAM. Oxide was completely

removed – established via Ellispsometer comparison with standard.

• Fig.3 depicts surface morphology after a post 2000 Å PECVD oxide deposition.

Fig. 3 Post 2000A PECVD Oxide Deposition.

• The Fig.4. shows a post oxide anneal at 500°C, 60 sec by rapid thermal annealing in N2. No blisters of any sorts were seen due to good adhesion of the oxide over layer.

Fig. 4 Post Oxide Anneal at 500°C, 60sec.s, N2. Note the absence of “Blister” defects.

• The Fig.5 shows the surface topography of the structures after a Ti/Pt (1600 Å) standard

deposition. The annealing process in ultra pure dry nitrogen completed the deposition of the metals Ti/Pt.

Proceedings of the 2003 ASEE Gulf-Southwest Annual Conference

The University of Texas at Arlington Copyright © 2003, American Society of Engineering Education

Fig. 5 TiPt 1600A deposition – Standard process

• The Fig. 6 shows the surface structure of Ti/Pt anneal at 500°C, 60 sec. in N2. (RTA) process had shown no blisters.

Fig.6 TiPt Anneal at 500°C, 60sec, N2. Note the absence of “Blister” defects.

• The Fig.7 shows deposition of 0.25 µm standard PZT deposition processes with a post

anneal at 500°C, 30 sec. in Air (RTA). During the PZT process four spins were observed through a color change. The deposition process was completed with annealing compressed dry air onto the sample.

Fig. 7 0.25µm PZT – post Anneal at 500°C, 30sec., Air

• The Fig. 8 shows a standard PZT device mask patterned for ion mill, the photo resist used was AZ 5214 and the Developer was AZ312. (1:1 with DI water).

Proceedings of the 2003 ASEE Gulf-Southwest Annual Conference

The University of Texas at Arlington Copyright © 2003, American Society of Engineering Education

Fig. 8 Photo Mask for Ion Mill – 5214E

• The Fig.9 shows the Post ion-mill structural topography of the surface where it took 24

minutes to remove (0.25 µm PZT/1600Å TiPt/2000Å-PECVD Oxide), everywhere except the top of the dots. The metal contacts were conductive as found by DVM and a probe station study. This ion-milling process ended with annealing of compressed dry air.

Fig.9 Post Ion Mill – 24min. – (.25µm PZT/1600A TiPt/2000A PECVD Oxide) Al contacts conductive – (Voltmeter/Probe Station).

• The Fig.10 shows the surface after resist removal from the carrier wafer and the top of the dots.

Fig.10 Resist Removal – Acetone/IP

The conclusion of the process shows that the final metal level can be deposited using TiPt metal over the CMOS and the PZT devices together or else, one can make separate mask for the metal deposit and rework on the present wafer. The best solution for integration of these processes is to deposit the metal at the end.

Proceedings of the 2003 ASEE Gulf-Southwest Annual Conference

The University of Texas at Arlington Copyright © 2003, American Society of Engineering Education

It was observed that the devices changed at 650°C during the RTA annealing process. One small sample was completely destroyed at this temperature, but only served as an experimental piece to test the maximum temperature that could be used during the annealing process with the CMOS devices and the PZT process. During the PZT process, lead was diffused through the capping oxide (cracks) onto the devices causing impurities to descend to the oxide level. The PZT material could not go through the devices, but lead was able to migrate into the devices. This observation that lead (Pb) migrated into the devices lead to the electrical study of the NMOS sample with the PZT process. I-V curve measurements were taken to observe what the lead migration had done on the NMOS sample. One phenomenon that was observed from an I-V measurement was that the affected devices were showing p-type characteristics. Fig. 11 and 12 show the measurements taken from the Semiconductor Parameter Analyzer using the probe station. The data was taken from the lower bottom-left chips of the NMOS sample wafer. These I-V curves were compared to an n-type I-V curve shown in Fig. 13 taken also to show the difference between the n-type and p-type I-V curve. Fig. 11 – p-type curve Fig. 12 – p-type curve

Fig. 13 – n-type curve

Results & Conclusion

Through previous studies that show lead diffusing through the capping oxide material of a CMOS wafer, this research was successfully completed. It was observed that the NMOS sample

Proceedings of the 2003 ASEE Gulf-Southwest Annual Conference

The University of Texas at Arlington Copyright © 2003, American Society of Engineering Education

could be annealed at a temperature of 650°C or less, so the sample was annealed at 500°C to be safe and to avoid any small damage that was observed at 600°C may present to the sample. I-V characteristic curves show the n-type with a positive gradient value and the p-type with a negative gradient value. The p-type transfer characteristic of the I-V curve proves to show where the lead had migrated the most on the NMOS sample. The lead was observed to have migrated to the bottom of the gate oxide. The lead deposited was obtained from the threshold voltage shift in the n-type and p-type curves. Using the threshold voltage equation:

∆VT = (qφImplant)/Cox q = electron charge in coulombs φImplant = ion dosage in Ω-cm Cox = εox/t ox; εox = permittivity of insulated oxide in cm; t ox = gate oxide thickness in cm Device #50, LD – 2: ∆VT = (qφImplant)/Cox = (9.23E00*3.4515E-11)/(1.6E-19*225E-10) = 8.85E16 Device #50, LD – 3: ∆VT = (qφImplant)/Cox = (12.9E00*3.4515E-11)/(1.6E-19*225E-10) = 1.237E17 Device #14, LD – 24: ∆VT = (qφImplant)/Cox = (-16E-3*3.4515E-11)/(1.6E-19*225E-10) = -1.534E14

Acknowledgements

I would like to thank the Army Research Laboratory in Adelphi, MY, and Mr. Ron Polcawich and Mr. Jeff Pulskamp as my team that I was assigned to work with there for completing my research.

References

1. Jaeger, Richard C., Introduction to microelectronic fabrication, Vol. 5, Modular Series on Solid State Devices, 2nd Ed. Prentice Hall, 2002.

2. Muller, R.S., Howe, R.T., Senturia, S.D., Smith, R.L., and White, R.M., [Eds.] Micro-sensors, Latest Ed. IEEE Press, New York, NY, 1999.

3. Plummer, James D., Deal, Michael D., and Griffin, Peter B. Silicon VLSI Technology 1st Ed. Prentice Hall, Upper Saddle River, NJ, 2000.

HAROLD SMITH Harold Smith is an undergraduate currently attending Southern University and majoring in Electrical Engineering. His research interests are in the microelectronics and signal processing area, including NMOS and CMOS technology. PRADEEP BHATTACHARYA Bio on other papers