P a g e | 1

EE 211 Electronics Devices Lab

NAME- Adit Bhardwaj

ROLL NO. 10002004 GROUP MEMBER- Arun kumar singh(10002034)

GROUP NO. - 23

Course instructor– Prof. Arup lal

EXPERIMENT NO.8

I-V CHARACTERSTICS OF JFET

DATE - 27/10/2011

P a g e | 2

OBJECTIVE: To observe the Drain Characteristics and Transconductance Characteristics of JFET.

EQUIPMENTS: JFET, Two variable D.C. voltage sources, 2 multi meters, two 100Ω resistors, breadboard.

PRINCIPLE: JFET: A field effect transistor (FET) is a unipolar device, conducting a current using only one kind of charge carrier. The junction field-effect transistor is the simplest type of field-effect transistor. In a JFET the voltage –variable depletion region width of a junction is used to control the effective cross-sectional area of a conducting channel.

n-Channel JFET p-Channel JFET

PROCEDURE PART1 1.Circuit components were arranged on the bread board according to the following circuit diagram.

CIRCUIT DIAGRAM: COMMON SOURCE CONFIGURATION OF JFET

P a g e | 3

2. ID is observed for different values of VDS and VGS is kept constant. VDD

is also kept below of 10V.

TABLE: Drain current (ID) versus the Drain-Source voltage (VDS) for a common Source configuration and VGS constant.

Table-1 VGS= -0.03V

S.no VDS (V) ID (mA)1. 0.001 0.004

2. 0.052 0.228

3. 0.107 0.447

4. 0.148 0.619

5. 0.177 0.735

6. 0.206 0.831

7. 0.224 0.903

8. 0.250 1.009

9. 0.314 1.258

10. 0.373 1.466

11. 0.439 1.655

12. 0.478 1.798

13. 0.557 2.000

14. 0.630 2.190

15. 0.695 2.438

16. 0.954 3.008

17. 1.265 3.500

18. 1.765 4.000

19. 2.889 4.500

Table-2 VGS=-.3V

S.no VDS (V) ID (mA)1. 0.003 0.015

2. 0.081 0.309

3. 0.192 0.696

4. 0.316 1.082

5. 0.45 1.455

P a g e | 4

6. 0.578 1.762

7. 0.751 2.098

8. 0.958 2.4

9. 1.219 2.652

10. 1.493 2.82

11. 1.867 2.951

12. 2.297 3

13. 2.757 3.014

14. 3.21 3.037

15. 3.69 3.05

16. 4.12 3.062

17. 4.61 3.1

18. 5.07 3.1

19. 5.62 3.1

20 6.04 3.1

Table-4 VGS= -0.5V

S.no VDS (V) ID (mA)1. 0.007 0.028

2. 0.039 0.139

3. 0.112 0.38

4. 0.166 0.549

5. 0.235 0.75

6. 0.353 1.068

7. 0.46 1.312

8. 0.554 1.508

9. 0.751 1.831

10. 1.014 2.114

11. 1.174 2.225

12. 1.511 2.366

13. 1.911 2.453

14. 2.429 2.515

15. 2.94 2.551

16. 3.38 2.574

17. 4.52 2.61

18. 5.32 2.626

19. 6.33 2.636

20. 7 2.647

P a g e | 5

Table-3 VGS= -1.5V

S.no VDS (V) ID (mA)1. 0.052 0.01

2. 0.216 0.024

3. 0.471 0.031

4. 1.011 0.039

5. 1.95 0.047

6. 2.89 0.051

7. 3.94 0.055

8. 4.97 0.059

9. 5.97 0.062

10. 6.9 0.064

11. 7.91 0.065

12. 9.96 0.066

Plot:

0 1 2 3 4 5 6 70

0.5

1

1.5

2

2.5

3

3.5

ID V/s VDS

VDS(V)

ID(m

A)

VGS= -0.03V

VGS= -0.3V

VGS= -0.5V

VGS= -1.5V

P a g e | 6

PART2 1. Circuit components are arranged on the bread board according to the following circuit diagram.

2. ID is observed for different values of VGS and VDS is kept constant. VDD is also kept below of 10V.

TABLE: Drain current (ID) versus the Gate-Source voltage (VGS) for a common Source configuration and VDS constant.

Table-1 VDS= 3V

S.no VGS (V) ID (mA)1. -2.26 0.001

2. -1.67 0.008

3. -1.5 0.072

4. -1.41 0.155

5. -1.3 0.296

6. -1.21 0.45

7. -1.1 0.67

8. -1 0.982

9. -0.8 1.532

10. -0.6 2.254

11. -0.41 2.8

12. -0.3 3.2

13. -0.2 3.7

CIRCUIT DIAGRAM: COMMON SOURCE CONFIGURATION OF JFET

P a g e | 7

14. -0.11 4.1

15. -0.02 4.5

Table-2 VDS= 5V

S.no VGS (V) ID (mA)1. -2.48 0

2. -3.23 0.001

3. -2.98 0.001

4. -2.74 0.002

5. -2.47 0.003

6. -2.23 0.004

7. -1.98 0.007

8. -1.73 0.023

9. -1.5 0.092

10. -1.22 0.51

11. -1 0.971

12. -0.78 1.61

13. -0.64 2.31

14. -0.52 2.55

15. -0.42 2.9

16. -0.39 3.1

17. -0.31 3.4

18. -0.19 3.8

19 -0.1 4.2

20 -0.03 4.5

Table-3 VDS=

S.no VGS (V) ID (mA)1. -0.02 4.6

2. -0.12 4.1

3. -0.25 3.6

4. -0.51 2.5

5. -0.39 3

6. -0.6 2.26

7. -0.74 1.772

8. -0.91 1.284

9. -1.1 0.748

10. -1.3 0.341

P a g e | 8

11. -1.51 0.064

12. -1.69 0.007

13. -2 0.002

14 -2.5 0.001

15 -3.5 0

-4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 00

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Series2Series4Series6

RESULTS: