art film - l1 top - analog devices
TRANSCRIPT
ART FILM - ASSY_PRIM
ART FILM - ASSY_PRIM
1
TP7
P2
1P1
TP17
TP4
1
EXT01
RT1
RT2
TP11
J4
MATE ENTRY
1
LK1
LK2
C4
C5
JMP2-1JMP2-2
E1E2
C1
USB
P9
R5
R4
U4
C11TP13
U1
J1
J3
C7
TP18
TP15TP16
TP1
C9
TP5
C8
TP8C10TP14
TP9U2
J6
TP10
J5
1J7
U3
D1
TP6
TP12
R1
TP2TP3
1P4
1P3
ASSEMBLY
ART FILM - SKT
ART FILM - SKT
EXT01
GND2
TP7
6P2
1P1
LTC2862A + ADuM6421A
8
A
TP17
GND
TP4
Fault Protected RS-485Arduino Shield Board
EXTERNAL 5V VIN
1
P9
LK1
RT1
RT2
E2TP11
6J4
GND ARD_DE TXDEN
5
1
LK2
C5 JMP2-1JMP2-2
E1
C4
DE
C2
C1
2
5V
6
5
J3
ARD5V EXT_VIN USB
USB
R5
TP18
R4
3.3V5V C11
C3
VDD1 SRC+3.3V_ARD
2
5V SRC
C7
E3
B
C10
U4
DI_ISO
TP13
TP16
U1
J6
VDD1
TP1
DE ARD_RE VDD1 GND
2J1
C9
TP5
3
4
DS1
DS2
C8
R2
R3
TP8
VDD2
TP14
RO_ISO
DE_ISO
TP15
TX
INPUT_SEL
TP9
VDD1 GND SEL_MODE
RE_N TP10
3.3V 5V
J5
J7
U3
TP6
GND2
RE_N_ISO
D1
RX
TP12DE
REC6
2U2
P4
R1
P3
GND1
2TP3
TP2
18
110
ART FILM - SKB
ART FILM - SKB
61
P1
TP7
P2
18
TP17
TP4
1EXT01
6 J4
TP11
5
1
LK2
LK1
2
6
5
P9
TP13
2J3
J1
TP18
TP16
TP1
2
TP5
3
4
TP8
TP14
TP15
6 J6 TP95
TP10
J7
J5
D1TP6
TP12
P4
2
P32
TP3
TP2
18
110
ART FILM - FAB
ART FILM - FAB
A
B
C
D
TEST REQUIREMENTS;
INTENTIONAL SHORTS;
SURFACE FINISH;
SILK SCREEN;
SOLDER MASK;
CLADDING;
MATERIAL FAMILY;
MATERIALS;
SPECIFICATIONS:
8
8
70.4
0.0762um - 0.127um (3-5 MICRO INCHES) GOLD 2.54um (100 MICRO INCHES) NICKEL/
"GERBER DATA" IS PROVIDED. THIS VERIFICATION ALSO
REQUIRED FOR "ODB++" DATA PER EMBEDDED NETLIST.
SUPPLIED IPC-D-356 NETLIST FOR OPENS AND SHORTS WHEN
100% NETLIST ELECTRICAL VERIFICATION USING CUSTOMER
DOES NOT MATCH "READ_ME.2" FILE PROVIDED.IS REQUIRED IF SUPPLIED DATA REPORTS ANY CONDITION THATINTENTIONAL NET SHORTS EXIST. CUSTOMER REVIEW AND APPROVALIF SUPPLIED DATA INCLUDES A FILE "READ_ME.2", THEN
ENIG (Electroless Nickel/Immersion Gold)
COLOR: WHITESYNTHETIC INKJET PRINTING ALLOWED FOR DENSE BOARDS,SHALL BE PERMANENT NON-CONDUCTIVE EPOXY INK, COLOR: WHITE
(LATEST REV.) CLASS 3. COLOR GREEN.OVER BARE COPPER OR GOLD AND SHALL MEET IPC-SM-840SHALL BE LIQUID PHOTOIMAGEABLE (LPI) APPLIED ON BOTH SIDES
TAKE PRECEDENCE.
NOTE: IF THE LAYER STACKUP CONFLICTS WITH THE ABOVECLADDING SPECIFICATIONS THEN THE LAYER STACKUP SHALL
INTERNAL PLANE LAYERS 1 OZ. COPPER.INTERNAL SIGNAL LAYERS .5 OZ. COPPER.EXTERNAL LAYERS .5 OZ. COPPER, OVERPLATE TO 1.5 OZ.
ISOLA 370HR OR EQUIVALENT
U.L. RATING OF 94 V-0IPC-4101 OR IPC-4103, MINIMUM Tg>130degC, Td>300degC,ALL LAMINATES AND BONDING MATERIALS SHOULD BE SELECTED FROM
52.9
7
7
8
DESIGN CROSS SECTION CHART___________________________TOTAL THICKNESS 1.595 MM
1-2
L2 BOTTOM CONDUCTOR - 0.0525 MM
* SURFACE - 0 MM
* DIELECTRIC - 1.49 MM
* SURFACE - 0 MM L1 TOP CONDUCTOR - 0.0525 MM
6
6
15. THRU VIAS FILLED WITH NON-CONDUCTIVE EPOXY AND PLATED OVER. COPLANAR ON BOTH SIDES WITHIN .001 INCH PRIOR TO FINAL PLATING.
14. REPAIRS PER IPC-7711/21 (LATEST REV.) ARE ALLOWED.
C. LOT NUMBER B. DATE CODE (STAMP). E. SUCCESSFUL ELECTRICAL TEST. A. U.L. CODE-FLAMMABILITY RATING D. MFGR LOGO
UNLESS OTHERWISE INDICATED;
13. MFGR. TO LEGIBLY ETCH OR STAMP/SCREEN WITH PERMANENT NON-CONDUCTIVE INK ON SECONDARY SIDE IN A CLEAR AREA
MASK OR INTERNAL COPPER PLANES.
ALL OTHER FEATURES TO BE 5.08MM (0.200 INCH) MINIMUM. B. THERE SHALL BE NO THIEVING IN ANY AREAS FREE OF SOLDER
A. THIEVING TO CARD EDGE, FIDUCIALS, NON-PLATED THROUGH HOLES,
THE CUSTOMER: AREAS ON THIS DESIGN ONLY AFTER REVIEW AND APPROVAL FROM12. THIEVING MAY BE ADDED TO COMPENSATE FOR LOW COPPER DENSITY
INTERSECTION ONLY AND ELECTRICAL INTEGRITY MUST BE MAINTAINED.) TEAR DROP PADS TO MAINTAIN ANNULAR RING. (AT PAD TO TRACE ANNULAR RING REQUIREMENT, MFGR. MAY REQUEST APPROVAL TO11. IF PAD SIZES PROVIDED ARE NOT LARGE ENOUGH TO MAINTAIN
PERFORMED AFTER CUSTOMER APPROVAL.10. NON-FUNCTIONAL PAD REMOVAL FROM INNER SIGNAL LAYERS MAY BE
9. MINIMUM DESIGN SPACING IS 0.2mm.
8. MINIMUM DESIGN LINE WIDTH IS 0.15mm.
CONDUCTOR THICKNESS.
7. FINISHED CONDUCTOR WIDTHS SHALL NOT BE REDUCED FROM THE NOMINAL INDICATED ON THE MASTER PATTERN, BY MORE THAN THE
6. HOLE DIAMETERS APPLY AFTER PLATING.
CROSS SECTION. MINIMUM AVERAGE, WITH NO READING LESS THAN 20um (.0008) BY 5. PLATED HOLE WALL THICKNESS SHALL NOT BE LESS THAN 25um (0.001 INCH)
A DIAMETER OF 0.127mm (0.005 INCHES) FROM THEIR TRUE POSITION. 4. HOLE PATTERN TOLERANCES FOR UNDIMENSIONED HOLES SHALL BE
WRITTEN AUTHORIZATION. 3. MODIFICATIONS TO THE ARTWORK ARE NOT ALLOWED WITHOUT
(LATEST REVISION.) 2. ACCEPTABILITY PER ANALOG DEVICES, INC. SPECIFICATION TST00115,
FABRICATION UNLESS OTHERWISE SPECIFIED. 1. REFER TO IPC-6010 SERIES (LATEST REV.), CLASS 2 FOR
REQUIREMENTS:
5
5
PRIMARY SIDE
FIGUREALL UNITS ARE IN MILLIMETERSDRILL CHART: TOP to BOTTOM
FINISHED_SIZE
NON PLATED: +/- .001
0.10160.1524
PLATED: +/- .003UNLESS SPECIFIED
4
1.0161.1431.271.397
HOLE TOLERANCE
4
PLATEDPLATEDPLATEDPLATEDPLATEDPLATEDPLATED
3
230
QTY
3
4
186962
2
2
.XX +-0.25
.XXX +-0.127
DECIMALS
DIMENSIONS ARE IN MMUNLESS OTHERWISE SPECIFIED
+- 1/32
FRACTIONS
TOLERANCES
+/- 2
ANGLES
A
REV
PADDY DUIGNAN
ASSEMBLY
25/02/19
INITIAL RELEASE
DESCRIPTION
A2
SDP-K1 TEST BOARD
REVISION
1/1
1
01-056538-01
1
ANALOG DEVICES INTERNATIONAL
ERDC Building
Raheen Business Park
Raheen, LIMERICK, IRELAND
DATE
1
APPROVED
1
A
A
B
C
D