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Arslan Azhar – CEO William Jones - COO

Ryan Winslow Alan Ford

Alonzo Browne Christopher Moreno

Matt Giordano Stephen Zelvis Andrew Taylor

Dan Colanduno

Overview DCTQ Controller Summary

DCTQ Process

Stage 1. Dualram & Multiplier [8x8]

Stage 2. Adder [12] & DCTreg

Stage 3. ROMC

Stage 4. ROMQ

Stage 5. Multiplier [11x8] & Adder [14] & Multiplier [12x8]

Conclusion (Initial and Final Images)

DCTQ Controller Summary The DCTQ controller outputs addresses to different

parts of the DCTQ and maintains the overall clock (clk) and read negative/write positive (rnw)

44 Total pipeline stages in the DCTQ run by the controller

Latency = 45 clock cycles (64 clk cycles per block once pipeline is full)

DCTQ Controller Summary (Continued) DCTQ Controller Pin Diagram

DCTQ Controller Summary (Continued) DCTQ Controller Input & Output Tables

Input Size (bits) Function

Reset_n 1 Reset DCTQ process

Start 1 Start DCTQ process

Hold 1 ‘Pause’ DCTQ process

clk 1 Master clock

Output Size (bits) Function

Ready 1 Checks if DCTQ is ready to begin

Rnw 1 Read negative / write positive

Encnt2 1 Enable address

Dctq_valid 1 Checks validity

Cnt1_reg[5:0] 6 [2:0] Address to Dualram & [5:3] address to romc

Cnt2_reg[2:0] 3 Address to DCTreg

Cnt3_reg[2:0] 3 Address to romc

Cnt4_reg[5:0] 6 Address to romq

Addr[5:0] 6 6 bit address to dctq block

DCTQ Process (Stage 1) Stage 1. Dualram & Multiplier [8x8]

Dualram

Image information is read in from computer file

Stored to the dualram (1 ram at a time)

DCT coefficients found

Image data/DCTQ computations output from Dualram

Multiplier [8 bits x 8 bits]

Image data from Dualram multiplied by the C matrix

Results from the 8 multiplications is output

DCTQ Process (Stage 1 continued) Stage 1. Dualram & Multiplier [8x8]

Pin diagram


Dualram Input & Output Tables


clk 1 Main clock, used to read input

pci_clk 1 Data is written at posedge of pci_clk

di[63:0] 64 Input image coefficients

din_valid 1 Validates of input image coefficients

be[7:0] 8 Bit enable

wa[2:0] 3 Used to write a pixel block

rnw 1 Read negative / write positive

ra[2:0] 3 Read address to process DCTQ input


do[63:0] 64 Column-wise output data to be read


Multiplier [8 bits x 8 bits] Input & Output Tables Input Size (bits) Function

Do[63:0] 64 Image data

C[63:0] 64 DCT matrix (‘C matrix’)

Clk 1 Clock


Result1 16 Result 1st C row * 1st image data column

Result2 16 Result 2nd C row * 2nd image data column

Result3 16 Result 3rd C row * 3rd image data column

Result4 16 Result 4th C row * 4th image data column





DCTQ Process (Stage 2) Stage 2. Adder [12 bits] & DCTreg

Adder [12 bits]

Adds the 8 results from the 8 x 8 multiplier

DCTreg

Register stores the additions from the adder for 8 clock cycles (partial products of C*image data)

DCTQ Process (Stage 2 continued) Stage 2. Adder [12 bits] & DCTreg

Pin Diagram


Adder [12 bits] Input & Output Tables


Result1[11:0] 16 Input 1 to be added.








Clk 1 Clock


SUM[14:0] 15 (12 bits) The sum of input N0 through N7


DCTreg Input & Output Tables


Sum1 12 Output (sum) from the 12 bit adder

Cnt2_reg[2:0] 3 Address selecting which register to use

Encnt2 1 Address enable

clk 1 clock


qr0 11 1st row of partial products of CX

qr1 11 2nd row of partial products of CX

qr2 11 3rd row of partial products of CX

qr3 11 4th row of partial products of CX





DCTQ Process (Stage 3) Stage 3. ROMC

Dual Input & Dual Output

Dual address inputs for fetching from 2 places at once

Dual data output allows for C and CT to be read out of the ROM at the same time (C and CT doubled for more accuracy)

DCTQ requires C and CT at the same time

DCTQ Process (Stage 3 continued) Stage 3. ROMC

Pin Diagram

DCTQ Process (Stage 3 continued) Stage 3. ROMC

ROMC Input & Output Tables


Cnt1_reg[5:3] 3 Input address from dctq controller


clk 1 clock


D1[63:0] 64 2 x C (cosine terms)

D2[63:0] 64 2 x CT (transpose cosine terms)

DCTQ Process (Stage 4) Stage 4. ROMQ

Single input & single output

ROMQ stores inverse quantization values

Output from ROMQ used to divide DCT coefficients

DCTQ Process (Stage 4 continued) Stage 4. ROMQ

Pin Diagram

DCTQ Process (Stage 4 continued) Stage 4. ROMQ

ROMQ Input & Output Tables



clk 1 clock


qout[7:0] 8 Inverse quantization values

DCTQ Process (Stage 5) Stage 5. Multiplier [11x8] & Adder [14] & Multiplier [12x8]

DCTQ Process (Stage 5 continued) Stage 5. Multiplier [11x8] & Adder [14] & Multiplier [12x8]

Multiplier [11 bits x 8 bits]

Multiplies the outputs from the DCTreg with CT

Adder [14 bits]

Sums outputs from the 11 x 8 Multiplier

Multiplier [12 bits x 8 bits] (‘divider’)

Multiplies the sum from the adder by the inverse quantization values

Outputs the final dctq


Multiplier [11 bits x 8 bits] Input & Output Tables


qr0 – qr7 11 Rows of partial products of CX

CT 8 Row from CT matrix

Clk 1 Clock


Res1 – res8 19 Results from partial CX * CT row multiplication


Adder [14 bits] Input & Output Tables


res1 – res8 14 Results from partial CX * CT row multiplication

Clk 1 Clock


Dct[13:0] 14 Sum of inputs res1-res8


Multiplier [12 bits x 8 bits] Input & Output Tables


Dct[11:0] 12 Sum of res1-res8 from 14 bit adder

qout 8 Inverse quantization values

Clk 1 Clock


Dctq[8:0] 9 Final output

Conclusion Original Image

Conclusion Final Image (after DCTQ)

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