arm soc exploration
TRANSCRIPT
ARM SoC exploration
Using gem5 for application specific
system-on-chip architecture exploration
Alexandre Romaña & Abhilash Nair
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How we do architecture exploration
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Simulation -architectural change
-IP enhancement -re-partitioning
-algorithmic enhancement
The Case for gem5
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Cycle accurate
Fast
• Late
• Expensive
• Slow
• Complex
Emulation
Architecture exploration for TCI6636K2H SoC for Small Cells (High End)
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Tera
Net
Multicore Navigator
Security AccelerationPac
Packet AccelerationPac
+ * - <<
C66x DSP
+ * - <<
C66x DSP
System Services
Power Manager
Debug
System Monitor
EDMA
Multicore Shared Memory Controller
011100
100010
001111
DDR3/3L 64/72b
DDR3/3L 64/72b
4MB ARM Shared Memory
1MB L2 Per C66x Core
Ethernet Switch
+ * - <<
C66x DSP
+ * - <<
C66x DSP
+ * - <<
C66x DSP
+ * - <<
C66x DSP
+ * - <<
C66x DSP
+ * - <<
C66x DSP
6MB
PCIE I2C USB 3 SRIO Ethernet EMIF 16 UART SPI Hyperlink
Radio AccelerationPac
FFTC TCP3d
ARM A15
VCP2
RAC TAC2 BCP
ARM A15
ARM A15
ARM A15
• First chip architected
using gem5:
– SL2$ size
– MSMC Coherency
– Arbitration
– …
System on a Chip components
• IPs in a SoC vs what gem5 supports:
– ARM
– DSP
– Caches
– Memories
– Core Interconnect
– Chip Interconnect
– Hardware accelerators
– External Interfaces
–…
• SystemC enabled full system benchmarking
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Use case example: Leveraging open source for linux fast path benchmarking
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Radio Access
Network
Network
Co-processor SoC
Zero overhead linux
The need for task partitioning
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Antenna interface
Frequency shift
Remove CP FFT PUSCH/PUCCH de-mapping
LTE PUCCH decoding taskflow
ARM A15
+ * - <<
C66x DSP
FFTC
Automated static mapping
+ * - <<
C66x DSP
+ * - <<
C66x DSP ARM A15 ARM A15
or Runtime load balancing
1000s of tasks
Leveraging checkpointing
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gem5 Check-
pointing closure
Useful for both bare metal and linux
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Source: http://www.arm.com/images/CoreLink_CCN-504_system_large.png
4x Gem5
Gem5
Topaz
SLICC
SimpleDRAM
TLM2.0 protocol bridging
Modeling today’s architectures ARM CCN-504
Thank You! Questions?
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