arm instruction set - iiit...
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ARM Instruction Set
Computer Organization and Assembly Languages p g z y g gYung-Yu Chuang
with slides by Peng-Sheng Chen
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Introduction
• The ARM processor is easy to program at the assembly level (It is a RISC)assembly level. (It is a RISC)
• We will learn ARM assembly programming at the l l d it GBA l tuser level and run it on a GBA emulator.
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ARM programmer model
• The state of an ARM system is determined by the content of visible registers and memorythe content of visible registers and memory.
• A user-mode program can see 15 32-bit general- i t (R0 R14) t purpose registers (R0-R14), program counter
(PC) and CPSR.• Instruction set defines the operations that can
change the state.
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Memory system
• Memory is a linear array of bytes addressed from 0 to
000x00000000bytes addressed from 0 to 232-1W d h lf d b t
10
200x000000010x00000002
• Word, half-word, byte• Little-endian
30
FF0x000000030x00000004
FF
FF
0x00000004
0x000000050x00000006
00
0x00000006
0 FFFFFFFD00
000xFFFFFFFE0xFFFFFFFD
0xFFFFFFFF
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Byte ordering
• Big EndianLeast significant byte has 000x00000000– Least significant byte has highest address
Word address 0x00000000
00
10
20
0x000000000x000000010 00000002
Value: 00102030• Little Endian
20
30
FF
0x000000020x00000003
– Least significant byte has lowest address
FF
FF
FF
0x00000004
0x00000005Word address 0x00000000 Value: 30201000
FF
00
0x00000006
00
000xFFFFFFFE0xFFFFFFFD
000xFFFFFFFF
0xFFFFFFFE
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ARM programmer model
000x0000000010
200x000000010x00000002
R0 R1 R2 R3
30
FF
0x000000020x000000030 00000004
R4 R5 R6 R7
R8 R9 R10 R11 FF
FF
FF
0x00000004
0x00000005
R8 R9 R10 R11
R12 R13 R14 PC FF
00
0x00000006
00
00
000xFFFFFFFE0xFFFFFFFD
000xFFFFFFFF
0
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Instruction set
ARM instructions are all 32 bit long are all 32-bit long (except for Thumb mode) Thumb mode). There are 232
possible machine possible machine instructions. Fortunately they Fortunately, they are structured.
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Features of ARM instruction set
• Load-store architecture3 dd i i• 3-address instructions
• Conditional execution of every instruction• Possible to load/store multiple registers at
once• Possible to combine shift and ALU operations in
a single instructiona single instruction
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Instruction set
• Data processingD • Data movement
• Flow control
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Data processing
• They are move, arithmetic, logical, comparison and multiply instructionsand multiply instructions.
• Most data processing instructions can process f th i d i th b l hift one of their operands using the barrel shifter.
• General rules:– All operands are 32-bit, coming
from registers or literals.– The result, if any, is 32-bit and
placed in a register (with the ti f l g lti l exception for long multiply
which produces a 64-bit result)3 address format– 3-address format
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Instruction set
MOV<cc><S> Rd, <operands>
MOVCS R0, R1 @ if carry is set@ then R0:=R1
MOVS R0, #0 @ R0:=0@ Z=1, N=0,@ C, V unaffected
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Conditional execution
• Almost all ARM instructions have a condition field which allows it to be executed field which allows it to be executed conditionally.
0 1movcs R0, R1
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Register movementimmediate,register,shift
• MOV R0, R2 @ R0 = R20 2 @ 0 2• MVN R0, R2 @ R0 = ~R2
t dmove negated
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Addressing modes
• Register operandsADD R0 R1 R2ADD R0, R1, R2
• Immediate operands
a literal; most can be represented
ADD R3 R3 #1 @ R3:=R3+1
a literal; most can be represented by (0..255)x22n 0<n<12
ADD R3, R3, #1 @ R3:=R3+1AND R8, R7, #0xff @ R8=R7[7:0]
a hexadecimal literalThis is assembler dependent syntaxThis is assembler dependent syntax.
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Shifted register operands
• One operand to ALU is routed through the Barrel routed through the Barrel shifter. Thus, the operand can be modified before it can be modified before it is used. Useful for fast multipliation and dealing p gwith lists, table and other complex data structure. (similar to the displacement addressing
d i C SC• Some instructions (e.g. MUL CLZ QADD) do mode in CISC.) MUL, CLZ, QADD) do not read barrel shifter.
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Shifted register operands
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Logical shift left
CC 0register
MOV R0, R2, LSL #2 @ R0:=R2<<2@ R2 unchangedg
Example: 0…0 0011 0000Before R2=0x00000030Before R2 0x00000030After R0=0x000000C0
R2=0x00000030R2=0x00000030
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Logical shift right
C0 register
MOV R0, R2, LSR #2 @ R0:=R2>>2@ R2 unchangedg
Example: 0…0 0011 0000Before R2=0x00000030Before R2 0x00000030After R0=0x0000000C
R2=0x00000030R2=0x00000030
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Arithmetic shift right
MSB register C
MOV R0, R2, ASR #2 @ R0:=R2>>2@ R2 unchangedg
Example: 1010 0…0 0011 0000Before R2=0xA0000030Before R2 0xA0000030After R0=0xE800000C
R2=0xA0000030R2=0xA0000030
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Rotate right
register
MOV R0, R2, ROR #2 @ R0:=R2 rotate@ R2 unchangedg
Example: 0…0 0011 0001Before R2=0x00000031Before R2 0x00000031After R0=0x4000000C
R2=0x00000031R2=0x00000031
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Rotate right extended
C registerC C
MOV R0, R2, RRX @ R0:=R2 rotate@ R2 unchangedg
Example: 0…0 0011 0001Before R2=0x00000031, C=1Before R2 0x00000031, C 1After R0=0x80000018, C=1
R2=0x00000031R2=0x00000031
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Shifted register operands
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Shifted register operands
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Shifted register operands
• It is possible to use a register to specify the number of bits to be shifted; only the bottom 8 number of bits to be shifted; only the bottom 8 bits of the register are significant.@ i d l l ti@ array index calculationADD R0, R1, R2, LSL R3 @ R0:=R1+R2*2R3
@ fast multiply R2=35xR0ADD R0, R0, R0, LSL #2 @ R0’=5xR0RSB R2, R0, R0, LSL #3 @ R2 =7xR0’
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Multiplication
MOV R1, #35MUL R2 R0 R1MUL R2, R0, R1
or0 0 0 #2 @ 0’ 5 0ADD R0, R0, R0, LSL #2 @ R0’=5xR0
RSB R2, R0, R0, LSL #3 @ R2 =7xR0’
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Shifted register operands
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Encoding data processing instructions
cond 0 0 operand 2# opcode S Rn Rd
31 28 27 26 25 24 21 20 19 16 15 12 11 0
destination register
first operand register
set condition codesset condition codes
arithmetic/logic function
8 bit i di t
25 11 8 7 0
# t 8-bit immediate1 #rot
11 7 6 5 4 3 0
immediate alignment
Rm#shift
0
25
Sh 0
immediate shift length
f
Rm
0
11 8 7 6 5 4 3 0
Rs 10 Sh
shift type
second operand register
RmRs 10 Sh
register shift length
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Arithmetic
• Add and subtraction
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Arithmetic
• ADD R0, R1, R2 @ R0 = R1+R2ADC R0 R1 R2 @ R0 R1 R2 C• ADC R0, R1, R2 @ R0 = R1+R2+C
• SUB R0, R1, R2 @ R0 = R1-R2• SBC R0, R1, R2 @ R0 = R1-R2-!C• RSB R0, R1, R2 @ R0 = R2-R1RSB R0, R1, R2 @ R0 R2 R1• RSC R0, R1, R2 @ R0 = R2-R1-!C
012712813
0127-128-1
255 128 127 0
-5
3-5=3+(-5) → sum<=255 → C=0 → borrow
255 128 127 0
5-3=5+(-3) → sum > 255 → C=1 → no borrow
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Arithmetic
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Arithmetic
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Setting the condition codes
• Any data processing instruction can set the condition codes if the programmers wish it tocondition codes if the programmers wish it to
64-bit additionR1 R0
ADDS R2, R2, R0ADC R3 R3 R1
R3 R2+ADC R3, R3, R1
R3 R2
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Logical
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Logical
• AND R0, R1, R2 @ R0 = R1 and R2ORR R0 R1 R2 @ R0 R1 R2• ORR R0, R1, R2 @ R0 = R1 or R2
• EOR R0, R1, R2 @ R0 = R1 xor R2• BIC R0, R1, R2 @ R0 = R1 and (~R2)
bit clear: R2 is a mask identifying which bits of R1 will be cleared to zero
R1=0x11111111 R2=0x01100101
BIC R0, R1, R2
R0=0x10011010R0=0x10011010
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Logical
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Comparison
• These instructions do not generate a result, but set condition code bits (N Z C V) in CPSR set condition code bits (N, Z, C, V) in CPSR. Often, a branch operation follows to change the program flowprogram flow.
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Comparison
• CMP R1 R2 @ set cc on R1-R2compare
• CMP R1, R2 @ set cc on R1-R2
• CMN R1 R2 @ set cc on R1+R2compare negated
• CMN R1, R2 @ set cc on R1+R2
TST R1 R2 @ set cc on R1 and R2bit test
• TST R1, R2 @ set cc on R1 and R2
TEQ R1 R2 @ t R1 R2test equal
• TEQ R1, R2 @ set cc on R1 xor R2
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Comparison
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Multiplication
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Multiplication
• MUL R0, R1, R2 @ R0 = (R1xR2)[31:0]
• Features:S d d ’t b i di t– Second operand can’t be immediate
– The result register must be different from the first operand
– Cycles depends on core typey p yp– If S bit is set, C flag is meaningless
See the reference manual (4 1 33)• See the reference manual (4.1.33)
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Multiplication
• Multiply-accumulate (2D array indexing)MLA R4 R3 R2 R1 @ R4 = R3xR2+R1MLA R4, R3, R2, R1 @ R4 = R3xR2+R1
M lti l ith t t ft b • Multiply with a constant can often be more efficiently implemented using shifted register operand operand MOV R1, #35MUL R2 R0 R1MUL R2, R0, R1
orADD R0, R0, R0, LSL #2 @ R0’=5xR0RSB R2, R0, R0, LSL #3 @ R2 =7xR0’
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Multiplication
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Multiplication
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Flow control instructions
• Determine the instruction to be executed next
pc-relative offset within 32MB
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Flow control instructions
• Branch instructionB l b lB label…
label: …
• Conditional branchesMOV R0, #0MOV R0, #0
loop: …ADD R0 R0 #1ADD R0, R0, #1CMP R0, #10BNE loop
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Branch conditions
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Branches
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Branch and link
• BL instruction save the return address to R14(lr)(lr)
BL sub @ call subCMP R1, #5 @ return to hereMOVEQ R1, #0…
sub: … @ sub entry point…MOV PC, LR @ return
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Branch and link
BL sub1 @ call sub1…
use stack to save/restore the return address and registers
sub1: STMFD R13!, {R0-R2,R14}BL sub2…LDMFD R13!, {R0-R2,PC}, { , }
sub2:sub2: ……MOV PC LRMOV PC, LR
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Conditional execution
CMP R0, #5BEQ b pass @ if (R0! 5) {BEQ bypass @ if (R0!=5) {ADD R1, R1, R0 @ R1=R1+R0-R2 SUB R1, R1, R2 @ }
bypass: …
CMP R0, #5 smaller and faster,ADDNE R1, R1, R0SUBNE R1 R1 R2SUBNE R1, R1, R2
Rule of thumb: if the conditional sequence is three instructionsqor less, it is better to use conditional execution than a branch.
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Conditional executionif ((R0==R1) && (R2==R3)) R4++
CMP R0, R1BNE skipBNE skipCMP R2, R3BNE skipBNE skipADD R4, R4, #1
skip:skip: …
CMP R0 R1CMP R0, R1CMPEQ R2, R3ADDEQ R4 R4 #1ADDEQ R4, R4, #1
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Data transfer instructions
• Move data between registers and memoryTh b i f• Three basic forms– Single register load/store– Multiple register load/store– Single register swap: SWP(B), atomic Single register swap: SWP(B), atomic
instruction for semaphore
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Single register load/store
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Single register load/store
No STRSB/STRSH since STRB/STRH stores both i d/ i d signed/unsigned ones
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Single register load/store
• The data items can be a 8-bit byte, 16-bit half-word or 32 bit word Addresses must be word or 32-bit word. Addresses must be boundary aligned. (e.g. 4’s multiple for LDR/STR)LDR/STR)
LDR R0, [R1] @ R0 := mem32[R1]STR R0, [R1] @ mem32[R1] := R0
LDR, LDRH, LDRB for 32, 16, 8 bits, , , ,STR, STRH, STRB for 32, 16, 8 bits
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Addressing modes
• Memory is addressed by a register and an offset.LDR R0 [R1] @ [R1]LDR R0, [R1] @ mem[R1]
• Three ways to specify offsets:– ImmediateLDR R0, [R1, #4] @ mem[R1+4]R i– RegisterLDR R0, [R1, R2] @ mem[R1+R2]Scaled register @ [R1+4*R2]– Scaled register @ mem[R1+4*R2]LDR R0, [R1, R2, LSL #2]
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Addressing modes
• Pre-index addressing (LDR R0, [R1, #4])i h i b kwithout a writeback
• Auto-indexing addressing (LDR R0, [R1, #4]!)Pre-index with writebackcalculation before accessing with a writeback calculation before accessing with a writeback
• Post-index addressing (LDR R0, [R1], #4)l l ti ft i ith it b k calculation after accessing with a writeback
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Pre-index addressing
LDR R0, [R1, #4] @ R0=mem[R1+4]@ R1 nchanged@ R1 unchanged
LDR R0, [R1, ]LDR R0, [R1, ]
R1 +
R0
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Auto-indexing addressing
LDR R0, [R1, #4]! @ R0=mem[R1+4]@ R1 R1+4@ R1=R1+4
No extra time; Fast;
LDR R0, [R1, ]!
; ;
LDR R0, [R1, ]!
R1 +
R0
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Post-index addressing
LDR R0, R1, #4 @ R0=mem[R1]@ R1 R1+4@ R1=R1+4
LDR R0,[R1],LDR R0,[R1],
R0R1
+
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Comparisons
• Pre-indexed addressingLDR R0 [R1 R2] @ R0=mem[R1+R2]LDR R0, [R1, R2] @ R0=mem[R1+R2]
@ R1 unchangedAuto indexing addressing• Auto-indexing addressing
LDR R0, [R1, R2]! @ R0=mem[R1+R2]@ R1 R1+R2@ R1=R1+R2
• Post-indexed addressingLDR R0, [R1], R2 @ R0=mem[R1]
@ R1=R1+R2
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Example
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Example
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Example
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Summary of addressing modes
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Summary of addressing modes
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Summary of addressing modes
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Summary of addressing modes
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Load an address into a register
• Note that all addressing modes are register-offseted Can we issue LDR R0 Table? The offseted. Can we issue LDR R0, Table? The pseudo instruction ADR loads a register with an address address
table: .word 10…
ADR R0, table
• Assembler transfer pseudo instruction into a psequence of appropriate instructions sub r0 pc #12sub r0, pc, #12
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Application
ADR R1, tableloop LDR R0 [R1] tableloop: LDR R0, [R1]
ADD R1, R1, #4R1
@ operations on R0…
ADR R1, table,loop: LDR R0, [R1], #4
@ operations on R0…
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Multiple register load/store
• Transfer a block of data more efficiently.U d f d d i f i • Used for procedure entry and exit for saving and restoring workspace registers and the
t ddreturn address• For ARM7, 2+Nt cycles (N:#words, t:time for a
word for sequential access). Increase interrupt latency since it can’t be interrupted.
registers are arranged an in increasing order; see manualLDMIA R1, {R0, R2, R5} @ R0 = mem[R1]
@ R2 = mem[r1+4]@ R5 = mem[r1+8]@ R5 mem[r1+8]
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Multiple load/store register
LDM load multiple registersSTM store m ltiple registersSTM store multiple registers
suffix meaningIA increase afterIB increase beforeDA decrease afterDB decrease before
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Addressing modes
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Multiple load/store registerLDM<mode> Rn, {<registers>}IA: addr:=RnIB: addr:=Rn+4DA: addr:=Rn-#<registers>*4+4
#DB: addr:=Rn-#<registers>*4For each Ri in <registers> IB: addr:=addr+4IB: addr:=addr+4DB: addr:=addr-4Ri:=M[addr]IA: addr:=addr+4DA: addr:=addr-4!
RnR1
<!>: Rn:=addr R2R3
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Multiple load/store registerLDM<mode> Rn, {<registers>}IA: addr:=RnIB: addr:=Rn+4DA: addr:=Rn-#<registers>*4+4
#DB: addr:=Rn-#<registers>*4For each Ri in <registers> IB: addr:=addr+4IB: addr:=addr+4DB: addr:=addr-4Ri:=M[addr]IA: addr:=addr+4DA: addr:=addr-4!
Rn
<!>: Rn:=addr R1
R2R3
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Multiple load/store registerLDM<mode> Rn, {<registers>}IA: addr:=RnIB: addr:=Rn+4DA: addr:=Rn-#<registers>*4+4
#DB: addr:=Rn-#<registers>*4For each Ri in <registers> IB: addr:=addr+4 R1IB: addr:=addr+4DB: addr:=addr-4Ri:=M[addr]
R3R2
R1
IA: addr:=addr+4DA: addr:=addr-4!
RnR3
<!>: Rn:=addr
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Multiple load/store registerLDM<mode> Rn, {<registers>}IA: addr:=RnIB: addr:=Rn+4DA: addr:=Rn-#<registers>*4+4
#DB: addr:=Rn-#<registers>*4For each Ri in <registers> IB: addr:=addr+4
R1R2IB: addr:=addr+4
DB: addr:=addr-4Ri:=M[addr]
R2R3
IA: addr:=addr+4DA: addr:=addr-4!
Rn
<!>: Rn:=addr
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Multiple load/store register
LDMIA R0, {R1,R2,R3}
orLDMIA R0, {R1-R3}
addr data0x010 10R0
R1: 10R2: 20
0x014 20
0x018 30
R0
R3: 30R0: 0x10
0x018 30
0x01C 40
0x020 50R0: 0x10 0x020 50
0x024 60
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Multiple load/store register
LDMIA R0!, {R1,R2,R3}
addr data0x010 10R0
R1: 10R2: 20
0x014 20
0x018 30
R0
R3: 30R0: 0x01C
0x018 30
0x01C 40
0x020 50R0: 0x01C 0x020 50
0x024 60
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Multiple load/store register
LDMIB R0!, {R1,R2,R3}
addr data0x010 10R0
R1: 20R2: 30
0x014 20
0x018 30
R0
R3: 40R0: 0x01C
0x018 30
0x01C 40
0x020 50R0: 0x01C 0x020 50
0x024 60
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Multiple load/store register
LDMDA R0!, {R1,R2,R3}
addr data0x010 10
R1: 40R2: 50
0x014 20
0x018 30R3: 60R0: 0x018
0x018 30
0x01C 40
0x020 50R0: 0x018 0x020 50
0x024 60R0
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Multiple load/store register
LDMDB R0!, {R1,R2,R3}
addr data0x010 10
R1: 30R2: 40
0x014 20
0x018 30R3: 50R0: 0x018
0x018 30
0x01C 40
0x020 50R0: 0x018 0x020 50
0x024 60R0
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Example
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Example
LDMIA r0!, {r1-r3}
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Example
LDMIB r0!, {r1-r3}
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Application
• Copy a block of memoryR9 dd f th – R9: address of the source
– R10: address of the destinationR11 d dd f th – R11: end address of the source
loop: LDMIA R9!, {R0-R7}STMIA R10!, {R0-R7}CMP R9, R11BNE loopBNE loop
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Application
• Stack (full: pointing to the last used; ascending: grow towards increasing memory addresses)grow towards increasing memory addresses)
mode POP =LDM PUSH =STM
Full ascending (FA) LDMFA LDMDA STMFA STMIB
Full descending (FD) LDMFD LDMIA STMFD STMDBFull descending (FD) LDMFD LDMIA STMFD STMDB
Empty ascending (EA) LDMEA LDMDB STMEA STMIA
E t d di ( ) LDMED LDMIB STMED STMDA
LDMFD R13! {R2 R9} @ used for ATPCS
Empty descending (ED) LDMED LDMIB STMED STMDA
LDMFD R13!, {R2-R9} @ used for ATPCS… @ modify R2-R9STMFD R13!, {R2-R9}
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Example
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Swap instruction
• Swap between memory and register. Atomic operation preventing any other instruction from operation preventing any other instruction from reading/writing to that location until it completescompletes
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Example
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Application
Process A Process BOS
While (1) {if (s==0) {
While (1) {if (s==0) {
S=0/1if (s 0) {s=1;
}}
if (s 0) {s=1;
}}}
// use the // resource
}// use the // resource
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Software interrupt
• A software interrupt instruction causes a software interrupt exception which provides a software interrupt exception, which provides a mechanism for applications to call OS routines.
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Example
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Load constants
• No ARM instruction loads a 32-bit constant into a register because ARM instructions are 32 bit a register because ARM instructions are 32-bit long. There is a pseudo code for this.
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Immediate numbers
cond 0 0 operand 2# opcode S Rn Rd
31 28 27 26 25 24 21 20 19 16 15 12 11 0
destination register
first operand register
set condition codesv=n ror 2r
set condition codes
arithmetic/logic function
8 bit i di t
25 11 8 7 0
# t
nr8-bit immediate1 #rot
11 7 6 5 4 3 0
immediate alignment
Rm#shift
0
25
Sh 0
immediate shift length
f
Rm
0
11 8 7 6 5 4 3 0
Rs 10 Sh
shift type
second operand registerencoding for data processing RmRs 10 Sh
register shift length
data processinginstructions
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Load constants
• Assemblers implement this usually with two options depending on the number you try to options depending on the number you try to load.
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Load constants
• Assume that you want to load 511 into R0C t t i lti l i t ti– Construct in multiple instructionsmov r0, #256dd 0 #255add r0, #255
– Load from memory; declare L511 .word 511#ldr r0, L511 ldr r0, [pc, #0]
• Guideline: if you can construct it in two instructions, do it; otherwise, load it.
• The assembler decides for you yldr r0, =255 mov r0, 255ldr r0, =511 ldr r0, [pc, #4], , [p , ]
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PC-relative modes
Impossible to use Impossible to use direct addressing
encoding for data transferdata transferinstructions
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PC-relative addressingmain:
MOV R0, #0MOV R0, #0ADR R1, a @ add r1, pc, #4STR R0 [R1]STR R0, [R1]SWI #11
a: word 100PCa: .word 100
.end
fetch decode exec
fetch decode exec
fetch decode execfetch decode exec
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Instruction set