arm cortex board
TRANSCRIPT
![Page 1: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/1.jpg)
1
ARM Cortex board
![Page 2: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/2.jpg)
2
ARM Cortex STM series
![Page 3: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/3.jpg)
STM32 Series
3
![Page 4: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/4.jpg)
Abbreviation • FS full speed
• HS high speed
• MC motor controller
• MSI multi speed internal oscillator
• RNG random number generator
• SDIO secure digital input output
• VScal voltage scaling
• DSC digital signal controller
• PGA programmable gain ampilier 4
![Page 5: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/5.jpg)
STM32F4xx block diagram
5
![Page 6: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/6.jpg)
Memory map (1)
6
![Page 7: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/7.jpg)
Memory Map (2)
7
![Page 8: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/8.jpg)
Memory Map (3)
8
![Page 9: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/9.jpg)
ARM Bus
• Introduced by ARM Ltd in 1996
• Widely used as the on-chip bus
![Page 10: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/10.jpg)
ARM BUS
• AMBA = ARM Memory Bus Architecture
• AHB = ARM High performance Bus
• APB = ARM Peripheral Bus
• AMBA-AHB connects ARM core with
memory, external DRAM
• AMBA-APB interfaces ARM core with
external low-speed I/O devices using
AMBA-APB bridge
![Page 11: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/11.jpg)
AMBA
• AMBA-AHB connects to 32-bit data and
32-bit address at high speed
• AHB maximum bps bandwidth is 16 times
ARM processor clock
• AMBA-APB bridge is used to
communicate AHB bus to APB bus
• The bridge communicates to memory
through AMBA-AHB
![Page 12: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/12.jpg)
AHB Bus
• AHB Bus are interconnected with:
– Cortex core
– Internal SRAM
– Internal Flash memory
– FSMC (Flexible Static Memory Controller)
– AHB to APB
– DMA
– Ethernet DMA
12
![Page 13: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/13.jpg)
APB bus
Connect:
• I2C
• Touch screen
• SDIO
• MMC (multimedia-bus)
• USB
• CAN bus
![Page 14: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/14.jpg)
ARM BUS
![Page 15: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/15.jpg)
System architecture
15
![Page 16: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/16.jpg)
System architecture connecting devices
16
![Page 17: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/17.jpg)
Bus system
• Icode bus : connects the instruction bus to the flash
memory instruction interface (FLITF)
• Dcode bus : connects to flash memory data interface
and debug access
• System bus : connects to bus matrix that manages the
arbitration between core and DMA
• DMA bus: AHB master interface of the DMA to bus
matrix
• Bus matrix: arbitrations between different buses
• AHB/APB bridge: bridge between AHB and APB
APB1 is limited at 45 MHz and APB2 is at 90 MHz
17
![Page 18: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/18.jpg)
AHB and APB
• AHB = Advance High Performance Bus with
max speed = 180 Mhz
• APB = Advance Peripheral Bus with APB1 max
speed = 45 Mhz and APB2 max speed = 90
MHz
• FSMC = Flexible static memory controller (able
to interface with synchronous and
asynchronous)
18
![Page 19: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/19.jpg)
Cyclic redundancy checking (CRC)
• Use to get a CRC code from a 32 bit data word
• Use to verify data transmission and storage
integrity
• Example of CRC calculation block diagram
• Example of CRC polynomial:
19
![Page 20: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/20.jpg)
Power supply overview
• The device requires 1.2-3.3V voltage supply.
20
![Page 21: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/21.jpg)
Power supply
• Voltage regulator to provide 1.2V for core
and memory
• Reset and Clock control, real time clock,
and LSE (Low speed external crystal)
oscillator are supported by backup domain
power source
• BDCR = Backup Domain Control Register 21
![Page 22: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/22.jpg)
Low power mode
• Normal condition: run mode
• Low power mode:
– Sleep mode
CPU clocks are off, all peripherals are running
– Stop mode
all clocks are off
– Standby mode
1.2 V power domain is off (enter backup domain)
22
![Page 23: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/23.jpg)
Low power mode
WFI (wait for interrupt) and WFE (wait for event) are special ARM
instructions
PDDS = Power down deep sleep. LPDS = Low-Power Deep sleep
23
![Page 24: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/24.jpg)
Reset
There are 3 types of reset:
• System reset
• Power reset
• Backup domain reset
24
![Page 25: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/25.jpg)
System reset
Set all registers to their reset values except reset
flags and registers in the backup domain
It is generated when:
• External reset pin is triggered
• Window watchdog ends of count condition
(WWDG reset)
• Independent watchdog ends of count condition
(IWDG reset)
• Software reset (SW reset)
• Low power management reset
25
![Page 26: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/26.jpg)
Power reset
Set all registers to their reset values except
registers in the backup domain
It is generated when:
• Power on/ Power down reset
• When exiting standby mode
26
![Page 27: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/27.jpg)
Backup domain reset
Effects only the backup domain
It is generated when:
• Software reset
• VDD or VBAT, if both supplies have previously
been off
27
![Page 28: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/28.jpg)
STM32F4xxx board
28
![Page 29: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/29.jpg)
STM32F4 Hardware diagram
29
![Page 30: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/30.jpg)
STM32F4 Hardware diagram
30
![Page 31: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/31.jpg)
Clocks Three different clock sources can be used to drive
SYSCLK
• HSI (High speed Internal) oscillator clock
• HSE (High speed External) oscillator clock
• PLL clock
The devices have two secondary clock sources
• 32 kHz low speed internal (LSI) RC for the
independent watchdog and optionally drive RTC
• 32.768 kHz low speed external crystal (LSE) which
optionally drive RTC
Each clock source can be switched on/off independently 31
![Page 32: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/32.jpg)
CLOCK
• HSI clock: provides a clock source at low
cost (no external component)
• HSE clock: provides higher accuracy
• LSE clock: low power, but high accuracy
• LSI clock: low power for stop and standby
mode
32
![Page 33: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/33.jpg)
SYSCLOCK
• After a system reset, HSI is selected as
system clock
• A switch from one clock source to another
occurs only if target clock source is ready
• If a target is not yet ready, the switch will
occur after the target is ready
33
![Page 34: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/34.jpg)
Clock Tree
34
![Page 35: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/35.jpg)
Clock Tree
35
![Page 36: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/36.jpg)
Our board
• HSE is 4-26 MHz crystal (16 MHz our case)
• HSI is 16 MHz
• PLL = Up to 168 MHz (Max. freq.)
• SYSCLK can be selected from PLL, HSE,
or HSI 36
![Page 37: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/37.jpg)
Real Time Clock (RTC)
• RTC can be either HSE (1MHz), LSE or
LSI clock which is set by the backup
domain control register
• If LSE is selected, RTC continues to work
even if system or backup supplies
disapeear
37
![Page 38: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/38.jpg)
Watchdog and clockout
• If independent watchdog is started either
by hardware or software, LSI oscillator is
forced ON and will supply the watchdog
• Microcontroller clock output (MCO pin)
allows clock to be outputted by selected
from: SYSCLOCK, HSI, HSE, PLL
38
![Page 39: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/39.jpg)
Output clock
• HCLK : for AHB bus, core, memory and DMA
• FCLK: free running clock
• APBx
• APBxTIMCLK
• ADCCLK: to ADC module
• I2S Clock
• Ethernet clock
• USB clock 39
![Page 40: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/40.jpg)
Reset and Clock Control (RCC)
• RCC is a set of register to setup for reset
and clock control
40
![Page 41: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/41.jpg)
Internet/External clock setup
This section provide functions allowing to configure the internal/external clocks,
PLLs, CSS and MCO pins.
1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or
through the PLL as System clock source.
2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG
and/or RTC clock source.
3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
through the PLL as System clock source. Can be used also as RTC clock
source.
4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
5. PLL (clocked by HSI or HSE), featuring two different output clocks:
- The first output is used to generate the high speed system clock (up to
168 MHz)
- The second output is used to generate the clock for the USB OTG FS
(48 MHz), the random analog generator (<=48 MHz) and the SDIO (<=
48 MHz). 41
![Page 42: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/42.jpg)
Internet/External clock setup
6. PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to
achieve high-quality audio performance on the I2S interface.
7. CSS (Clock security system), once enable and if a HSE clock failure occurs
(HSE used directly or through PLL as System clock source), the System
clock is automatically switched to HSI and an interrupt is generated if
enabled. The interrupt is linked to the Cortex-M4 NMI (Non-Maskable
Interrupt) exception vector.
8. MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
clock (through a configurable prescaler) on PA8 pin.
9. MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or
PLLI2S clock (through a configurable prescaler) on PC9 pin.
42
![Page 43: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/43.jpg)
Example /** @brief System Clock Configuration
* The system Clock is configured as follow :
* System Clock source = PLL (HSE)
* SYSCLK(Hz) = 168000000
* HCLK(Hz) = 168000000
* AHB Prescaler = 1
* APB1 Prescaler = 4
* APB2 Prescaler = 2
* HSE Frequency(Hz) = 8000000
* PLL_M = 8 ( VCO input frequency ranges from 1 to 2 MHz.
VCO = HSE/ PLL_M)
* PLL_N = 336 (set freq. 336 MHz)
* PLL_P = 2 (sysclk = PLL_N/PLL_P but not exceed 168MHz)
* PLL_Q = 7 (USBclk = PLL_N/PLL_Q)
* VDD(V) = 3.3
* Main regulator output voltage = Scale1 mode
* Flash Latency(WS) = 5
* @param None
* @retval None
*/
43
![Page 44: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/44.jpg)
static void SystemClock_Config(void)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
/* Enable Power Control clock */
__PWR_CLK_ENABLE();
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1)
;
/* Enable HSE Oscillator and activate PLL with HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 8;
RCC_OscInitStruct.PLL.PLLN = 336;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 7;
44
![Page 45: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/45.jpg)
if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK |
RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 |
RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
{
Error_Handler();
}
}
45
![Page 46: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/46.jpg)
Simulink Configuration
46
![Page 47: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/47.jpg)
Questions?
• Write a program to output clock as follows:
SYSCLK = 160 MHz
PCLK1 = 45 MHz
PCLK2 = 90 MHz
47
![Page 48: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/48.jpg)
Boot configuration
• In STM32F10xxx, 3 different boot modes
are provided and can be selected from the
pin.
48
![Page 49: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/49.jpg)
Boot mode
• Boot from main flash memory: flash memory is
aliased to address 0x0000 0000, but can also
accessed from address 0x0800 0000
• Boot from system memory: it can be acces from
aliasing address: 0x0000 0000 or 0x1FFF B000
• Boot from embedded SRAM: only at address
0x2000 0000
Note: when booting from SRAM, NVIC exception
table has to be relocated 49
![Page 50: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/50.jpg)
Bit banding
• Bit band operation support allows a single
load/store operation to access a single
data bit
• In ARM Cortex M3, this is supported in two
predefined memory regions call bit-band
regions
• One of them is located in the first 1 MB of
the SRAM and the other is located in the
first 1 MB of the peripheral region
50
![Page 51: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/51.jpg)
Bit-band region
51
![Page 52: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/52.jpg)
Example of bit-band access
52
![Page 53: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/53.jpg)
Data mapping (from bit to word)
Bit_word_address = bit_band_base +
(byte_offset*32) + (bit_number x 4)
Example: To access bit 2 of the byte located
in SRAM address 0x20000300
= 0x22000000 + (0x300*32) + 2*4
= 0x22008008
53
![Page 54: ARM Cortex board](https://reader033.vdocuments.us/reader033/viewer/2022042313/625c5a20ab40e837b2071517/html5/thumbnails/54.jpg)
Questions?
54