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0 Aiy RESEARCH LORATORY00 ----

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Evaluation of a Multiple Instruction/Multiple Data (MIMD) Parallel Computer

for CFD Applications

72 Stephen J. Schraml

ARL-TR-589 October 1994

TTC T--S"'" O•T2 7 1994

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94-33314

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9410 26 009

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Id

REPORT DOCUMENTATION PAGE 1Opm oft -oe

1. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ S A YUlCOT(ev AW .M IDV . TYPt ANO DATIS COVIRSOI October 1994 Final, April 1991 - November 1992

Evaluation of a Multiple Instruction/Multiple Data (MIHD)Parallel Computer for CFD Applications WdO: 4C592-42l-U2-U042

it AIDNOaw )

Stephen J. Schraml

7. -RWI 00ONAWST %~W() AW ADM SS(tS) 8.P10100 00 UZATION

U.S. Army Research LaboratoryATTN: hM.L-VT-OCAberdeen Proving Ground, MD 21005-5066

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Approved far public release; distriteation is unlimited. [13. ABSTRACT (Mwmmum 200 wovqkIn an attempt to evaluate the merits of massively parallel processing computers forthe numerical simulation of blast phenomena. the U.S. Army Research Laboratory (ARL)has adapted one of its blast modeling tools to several unique parallel architec-tures. This report describes the adaptation of the BRL-4Q1D code, a quasi-one--dimensional, finite difference Euler solver, to the Intel iPSCI86O parallelI super-computer. The code was reconfigured for the iPSCI86O using FORTRAN4 77 and theIntel LPSCI86O message-passing library. The performance of the code was measuredon the iPSC/860 for a vAriety of problem sizes and processor configurations. Tl;e

w performance was found to be highly dependent on the size of the problem. Thisproblem size dependency was most noticeable when fever processors were employed.Results of scalability tests indicate that the code performance sc.nles in aroughly linear fashion about extrapolated lines of ideal performance.

R.~~~ ISTTia1. NUMBER OF PAGESnuclear explosion simulation, shock tubes, computer programming I26

17. ERM0"06TUM 16.SIMMCLASIFCATO i . SECURITY CLASSIFICATION 120. LIMITATION Of ABSTRACT

MN Standard Form 298 (Rev 2-89)Pv.Webd OV AMJ Sid M3 1S

M_. 102

Inteiitionally Loeft Blank

Acknowledgments

The BRL-Q1D code adaptation and performance trials were conducted withthe resources provided by the U.S. Army Research Laboratory (ARL), the StateUniversity of New York at Stony Brcok and the California Institute of Technology.The author acknowledges the assistance provided by the support staffs of theseorganizations.

V The author also acknowledges Mr. Monte W. Colcman, ARL, for assistanceprovided in executing the calculations described in this report, and Mr. ThomasM. Kendall, also of ARL, for reviewing this report.

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Table of Contents

Acknowledgments ................................... .

List of Figures ........ ................................... . .

1. Background .......... .................................... 1

V 2. The iPSC/860 .......... ................................... 1

3. Blast Modeling Application ........ ........................... 3

4. Results .......... ....................................... 7

5. Conclusions .......... .................................... 9

References .......... ..................................... 13

Distribution List ......... ................................. 15

U

I


vi

List of Figures

Figure Page

1 Measured Performance of BRL-Q1D Code ........................ 10

2 Scalability Using 512 Grid Points / Node .......................... 10

3 Scakbility Using 1024 Grid Points / Node ........................ 11

4 Scalability Using 2048 Grid Points / Node ........................ 11



vii

II


VIII

1. Background

Due to the rising costs of large-scale experimentation and the uncertainty of scalingeffects in experiments, the U.S. Army is becoming increasingly dependent on computer sim-ulations to assess the vulnerability of military systems to nuclear blast. Present vectorsupercomputer technology can provide detailed fluid dynamic simulations in two dimensionsin a production environment (less than 10 CPU hours). Three-dimensional simulations em-ploying limited spatial resolution, whiich are only sufficient for modeling relatively simplegeometries, still require 100 or more CPU hours on a vector supercomputer.

Obviously, these low resolution simulations with simple geometries do not provide suffi-cient information about the vulnerability of specific military systems to the overturning orcrushing effects of blast produced by tactical nuclear weapons. To provide accurate assess-ments of system vulnerability, highly detailed three-dimensional simulations with coupledfluid-structure interaction are required. To make this type of numerical simulation possi-ble, increases in supercomputer performance of two or more orders of magnitude must berealized.

The rapidly maturing field of massively parallel processing (MPP) has the potential tooffer the compute performance required for detailed three-dimensional fluid dynamic simu-lations. There are many different types MPP machines available oln the computer markettoday. However, generally speaking, most current MPP computers have the following twobasic characteristics:

1. They combine the resources of a large number of processors to simultaneously solvedifferent parts of a large problem.

2. Each processor has its own bank of local memory.

Particular MPP computers differ primarily in the way the processors access data in their ownmemory and data in the memory of other processors. These data access methods typicallydefine the programming methods which are required to extract maximum performance fromall of the resources that the machine has to offer.

As a means of evaluating MPP technology, the U.S. Army Research Laboratory (ARL)continuously adapts one of its blast modeling tools to emerging MPP computer platforms.)Through continuous evaluation of MPP computers, the ARL can configure its software toolsto exploit this techncology, thus making detailed three-dimensional fluid dynamic simulationsavailable in a production computing environment.

2. The iPSC/860

The Intel iPSC/860 was the parallel computer chosen for the adaptation and evaluationdescribed in this report. The iPSC/860 is a Multiple Instruction / Multiple Data (MIMD)parallel computer. This implies that the processors of the computer can perform a number of

1

different operations simultaneously, if requested to do so. This is quite different from a SingleInstruction / Multiple Data (SIMD) computer, in which all of the computers processorsperform identical operations, simultaneously, on different sections of data.

The heart of the iPSC/860 is a set of Intel i860 microprocessors. Each of these proces-sors has a fixed amount of local memory. Systems configured this way are often referredto as "distributed memory multiprocessors." Most current MPP machines are distributedmemory architectures. The individual processors of tile iPSC/860 are linked together by aninterconnect network which allows high bandwidth data transfer between processors. Theearlier model of the iPSC/860, known as the Gamma, employs a hypercube topology as theinterconnect network. 2 A hypercube can be envisioned as a large number of nested cubeswith each point of a cube representing a node, or processor, in the system. The later modeliPSC/860, called the Delta, employs a two-dimensional mesh topology as the processor in-terconnect network. Each type of interconnect network is designed to have a max-mumnumber of connections between available processors, while at the same time minimizing thedistance that data must travel when moving from its originating processor to its destinationprocessor.

Like most MPP machines, the iPSC/860 is designed to be a scalable system. As such,it should be possible to linearly increase the compute performance of an application byincreasing the number of processors allocated to the application. Thus scalability is themotivation in the development of MPP computers. In a truly scalable system, a desired levelof performance can be obtained by simply acquiring the necessary quantity of processors.This is potentially more cost-effective than obtaining performance gains through advancesin single processor design.

Unfortunately, building a scalable architecture is only half of the solution to obtainingincreased performance. To optimally employ all of the iesources provided by MPP com-puters, the application's algorithm must be designed to be scalable as well. Optimum algo-rithm design for the iPSC/860, and most other MIMD machines, is accomplished througha style of programming known as message-passing. When a parallel application is run onthe iPSC/860, the data is distributed among the available memory of the processors beingused. If a particular processor needs access to a piece of data stored in another processor'smemory to perform a calculation, then that data must be transterred from khe originatingprocessor to the processor which needs the data. To accomplish this data transmission, theapplication must be written to explicitly pass the data from the original processor, to thetarget processor.

3

One potential bottleneck in distributed memory parallel computers is this transfer ofdata between processors. Even though the processors are connected by a high-speed net-work, the time required to move data between processors is typically much greater than thetime spent by the receiving processor executing a floating point instruction using that data.Consequently, the ultimate goal in developing an algorithmr which employs message-passingtechniques is to minimize time spent transferring data, thereby maximizing the time spent incomputing the solu'tion. With this in mind, the algorithm designer must be sure to transferonly that data which is necessary for the calculations to be performed correctly.

2

3. Blast Modeling Application

The BRL-Q1D code was selected as the blast modeling application which is used bythe ARL to eva!'jate the programming environment and the computational performance ofmassively parallel computers. BRL-Q1D is a quasi-one-dimensional, finite difference, singlematerial, polytroý'-" gas fluid dynamics code and is primarily used to simulate flow in shocktubes. This code was chosen for its relative simplicity and its algorithmic similarities to thetwo- and three-dimensional codes that are currently used for blast modeling applications.Therefore, adaptation of this code is the most cost-effective means of evaluating massivelyparallel computer architectures. The similarities in the solution algorithms of BRL-Q1D andmore complex multidimensional codes can provide insight to the potential performance ofthese more complex codes on MPP computers.

The BRL-QLD code incorporates two computational techniques, an implicit finite dif-ference technique 4 and an explicit finite difference scheme.5 Only one of these algorithmsmay be used in a particular BRL-Q1D calculation. The solution scheme which is employedis determined by a set of user-defined input options. The solution algorithms are applied tothe quasi-one-dimensional Euler equations in th 'r weak conservative form. 6

One multidimensional fluid dynamics code used extensively at ARL for the numericalsimulation of blast effects is the SHARC code. SHARC is an explicit, finite differenceEuler solver which is second-order accurate in space and time.7 Because of its algorithmicsimilarities to the SHARC code, only the explicit algorithm of the BRL-Q1D code wasadapted to the iPSC/860.

The MacCormack explicit scheme employed in BRL-Q1D is a second-order, non-centered,predictor-corrector technique that alternatively uses forward and backward differences forthe two steps. The first step predicts the value of the state variables at a grid point basedon the values of the grid point and its neighboring downstream grid point. The second stepthen corrects these state variables based on the values at the grid point and its neighboringupstream grid point.

Prior to its adaptation to the iPSC/860, the BRL-Q1D code existed in standard For-tran 77 form and the explicit, finite difference algorithm had been optimized for maximumperformance on vector supercomputers. So that it could obtain maximum performance onthe iPSC/860, the code was modified to evenly distribute the arrays among the availableprocessors and then calls to the iPSC message-passing library were inserted where necessaryfor the transmission of data between processors.

The even distribution of arrays among available processors is a technique which is oftenreferred to as "domain decomposition." In the case of the one-dimensional code, domaindecomposition is nothing more than evenly dividing the number of available processors intothe number of grid points being used by the calculation, then placing that number of adjacentgrid points on successive processors. For example, to distribute an 800 grid point calculationamong 8 processors, grid points 1 to 100 would be placed on processor 0, 101 to 200 onprocessor 1, etc. The BRL-QLD code was modified in such a way that each time the codewas run, it would •;atomatically determine the number of processors that were available,

3

and dynamically allocate the arrays based on the grid size and this returned number ofprocessors. Of course, domain decomposition in two or three spatial dimensions can bemucha more complex than this simple one-dimensional case. This is especially true whencomplex geometries are being modeled.

After the domain decomposition scheme had been developed, it was then imposed on thesolution algorithm, so that the computational load would be evenly distributed among theprocessors. In the original Fortran 77 implementation of the BRL-QlD code, the successiveprediction and correction of state variables was accomplished through the use of DO loopswhich proceed through the one-dimensional grid, from beginning to end, in one grid pointincrements. For the message-passing implementation, the range of DO loop operation on aparticular processor was limited to the grid points which were allocated to that processor.If a calculation required data from a grid point which does not reside on the processor doingthe calculation, that data is passed to the processor prior to the calculation. The followingexamples of original Fortran 77 code and message-passing code illustrate this logic.

Segment of Original Fortran 77 Code

do 20 jw2,jmax-ls(j,1) - q(j,1) - dt*(f(j+1,1)-f(j,1))

20 continue

Segment of Equivalent Message Passing Code

istart'-ibeg(mynode ( ) +1)istop -iend(mynode(+1)if (istart.eq. 1) istart=2if (istop .eq.jmax) istop =jmax-1if (nuamnodeso.ne.1) call passleft(f,l)do 20 j-istart,istop

s(j,l) - q(j,l) - dt*(f(j+1,1)-f(j,M))20 continue

These code segments bre examples of a predictor step in the explicit algorithm. In theseexamples, the array s is being calculated from the arrays q and f and a constant, dt forall grid points between the second and the next to the last, inclusive. The calculations forthe first and last grid points are performed in a separate boundary condition subroutine.The functionality of the Fortran 77 code is obvious from the example given above. In themessage-passing example, the vectors ibeg and lend represent the beginning and ending arrayindices assigned to each processor in the domain decomposition subroutine. In the case of 3the first processor, the value of ibeg is reset from a value of 1 to 2 in order to conform to thelimits on the DO loop in the Fortran 77 example. In a similar fashion, the value of iend isreset from Jmax to jmax-1.

In the message-passing example, when the calculation of the state variable s reachesthe last iteration in the loop on a particular processor, a value from the f array whichresides on a neighboring processor is required. For this calculation to be performed properly,

4

all processors except the first pass the first element of f on the processor to the adjacentprocessor on the left. This operation is initiated by the call to the subroutine passlft in theexample. The first argument in the call to the passleft subroutine is the name of the array tobe passed. The second argument is the number of elements to be passed between processors.If the caculation of s had used a f(j+'2,1) term, then all processors except the first wouldpass two elements of f to the left neighboring processor. For the the corrector step in theexplicit algorithm, an analogous passright subroutine is used in which all processors exceptthe last pass data from the specified array to the neighboring processor on the right.

To further illustrate the techniques employed in message-passing programming, thepassleft subroutine is listed below. This subroutine listing shows the process by which proces-sors pass the first n sub-array elements in their memory to their respective left neighboringprocessor. The receiving processors then store this data as the last n sub-array elements inmemory.

In studying the function of this subroutine, it is important to remember that the sub-routine runs simultaneously on all of the assigned processors. When the passleft subroutineis called, data from a particular flow parameter array are stored in a dummy array a. Thisdummy array, is a two-dimensional array with the first dimension assigned to be the numberof grid points, jmax, and the second dimension assigned as the number of variables per gridpoint for the array, in this case three (energy, density and momentum, for example). Thepassleft subroutine is designed to transfer all three of these variables for a given grid pointfor any particular call to the subroutine. The listing of the passleft subroutine shows thefollowing steps which are taken to transfer the data:

1. The send and receive indices for each processor are defined. These indices becomescounters in a DO loop if data from multiple grid points are to be transferred betweenprocessors.

2. All of the processors are synchronized in time so that the communication takes placesimultaneously on the processors.

3. On all processors except the first, the three variables for a given grid point of the dummyarray a are written into a temporary, three elemer't array b. The particular grid pointis defined by the send index.

4. All of the processors except the first send the contents of array b to the left neighboringprocessor.

5. All of the proccessors except the last receive the data sent from the right neighboringprocessor and store the data in the temporary, three elemenc array b.

6. On all of the processors except the last, the three variables stored in the b array arewritten into the dummy array a for the proper grid point. The particular grid point isdefined here by the receive index.

7. This process is repeated if data from more than one grid point is being transferred.

5

Listing of Passleft Subroutine

subroutine pausleft (a,n)c

c this subroutine passes the first a elements of sub-arrayc a from a processor to its left neighbor processor.c the receiving processor stores the data as the last nc elements of the sub-array a.c

include 'param.h:include 'mimd.h'

C

dimension a(jmax,3),b(3)C

c is a send index for local nodec ir a receive index for local nodec

is = ibeg(mynodeo+))-Iir a iend(mynode)+1)

c

do 10 kil,ni-is-+1ir=ir+l

call gsync()if (mynodeo.ne.0) then

do 20 j=1,3b(j) - a(is,j)

20 continuecall csend (O0b,3*4,mynodeO-1,mypidO)

endifif (mynodeG).ne.nuimnodesO-1) then

call crecv (0,b,3*4)do 30 j-1,3

a(ir,j) b(j)30 continue

endif10 continue

creturnend

6

4. Results

Whei the adaptation of the BRL-QlD code was completed, the performance of thecode was tested on both Gamma and Delta models of the iPSC/860 architecture. Dueto the nature of the hypercube topology of the iPSC/860 Gamma model, the number ofavailable processors is always an exact power of two. A Gamma model with 16 processorswas employed for these tests. The iPSC/860 Delta model, with its mesh topology, is notconstrained to the power of two processor requirement of the Gamma. The particular Deltamachine used for the tests has 532 processors. However, only 256 processors were used inthe maximum Delta configuration tests. So that Delta results could be directly comparedwith Gamma results, all Delta trials employed power of two processor configurations andproblem sizes.

In all cases, the measured performance of the BRL-QiD code was represented as the"whiz factor." This is a measure of the average CPU time required for the code to computea solution, divided by product of the number of grid points and the number of cycles inthe calculation (ps/grid point/cycle). This is a convenient method of measuring the code'sperformance because it normalizes the run time against the problem size and the number oftime steps in the calculations. Thus using the whiz factor as a benchmark, results of differentcalculations can be compared directly. For a particular processor configuration and problemsize, the reported performance is the minimum whiz factor (i.e., best performance) out of aset of several identical trials.

The first set of tests was performed to determine the influence of varying problem sizeon code performance. These tests were performed only on the Gamma model. The resultsof these tests are illustrated in Figure 1. This figure shows several curves illustrating therelationship between whiz factor and problem size for different processor configurations. Thisfigure shows that, for small problems, the performance of the iPSC/860 is highly dependenton the size of the problem. As the problem size is increased, all of the processor configurationsapproach an upper limit on performance (i.e., a minimum whiz factor). All of the curves inFigure 1 have a similar shape; an initially sharp drop in whiz factor as the problem size isincreased, followed by a bump in the middle of the curve, and ending with a leveling off as themaximum performance for that processor configuration is reached. The bump in the middleof each curve is a result of the increasing size of the problem filling the memory systems ofeach processor. The curve representing the trials with eight processors is slightly differentfrom the other curves at the data points corresponding to problem sizes of 2"0 and 211. Forthis processor configuration, the performance increased very little from a problem size of 2'to 210. Then, from 2"0 to 211 the performance increased significantly. In fact, the measuredperformance of the code on eight processors is exactly the same as the sixteen processorresult for the same problem size of 2"1. Several additional trials were performed here toveryify the result, and results were consistent. Thus this appears to be merely an interestingcharacteristic of the Gamma model, most likely resulting from a fortuitously optimum layoutof the data in memory for the particular configuration of eight processors running a problemsize of 211.

7

As previously discussed, the Delta model allows the user to access arbitrary numbers ofavailable processors. The Delta also allows users to define the two-dimensional layout of theprocessors within the mesh topology. With this in mind, a series of tests was performed todetermine the influence of processor layout on code performance. In this series, a problemsize of 16384 was run on 16 processors of the Delta. Five tests were performed in whichprocessor layouts of lx16, 2x8, 4x4, 8x2 and 16xl were employed. The results of these testsare provided in Table 1. Also included in this table is the result of the identical calculation onthe Gamma. These results illustrate that the performance of the BRL-QlD code on the Deltais independent of processor configuration. Thus it can be assumed that communication ofdata between processors is not heavily influenced by the proximity of any two communicatingprocessors.

Table 1. BRL-Q1D Performance on Delta as a Function of Processor Layout

Processor Whiz FactorLayout (ps/grid point/cycle)

1x16 7.752x8 7.794x4 8.428x2 7.7516xl 7.81

G _ma 2_ 4 9.00

As previously discussed, true scalability of both the architecture and the algorithm areessential to successful exploitation of MPP technology. Thus to determine the scalability ofthe BRL-Q1D code on the iPSC/860, a final series of tests was performed in which successivetests employed increasing numbers of processors. The problem size was accordingly increasedwith the increase iii processors, so that lines of constant problem size per processor could bedetermined. These tests were performed on both the Gamma and the Delta models and areillustrated in Figures 2 through 6.

The results shown in Figures 2 to 6 illustrate the scalability te.3ts of Gamma and Deltausing 512 grid points per processor. In these figures, the measured performance data pointsfor the Gamma are represented by the solid dots, while the data for the Delta is repre-sented by the star symbols. If the adapted BRL-Q1D algorithm were perfectly scalable onthe Gamma and Delta architectures, then doubling the number of processors used wouldresult in a factor of two decrease in the whiz factor (i.e., doubling the number of processorswould double the performance). The solid !ine in Figures 2 to 6 represents this ideal scala-bility which is extrapolated from the measured whiz factor for one processor of the Gamma.Accordingly, the dashed line represents the same ideal scalability relationship for the Delta.

Due to the logarithmic formulation of the scalability relationship, the ideal scalabilitycurves result in straight lines when plotted against log-log axes. Figures 2 to 6 show that thel;nes of ideal scalabilty for both Gamma and Delta pass through the scatter of the measureddata, indicating perfect scalability. These figures also illustrate that the performance of theDelta is slightly better than that of the Gamma for all cases. This improvement can be

8

attributed to advances in compiler technology and system software on the Delta, the laterof the Lwo architectures.

5. Conclusions

This report has outlined the successful implementation of the explicit, finite differenceBRL-QID algorithm on the Intel iPSC/860 parallel conmputer. A division of labor amongprocessors along with a coordinated use of message-passing between processors was usedto evenly distribute the algorithm across the resources of the architecture. The resultspresented in the figures lead us to conclude that this message-passing implementation of theBRL-Q1D code is indeed perfectly scalable on both hypercube and mesh processor topologyMIMD computers.

The likelihood of a successful implementation to parallel architectures is dependent or.the level of inherent parallelism ;n the algorithm. The explicit BRL-Q1D algorithm is inher-ently data parallel. Its inner DO loops typically span the entire computational mesh. As aresult, distribution of the algorithm across processors is easily accomplished.

As stated earlier, the adaptation of the BRL-Q1D code to the iPSC/860 was part of anattempt to evaluate MPP technology for blast modeling applications. The success of thisand other implementations of the code on MPP computers is an indication that significantperformance improvements can be obtained from the adaptation of large, multidimensionalfluid dynamics codes to MPP platforms.

Other types of codes, however, may not be good candidates for adaptation to parallelcomputers. When this is the case, it may be necessary to completely restructure the basicalgorithm in order to increase the level of inherent parallelism. Once this is done, thenthe algorithm can be adapted to parallel computers with greater likelihood of a successfulimplementation.

9

BRL-QID Performance

Intel IPSC/860 (y)

500

Number of Processors

0

" 400- - 2

-440

2008

8" - 16

300-

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2 2 2" 2" 2' 2" 2" 2" 2"'

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Figure 1. Measured Performance of BRL-Q1 D Code

BRL-O1D Scalability

Intel IPSC/86O with 512 Grid Points Per ilode

4) " 100-1A-

0

.. N.

• • -y Measured •NIdealt- -N• -

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Figure 2. Scalability Using 512 Grid Points / Node

10

BRL-QID Scolobility

Intel IPSC/860 wilh 1024 Grid Points Per Node

UN, 100-U

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References

1. Schraml, S.J. "A Data Parallel Implementation of the BRL-Q1D Code." TechnicalReport BRL-TR-3389. U.S. Airny Ballistic Research Laboratory, Aberdeen ProvingGround, Maryland. September 1992.

2. Intel Scientific Computers. "iPSC/860 User's Guide." Order Number 311532-001,Beaverton, Oregon. June 1990.

3. Intel Scientific Computers. "Parallel Programming Primer." Order Number 311914-001,Beaverton, Oregon. March 1990.

4. Beam, R.M., and R.F. Warming. "An Implicit Factored Scheme for the CompressibleNavier-Stokes Equatiors." AIAA&Journal, Vol. 16, No. 4. April 1978: 393-402.

5. MacCormack, R.W. "The Effect of Viscosity in Hypervelocity Impact Cratering." AIAAPaper, No. 69-354.

6. Opalka, K.O., and A. Mark. "The BRL-Q1D Code: A Tool for the Numerical Simula-tion of Flows in Shock Tubes with Variable Cross-Sectional Areas." Technical ReportBRL-TR-2763. U.S. Army Ballistic Research Laboratory, Aberdeen Proving Ground,Maryland. October 1986.

7. Hikida, S., R. Bell, and C. Needham. "The SHARC Codes: Documentation and SampleProblems." SSS-R-89-9878, S-CUBED, September 1988.

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14

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