area efficient low power fft design using vedic multiplier and csla

AREA EFFICIENT LOW POWER FFT DESIGN USING

CARRY SELECT ADDER AND VEDIC MULTIPLIER

By

ANAND.S

Reg. No. 212111419002

A PROJECT REPORT

PHASE II

Submitted to the

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

In partial fulfillment of the requirements

for the award of the degree

of

MASTER OF ENGINEERING

IN

VLSI DESIGN

SAKTHI MARIAMMAN ENGINEERING COLLEGE, THANDALAM-602 105

ANNA UNIVERSITY: CHENNAI 600 025

JULY- 2013

ii

BONAFIDE CERTIFICATE

Certified that this project report titled AREA EFFICIENT LOW POWER FFT

DESIGN USING CARRY SELECT ADDER AND VEDIC MULTIPLIER is the

bonafide work of Mr. ANAND.S who carried out the research under my supervision.

Certified further, that to the best of my knowledge the work reported herein does not form

part of any other project report or dissertation on the basis of which a degree or award was

conferred on an earlier occasion on this or any other candidate.

Supervisor Head of the Department

Ms. J. Sandhana Nirmala Kaviya M.E., Mrs. D. Lakshmi M.E.,Ph.D.,

Assistant Professor, Professor& HOD,

Department of ECE, Department of ECE,

Sakthi Mariamman Engineering College, Sakthi Mariamman Engineering College

Thandalam, Thandalam,

Chennai-602 105. Chennai-602 105.

Submitted to the Project Work Viva-Voice Examination held on……………………..

INTERNAL EXAMINER EXTERNAL EXAMINER

iii

குறந்த சக்தி நற்றும் குதி திறநனா சசர்க்க நற்றும்

பருக்கி உனர்ிற பசனல்தின் பசனிகள் அறநப்புகில் ஒரு

அடிப்றை சதறய இருந்தது. ஃாஸ்ட் ஃபூரினர்

.

ச ாடிகள் தி னன்டுத்தி நிதநா தாநதம், பரின

குதி நற்றும் உனர்ிற ஆற்ல் யமங்குகிது. சயதகாத்து பருக்கி

பருக்கல்கள் ஒரு மறநனா யடியில் சயகநா பருக்கல்கள்

பசனல்பறறன யமங்குகிது. இது சூத்திபங்கள்

னன்டுத்துகின்து. டிகள் எண்ணிக்றக இந்தப் பருக்கல்கள்

பறனில் குறகிது. அதால் சப, பப்பு நற்றும் தாநதம்

சான்றய குறக்கப்டுகின். சயதகாத்து பருக்கி நற்றும் CSLA

ஒரு ஃாஸ்ட் பூரினர் நாற்று யடியறநக்க னன்டுத்தப்டுகிது. இது

பயினடீ்றை ஒரு நிக சயகநா சபத்தில் தனாரித்தது தாநதம்

நற்றும் பப்பு குறக்கப்டுகிது. தி நற்றும்

உத்சதச திட்ைத்தில் டி தாழ் பகாண்டு நாற்ப்ட்டுள்து.

iv

ABSTRACT

Low power and area efficient adder and multiplier have always been a fundamental

requirement of high performance processors and systems. To design a Fast Fourier

Transform (FFT) its speed greatly depends on the multiplier and adder. Carry select adder

is one of the fast adders used in many processors to increase their speed with reduced size

and low power, reduced complexity. Carry Select Adder (CSLA) that uses multiple pairs

of Ripple Carry Adder (RCA) uses moderate delay, larger area and high power. Vedic

multiplier is an ancient form of multiplication which performs the multiplication operation

faster. It uses 16-sutras. The number of steps is reduced by this multiplication method. So

the time, area and delay are reduced. Vedic multiplier and carry select adder can be used to

design a Fast Fourier Transform (FFT) which produces an output at a very faster time and

the delay, area can be reduced. The CSLA used in the proposed replaces RCA and BEC by

D-Latch.

v

ACKNOWLEDGEMENT

First and foremost we thank GOD ALMIGHTY for his grace enabling us to

complete this work in time.

I am grateful to our beloved CHAIRMAN Thiru K.N. RAMACHANDRAN,M.A

for providing me all the facilities to complete my project.

I am happy to express my heartfelt thanks and gratitude to our beloved

PRINCIPAL Dr. S. RAMAKRISHNAN, for his complete encouragement and

motivation in successfully completing this project.

I like to express my sincere thanks to the HEAD OF THE DEPARTMENT

Prof. D. LAKSHMI, M.E., Ph.D, and to the INTERNAL GUIDE, Ms. J. SANDHANA

NIRMALA KAVIYA M.E., Department of Electronics and Communication Engineering

for her encouragement and guidance while developing my project.

And last but not the least we thank all OUR DEPARTMENT STAFF

MEMBERS who helped us a lot in completing this project.

Also, I express our great gratitude to OUR PARENTS AND THE FRIENDS for

their encouragement and kind help in all needs and deeds.

vi

TABLE OF CONTENTS

CHAPTER NO TITLE PAGE NO

iii

ABSTRACT iv LIST OF TABLES vii

LIST OF FIGURES viii

LIST OF ABBREVIATIONS ix

1 INTRODUCTION 1

1.1 Objective 2

1.2 Thesis organization 2

1.3 Tools Used 2

2 LITERATURE SURVEY 3

3 PROPOSED SYSTEM 8

3.1 System Explanation 8

3.2 Carry Select Adder with D-latch 9

3.3 Vedic Multiplier

3.3.1 Urdhva Tiryakbhayam Sutra 10

4 RESULTS AND DISCUSSIONS 19

5 CONCLUSION 33

REFERENCES 34

LIST OF PUBLICATION 35

vii

LIST OF TABLES

Table. No TABLES LIST Pg. No

4.1 Comparison Table of adder 27

4.2 Comparison table of multipliers 27

viii

LIST OF FIGURES

Fig. No FIGURES LIST Pg. No

3.1 Carry Select Adder 8

3.2 A large carry select Adder 9

3.3 32-bit non-linear carry select adder 9

3.4 Steps involved in UT sutra 11

3.5 Example of UT sutra 12

3.6 Carry Select Adder 17

3.7 A large CSLA 18

3.8 32-bit Non-linear CSLA 18

4.1 CSLA output 19

4.2 Vedic Multiplier output 20

4.3 FFT Output 21

4.4 RTL of CSLA with BEC 22

4.5 RTL of CSLA with D-Latch 23

4.6 RTL of Booth Multiplier 24

4.7 RTL of Vedic Multiplier 25

4.8 RTL of FFT 26

ix

LIST OF ABBREVIATIONS

FFT Fast Fourier Transform

DSP Digital Signal Processing

CSLA Carry Select Adder

RCA Ripple Carry Adder

SQRT Square RooT

BEC Binary to Excess Converter

RTL Register Transistor Logic

UT Urdhva Tirkabyam

1

CHAPTER 1

INTRODUCTION

The increase in the popularity of portable systems as well as the rapid growth of the

power density in integrated circuits have made power dissipation one of the important

design objectives, second thing area & performance. So here the carry select adder and

Vedic multiplier are modified for reducing the above factors. The Fast Fourier Transform

(FFT) is a computationally intensive digital signal processing (DSP) function widely used

in applications such as imaging, software-defined radio, wireless communication,

instrumentation and machine inspection. The choice of FFT sizes is decided by different

operation standards. It is desirable to make the FFT size changeable according to the

operation environment. Achieving a successful design means the system should be able to

support different operating modes required by diverse applications with low power

consumption requirement.

Based on the idea of sharing two adders used in the Carry Select Adder (CSLA), a

new design of a low-power high performance adder is presented. The new adder is faster

than a Ripple Carry Adder (RCA), which reduces the area, delay and power. In a typical

processor, Multiplication is one of the basic arithmetic operations and it requires

substantially more hardware resources and processing time than addition and subtraction.

In fact, 8.72% of all the instruction in typical processing units is multipliers. In computers,

a typical central processing unit devotes a considerable amount of processing time in

implementing arithmetic operations, particularly multiplication operations. In this paper,

comparative study of different multipliers is done for low power requirement and high

speed. The paper gives information of “Urdhva Tiryakbhyam” algorithm of Ancient Indian

Vedic Mathematics which is utilized for multiplication to improve the speed, area

parameters of multipliers. Vedic Mathematics also suggests one more formulae for

2

multiplication i.e. “Nikhilam Sutra” which can increase the speed of multiplier by reducing

the number of iterations.

1.1 OBJECTIVE

The main objective of this work is to reduce the power consumption, area and also

increasing the performance speed for adder & multiplier in FFT, so here some

modifications in FFT is that the normal full adder is replaced by carry select adder

(CSLA)and multiplier is replaced by Vedic multiplier. In this paper, we propose a

modified carry select adder and Vedic multiplier for FFT.

1.2 THESIS ORGANIZATION

The basic concept of adders and multiplication, to motivate creativity and

innovation has been discussed first of all, and then the focus has been brought to carry

select adder and Vedic multiplier. Chapter 2 the literature survey related to project work.

In Chapter 3 proposed systems is discussed with block diagram. Chapter 4 results and

discussions.

1.3 TOOLS USED

Software used: Xilinx ISE has been used for simulation.

Hardware used: Xilinx Spartan3E (Family).

3

CHAPTER 2

LITERATURE SURVEY

The adders are the most widely used components in such circuits; design of

efficient adder is of much concern for researchers. Addition usually impacts widely the

overall performance of digital systems and a crucial arithmetic function. In electronic

applications adders are most widely used. As we know millions of instructions per second

are performed in microprocessors. So, speed of operation is the most important constraint

to be considered while designing multipliers.

Carry Select Adder (CSLA) is one of the fastest adders used in many data-

processing processors to perform fast arithmetic functions. From the structure of the

CSLA, it is clear that there is scope for reducing the area and power consumption in the

CSLA. In the literature (Sreenivasulu 2012) uses a simple and efficient gate-level

modification to significantly reduce the area and power of the CSLA. Based on this

modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have

been developed and compared with the regular SQRT CSLA architecture. The proposed

design has reduced area and power as compared with the regular SQRT CSLA with only a

slight increase in the delay. This work evaluates the performance of the proposed designs

in terms of delay, area, power, and their products by hand with logical effort and through

custom design and layout in 0.18- m CMOS process technology. The results analysis

shows that the proposed CSLA structure is better than the regular SQRT CSLA.

4

Vedic Mathematics is the ancient methodology of Indian mathematics which has a

unique technique of calculations based on 16 Sutras (Formulae). A high speed complex

multiplier design (ASIC) using Vedic Mathematics is presented in literature (Gankhuyag

2008). The idea for designing the multiplier and adder subtractor unit is adopted from

ancient Indian mathematics "Vedas". On account of those formulas, the partial products

and sums are generated in one step which reduces the carry propagation from LSB to

MSB. The implementation of the Vedic mathematics and their application to the complex

multiplier ensure substantial reduction of propagation delay in comparison with DA based

architecture and parallel adder based implementation which are most commonly used

architectures. The functionality of these circuits was checked and performance parameters

like propagation delay and dynamic power consumption were calculated by spice spectre

using standard 90nm CMOS technology. The propagation delay of the resulting (16,

16)x(16, 16) complex multiplier is only 4ns and consume 6.5 mW power. This achieved

almost 25% improvement in speed from earlier reported complex multipliers, e.g. parallel

adder and DA based architectures.

Carry Select Adder (CSLA) is one of the fastest adders used in many data

processing processors to perform fast arithmetic functions. From the structure of the

CSLA, it is clear that there is scope for reducing the area and power consumption in the

CSLA. This work uses a simple and efficient gate-level modification to significantly reduce

the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-

root CSLA (SQRT CSLA) architecture have been developed and compared with the

regular SQRT CSLA architecture. The proposed design has reduced area and power as

compared with the regular SQRT CSLA with only a slight increase in the delay.Literature

(Behnam Amelifard 2005) evaluates the performance of the proposed designs in terms of

delay, area, power, and their products by hand with logical effort and through custom

design and layout in 0.18- m CMOS process technology. The results analysis shows that

the proposed CSLA structure is better than the regular SQRT CSLA.

Based on the idea in the literature (Behnam Amelifard 2005) sharing two adders

used in the Carry Select Adder (CSA), a new design of a low-power high performance

adder is presented. The new adder in the literature (Sreenivasulu 2012) is faster than a

5

Ripple Carry Adder (RCA), but slower than a CSA. On the other hand, its area and power

dissipation are smaller than those of a CSA. The proposed innovation for doing addition is

that instead of using two separate adders in CSA, one for the case CS1=1 and the other for

the case CS1=0 (CS1 is the carry propagated from the first partition to the second one), one

adder will be used to reduce the area and power dissipation. In this scheme, each of the two

additions is done in half of the clock cycle. To accomplish this sharing, some latches are

required. This adder is called Carry Select Adder with Sharing (CSAS).

The literature (Anvesh Kumar 2010) presents a design of efficient Digital Vedic

Multiplier using the Vedic sutras from ancient Indian Vedic mathematics. If we are looking

towards the signal processing, we will find multipliers and adders plays a very important

roll. In fact if we make our focus we can see speed of the Digital signal processing systems

is mainly dependent on multipliers and adders. A processor requires more hardware and

processing time during multiplication rather than addition and subtraction. In the literature

(Jai Skand 2012) there proposed a new digital Vedic multiplier structure based on a new

encoding algorithm. We found that this algorithm reduces the number of partial products

so reduces the adders. Thus multiplier is going to faster. In this paper we use Xilinx VHDL

module for simulation of Encoder.

A high speed processor depends greatly on the multiplier as it is one of the key

hardware blocks in most digital signal processing systems as well as in general processors.

Literature (Gankhuyag 2008) presents a high speed 8x8 bit Vedic multiplier architecture

which is quite different from the Conventional method of multiplication like add and shift.

The most significant aspect of the proposed method is that, the developed multiplier

architecture is based on Vertical and Crosswise structure of Ancient Indian Vedic

Mathematics. It generates all partial products and their sum in one step. This also gives

chances for modular design where smaller block can be used to design the bigger one. So

the design complexity gets reduced for inputs of larger no of bits and modularity gets

increased. The proposed Vedic multiplier is coded in VHDL (Very High Speed Integrated

Circuits Hardware Description Language), synthesized and simulated using EDA

(Electronic Design Automation) tool - XilinxISE12.1i. Finally the results are compared

with Conventional multipliers to show the significant improvement in its efficiency in

6

terms of path delay (speed). The high speed processor requires high speed multipliers and

the Vedic Multiplication technique is very much suitable for this purpose.

High speed and efficient multipliers are required in day today complex

computational circuits like digital signal processing, cryptography algorithms and high

speed processors. Among various methods of multiplication, recently [6]Vedic multipliers

are being more efficient. Literature (Ram Kumar 2012) presents a design of high speed

4X4 bit Vedic multiplier architectures based on two different Vedic sutras namely,

Urdhva-Triyag and Nikhilam. These sutras meant for faster mental calculation. Among

these two sutras Urdhva-Triyag is more efficient than Nikhilam and other multipliers with

respect to speed. The most significant aspect of Urdhva-Triyag sutra is that, the developed

multiplier generates all partial products in one step. In Nikhilam multiplier architecture

Urdhva-Triyag sutra is used for more efficiency. The Vedic multiplier architectures are

coded in Verilog HDL and synthesized using Xilinx ISE 13.3. The proposed multiplier

architectures are targeted to Spartan3E FPGA. Finally the results are compared with

conventional multipliers to show the efficiency in terms of speed.

Increasingly huge data sets and the need for low power in adders tend to increase.

The traditional serial adders are no longer suitable for large adders because of its huge area

and high power. All systems tend to trade-off between speed and power. The computation

time taken by the array multiplier is comparatively less because the partial products are

calculated independently in parallel. The delay associated with the array multiplier is the

time taken by the signals to propagate through the gates that form the multiplication array.

Large booth arrays are required for high speed multiplication and exponential operations

which in turn require large partial sum and partial carry registers. In the literature (Anvesh

Kumar 2010) the carry select adder designed only 64-bit and Vedic multiplier designed 16

– bit.

The basic idea of this literature (Sreeni vasulu 2012) is to use Binary to Excess-1

Converter (BEC) instead of RCA with cin=1 in the regular CSLA to achieve lower area

and power consumption. The main advantage of this BEC logic comes from the lesser

7

number of logic gates than the n-bit Full Adder (FA) structure. As stated above the main

idea of this work is to use BEC instead of the RCA with cin=1 in order to reduce the area

and power consumption of the regular CSLA. To replace the 4-bit RCA, an 4-bit BEC is

required.

Vedic mathematics is the name given to the ancient Indian system of mathematics

that was rediscovered in the early twentieth century from ancient Indian sculptures

(Vedas). It mainly deals with Vedic mathematical formulae and their application to various

branches of mathematics. The algorithms based on conventional mathematics can be

simplified and even optimized by the use of Vedic Sutras. These methods and ideas can be

directly applied to trigonometry, plain and spherical geometry, conics, calculus (both

differential and integral), and applied mathematics of various kinds. In the literature( Tam

Anh chu 2002) new multiplier and square architecture is proposed based on algorithm of

ancient Indian Vedic Mathematics, for low power and high speed applications. It is based

on generating all partial products and their sums in one step. The design implementation on

ALTERA Cyclone -II FPGA shows that the proposed Vedic multiplier and square are

faster than array multiplier and Booth multiplier.

8

CHAPTER 3

PROPOSED SYSTEM

3.1 SYSTEM EXPLANATION

Proposed system is to use both CSLA and BEC for a simple application to design a

single point FFT. FFT operation greatly depends on multiplier and adder. So the adder

selected here is Carry Select Adder and multiplier selected is vedic multiplier. This adder

and multiplier are proved as fast to provide their output at a high speed with less delay and

reduced power Consumption. This FFT is area efficient. Power consumed is less and

produces output fast with less delay. The use of Adder and multiplier can be seen in Fig

3.1.

Fig 3.1 BLOCK DIAGRAM

CSLA

VEDIC

MULTI SUB

Twiddle Factor

B Y

X A

9

3.2. CSLA USING D-LATCH

Fig 3.2 CSLA USING D-LATCH

Fig 3.3 D-Latch

10

Latches are used to store one bit information. Their outputs are constantly affected

by their inputs as long as the enable signal is asserted. In other words, when they are

enabled, their content changes immediately according to their inputs.

It has different five groups of different bit size RCA and D-Latch. Instead of using

two separate adders in the regular CSLA, in this method only one adder is used to reduce

the area, power consumption and delay. Each of the two additions is performed in one

clock cycle.

This is 16-bit adder in which least significant bit (LSB) adder is ripple carry adder,

which is 2 bit wide. The upper half of the adder i.e, most significant part is 14-bit wide

which works according to the clock. Whenever clock goes high addition for carry input

one is performed. When clock goes low then carry input is assumed as zero and sum is

stored in adder itself.

When the clock is low a2 and b2 are added with carry is equal to zero. Because of

low clock, the D-Latch is not enabled. When the clock is high, the addition is performed

with carry is equal to one. All the D-Latches are enabled and store the sum and carry for

carry is equal to one. According to the value of c1 whether it is 0 or 1, the multiplexer

selected the actual sum and carry.

3.3 VEDIC MULTIPLIER

3.3.1 Urdhva Tiryakbhyam Sutra

The given Vedic multiplier based on the Vedic multiplication formulae (Sutra).

This Sutra has been traditionally used for the multiplication of two numbers. In proposed

work, we will apply the same ideas to make the proposed work compatible with the digital

hardware. Urdhva Tiryakbhyam Sutra is a general multiplication formula applicable to all

cases of multiplication. It means “Vertically and crosswise”. The digits on the two ends of

the line are multiplied and the result is added with the previous carry. When there are more

11

lines in one step, all the results are added to the previous carry. The least significant digit

of the number thus obtained acts as one of the result digits and the rest act as the carry for

the next step. Initially the carry is taken to be as zero. The line diagram is for

multiplication of two 4-bit numbers.

Fig 3.4 Steps involved in Urdhva Tiryakbayam Sutra

For this multiplication scheme, let us consider the multiplication of two decimal

numbers (325 × 728). Line diagram for the multiplication is shown in Fig. 4. The digits on

the two ends of the line are multiplied and the result is added with the previous carry.

When there are more lines in one step, all the results are added to the previous carry. The

least significant digit of the number thus obtained acts as one of the result digits and the

rest act as the carry for the next step. Initially the carry is taken to be as zero.

Suppose we have to multiply 12 by 13

(i) We multiply the most significant digit 1 of multiplicand vertically by most

significant digit 1 of the multiplier, get their product 1 and set it down as the

most significant part of the answer

(ii) We then multiply 1 and 3, and 1 and 2 crosswise, add the two, get 5 as the

sum and set it down as the middle part of the answer and

12

We multiply 2 and 3 vertically, get 6 as their product and put it down as the last the

right hand most part of the answer. Thus 12 x 13 = 156. It bears a simple extendible form

in a similar way for multi-digit multiplication.

Step 1 Step 2 Step 3

1 3 Result = 6 1 3 Result = 5 1 3 Result =

1

Perv.Carry = 0 Perv.Carry = 0 Prev.Carry =

0

1 2 1 2 1 2

6 5 6 1 5 6

Fig 3.5 Example of Urdhva Tiryakbayam Sutra

For the multiplication algorithm, let us consider the multiplication of two 8 bit

binary numbers A7A6A5A4A3A2A1A0 and 7B6B5B4B3B2B1B0. As the result of this

multiplication would be more than 8 bits, we express it as R7R6R5R4R3R2R1R0. As in

the last case, the digits on the both sides of the line are multiplied and added with the carry

from the previous step. This generates one of the bits of the result and a carry. This carry is

added in the next step and hence the process goes on. If more than one line are there in one

step, all the results are added to the previous carry. In each step,Least significant bit acts as

the result bit and the other entire bits act as carry. For example, if in some intermediate

step, we will get 011, then1 will act as result bit and 01 as the carry. Thus we will get the

following expressions:

R0=A0B0

C1R1=A0B1+A1B0

6 5 1

13

C2R2=C1+A0B2+A2B0+A1B1

C3R3=C2+A3B0+A0B3+A1B2+A2B1

C4R4=C3+A4B0+A0B4+A3B1+A1B3+A2B2

C5R5=C4+A5B0+A0B5+A4B1+A1B4+A3B2+A2B3

C6R6=C5+A6B0+A0B6+A5B1+A1B5+A4B2+A2B4 +A3B3

C7R7=C6+A7B0+A0B7+A6B1+A1B6+A5B2+A2B5 +A4B3+A3B4

C8R8=C7+A7B1+A1B7+A6B2+A2B6+A5B3+A3B5+A4B4

C9R9=C8+A7B2+A2B7+A6B3+A3B6+A5B4 +A4B5

C10R10=C9+A7B3+A3B7+A6B4+A4B6+A5B5

C11R11=C10+A7B4+A4B7+A6B5+A5B6

C12R12=C11+A7B5+A5B7+A6B6

C13R13=C12+A7B6+A6B7

C14R14=C13+A7B7

C14R14R13R12R11R10R9R8R7R6R5R4R3R2R1R0

being the final product. Hence this is the general mathematical formula applicable to all

cases of multiplication. All the partial products are calculated in parallel and the delay

associated is mainly the time taken by the carry to propagate through the adders which

form the multiplication array. So, this is not an efficient algorithm for the multiplication of

large numbers as a lot of propagation delay will be involved in such cases. To overcome

this problem, Nikhilam Sutra will present an efficient method of multiplying two large

numbers.

Vedic mathematics is a gift given to this world by the ancient sages of India. This is

far simpler and more enjoyable than modern mathematics. The simplicity of Vedic

Mathematics means that calculations can be carried out mentally though the methods can

also be written down. There are many advantages in using a flexible, mental system. Pupils

can invent their own methods; they are not limited to one method. This leads to more

creative, interested and intelligent pupils. Vedic Mathematics refers to the technique of

Calculations based on a set of 16 Sutras, or aphorisms, as algorithms and their up a-sutras

14

or corollaries derived from these Sutras. Any mathematical problems (algebra, arithmetic,

geometry or trigonometry) solved mentally with these sutras. Vedic Mathematics is more

coherent than modern mathematics.

Vedic Mathematics offers a fresh and highly efficient approach to mathematics

covering a wide range - starts with elementary multiplication and concludes with a

relatively advanced topic, the solution of non-linear partial differential equations. But the

Vedic scheme is not simply a collection of rapid methods; it is a system, a unified

approach. Vedic Mathematics extensively exploits the properties of numbers in every

practical application.

VEDIC SUTRAS

The word „Vedic‟ is derived from the word “Veda‟ which means the store-house of

all knowledge. Vedic mathematics is mainly based on 16 Sutras (or aphorisms) dealing

with various branches of mathematics like arithmetic, algebra, geometry etc. These Sutras

along with their brief meanings are enlisted below alphabetically

1) (Anurupye) Shunyamanyat - If one is in ratio, the other is zero

2) Chalana-Kalanabyham - Differences and Similarities.

3) Ekadhikina Parvena - By one more than the previous one

4) Ekanyunena Purvena - By one less than the previous one

5) Gunakasamuchyah - The factors of the sum is equal to the

sum of the factors

6) Gunitasamuchyah - The product of the sum is equal to the sum of the

product

7) Nikhilam Navatashcaramam

Dashatah - All from 9 and the last from 10

8) Paraavartya Yojayet - Transpose and adjust.

9) Puranapuranabyham - By the completion or noncompletion

15

10) Sankalana-vyavakalanabhyam - By addition and by subtraction

11) Shesanyankena Charamena - The remainders by the last digit

12) Shunyam Saamyasamuccaye - When the sum is the same that sum is zero

13) Sopaantyadvayamantyam - The ultimate and twice the penultimate

14) Urdhva-tiryakbyham - Vertically and crosswise

15) Puranapuranabyham - By the completion or non-completion

16) Yaavadunam - Whatever the extent of its deficiency

ADVANTAGES OF VEDIC MATHEMATICS

It is very original, totally unconventional and provides a new thinking and

approach.

It encourages mental calculations. It is easy, simple, direct and straightforward.

Math‟s, a dreadful subject is converted into a playful and blissful subject, which we

keep on

Learning with smiles on the face and joy in the heart.

Vedic Maths enriches our knowledge and understanding of maths, which shows

clear links

Continuity between different branches of maths.

We are living in the age of competitions. Vedic Mathematics methods come to us

as a boon

For all competitions. Present maths requires much effort in learning. Vedic Maths

being most natural way of working can be learnt and mastered with very little

efforts and in a very short time.

Vedic Math‟s system also provides us with a set of checking procedures for

independent

Crosschecking of whatever we do. If you make the habit of applying the simple and

quick

Checks at different stages of working. We move on confidently, and keep on

smiling at

16

Every stage, after confirming the correctness of work.

The element of choice and flexibility at each stage keeps the mind lively and alert

and

Develops clarity of mind and intuition by integrated training of the two

hemispheres of brain and there by Holistic development of the human brain

automatically takes place through Vedic Mathematics multidimensional thinking.

CARRY-SELECT ADDER

The concept of the carry-select adder is to compute alternative results in parallel and

subsequently selecting the correct result with single or multiple stage hierarchical

techniques [8]. In order to enhance its speed performance, the carry-select adder increases

its area requirements. In carry-select adders both sum and carry bits are calculated for the

two alternatives: input carry “0” and “1”. Once the carry-in is delivered, the correct

computation is chosen (using a MUX) to produce the desired output. Therefore instead of

waiting for the carry-in to calculate the sum, the sum is correctly output as soon as the

carry-in gets there. The time taken to compute the sum is 18 then avoided which results in

a good improvement in speed.

Carry-select adders can be divided into equal or unequal sections.

17

Fig 3.6 Carry Select Adder

For each section, shown, the calculation of two sums is accomplished using two 4-

bit ripple-carry adders. One of these adders is fed with a 0 as carry-in whereas the other is

fed a 1. Then using a multiplexer, depending on the real carryout of the previous section,

the correct sum is chosen. Similarly, the carryout of the section is computed twice and

chosen depending of the carryout of the previous section. The concept can be expanded to

any length for example a 16-bits carry-select adder can be composed of four sections. Each

of these sections is composed of two 4-bits ripple-carry adders. This is referred as linear

expansion.

The delay of n-bit carry select adder based on an m-bit CLA blocks can be given by

the following Equation when using constant carry number blocks

T=tseup + m tcarry + (n/m) t tmux + t sum

And by the following equation when using successively incremented carry number

blocks respectively.

T=tseup + m tcarry + (2n) 1/2 t tmux + t sum

18

Fig 3.7 A large Carry select adder

Other method which gives more optimum results is to apportion the adder non-

linearly. For example to design a 32 bit Carry-Select Adder one can use 6 stages of adders

with sizes: 4, 4, 5, 6, 7, 6 = 32 bits. Each stage computes a partial sum; Ripple adders can

be used for stage adders. Fig. 14 below shows 32-bit carry select adder design.

Fig 3.8 32- bit non-linear carry select adder

19

CHAPTER-4

RESULTS AND DISCUSSIONS

Fig 4.1 shows the simulated output of a 16-bit carry select adder. For this carry

select adder the inputs are a, b, cin. A and b are 16 bit inputs, And cin is carry input to

select the carry. Inputs a=111111000011111, b= 1010010100100010, Intial input to the

cin= 0 so the output is 1010000101000001 with a cout of 1. Now that cout is given as

cin=1 to the next stage so that the output is 1010000101000010.

Fig 4.1 CSLA OUTPUT

Fig 4.2 shows the output of Vedic Multiplier. X and Y are two 16 bit inputs and clk

is the third input signal. P is the output of 32 bit. P1 is used as a register to store the initial

multiplied values and P2 is used as a register to store the successively generated carries

during each multiplication process. After completion of this both stages, the final output P

20

is predicted by P=P1 + P2. Input X= 1111111111111111, Y= 0000111100110011, clk is

assigned as leading from 1 and trails to 0 with a period of 100 ns.

P1=00001110110010101100110010001101 (multiplied output1)

P2=00000000011010000010010001000000 (generated carries)

P=00001111001100101111000011001101 (P1+P2)

Fig 4.2 VEDIC MULTIPLIER OUTPUT

21

Figure 4.3 shows the FFT output. Inputs are in1= 1111111111111111 and

in2=11110001111000000. The output out1=00000000000000011111000111011111(

in1+1*in2); 1 is the twiddle factor for basic 2- point FFT

out2=00000000000000000000111000011111(in1-in2).

Fig 4.3 FFT OUTPUT

22

Fig4.4. RTL schematic of CSLA with BEC (Existing)

23

Fig 4.5 RTL Schematic of CSLA with D-Latch (Proposed)

Comparing 4.4 and 4.5 its known that CSLA using D-Latch reduces the area used.

So BEC is replaced by D-latch for an efficient Carry Select adder.

24

Fig 4.6 RTL schematic of Booth Multiplier

25

Fig 4.7 RTL schematic of Vedic Multiplier

Comparing 4.6 and 4.7 its known that usage of vedic multiplier leads to the

reduction of gates.

26

With these results its sure that usage of Carry select Adder using D-latch and vedic

multiplier uses less number of gates. So there wil be decrease in delay with less power

consumption.

Fig 4.8 RTL Schematic of FFT

27

Existing

CSLA with BEC

Proposed

CSLA with D-Latch

Gate count = 60

Cell usage = 330

Delay = 24.97 ns

Gate count = 40

Cell usage = 256

Delay = 11.894 ns

Table 4.1 Adder Comparison

Existing

Booth Multiplier

Proposed

Vedic Multiplier

Gate count = 1978

Cell usage = 7548

Delay = 30.485 ns

Gate count = 750

Cell usage = 2030

Delay = 18.817 ns

Table 4.2 Multiplier Comparison

28

SYNTHESIS REPORT

1. FOR CARRY SELECT ADDER USING BEC CONVERTER

HDL Synthesis Report

# Xors : 30

1-bit xor2 : 14

1-bit xor3 : 16

Design Statistics:

# IOs : 50

Cell Usage:

# BELS : 63

# LUT2 : 6

# LUT3 : 24

# LUT4 : 21

# MUXF5 : 6

# IO Buffers : 50

# IBUF : 33

# OBUF : 17

Maximum combinational path delay: 24.970ns

2. FOR CARRY SELECT ADDER USING D-LATCH

Macro Statistics

# Adders/Subtractors : 4

3-bit adder : 1

4-bit adder : 1

5-bit adder : 1

6-bit adder : 1

# Xors : 16

1-bit xor3 : 16

29

Advanced HDL Synthesis Report

Macro Statistics


3-bit adder : 1

4-bit adder : 1

5-bit adder : 1

6-bit adder : 1

# Xors : 16

1-bit xor3 : 16

Design Statistics

# IOs : 50

Cell Usage :

# BELS : 53

# LUT2 : 5

# LUT3 : 23

# LUT4 : 21

# MUXF5 : 3

# VCC : 1

# IO Buffers : 50

# IBUF : 33

# OBUF : 17


3. FOR BOOTH MULTIPLIER

HDL Synthesis Report

Macro Statistics

# Multiplexers : 32

17-bit 4-to-1 multiplexer : 4


30

# Xors : 957

1-bit xor2 : 513

1-bit xor3 : 444


Macro Statistics

# Multiplexers : 32



# Xors : 957

1-bit xor2 : 513

1-bit xor3 : 444

Design Statistics

# IOs : 130

Cell Usage :

# BELS : 3646

# GND : 1

# INV : 4

# LUT2 : 72

# LUT3 : 878

# LUT4 : 2214

# MUXF5 : 476

# VCC : 1

# IO Buffers : 128

# IBUF : 64

# OBUF : 64


31

4. FOR VEDIC MULTIPLIER


Macro Statistics


1-bit adder carry out : 194

2-bit adder : 33


3-bit adder : 13


32-bit adder : 1

4-bit adder : 14


# Registers : 32

Flip-Flops : 32

Final Register Report

Macro Statistics

# Registers : 32

Flip-Flops : 32

Design Statistics

# IOs : 65

Cell Usage :

# BELS : 918

# GND : 1

# LUT2 : 60

# LUT3 : 112

# LUT4 : 638

# MUXCY : 27

# MUXF5 : 52

32

# XORCY : 28

# FlipFlops/Latches : 32

# FD : 32

# Clock Buffers : 1

# BUFGP : 1

# IO Buffers : 64

# IBUF : 32

# OBUF : 32

Minimum input arrival time before clock: 18.817ns

33

CHAPTER-5

CONCLUSION

Fast Fourier Transform (FFT) is a combination of Adder and Multiplier. General 16

bit SQRT CSLA is a combination of two pairs of RCA and a MUX. This configuration

produces output with a great delay and uses large number of gates which occupies a larger

area. BEC is replaced with D-latch in order to reduce its delay with the reduction of power

and area. This is modified SQRT CSLA. The next part of FFT is to use a multiplier to

multiply the twiddle factor component with the input values. The multiplier operation

performed to be fast. The speed of multiplier component is increased by vedic multiplier.

The modified CSLA with vedic multiplier output is of less delay, less number of gates lead

to reduction of area and the power consumed is less. This is simple and efficient for VLSI

hardware implementation. In the future this operation can be done for various bits of

higher order and the sutras used for multiplier can be different.

34

REFERENCES

1. Anvesh kumar, Ashish Raman and Sarin Arun Khosla R.K. (2010) „Small Area

Reconfigurable FFT Design by Vedic Mathematics‟, in Proc IEEE

ICAAE‟10,Singapoure, vol 5,pp. 836-838,.

2. Behnam Amelifard, Farzan Fallah and Massoud Pedram (2005) „Closing the gap

between carry select adder and ripple carry adder: a new class of low-power high-

performance adders‟, in Proc. of IEEE International Symposium on Quality

Electronic Design (ISQED).

3. Gankhuyag G., Chan Mo Kim and Yong Beom Cho (2008) „Multiplier Design

based on ancient Indian Vedic Mathematics‟, in SOC Design Conference,

Volume 2.

4. Jai Skand, Priya Keerthu and Deepthi Shakti (2012) „An Efficient Design of Vedic

Multiplier using New Encoding Scheme‟, International Journal on Computer

Applications,Vol-53,No.11.

5. Ramkumar B. and Kittur H.M. (2012) „Low Power and Area Efiicient Carry Select

Adder‟, IEEE transactions on VLSI systems, Vol 20, No.2.

6. Saha P., Banerjee A., Bhattacharyya P. and Dandapat A. (2011) „High Speed ASIC

Design of Complex Multiplier Using Vedic Mathematics‟, Proceedings of the IEEE

students technology symposium.

7. Sreeni vasulu P., Srinivasa Rao K. and Vinay Babu A. (2012) „Energy And Area

Efficient Carry Select Adder on a Reconfigurable Hardware‟, International Journal

of Engineering Research and Application, Vol 2, Issue 2.

8. Tam Anh Chu (2002) „Booth Multiplier with Low Power High Performance Input

Circuitry‟, US Patent, 6.393.454 B1.

35

LIST OF PUBLICATION

1. Anand S. and Sandhana Nirmala Kaviya J. (2013) „AREA EFFICIENT LOW

POWER FFT DESIGN USING CARRY SELECT ADDER AND VEDIC

MULTIPLIER‟, Second International Conference on Computing and

Communication Technology (ICCCT‟13).

area efficient low power fft design using vedic multiplier and csla

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