architecture of datapath-oriented coarse-grain logic and routing for fpgas
DESCRIPTION
Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs. Andy Ye, Jonathan Rose, David Lewis Department of Electrical and Computer Engineering University of Toronto {yeandy, jayar, lewis}@eecg.utoronto.ca. Outline. Motivation Datapath regularity An datapath-oriented FPGA - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/1.jpg)
1
Architecture of Datapath-oriented Coarse-grain Logic
and Routing for FPGAs
Andy Ye, Jonathan Rose, David Lewis
Department of Electrical and Computer Engineering University of Toronto
{yeandy, jayar, lewis}@eecg.utoronto.ca
![Page 2: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/2.jpg)
2
Outline
• Motivation– Datapath regularity
• An datapath-oriented FPGA– Architecture
– CAD flow
• Experimental results– Area efficiency
• Conclusion
![Page 3: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/3.jpg)
3
Modern FPGAs
• Very large logic capacities– Over 10 million equivalent logic gates
• Increasingly used to implement large and complex applications– Central processing units
– Graphics accelerators
– Digital signal processors
– Packet switching networks
![Page 4: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/4.jpg)
4
Datapath Circuits
• Large applications– Contain a greater amount of datapath circuits
• Datapath circuits – Consist of multiple identical logic structures
called bit-slices• Regularity
• Predictability
![Page 5: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/5.jpg)
5
An Example
FullAdder
FullAdder
FullAdder
FullAdder
A0 A1 A2 A3B0 B1 B2 B3
C0 C1 C2 C3
Carry In
CarryOut
![Page 6: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/6.jpg)
6
An Example
![Page 7: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/7.jpg)
7
Research Goal
• Design a new FPGA architecture– Utilize datapath regularity
• Reduce the implementation area of datapath circuits on FPGAs
• Implement a full set of CAD tools for the new architecture– Synthesis
– Packing
– Placement
– Routing
![Page 8: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/8.jpg)
8
Key Architectural Features
• A bus-oriented logic block architecture
• A mixture of coarse-grain tracks and fine-grain routing tracks
![Page 9: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/9.jpg)
9
Datapath FPGA Overview
L L
L L
S
L Logic Block
Coarse grain routing tracksFine grain routing tracks
S Switch Block
RoutingChannels
![Page 10: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/10.jpg)
10
Logic Block — Super-clusterBLEBLEBLEBLE
BLEBLEBLEBLE
BLEBLEBLEBLE
BLEBLEBLEBLE
Cluster 4Cluster 3Cluster 2Cluster 1
LocalRoutingNetwork
BLEBLEBLEBLE
A Cluster
MU
X
LUT
DFF
MA Basic Logic Element (BLE)
![Page 11: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/11.jpg)
11
Datapath FPGA Overview
L L
L L
S
L Super-cluster
Coarse grain routing tracksFine grain routing tracks
S Switch Block
RoutingChannels
![Page 12: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/12.jpg)
12
Coarse-grain Routing Tracks
Super-cluster
Cluster Cluster ClusterCluster
M
Sw
itch
Blo
ck
M
M
Coarse-grain Routing
M M M M
Fine-grain Routing
![Page 13: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/13.jpg)
13
• CAD flow for the datapath-oriented FPGA consists of– Synthesis– Packing– Placement– Routing
• Conventional CAD flow– Minimize area and delay metrics– Destroy datapath regularity
CAD Flow
![Page 14: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/14.jpg)
14
Datapath-oriented CAD Flow
• Preserve datapath regularity (bit-sliced structures)
• Map the preserved regularity onto the datapath-oriented FPGA architecture
• Maximize the utilization of coarse-grain routing tracks– Minimize the implementation area of datapath
structures
![Page 15: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/15.jpg)
15
Datapath Representation
• Datapath circuits are represent by netlists of datapath components (VHDL or Verilog)
• Datapath component library– Multiplexers
– Adders/subtracters
– Shifters
– Comparators
– Registers
• Each component consists of identical bit-slices
![Page 16: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/16.jpg)
16
Synthesis
• Enhanced module compaction algorithm
• Based on the Synopsys FPGA compiler
• Augmented with several datapath-oriented features– Preserve datapath regularity by preserving bit-
slice boundaries
– Achieve as good area results as the conventional synthesis tools
![Page 17: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/17.jpg)
17
An Example Datapath Circuit
mux
+
c1
a1 b1
d1
s1
mux
+
c2
a2 b2
d2
s2
mux
+
c3
a3 b3
d3
s3
sel mux
+
c0
a0 b0
d0
s0
cin cout
![Page 18: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/18.jpg)
18
Synthesis
mux
c0
a0 b0
d0
s0
sel
cin
4-LUT
a0 b0 c0 sel
4-LUT
4-LUT
d0
s0
cin
+
![Page 19: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/19.jpg)
19
Synthesis
4-LUT
a2 b2 c2 sel
4-LUT
4-LUT
d2
s2
4-LUT
a1 b1 c1 sel
4-LUT
4-LUT
d1
s1
4-LUT
a0 b0 c0 sel
4-LUT
4-LUT
d0
s0
cin
4-LUT
a3 b3 c3 sel
4-LUT
4-LUT
d3
s3
cout
![Page 20: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/20.jpg)
20
Packing
• Based on the T-VPACK packing algorithm
• Pack adjacent bit-slices into super-clusters
• Utilize carry connections in super-clusters to minimize the delay of carry chains
![Page 21: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/21.jpg)
21
An Example
• Four clusters per super-cluster
• Two BLEs per cluster
• Six inputs per cluster
BLEBLE
BLEBLE
BLEBLE
BLEBLE
![Page 22: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/22.jpg)
22
Packing Into Clusters
4-LUT
a0 b0 c0 sel
4-LUT
4-LUT
d0
s0
cin BLE
a0 b0 c0 sel
d0
s0
cin
BLE
BLEBLE
BLE
BLEBLE
![Page 23: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/23.jpg)
23
Packing Into Super-clusters
BLEBLE
BLEBLE
BLEBLE
BLEBLE
BLEBLE
BLEBLE
BLEBLE
BLEBLE
a0 b0 c0 sel a2 b2 c2 sel a3 b3 c3 sel
d0 d1 d2 d3
s0 s1 s2 s3
cin
cout
a1 b1 c1 sel
![Page 24: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/24.jpg)
24
Placement
• Based on the VPR placer
• Use simulated annealing algorithm
• For super-clusters containing datapath circuits– Move super-clusters only
• For super-clusters containing non-datapath circuits- Move individual clusters
![Page 25: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/25.jpg)
25
Routing
• Based on the VPR router
• Use the path finder algorithm
• As much as possible– Route buses through coarse-grain routing tracks
– Route individual signals through fine-grain routing tracks
• When necessary– Use coarse-grain routing tracks for individual signals
– Use fine-grain routing tracks for buses
![Page 26: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/26.jpg)
26
Area Efficiency
• Benchmarks– 15 datapath circuits from the Pico-java processor
• Architectural assumptions– Four BLEs per cluster– Four clusters per super-cluster– Four coarse-grain tracks sharing configuration memory– Logic track length of two– Disjoint switch block topology
• Architectural variables– Number of coarse-grain tracks
![Page 27: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/27.jpg)
27
Area Efficiency
1.60
1.50
1.40
100.0%
95.0%
90.0%0% 0%-
10%10%-20%
20%-30%
30%-40%
40%-50%
50%-60%
60%-70%
circuit area in minimumtransistor area (x106)
normalizedcircuit area
% of coarse-grain tracks
![Page 28: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/28.jpg)
28
Logic Track Length Vs. Area
• Architectural assumptions– Four clusters per super-cluster– Four coarse-grain tracks share configuration
memory– 50% of tracks are coarse-grain tracks– Disjoint switch block topology
• Architectural variables– Number of BLEs per cluster– Logic track length
![Page 29: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/29.jpg)
29
Logic Track Length Vs. Area
1 2 4 8 16track length1.60
1.80
2.00
2.20
circuit area inminimum transistor area (x106) N = 2
N = 4
N = 8
N = 10
![Page 30: Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs](https://reader036.vdocuments.us/reader036/viewer/2022062409/56814e17550346895dbb7ed0/html5/thumbnails/30.jpg)
30
Conclusion
• Proposed a datapath-oriented FPGA architecture and its CAD tools
• Best area is achieved when – 40% - 50% of tracks are coarse-grain routing
tracks– Four BLEs per cluster– Logic track length of two
• Best area is 9.6% smaller than conventional FPGAs