Architectural Complexity: Opening the Black BoxMethods for Exposing Internal Functionality of Complex Single and Multiple Processor SystemsEECC-756

Modern Design TrendsLarger on-chip cachesExtended levels of cacheSystem-on-a-chip integrationOverall increasing design complexity

All lead to more complex debugging of designs

The Good NewsAutomated design tools are minimizing design errorsIP reuse minimizes bugsSimulation tools discover most logic errors before fabricationMassive test suites allow comprehensive testingSo what happened to Intel with FPU flaw?

Past Methods for DebuggingSignal probingBus monitoringSoftware debugging

Past Methods for Debugging (contd)Signal probingMore internal logic per pin = less info on pinPin inaccessibility due to modern packages (i.e. sockets, BGAs) Bus monitoringCaches hide data accessesSoftware debuggingImpractical for real-time applicationsLittle or no hardware support in the past

SolutionsTest Access Port (TAP)Uses JTAG IEEE1149.1 specification for boundary scanProbe ModeAllows step by step analysis of code impact on internal registersIn-circuit Emulation (ICE)Allows execution tracingReal-time applicability

Test Access Port (TAP)Implementation of boundary scan JTAG IEEE1149.1 specificationAllows access to all internal flip-flops in boundary scan chainNumerous chains serve different functions (i.e. IO flip-flops)Allows non-destructive snapshot of internal state at any point in time

Test Access Port (contd)Single instruction registerMultiple data registers (scan chains)

Probe ModeSpecial processor mode halts program executionUses the TAP interface to receive instructions and output internal dataAllows read/write access to any internal registersAllows memory accesses to test cache functionality

Probe Mode (contd)

In-Circuit Emulation (ICE) Support Special pins provide branching information

Example: Pentium Dual Pipeline3 dedicated pinsIU Asserted when instruction completes in the U instruction pipelineIV Asserted when instruction completes in the V instruction pipelineIBT (Instruction Branch Taken) Asserted when a branch is taken

In-Circuit Emulation (contd)Branch signal information provides realtime code tracingBranch trace message buffers provide further informationBranch trace message buffers in conjunction with Probe Mode allow detailed realtime code tracing

Branch Trace Message BuffersFIFO queueCan be read through TAP during program executionCircular mode (trace-back from breakpoint) vs. Jump-to-Probe Mode (maintain instruction stream)Incident counter expands buffer sizeIntel automatically generates a special BTM cycle on local bus to export BTM info

Branch Trace Buffer Logic Implementation

Multiprocessor IssuesThree methods for opening the black box on a single processor systemTAP (boundary scan)Probe ModeBranch Tracing Methods for ICE

Multiple processor system design also has challenges

Multiprocessor ChallengesRace conditions due to parallel data accessesInconsistent and unpredictable network pathsDiffering processor behaviors on heterogeneous networksCommunication patterns that restrict performance or scalability

Multiprocessor Solutions : Debugging CodeCreate sequential version of codeExecute parallel tasks on a single computer as separate processesVisualization tools that create space-time diagrams or animations to show 2-dimensional changes of stateUnified Trace Environment (IBM)

Multiprocessor Solutions : Debugging DesignsAbility to monitor communication packets circumvents most visibility problemsDebug messages can be included in packetNetwork protocol simulationsProtocol verification programs(i.e. petri-nets)Network communication pattern simulatorsHowever ...

Multiprocessor Design TrendsCurrently, uniprocessor designs are hitting roadblockslarge dies impractical signal transit timerouting increases exponentially with die size

One possible solution : multiple processors on a single die re-emergence of visibility problems

ConclusionSeveral methods available for internal execution tracing of uniprocessorsTest Access Port (JTAG IEEE1149.1)Probe Mode extensionBranch TracingDont count out TAP, Probe Mode, and ICE for multiprocessors

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