3 14 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 37. NO. I . JANUARY 1990

I I

I l l I I I I

-8 - 4 0 I 8 12 16

YG (U

Fig. 2. n-channel source-drain current per micrometer of channel width as a function of gate voltage for various silicon implant doses. Silicon films were deposited at 560°C and annealed at 650°C in steam for 28 h.

I I I I I I

’ -16 - 1 2 -8 - 4 0 +4 + 8

VG (v)

Fig. 3. p-channel source-drain current per micrometer of channel width as a function of gate voltage for various silicon implant doses. Silicon films were deposited at 560°C and annealed at 650°C in steam for 28 h.

111. DISCUSSION The results in Fig. 1 indicate that there is a peak in the MOS

field effect mobility for electron and holes as a function of implant dose. It was suggested by Iverson and Reif [2] that an implant dose of about 2 X 10’5/cm2 may be optimum for polysilicon grain growth because this dose may, in turn, optimize the number of nucleation centers remaining after implantation. Lower doses may

not remove a sufficient number of nucleation sites, while higher implant doses may amorphize too many of the nucleation sites. This theory may also be used to explain the observed peak in elec- tron field effect mobility which results as a function of LPCVD silicon deposition temperature [6]. It has been shown that electron mobilities reach a peak value at a deposition temperature of about 550°C. It may be that, for lower deposition temperatures, the film is amorphous or contains an insufficient number of nucleation sites while, for higher deposition temperatures, too many nucleation sites are present.

The mobility peak that we observe appears to contradict the re- cent data of Noguchi er al . (31, which indicate a constant mobility value for implant doses greater than about 1.5 X lOI5/cm2. Their results, however, indicate that for an implant dose of 5 X 10’5/cm2, a substantial time lag exists before crystallization begins. It may be that in our case, the 650°C anneal in steam for 28 h was not sufficient to fully crystallize the films implanted at doses greater than 2 X 10’5/cm2. The phenomenon of continually increasing grain growth with increasing silicon implant dose would, however, tend to contradict the theory of Iverson and Reif [2].

There is, at present, no explanation for the increase in leakage current with silicon implant dose observed in n-channel devices. Possible theories are the formation of donor states by the implanted silicon or donor contamination during the implant. Measurements of edgeless devices indicate the phenomenon is not an edge related problem. Measurements on thinner silicon films do not show this effect [3], indicating that it is not present in these thin films or that it is possible to deplete through the leakage layer in thin films.

REFERENCES

[l] R. B . Iverson and R. Reif, “Stochastic model for grain size versus dose in implanted and annealed polycrystalline silicon films on SiOz.” J . Appl. Phys. vol. 57, no. 12, pp. 5169-5175, June 1985.

[2] -, “Large spontaneous nucleation rate in implanted polycrystalline silicon films on SiO2,” Muter. Lett., vol. 5 , no. 10, pp. 393-395, Sept. 1987.

[3] T. Noguchi, H. Hayashi, and T. Ohshima, “Low temperature poly- silicon super-thin-film transistor (LSFT),” Japan J . Appl. Phys., vol. 25, no. 2, pp. L121-Ll23, Feb. 1986.

[4] -, “Advanced superthin polysilicon film obtained by Si implanta- tion and subsequent annealing,” J . Electrochem. Soc., vol. 134, no.

[5] A. C. Ipri, R. G. Stewart, G. Kaganowicz, B. Faughnan, and J . Va- lachovic, “A 600-650°C polysilicon CMOS process for fabricating fully scanned active-Matrix LCD’s, Proc. SID, vol. 29, no. 2, pp. 167-172, 1988.

[6] A. Mimura et a l . , “High performance low temperature poly-Si TFT’s fGr LCD,” in IEDM Tech. D i g . , Dec. 1987, pp. 436, 437.

7, pp. 1771-1777, July 1987.

Approximate Analytic Current-Voltage Calculations for MODFET’s

A. N. KHONDKER AND A. F. M. ANWAR

Abstract-We present two analytic techniques to calculate the cur- rent-voltage ( I -V) characteristics of modulation-doped field-effect

Manuscript received August 11, 1988; revised August 17, 1989. This work was supported in part by the National Science Foundation under Grant ECS-8808613. The review of this brief was arranged by Associate Editor S . 4 . Pei.

A. N. Khondker is with the Electrical and Computer Engineering De- partment, Clarkson University, Potsdam, NY 13676.

A. F. M. Anwar is with the Electrical and Systems Engineering De- partment, University of Connecticut, Storrs, CT 06269.

IEEE Log Number 8931656.

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IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 37. NO. I , JANUARY 1990 315

transistors (MODFET’s). The present methods are based on the Chang and Fetterman model. However, we have approximated the velocity- field dependence by a different empirical relation that was used to model Si MOSFET’s. The advantage of using this empirical relation is that it gives analytic expressions for the I-V characteristics and the micro- wave small signal parameters. Moreover, the theoretical results are in good agreement with the experimental results.

I. INTRODUCTION The recent literature on GaAs/AlGaAs structures includes a

number of papers that deal with the current-voltage characteristics ( I -V) of modulation-doped field-effect transistors (MODFET’s) [ 11-[7]. In these analytical models, several empirical relationships of the velocity-electric field ( u d - & ) dependence have been used to achieve a fit to the experimental I-V data [2], [3], [SI, 161. Cil and Tansal [5] used an expression suggested by Trofimenkoff [8], given as

where ud is the electron drift velocity and &, = U , ~ / P ~ , with po the low field mobility, vs the saturation velocity, and & the electric field. Chang and Fetterman [3], [6] used the following empirical formula, suggested by Giblin et al. [9]:

ud = us[ 1 - exp ( - & / & , ) I . (2 ) The I-V model derived by Chang and Fetterman is in good

agreement with experimental data. However, their model uses two functions C2 and C3 in the expression for saturation current and for the unity current gain frequency f,. These functions, for which there are no closed form solutions, are defined as follows [3]: C 2 ( z ) = 5: d t / t 2 In ( 1 - t ) and C3(z) = d t / t 3 In ( 1 - t ) for 0 < z < 1.

In this brief paper we use the following empirical relationship [lo]:

( 3 )

The present ud-& relationship compares well with that given by (2). However, the velocity described by (3) converges to the saturation velocity slowly when compared with that described by Giblin’s equation. For example, if Go represents the field at which Vd =

0.99vS, then from (3) and (2) we have GO = 7.02&, and lo = 4.6&,, respectively. This slow convergence has a minimal effect on the calculated I-V curve. as is shown later.

11. CALCULATION OF THE I-V CHARACTERISTICS Two analytic techniques are developed to calculate the I-V char-

acteristics and the microwave signal parameters of MODFET’s. The first method is in essence similar to the model proposed by Chang and Fetterman [3], [6]; however, the present model does not require any numerical integration procedure. The second ana- lytic method is approximate, and it provides a simple technique to calculate theoretical I-V characteristics.

11. EXACT TECHNIQUE In our derivation, we use the notations of Chang et al. [3], [6].

The charge control is given by the following equation [l 11:

€ 2 = - [ VG - V ( x ) - vm] 4d

(4)

where n, is the channel electron density, e 2 is the permittivity of AlGaAs, dd and d, are the thicknesses of the doped and undoped AlGaAs layer, Ad is the moment distance of the electrons from the heterointerface [2], V, and V ( x ) are the applied gate voltage and

the channel potential at any point x, respectively, and VTo is the threshold voltage given by [2], [3]

in which c$b is the Schottky barrier height between the metal and the AlGaAs layer, A E, is the conduction hand discontinuity, and N D is the doping density in the AlGaAs layer.

The current in the channel of a MODFET is given by IC = qn, ( x ) zud ( x ) , where Z is the gate width. Substituting (3) and (4) in the expression for IC gives

where Go = E2Zu,/d. After rearranging and integrating (6) from x = 0 to x = L , we get

where

which upon integration yields

Jl - 2 2 1 1 + J 1 - z 2 D 2 ( z ) = 7 - 5 In , O < z < l .

Z

Equations for microwave small signal parameters are listed in Table I. The expressions for IC,,,, , g,,,,,, CG, and fT are almost identical to those derived by Chang and Fetterman. However, the most attractive part of choosing the empirical ud-& relationship is that it replaces the two functions C 2 and C3 by two functions D2 and D3 ((10) and Table I), which have closed form solutions. Thus the present technique retains all the attractiveness of Chang and Fetterman’s model, but it simplifies the calculations by eliminating a numerical integration step. The I-V characteristics of MOD- FET’s can be easily calculated using (7). For drain current greater than a technique similar to that proposed by Grebene and Ghandi [12] for MESFET and used by Chang and Fetterman [6] is followed. Near saturation the gradual channel approximation (GCA) becomes invalid since the longitudinal component of the electric field is no longer negligible. Therefore, one has to solve a two-dimensional Poisson equation in a region where the GCA breaks down. Following the analysis of Chang and Fetterman [6], the channel region of length L is subdivided into two regions. In region L I the GCA is valid, whereas, in region L 2 a two-dimen- sional Poisson equation has to be solved.

The extent of the first region L, is calculated with the help of (7), which can be rewritten, considering that saturation has taken place, i.e., D 2 ( t L ) = 0 and tL = 1. Thus we have

L , = & D ( t ) vsGo Os .

In the second region, the longitudinal component of the electric field is not negligible, and the extent of the second region L 2 is written as

(13) 2d . - L2 = - S l n h ‘ x 7r

where A = ( 7r/2dEo) ( V , - V , + V , + I , ( l /Go - R,) ) . Using (12) and (13), the length of the channel, which is the summation

316 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 37, NO. I. JANUARY 1990

l . OE-3 t

F ( 2 ) = - 2 * + 3 3 - l

of Ll and L 2 , can now be written as

2d . -, L = L, + L, = ""'TD2(t0,) + -sinh X (14) vs Go

which yields the current-voltage characteristics beyond saturation. The actual drain current is then computed by including a parallel component due to the parasitic channel of resistance Rp. The final drain current expression then assumes the form [6], [13]: 1, = IC

111. APPROXIMATE METHOD In our method, the evaluation of D2 ( z ) and D, ( z ) clearly does

not require any numerical technique. However, one has to calculate the I-V characteristics by numerical techniques. The following method can be used instead of the numerical procedure at the ex- pense of only a few percent loss of accuracy. We suggest an em- pirical function D i ( z ) , which approximates the relationship be- tween D2 ( z ) and z :

+ v D / R P .

where a! = 1 / f l = 3 /2 . The relationship between z and D i ( z ) is given as

The function values of D 2 ( z ) and D i ( z ) are shown in Fig. 1. It can be seen that for z > 0.5, D i ( z ) approximates D 2 ( z ) quite reasonably. The slight difference in these two functions actually leads to only a few percent error in the calculations. This error is mainly due to a slight underestimation of the velocity of electrons for G < G,. However, this approximation can be used to achieve a much better computational simplicity. Thus, using (15) we can

- 0.0 0.5

2

! .o

Fig. 1. The functions D , ( z ) (solid line), D3 ( z ) (dot and dashed line), and D ; ( z ) (dashed line).

rewrite (12) as

and the magnitude of the drain voltage for a given value of drain current is given by

VD = (Vc - V m ) + IcRD - GO

(18) where 0 < IC < IC,sat. Note that IC = IC,sat when t , = 1. For IC > (17) can be rewritten as

VD = VG - Vm - 1, ( 1 /Go - RD)

+ 3 sinh ($ [ L - IC (y)']). (19) 80 Go

The theoretical I-V curves can be calculated in the following man- ner. For a given value of the gate voltage V,, can one calculate the value of I,,,,,. For a given drain current, less than and greater than I,,,,,, the drain voltage is then calculated using (18) and (19), re- spectively.

IV. RESULTS The theoretical I-V characteristics calculated using (7) and (14)

are compared with experimental results reported by Drummond et al. [2]. In Fig. 2, we present the calculated I-V characteristics. The parameters used in these calculations are shown in Table 11. The values of the parameters used in these calculations are shown in Table 11. The values of the parameters are the same as those used by Chang and Fetterman except for the value of R,. Chang and Fetterman used R, = 12 0. Our theoretical plots are in good agreement with data. We mention here that the present technique also had good agreement with the data reported by Morkoc [4].

In Fig. 3, we compare the theoretical I-V plot presented in Fig. 2 with the theoretical plots generated by using the approximate for- mulation. Note that the approximate equation slightly underesti- mates the current. However, it provides an excellent method to calculate the I-V characteristics.

V. CONCLUSIONS We have modified the analytical model derived by Chang and

Fetterman by using a new empirical vd-& relationship. We have

317 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 37. NO. I. JANUARY 1990

N~ = 1 0 1 8 ~ ~ - 3

po = 4300cm2 V-ls-l d d = 300 A

_ _ - - - 8.0

RD = 25R R, = 40000 62 = 12.2€”

0.0 0.5 1 .o 1.5

Fig. 2. Output I-V characteristics. The solid lines represent results ob- tained from exact theoretical analysis for VG = 0.2, 0.4, 0.6, and 0.74 V. The dashed lines represent experimental results as reported by Drum- mond er al. [2] for V , = 0.2, 0.4, 0.6, and 0.8 V , respectively [3]. The parameters used in this calculation are listed in Table 11.

0.0 0.5 1 .o 1.5

VDW) Fig. 3. Comparison of the theoretical plots using exact formulation (solid

lines) with the plots generated by approximation formulation (dashed lines). These curves are for VG = 0.2, 0.4, 0.6, and 0.74 V, respec- tively.

TABLE I1 PARAMETERS USED TO CALCULATE THEORETICAL I-V CURVES

R, = 150 En = 7.02&,

ACKNOWLEDGMENT We would like to acknowledge technical discussions on this sub-

with Dr. C. S . Chang.

REFERENCES

K. Park and K. D. Kwack, “A model for the current-voltage char- acteristics of MODFET’s,” IEEE Trans. Electron Devices, vol. ED- 33, no. 5 , pp. 673-676, 1986. T. J. Drummond, H. Morkoc, K. Lee, and M. S. Shur, “Model for modulation-doped field effect transistors,” IEEE Electron Device Lett., vol. EDL-3, pp. 338-341, 1982. C. S. Chang and H. R. Fetterman, “An analytical model for high- electron mobility transistors,” Solid-State Electron., vol. 30, no. 5 ,

H. Morkoc, “High-speed modulation-doped AlGaAs/GaAs field ef- fect transistors (MODFET’s): Analysis, fabrication, and perfor- mance,” Internal Rep., Dept. Electrical Eng. and Coordinated Sci. Lab., Univ. of Illinois, Urbana. C. Z. Cil and S. Tansal, “A new model for modulation-doped FET’s,” IEEE Electron Device Lett . , vol. EDL-6, no. 8, pp. 434- 436, 1985. C. S. Chang and H. R. Fetterman, “An analytic model for HEMT’s using new velocity-field dependence,” IEEE Trans. Electron De- vices, vol. ED-34, no. 7, pp. 1456-1462, 1987. H. Rohdin and P. Roblin, “A MODFET dc model with improved pinchoff and saturation characteristics,” IEEE Trans. Electron De- vices, vol. ED-33, no. 5 , pp. 664-672, 1986. F. N. Trofimenkoff, Proc. IEEE, vol. 53, p. 1765, 1965. R. A. Giblin, E. F. Scherer, and R. L. Wierich, “Computer simu- lation of instability and noise in high-power avalanche devices,” IEEE Trans. Electron Devices, vol. ED-20, pp. 404-418, 1973. S . Selberherr, Analysis and Simulation of Semiconductor Devices. New York: Springer-Verlag, 1984. D. Delagebeaudeuf and N. T. Linh, “Metal-(n)AlGaAs-GaAs two dimensional electron gas FET, IEEE Trans. Electron Devices, vol. ED-29, no. 6, pp. 955-960, 1982. A. B. Grebene and S. K. Ghandi, “General theory for pinched op- eration of the junction-gate FET,” Solid-State Electron., vol. 12, pp.

Y. M. Kim and P. Roblin, “Two-dimensional charge-control model for MODFET’s,” IEEE Trans. Electron Devices, vol. ED-33, no.

pp. 485-491, 1987.

573-589, 1969.

11, pp. 1644-1651, 1986.

A Simple Method for Separation of the Intrinsic and Peripheral Junction Capacitances in Bipolar

Transistors

MYUNGSUK .IO A N D DOROTHEA E. BURK

Abstract-A simple technique is presented for extracting the intrin- sic and peripheral capacitances from measurements on transistors which are fabricated in the same process but have different emitter areas. The accuracy of the technique is verified by simulations of junc- tion capacitance as a function of bias for individual transistors.

also presented an approximate method which simplifies calcula- tions for the I-Vcharacteristics of MODFET’s. The proposed tech- nique introduces three analytic functions, namely, D2 ( z ) , D, ( z ) , and D i ( z ) and shows excellent agreement with the experimental data presented in the literature.

Manuscript received May 2, 1989; revised August 18, 1989. This work was supported by the Semiconductor Research Corporation under Contract 88-SP-087. The review of this brief was arranged by Associate Editor T. H. Ning.

The authors are with the Department of Electrical Engineering, Univer- sity of Florida, Gainesville, FL 3261 1.

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