applied physics reviews—focused review negative bias …web.cecs.pdx.edu/~cgshirl/documents/2003...

JOURNAL OF APPLIED PHYSICS VOLUME 94, NUMBER 1 1 JULY 2003

APPLIED PHYSICS REVIEWS—FOCUSED REVIEW

Negative bias temperature instability: Road to cross in deep submicronsilicon semiconductor manufacturing

Dieter K. Schrodera)

Department of Electrical Engineering and Center for Low Power Electronics, Arizona State University,Tempe, Arizona 85287-5706

Jeff A. BabcockPDF Solutions, Inc., 101 West Renner Road, Suite 325, Richardson, Texas 75082

~Received 11 July 2002; accepted 17 February 2003!

We present an overview of negative bias temperature instability~NBTI! commonly observed inp-channel metal–oxide–semiconductor field-effect transistors when stressed with negative gatevoltages at elevated temperatures. We discuss the results of such stress on device and circuitperformance and review interface traps and oxide charges, their origin, present understanding, andchanges due to NBTI. Next we discuss the effects of varying parameters~hydrogen, deuterium,nitrogen, nitride, water, fluorine, boron, gate material, holes, temperature, electric field, and gatelength! on NBTI. We conclude with the present understanding of NBTI and its minimization.© 2003 American Institute of Physics.@DOI: 10.1063/1.1567461#

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TABLE OF CONTENTS

I. MOTIVATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1II. INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . 2III. INTERFACE TRAPPED CHARGE AND

FIXED OXIDE CHARGE. . . . . . . . . . . . . . . . . . . . 3A. Interface trapped charge. . . . . . . . . . . . . . . . . . . . 4

IV. NBTI TRAP GENERATION MODELS.. . . . . . . . 6A. Hydrogen models. . . . . . . . . . . . . . . . . . . . . . . . . 6B. NBTI chemical reacting species models. . . . . . . 7C. Fixed charge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

V. EFFECTS OF VARIOUS PROCESS/DEVICEPARAMETERS ON NBTI. . . . . . . . . . . . . . . . . . . . 9A. Hydrogen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9B. Deuterium. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9C. Nitrogen and nitrides. . . . . . . . . . . . . . . . . . . . . . 9D. Water. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1E. Fluorine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11F. Boron. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1G. Oxide damage. .. . . . . . . . . . . . . . . . . . . . . . . . . . 11H. Gate material. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11I. Gate precleans. . . . . . . . . . . . . . . . . . . . . . . . . . . 11J. Silicon starting material. . . . . . . . . . . . . . . . . . . . 12K. Holes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1L. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13M. Interconnects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14N. Mechanical stress. . . . . . . . . . . . . . . . . . . . . . . . . 14O. Oxide electric field. . . . . . . . . . . . . . . . . . . . . . . . 14P. Gate length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

a!Author to whom correspondence should be addressed; [email protected]

10021-8979/2003/94(1)/1/18/$20.00

Downloaded 22 May 2009 to 131.252.222.238. Redistribution subject to A

VI. NBTI MINIMIZATION . . . . . . . . . . . . . . . . . . . . . . 15VII. CONCLUSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

I. MOTIVATION

For more then 30 years the semiconductor industrywitnessed exceptional growth and achievements in integrcircuit ~IC! manufacturing. In the last 10 years, this growhas outpaced Moore’s Law,1 causing numerous modificationof the SIA roadmap to ensure leading edge semicondumanufacturing remains on target for high performance pructs and integration of system-on-a-chip~SOC! where bothanalog and digital signal processing can occur. In spitesome claims that the industry will hit a ‘‘red brick’’ wall athe 100 nm technology node just 4 years ago,2 leading edgeresearch and development is now working on developingnm technology for release to manufacturing within the n1–3 years. Of course, at some point, semiconductor scawill approach its final limits3 and silicon semiconductomanufacturing will become more of a commodity marke4

The key determining factor in approaching the endpointscaling of complementary metal–oxide–semiconduc~CMOS! in semiconductor manufactuarable environmewill ultimately be in the economics and not in the physics5,6

However, statistical physics and the physics of understandhow complex systems interact will become increasingly iportant especially as we enter the era of megascale intetion and SOC IC production. This is especially true for vaance and defect interactions that become magnified winvestigating the electrical output characteristics as devgeometry shrinks.7

Today, we are truly in a global market where manyour day-to-day applications and interactions require interfil:

© 2003 American Institute of Physics

IP license or copyright; see http://jap.aip.org/jap/copyright.jsp

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2 J. Appl. Phys., Vol. 94, No. 1, 1 July 2003 Appl. Phys. Rev.: D. K. Schroder and J. A. Babcock

ing with integrated circuits and the millions of transistocontained in these building blocks. To the average consuthe dynamics of these ICs are transparent while the expetion for increasing functionality with unquestioned accuraand quality drive the industry to new heights. This resultsa tremendous driving force to continue to scale technologno matter what roadblocks may be encountered. As semiductor manufacturing migrates to more advanced desubmicron technologies,8 we are facing a new barrage ochallenges to overcome for the next generation of SOCIC products.9,10 The bulk of these challenges arise duetheir impact on product yield, product reliability, chitestability/performance prediction, and understanding hprocess integration and design layout interact. Someamples of key areas now affecting semiconductor manuturing include negative bias temperature instability~NBTI!,gate oxide leakage current, power consumption, testingcomplex product, interaction of layout on chip yield, eBased on these issues, within the next 5 years the semiductor industry is poised for a paradigm shift pointMoore’s Law and technology scaling if yield and perfomance prediction of complex circuits such as SOC areaddressed. The pressure to maintain the roadmaps outabove will continue to increase, but without addressing thsecondary issues, multibillion dollar fabrication facilitiemay not be able to deliver competitive products. Secondsigners are now under extensive economic pressure totheir designs work the first time. Several factors are leadto this paradigm shift but the strongest ones include cosgenerating mask sets, which can now approach a mildollars and higher, time-to-market pressure, and wafer cThis is exacerbated by the fact that the cost of fabricatwafers and that IC processing typically requires wafers toprocessed in wafer lots containing 25 wafers. State-of-thevolume manufacturing can achieve 1.5 d per level of pcessing, which translates to best in the world full flow cyctimes of 37.5 d.11 If failures or yield issues are detected, thtypically occurs after wafers have been processed, whmeans that time delays for implementing process fixesimpact many wafers in the line. Because of these multiplyeffects and considering a typical high volume wafer fab wthroughput capacity for 25 000 wafers/month,12 mistakes orlow yielding products can result in severe economic conquences to a manufacturer. The ability to address these iswill make the difference between having a highly profitabproduct versus an uncompetitive high loss product.pointed out, multi-redesign of product or technology nodare no longer available options. This pressure will be eworse as we go to 300 mm wafers.

In this article, we address the issue of NBTI with firstreview of the present day understanding of the mechanigoverning NBTI, second, the process interactions affecNBTI, and finally a review of some potential solutionsminimized the impact of NBTI induced from the technologprocessing.

II. INTRODUCTION

NBTI occurs in p-channel MOS devices stressed winegative gate voltages at elevated temperatures. It mani


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itself as absolute drain currentI Dsat, and transconductancgm , decrease and absolute ‘‘off’’ currentI off , and thresholdvoltage VT increase. Typical stress temperatures lie in100– 250 °C range with oxide electric fields typically belo6 MV/cm, i.e., fields below those that lead to hot carrdegradation. Such fields and temperatures are typicallycountered during burn in, but are also approached in hiperformance ICs during routine operation. Figure 1 shothe trend in electric fields for CMOS circuits, showing thoxide electric fields of the magnitude to generate NBTI atypical in today’s circuits. Either negative gate voltageselevated temperatures can produce NBTI, but a strongerfaster effect is produced by their combined action. It occprimarily in p-channel MOSFETs with negative gate voltabias and appears to be negligible for positive gate voltand for either positive or negative gate voltages inn-channelMOSFETs.13 In MOS circuits, it occurs most commonly duing the ‘‘high’’ state ofp-channel MOSFETs inverter operation. It also leads to timing shifts and potential circuit failudue to increased spreads in signal arrival in logic circuAsymmetric degradation in timing paths can lead to nofunctionality of sensitive logic circuits and hence leadproduct field failures.

A fraction of NBTI degradation can be recovered bannealing at high temperatures if the NBTI stress voltagremoved. The electric field applied during anneal can plarole in the recovery of NBTI degradation. Positive bias aneals exhibit the largest recovery in device characteristic14

Although it has not been reported yet, however, based onhistorical results we expect this recovery to be unstablefor the original degradation to reappear soon after reappltion of the stress condition, assuming that hydrogen doesplay a reversible role under this condition.

Since NBTI occurs for negative gate voltages, it is pticularly detrimental forp-MOSFETs with eitherp1 or n1

poly-Si gates. However, recent data suggest that burchannel~BC! p-MOSFETs are significantly less susceptibto NBTI.15 The improved reliability in buried-channel compared to surface-channel devices is attributed to the natureduced oxide field for the same gate voltage due to the w

FIG. 1. Oxide electric field as a function of time for CMOS circuits.


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3J. Appl. Phys., Vol. 94, No. 1, 1 July 2003 Appl. Phys. Rev.: D. K. Schroder and J. A. Babcock

function difference ofn1 gates compared top1 gates and noboron diffusion from then1 gate. Also, the effective oxide ithicker in buried- than in surface-channel devices.16 Thustheir use can improve NBTI and 1/f noise, though sufferingfrom worse short-channel effects and difficulty in manufaturing due to variance control issues. Currently the majoof digital CMOS technology requires surface channelvices, with this trend continuing into the future. Scalingtechnology results in a significant increase in the susceptity to NBTI degradation. Hence it may ultimately limit device lifetime, since NBTI is more severe than hot carrstress for thin oxides at low electric fields.

Many advanced CMOS technologies now offer dual-multigate oxide processes, with thicker gate oxidesanalog-sensitive circuits, while logic performance optimiztion requires thin and medium thick gate oxides. Becathese thicker gate oxides typically have lower nitrogen incporation near the Si/SiO2 interface, these devices tend to bless susceptible to NBTI, but it is still a concern for its impact on analog mixed signal circuit applications, becauseVT

shifts are a major reliability concern. This is especiallyconcern in matching applications where circuit operatmay force matched transistors into asymmetrical bias cotions resulting in a significant asymmetric stress inducmismatch.17 If the mismatch exceeds circuit tolerancewhich can be as tight as 100 ppm, differences in operacharacteristics between devices for some high performadesign applications result in a failure or yield loss duriburn-in or worse yet in field operation. Analog design tecniques can circumvent some of these issues and minimasymmetric NBTI bias stress conditions, but this comesthe expense of design complexity and potential performatradeoffs such as power consumption, noise margins, orcreased chip area.18

Because digital circuits tend to dominate most ICs amost SOCs and the number of digital transistors appromillions of devices on a chip, NBTI-induced shifts have bcome a critical issue for most manufacturers. NBTI streinduced variances in digital device saturation drive curr(I Dsat), due to degradation inp-channel MOSFETI Dsat, leadto significant timing issues. If digital signals arrive at diffeent times, signal processing becomes corrupted andmately results in circuit failure. WithVT degradation, thegate overdrive (VG–VT) decreases, leading to reduced crent and frequency degradation of ring oscillators andduced standard random access memory noise margin.19 De-sign modifications can alleviate some of these problemthe expense of circuit complexity or performance degration. Of more ominous concern for future SOC designsthe potential for statistical variation of NBTI tails of the faiure time distribution that impact chip failures when millionof devices are present.20 The reason for concern is the proability of a circuit encountering lethal accelerated NBTI deradation in single devices increase as both devices are scand the number of devices on chip increases. Hence thepact of NBTI on yield is expected to increase as SOC coplexity and integration increase, even if design modificatioare used.


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NBTI has been known since the very early days of MOdevice development, having been observed as early1967.21 Deal named it Instability Number VI.22 Goetzbergeret al. at Bell Labs were one of the first groups to show dtailed characterization of negative bias, temperature stre23

They used metal gate devices on 100 nm oxides, stresse2106 V/cm at 300 °C and found an interface trap densityD it

peak in the lower half of the band gap. The higher the sting D it , the higher the final stress-inducedD it . For positivegate voltage, they noted a very smallD it increase.D it in-creased with gate voltage and with time with a time depdence of t0.25. D it (T5300 °C).D it (T5250 °C) andp-type substrates gave higherD it than n-type substratesEarly MOS devices containing oxides as the gate dielecexhibited NBTI. Migration to nitrided oxides aggravateNBTI coinciding with a shift from the research stage to tforefront by around 1999 shortly after nitrided oxides bcame the industry standard in advanced CMOS.

The interface trap density induced by NBTI increaswith decreasing oxide thickness, whereas the fixed oxcharge density induced by NBTI appears to have no thiness dependence. Thistox

21 dependence of interface-trap geeration implies that NBTI becomes more severe for ultratoxides. Furthermore, the NBTI-generated interface trapsfixed charges are likely to have an adverse effect onfnoise, which is believed to be closely related to thecharges. NBTI has also been reported for HfO2 high-kinsulators.24

Examples of NBTI degradation are shown in Fig. 2. Fure 2~a! shows the change of threshold voltage and chapumping current as a function of stress time.25 Charge pump-ing current is used to measure the increase in interfacedensity with degradation. Clearly, bothVT andI cp change bysimilar amounts, plainly indicating that interface traps acreated. Figure 2~b! shows similar behavior for thresholvoltage and transconductance change.26 Transconductance isrelated to mobility that is degraded during the stress.though such plots vary from researcher to researcher,general NBTI trends are embodied in these figures.

III. INTERFACE TRAPPED CHARGE AND FIXEDOXIDE CHARGE

Before discussing the published experimental dataproposed models of NBTI stress, it is useful to review sobasic MOSFET concepts such as threshold voltage, intertrapped charge and fixed oxide charge. Thep-channelMOSFET threshold voltage is given by

VT5VFB22fF2uQBu/Cox , ~1!

where fF5(kT/q)ln(ND /ni), uQBu5(4qKs«ofFND)1/2 andCox is the oxide capacitance per unit area. The other symbhave their usual meaning. The flatband voltage is given

VFB5fMS2Qf

Cox2

Qit~fs!

Cox, ~2!

where Qf is the fixed charge density andQit the interfacetrap density. We assume that neither substrate doping deND nor oxide thickness vary with NBTI stress. This may n


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be true if hydrogen in the silicon has deactivated some ofsubstrate doping atoms.27 Such activation can, of course alsoccur in the poly-Si gates. Boron–hydrogen pair formatoccurs typically in theT590– 130 °C temperature range.

The only parameters that can lead to threshold voltshifts are the fixed charge densityQf and the interfacetrapped charge densityQit . Qit in Eq. ~2! depends on thesurface potentialfs , because the occupancy of the interfatrapped charge is surface potential dependent. Positivecreases in either of these charge densities, leads to negthreshold voltage shifts. Since NBTI typically leads to negtive threshold voltage shifts, either or both of these chadensities are changed during NBTI stress.

The MOSFET saturation drain current and transcondtance in its simplest form are given by

I D5~W/2L !meffCox~VG2VT!2;~3!

gm5~W/L !meffCox~VG2VT!.

Two parameters leading toI D andgm degradation are threshold voltage and mobilitymeff changes. Threshold voltag

FIG. 2. ~a! Time-dependent threshold voltage and stress-induced chpumping current increase forp-MOSFETs. Data after Schlu¨nderet al. Ref.25; ~b! time-dependent threshold voltage and stress-induced transcontance increase. Data after Kimizukaet al. Ref. 26.


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changes are discussed above. Mobility changes come athrough interface trap generation, leading to additiosurface-related scattering. For saturation velocity dominadevices, it is the velocity that is degraded.

A. Interface trapped charge

Silicon is tetrahedrally bonded with each Si atom bondto four Si atoms in the wafer bulk. When the Si is oxidizethe bonding configuration at the surface is as shown in F3~a! and 3~b! with most Si atoms bonded to oxygen at thsurface. Some Si atoms bond to hydrogen. An interftrapped charge, often called interface trap, is an interftrivalent Si atom with an unsaturated~unpaired! valenceelectron at the SiO2 /Si interface. It is usually denoted by

Si3[Si". ~4!

The [ represents three complete bonds to other Si ato~the Si3) and the" represents the fourth, unpaired electrona dangling orbital~dangling bond!. Interface traps are alsoknown as Pb centers.28 Interface traps are designatedD it (cm22 eV21), Qit (C/cm2), andNit (cm22).

On ~111!-oriented wafers, thePb center is a Si3[Si"center, situated at the Si/SiO2 interface with its unbondedcentral-atom orbital perpendicular to the interface and aiminto a vacancy in the oxide immediately above it, as shoin Fig. 3~a!. On ~100! Si, the four tetrahedral Si-Si directionintersect the interface plane at the same angle. Two defenamedPb1 and Pb0 , have been detected by electron spresonance~ESR!, shown in Fig. 3~b!. The Pb1 center wasoriginally thought to be a Si atom backbonded to two sustrate Si atoms, with the third saturated bond attached tooxygen atom, designated as Si2O[Si".28 This identificationwas found to be incorrect, as the calculated energy levels

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FIG. 3. Structural model of the:~a! ~111! Si surface and~b! ~100! Si surface.


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FIG. 4. Band diagrams of the Si substrate of a p-channel MOS deviceshowing the occupancy of interfactraps and the various charge polaritiefor a p-substrate with~a! negative in-terface trap charge at flatband and~b!positive interface trap charge at invesion. Each of the small horizontal linerepresents an interface trap. It is eithoccupied by an electron~solid circle!or occupied by a hole~unoccupied byan electron!, shown by the lines.

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this defect do not agree with experiment.29 A recent calcula-tion suggests thePb1 center to be an asymmetrically oxdized dimer, with no first neighbor oxygen atoms.30 By 1999,it was unambiguously established that bothPb0 andPb1 arechemically identical to thePb center.31 However, there is acharge state difference between these two centers indicaPb0 is electrically active, while some authors believe thePb1

to be electrically inactive.32 The two different effects are thresult of strain relief in~100! silicon. The defects result fromthe naturally occurring mismatch induced stress inSiO2 /Si layer during oxide growth.

Pb0 centers result when strain relaxation occurs withdefect residing at~111! microfacets at the Si/SiO2 interface,while Pb1 centers result when strain relaxation occurs witdefect at~100! Si/SiO2 transition regions. Based on thesresults and the fact thatPb1 centers are believed to be eletrically inactive, defects resulting fromPb0 centers are considered the key culprits in creating interface traps in~100!silicon. It is worth mentioning that recent work indicatesPb1

centers to be electrically inactive at low temperaturesT577 K). However, at room temperature and higher thdefects contribute to the electrical activity of total interfatraps.33 Recent ESR measurements show thePb1 center to beelectrically active with two distinct, narrow peaks closemidgap in the silicon band gap.34 However,Pb1 centers aretypically generated at densities considerably lower thanPb0

centers, making them potentially less important.Interface traps are electrically active defects with an

ergy distribution throughout the Si band gap. They actgeneration/recombination centers and contribute to leakcurrent, low-frequency noise, and reduced mobility, drcurrent, and transconductance. Since electrons or holescupy interface traps, they also contribute to threshold voltshifts, given by

DVT52DQit~fs!

Cox, ~5!

wherefs is the surface potential. The surface potential dpendence of the occupancy of interface traps is illustrateFig. 4.

Interface traps at the SiO2 /Si interface are acceptor-likin the upper half and donor-like in the lower half of the bagap.35 This is in contrast to doping atoms, which are donoin the upper half and acceptors in the lower half of the bagap. Hence, as shown in Fig. 4~a!, at flatband, where electrons occupy states below the Fermi energy, the states in


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lower half of the band gap are neutral~designated by ‘‘0’’!,being occupied donor states. Those between mid gap andFermi energy are negatively charged~designated by ‘‘2 ’’ !,being occupied acceptor states and those aboveEF are neu-tral ~unoccupied acceptors!. For an invertedp-channel MOS-FET, shown in Fig. 4~b!, the fraction of interface traps between mid gap and the Fermi level is now unoccupdonors, leading to positively charged interface traps~desig-nated by ‘‘1 ’’ !. Hence interface traps inp-channel devicesin inversion arepositively charged, leading to negativethreshold voltage shifts.

Interface traps, beingacceptorsin the upper half of theband gap anddonors in the lower half, affectVT shifts inn-channel andp-channel MOSFETs differently. Figureshows ann channel in~a! andp channel in~b!. At flatband,the n channel haspositiveand thep channel hasnegativeinterface trap charge. At inversion,fs5u2fFu, then channelhas negativeand thep channel haspositive interface trapcharge. Since the fixed charge is positive, we have at insion: n channel: Qf2Qit , p channel: Qf1Qit , hence pchannel MOSFETs are more severely affected. This wclearly shown by Sinha and Smith where the threshold vage of MOS capacitors on~111! n-Si decreases by 1.5 Vwhile VT of ~111! p-Si decreases by only about 0.2 V.36

Negative bias stress generates donor states in the lowerof the band gap.19,37

Both interface trap and fixed charge densities of statethe-art devices are in the range of 1010 cm22 or lower. For aMOSFET with a 0.1mm31.0mm gate, i.e.,A51029 cm2,and Nf5Nit51010 cm22, there are only ten interface trapand ten fixed charges at the SiO2 /Si interface under the gateTwenty charges lead to a threshold voltage shift of

DVT52Qit1Qf

Cox

5220q

Kox«oAtox

521.6310219320

3.4531021331029 tox

529.23103tox . ~6!

For tox55 nm, this givesDVT'25 mV. Device failure issometimes defined asDVT5250 mV, corresponding toDNit5DNf51011 cm22, showing that a modest increase


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FIG. 5. Band diagrams of the Si substrate showing the occupancy of interface traps and the various charge polarities:~a! p substrate with positive interfacetrap charge at flatband and negative interface trap charge at inversion and~b! n substrate with negative interface trap charge at flatband and positive intetrap charge at inversion.

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Nit and Nf suffices to cause failure. Since NBTI-generatDNit and DNf are random in nature, suppose that inmatched analog circuit, one MOSFET experiencesDVT

'210 mV and the otherDVT'225 mV. This 15 mV mis-match in aVT520.3 V technology is a 5% mismatch. This a very significant mismatch, especially if one considhigh performance analog transistor pairs that can reqmismatch tolerances of 0.1%–0.01%. Of course designcan trade off area to improve mismatch, but at the expensadding capacitance and increasing chip area. Unfortunathere are no simple design solutions for some circuit buildblocks where the existence of asymmetric bias conditiwill induce NBTI asymmetric mismatch degradation. Theissues are also of importance for sensitive digital circuwhere such mismatch affects timing and edge triggeringhigh-performance digital circuits and adds to variancesready present in the process. These undesirable NBTI effcan potentially affect yield seriously.

Rauch shows that NBTI-induced mismatch shifts arecorrelated to the initial mismatch and that variances ofmismatch shifts add to the initial mismatch variations38

Threshold voltage shifts of only 20–40 mV increase theVT

sigma mismatch by.10%. MOSFET b mismatch wasfound to be relatively unimportant at low gate overdrive, bbecame important at higher overdrives.

IV. NBTI TRAP GENERATION MODELS

In this section we discuss two basic approaches for meling interface trap generation during NBTI processes. Tfirst models discuss trap creation via hydrogen interacdynamics. The second set of models describes more ge


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trap creation via chemical species interaction and diffusiThe exact model describing the NBTI physics remains somwhat elusive at this time. However, these models are content with a number of observations in NBTI degradation aare expected to form the building blocks for a more complunderstanding of NBTI physics.

A. Hydrogen models

A hydrogen terminated interface trap, shown in Fig. 3denoted by

Si3[SiH. ~7!

Since a definitive model of interface trap and fixed chacreation is yet to be developed, we describe the various mels that have been put forth. High electric fields can dissoate the silicon–hydrogen bond, according to the model

Si3[SiH→Si3[Si"1H0 ~8!

where H0 is a neutral interstitial hydrogen atom or atomhydrogen. Recent first-principles calculations show thatpositively charged hydrogen or proton H1 is the only stablecharge state of hydrogen at the interface and that H1 reactsdirectly with the SiH to form an interface trap, accordingthe reaction39

Si3[SiH1H1→Si3[Si"1H2. ~9!

This model uses the fact that the SiH complex~or passivateddangling bond chemical species! is polarized such that amore positive charge resides near the Si atom and a mnegative charge resides near the hydrogen atom. Mo


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positive H1 migrates towards the negatively charged dipregion of the SiH molecule. The H1 atom then reacts withthe H2 to form H2 leaving behind a positively charged Sdangling bond~or trapping center!. This is an appealingmechanism of the model since it is consistent with theorcal models that predict lower activation energies for hydgen dissociation from SiH when charged states exist.40 Inthis model, H2 can later dissociate to again act as a catato disrupt additional SiH bonds. This process, in theory, ccontinue so long as hydrogen is available and SiH bondsavailable to react.

Since it is the proton that disrupts the SiH complex aforms the interface trap, interface trap formation dependsthe oxide electric field that aids in the transport of the proto the SiO2 /Si interface. Radiation experiments have shothat the electric field must be directedtoward the Si sub-strate, for efficient interface trap formation to occur, if H1 iscreated or released in the bulk SiO2 .41 This is the typicalcondition during radiation experiments, where the elecfield is directed from the gate to the substrate. Suradiation-induced degradation affects bothn- andp-channelMOSFETs. This model is also consistent with the predictthat H0 is unstable in both Si and SiO2 .42 Although themodel has successfully explained radiation experimewhere ionizing radiation creates H1 in the oxide, it is incon-sistent with NBTI experiments. The model is inconsistewith H1 generated in the bulk oxide since a negative biasthe poly-Si gate causes the charged hydrogen to drift frthe Si/SiO2 interface at the channel. On the other hand,model is consistent if one assumes H1 can exist in the sili-con below the Si/SiO2 interface. At present this remains cotroversial since the literature claims H2 exists inn-type andH1 exists inp-type Si. Hence if true, hydrogen would agamove in the wrong direction for the applied fields, sinp-MOSFETs are fabricated inn wells. H2 does not make

FIG. 6. Schematic two-dimensional representation of the Si– SiO2 interface,showing~a! the [SiH defect,~b! how this defect may be electrically actvated during NBTI to form an interface trap, a fixed oxide charge, anhydroxyl group, and~c! the OH diffuses through the oxide. After Jeppsoand Svensson Ref. 45.


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intuitive sense since it would require two electrons circuling the proton. Hence H1 may still exist inn-type Si, but italters the material characteristics to appear similar to2

existing in this material. It has been shown that SiH disciation in n-type Si has lower activation energy thanp-type Si.43 As the carrier density increases, the interactiof SiH dissociation mechanisms is expected to increase. Tis consistent withp-MOSFETs showing more sensitivity tNBTI thann-MOSFETs.44 It is also consistent with the activation energy for hydrogen dissociation in SiH bonds belower in bulk Si than in SiO2 . Additional research will berequired to confirm or dismiss this hypothesis. However, tis the most consistent NBTI model.

A different model that is sometimes used to explaNBTI induced trap formation considers the interactionSiH with ‘‘hot holes’’ or holes near or at the Si/SiO2 inter-face. Dissociation involving holes is given by

Si3[SiH1h1→Si3[Si"1H1. ~10!

During NBTI stress, the proton is transportedfrom theSiO2 /Si interface by the electric field directed from substrato gate. Although this is still somewhat controversial, itconsistent with recent results indicating reverse substbias (VBS) accelerates NBTI mechanisms.25 This model isalso consistent with hydrogen dissociation from SiH havreduced activation energy as the free carrier denincreases.43 It is not clear if it is consistent with dissociatiodynamics inn-type Si ~free carriers being electrons! versuschannel inversion~free carriers being holes!.

B. NBTI chemical reacting species models

We briefly describe some of the models that have bproposed. One model assumes that species Y diffuses tointerface and creates an interface trap

Si3[SiH1Y→Si3[Si"1X, ~11!

whereY is unknown. Jeppson and Svensson were the firspropose a model of NBTI.45 They stressed MOS devicewith Al gates and 95 nm thick oxides at24 to 273106 V/cm. These devices had been annealed in formgas at 500 °C for 10 min. They find equal densities ofQit andQf formation during NBTI stress. TheD it density createdduring NBTI stress decreases slowly if the device remainthe stress temperature with grounded gate. They also fint0.25 dependence and propose the model in Fig. 6. The Hthe SiH bond reacts with the SiO2 lattice to form an OHgroup bonded to an oxide atom, leaving a trivalent Si at(Si0

1) in the oxide and one trivalent Sis at the Si surface. TheSi0

1 forms the fixed positive charge and the Sis forms theinterface trap. Their model forms the basis for models ssequently modified by others. They propose

a

Si3[SiH1O3[SiOSi[O3→Si3[Si"1O3[Si11O3[SiOH1e2

Y D it Qf X to Si. ~12!


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For the interstitial hydrogen attack model X is H2 and Y isH0.

C. Fixed charge

Fixed charges are designated asQf (C/cm2) andNf (cm22).46 The fixed charge is a charge near the SiO2 /Siinterface, contributing mainly to threshold voltage shift.Qf

is also a byproduct trivalent Si defect in the oxide, denoby

O3[Si1. ~13!

Similar to interface trap creation modeled as

Si3[SiH1h1→Si3[Si•1H1 ~14!

Qf generation can be modeled as

O3[SiH1h1→O3[Si11H0 ~15!

Both interface traps and fixed charges are generated fromdissociation of SiH bonds. ForQf this may take place at thinterface or in the oxide close to the interface. Ogawaet al.from NTT determined fixed oxide charge densities frocapacitance–voltage measurements and interface trap dties from conductance measurements of MOS capacito47

Based on these measurements, they formulated expresfor Nit andNf generation

DNit~Eox ,T,t,tox!5931024Eox1.5t0.25exp~20.2/kT!/tox

~16!

DNf~Eox ,T,t !5490Eox1.5t0.14exp~20.15/kT!, ~17!

where t is the time. They findDNf to be independent ooxide thickness, butDNit to be inversely proportional totox .This suggests that NBTI is worse for thinner oxides. Thisnot always observed, however, and is highly dependenthe process conditions. Their model is consistent with afusion model forNit formation.

Until this point we have considered that NBTI shifts dnot saturate as can be seen in Eqs.~16! and~17!. More recentresults indicate NBTI shifts tend to saturate over time, incating a reaction-limited mechanism. Under these conditioone would expect the total shift in device characteristisuch asDVT5 f (DNit ,DNot), to be limited by the totalamount of hydrogen available for breaking SiH bonds athe total number of potential trapping sites at the Si/S2interface and in the oxide. In this caseDVT is given by48

DVT~DNit ,DNf !5B1@12exp~2t/t1!#

1B2@12exp~2t/t2!#, ~18!

whereB1 andB2 can be related to Eqs.~16! and~17! andt1

andt2 are the reaction limiting time constants, related toforward and reverse reaction rates for trap formation vertrap passivation.

Equation~18! is based on the electrochemical reaction48

Si3[SiH1A1h1↔Si3[Si"1H1, ~19!

O3[SiH1A1h1↔O3[Si"1H1, ~20!

where A is a neutral water-related species at the SiO2 /Siinterface andh1 is a hole at the silicon surface. Durin


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NBTI stress, positive hydrogen ions are released frhydrogen-terminated silicon bonds. Some of the hydrogions diffuse from the interface into the oxide bulk whesome are trapped, causing a threshold voltage shift. Duthe early stress stage, reactions~19! and ~20! favor the gen-eration of interface states and positive hydrogen ions atinterface. The process is limited by the dissociation ratehydrogen terminated silicon bonds. However, after sostress time, the transport of hydrogen ions from the interfinto the oxide limits the process and the diffusion ratecontrolled by a gradually decreasing electric field at tSiO2 /Si interface due to positive charge trapping in the oide and increasing interface state density. As a result, furdiffusion of hydrogen ions is reduced andDVT is reducedand finally saturates.

Although mobile oxide charge usually results from ioncontamination due to sodium ions or other ions such as L1,K1, Ca11, and Mg11, there is strong evidence that H1 canalso readily exist for prolonged periods in oxides as mobcharge that can be cycled in the gate oxide.48,49 AlthoughNBTI has been concerned primarily with unidirectional deradation shifts inVT and I Dsat, the interaction of mobile H1

remains a concern that should be de-embedded from noversible stress induced effects. This is especially true incase where mobile charge induced shifts inp-MOS devicesare in the range of expected NBTI inducedVT shifts of20–30 mV.50

Before leaving this topic, we would like to point out thathere are some additional comments and concerns withgard to the NBTI degradation models as predicted by E~16! and ~17!. Although these equations remain as a fundmental building block for modeling and understanding NBin p-MOSFETs, deep submicron technologies may devisomewhat from these predictions.51 Deviations have beenobserved in the electric field dependence, the activationergies, and in the time evolution of interface and fixed trcreation. Depending on the gate oxide process and wheor not the oxide has received plasma-induced damage,NBTI oxide electric field exponent m (Eox

m ) lies in the rangeof 1.5<m<3.0. The activation energies (Ea) appear to be inthe range 0.15 eV<EA<0.325 eV and may even be modelewith some stretched exponents and distributions inEA

6sEA , depending on what dominates the reaction kinetand species involved, for example H2O, H1, SiH, SiN, SiO,SiF, etc.52 Regarding the time dependence, more recent dsuggest that interface and fixed charge are time evolvwith similar dependences oft0.25, although some deviationhave been observed it appears that the time dependencetor lies in the range of 0.2–0.3.

Because of the variance in activation energies amechanisms governing the reaction kinetics of NBTI degdation, it is critical to use statistical reliability models fopredicting IC performance, yield, and reliability.9 The impor-tance of this increases directly as the level of complexity athe number of devices on a chip increase. Accuracy andderstanding the deviation in the statistical distribution of fshifting devices versus slow shifting devices can meandifference between successful product introduction and enomic disaster. Currently, the statistically small sample si


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used in many investigations do not address these issueequately.

V. EFFECTS OF VARIOUS PROCESSÕDEVICEPARAMETERS ON NBTI

In this section we review process conditions that impNBTI sensitivity in advanced CMOS processing. Wherevpossible we provide references and interpret results andommendations for improving NBTI performance.

A. Hydrogen

Hydrogen is a most common impurity in MOS integrated circuits oxides, being incorporated into the oxide ding various phases of IC fabrication, e.g., nitride depositand forming gas anneal. Hydrogen has been found at ccentrations of 1019 cm23 in dry oxides and concentrations o1020 cm23 in steam oxides.53 The distribution is nonuniformwith a substantial pileup near the SiO2 /Si interface.54 Higherconcentrations can exist depending on processing and anconditions. Hydrogen can exist in its atomic state H0, asmolecular hydrogen H2, as positively charged hydrogen oproton H1, as part of the hydroxyl group OH, as hydroniumH3O1, or as hydroxide ions OH2. More recent literaturesuggests that H0 is unstable in both silicon and SiO2 and isnot expected to exist.42 As discussed earlier, hydrogen is blieved to be the main passivating species for Si dangbonds and plays a major role during NBTI stress, when Sbonds are depassivated forming interface traps. Hydroand its interaction with nitrogen in nitrided gate oxides aalso a concern. During NBTI stress, because of lower avation energy, mobile hydrogen ions are more likely to cobine with nitrogen in Si–N bonds rather then with Si–bonds and hence form positive fixed charge in nitridoxides.55

B. Deuterium

Deuterium has been shown to reduce NBTI. Deuteri~D!—a ‘‘heavy’’ variant of hydrogen—is a stable isotopehydrogen with a natural abundance of 0.015% containinproton as well as a neutron in its nucleus. Due to its heamass or giant isotope effect, SiD bonds are more resisthan SiH bonds to hot carrier stress as well as NBTI. NBdegradation with deuterium passivation generally exhibitparallel shift compared to hydrogen passivation with a silar t0.25 dependence. This is likely due to its slower diffusiocoefficient. Deuterium can be introduced early or late inthe device fabrication process. Its incorporation atoxide/Si interface by thermal annealing involves three pcesses:~i! deuterium must diffuse through the insulating laer~s!; ~ii ! it must passivate unpassivated interface traps;~iii ! it must replace the existing hydrogen in SiH bondMechanism~iii ! is believed to be the rate limiting process56

In addition to the differences in the expected arrival rof H and D, recent results indicate that deuterium desorpis not only governed by the isotope effect~a difference invibrational excitation of SiH versus SiD!, but also by theprobability of D recombination enhancement due toslower movement of D. This effect has been observed a


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factor of 10 increase in the capture cross section of D copared to H.57 Of course, this effect may be somewhat detmental if deuterium is breaking the SiH bond since itpossible that deuterium may remain longer at a SiH bondhence enhance the interface trap formation once nearmolecular complex. However, it is expected that this effecmore significant for desorption then for absorption. Basedthese results of slower deuterium diffusion and some mrecent work,58 it is also expected that D should help reduNBTI even further at lower electric fields. This potential beeficial effect is expected to be more important for normcircuit operation compared to the high fields used for accerated NBTI studies. Regardless of the final mechanisgoverning D2 physics, it is clear that D2 can significantlyreduce NBTI sensitivity. It is not clear yet, whether this improvement is enhanced at the low fields that are more typof actual circuits.

Deuterium passivation can be significantly improveddepassivating SiH bondsbefore deuterium anneal or withdeuterium-containing processes, e.g., D2 instead of H2 informing gas, deuterated silane SiD4 instead of SiH4 , anddeuterated ammonia ND3 instead of NH3. By annealing thedevices in a 10% deuterium ambient forming gas and pviding the devices with a deuterated barrier nitride film, itpossible to retain the SiD bonds even if later stages ofprocess use hydrogen-containing forming gas.59 The deuter-ated silicon nitride provides a deuterium reservoir and a brier to subsequent in-diffusion of hydrogen and outdiffusiof deuterium. Clarket al. at IBM verified the efficacy of thisprocess with hot carrier stress measurements.60 Liu et al.from United Microelectronics/Infineon/IBM61 and Kimizukaet al. from NEC/Bell Labs26 find deuterium to reduce NBTIHowever, there are some concerns when using early deption of deuterium rich layers in process integration, escially if the layer is subjected to high energy implants at lasteps in the process. Higher energy implants through derium rich layers risk activation and gamma ray productiincreases during processing.60,62

C. Nitrogen and nitrides

Nitrogen generally enhances NBTI. Nitrogen is commonly incorporated into gate oxides to reduce boron difsion in p-channel MOSFETs, improve hot carrier resistanand increase the dielectric constant. However, nitrogen teto degrade NBTI. Chaparalaet al.63 from National Semicon-ductor usedL50.4mm MOSFETs with tox56.8 nm atT585 and 150 °C. They measured hot carrier instability aNBTI and find that higher nitrogen concentration makNBTI worse with an activation energy ofEA50.84 eV.Kimizuka et al.64 from NEC used 0.18mm MOSFETs withtox52 – 4 nm. They measuredVT , gm , andI G and find moresevere NBTI forp-channel than forn-channel MOSFETs.Nitrided oxide made NBTI worse. Liuet al. found N2O ni-trided oxides, rapid thermal anneal nitric oxides, and remplasma nitrided~RPN! oxides, where the gate oxide is exposed to a high density of remote nitrogen discharge, andhad lower NBTI degradation than SiO2 .61 However, RPNoxides with higher nitrogen density exhibited worse NB


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than those oxides with lower nitrogen. Kimizukaet al. findnitrogen to degrade NBTI, with higher nitrogen content leaing to more severe degradation.64 Ichinoseet al. used Si3N4

deposition to form sidewalls and find the NBTI lifetimedepend on the SiH concentration in the nitride film.65 LowerSiH concentrations lead to longer NBTI lifetimes. Liuet al.from United Microelectronics compared NO-nitrided oxideRPN, N2O1RPN1NO, and reoxidized RPN.66 They findthe N2O1RPN1NO to give the best NBTI behavior interms of interface roughness, effective mobility, gate curreNBTI VT shift, and hot carrier degradation. They attributhis to low SiH bond densities due to the smooth SiO2 /Siinterface as a result of the NO anneal. Onoet al. also attrib-uted the better NBTI behavior to a smoother interface67

They achieved this through a hydrogen pretreatment ofwafer prior to oxidation, removing any chemical oxide. Rcent work from Chartered Semiconductor provides adtional support that decoupled plasma-nitrided oxid~DPNOs!, where a pure thermally grown oxide is exposeda high density decoupled nitrogen plasma source andsignificant NBTI improvement compared to rapid thermnitrided oxides~RTNOs!.68 Indeed, their results indicate thNBTI activation energy of DPNO oxides is 0.325 eV compared with 0.25 eV for RTNO oxides. This increase in acvation energy translates directly to significantly improvNBTI lifetimes in DPNO oxides although the time dependedegradation remains proportional tot0.25 for both DPNO andRTNO oxides, which indicates diffusion of a reaction specsuch as positively charged hydrogen is still a dominatmechanism for NBTI in these structures.

Imai and Ono used radical nitridation from electron cclotron resonance to increase the nitrogen concentrationthe gate/oxide interface in a 1.6 nm gate oxide, poly-Sgate technology.69 As shown in Fig. 7, the nitrogen must bcarefully controlled or it leads to excessive NBTI degradtion. That paper clearly illustrates the tradeoff between omizing for good NBTI lifetime and optimal device perfomance~gate leakage current, gate insulator boron penetraetc.!.

FIG. 7. NBTI lifetime as a function of nitrogen concentration in the oxytride film. After Imai and Ono, Ref. 69.


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D. Water

Water in the oxide enhances NBTI. Sasadaet al.70 fromSanyo stressed 11 nm oxide devices atT5200 °C, usingcharge pumping to determineD it . By covering various re-gions of the device with nitride, a barrier to water diffusiothey found that water vapor is the dominant degrader. Tactivation energy ofEA51 eV is consistent with water dif-fusion through oxide. Blatet al.71 carried out a series oexperiments growing 56 nm oxides on~111! oriented Si in‘‘dry,’’ ‘‘damp,’’ and ‘‘wet’’ environments. Dry oxides aregrown in dry oxygen. Damp oxides are formed by exposdry oxides to a postmetal anneal at 450 °C, driving the twater layer that forms on the oxide surface when the wafewithdrawn from the oxidation furnace, into the oxide. Oxdizing in the presence of water vapor forms wet oxides.D it

andQf increases are observed in damp and wet oxidesthe authors conclude that the diffusion species is waKimizuka et al. find wet H2– O2 grown oxide to exhibitworse NBTI than dry O2 grown oxides.26

Helms and Poindexter in their review paper on tSi/SiO2 system, propose water as the NBTI culprit.72 Sur-veying the pre-1994 literature, they conclude that H2O is themost likely—if unproven—depassivating reactant. H appeto be the less likely attacking reactant. The H2O model isshown in Fig. 8. In Fig. 8~a!, the prospective reactant H2O isnear the passivatedPb center and in~b! the electric field hasoriented it into its attack position. In~c!, the proton has beendislodged from the[SiH site and combined with the H2Omolecule to yield H3O1. Finally, in ~d!, the now positivelycharged H3O1 is pulled away by the electric field preventinany reverse reaction.

Ushioet al.73 from Hitachi did a first-principles molecular calculation to investigate hole-trapping reactions. Thdetermined the reaction energies of hole trapping by stracting the total molecular energy before hole trappinghole reaction energy from that after hole trapping. The boing configurations are shown in Fig. 9. Figure 9~a! shows thebonding configurations for an interface trap creation by HSiO2 . Figure 9~b! shows the bonding configurations for ainterface trap creation by H2O in SiO2 and Fig. 9~c! for aninterface trap creation by H2O in SiOxNy . Water has a lowerreaction energy than hydrogen. H2O reacts with O or N va-cancies by inserting OH into the vacancy and generatingatom to stabilize the hole-trapped state. The H atom cobines with the H of a nearby Si–H bond, creating an intface trap. The final products areD it , Qf , and H2. Theirconclusions: water-originated reaction has lower energythe Si/SiOxNy interface than at the Si/SiO2 interface, i.e.,NBTI is enhanced by water and by nitrogen incorporationthe oxide.

Water is often present on wafers from the contact andformation. When the wafers are etched and cleaned, theno problem getting water into the small holes mainly throucapillary action, the problem is getting water out of thholes. An N2 bake at 200 °C for.24 h is often used forgood contact and via resistances. Water and moisture motravel along interfaces. This potentially makes water a kissue in pattern or layout dependent NBTI shifts. As poin


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FIG. 8. Depassivation ofPb center byattack of H2O molecule under electricfield stress:~a! passivated, unstressecondition; ~b! orienting of H2O mol-ecule and attraction of holes (h) to theinterface by the electric field;~c! cap-ture of a hole and H atom from thePb

center, forming H3O1; and ~d! H3O1

removed from the reaction site by thelectric field, leaving an active interface trap. After Helms and PoindexteRef. 72.

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out several times throughout this article, this can lead toNBTI tails in the distribution of lifetimes if just a smalamount of water is present in some pattern dependent ltions within the die. Failure of a critical path device cacause yield loss during burn-in or field operation. Hence cmust be taken to minimize the presence of water during pcessing.

E. Fluorine

Fluorine reduces NBTI. Fluorine is known to have mabeneficial effects on MOS devices, improving hot carrier imunity, dielectric integrity, and NBTI. Hooket al. from IBMshow that fluorine reduces NBTI and the reduction increawith increasing implanted fluorine dose, as shown in F10.74 Liu et al. also observe an NBTI improvement.61 How-ever, these beneficial effects need to be weighed againstrimental effects such as enhanced boron diffusion in the goxide and higher junction leakage current in some devic

F. Boron

Boron enhances NBTI. Boron diffuses into the gate oide from the boron-doped gate and from the source/dimplants. NBTI should be gate-length dependent, if diffusfrom the source/drain regions is important. A significant liftime improvement is observed, as shown in Fig. 11, if bois kept out of the gate oxide. Boron penetration has bobserved to enhance fixed charge generation but to suppinterface trap generation. Reduced interface trap formatioattributed to the formation of Si–F bonds from the BF2 bo-ron implant. EnhancedQf has been attributed to increaseoxide defects due to boron in the oxide.75 As long as boronpenetration into the gate oxide can be prevented, the usBF2 implants compared to standard B implants can gainmost a 1 order of magnitude improvement in NBlifetimes.76


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G. Oxide damage

Oxide damage enhances NBTI. Damage in the oxiparticularly at the SiO2 /Si interface is detrimental for NBTI.For example, ion implantation creates defects at the interfthat subsequently lead to more severe NBTI. Several artireport higher NBTI degradation for higher initial interfactrap density. In fact, NBTI has been used to characteplasma-induced damage and was shown to be a good prtor of oxide susceptibility to plasma charging.77

H. Gate material

Blat et al. use evaporated Al gates.71 Gerardiet al.78 donot use gates at all, but use negative corona charge andserve Pb formation on ~111! Si. Most others use poly-Sgates. This implies that gate metal or poly-Si is not requiand NBTI appears to be independent of gate material.

I. Gate precleans

Although there are few publications on the interactiongate precleans with NBTI sensitivity, it is obvious that thstep can potentially impact NBTI performance. Gate pcleans are known to impact the gate oxide quality. Improcleans can leave contaminants or damage nucleationthat affect NBTI and 1/f noise. One of the more interestinreports for improving NBTI is to use hydrogen pretreatmeof the silicon surface before gate oxide growth.67 Unfortu-nately, the authors did not give details of their hydrogpretreatment technique. However, it is well know that hydgen binds to exposed silicon protecting it from oxidation afrom contaminants such as water and carbon.79 Hydrogenambient at high temperatures results in breaking up of naoxides and removal of contaminants and is used extensiin SiGe epitaxial technologies.80


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J. Silicon starting material

As we discussed earlier in the article, the type of silicstarting material orientation can have a direct impact

FIG. 9. ~a! Interface trap formation in Si/SiO2 with H ~9.19 eV!; ~b! inter-face trap formation in Si/SiO2 with H2O ~7.43 eV!; and ~c! interface trapformation in Si/SiOxNy with H2O ~5.82 eV!. After Ushioet al., in Ref. 73.

FIG. 10. Normalized NBTIVT shift as a function of fluorine dose. AfteHook et al., Ref. 74.


n

NBTI sensitivity. Typically ~100! silicon has been preferreover ~111! silicon due to fewerPb centers. Interestinglyhowever, recent results indicate improved device permance ofp-MOSFETs fabricated on~110! silicon wafers.Momoseet al. have observed a factor of 1.5–1.9 improvment in low field mobility and transconductance and simiimprovements in drive current of these devices~thoughn-MOSFETs showed less improvements!.81 Unfortunately,p-MOSFET NBTI sensitivity was much worse in~110! sili-con compared to~100!. This increased sensitivity was founto correlate with significantly increased 1/f noise. Transmis-sion electron microscope cross section indicated that surroughness may have played a role in the NBTI sensitivand hence it is speculated that it may be possible to ocome these issues with more careful gate oxidation methMore research will be required in order to quantify if~110!silicon can maintain betterp-MOSFET device characteristicsuch asI Dsat while minimizing NBTI and 1/f noise sensitiv-ity.

In addition to the starting material orientation, some pcessing steps can induce changes in the orientation ofposed surfaces, which may become more sensitive to NBLocal oxidation of silicon~LOCOS! oxides with too muchstress can change~100! Si to ~111! Si at the bird’s beak edgeand shallow trench isolation~STI! can change~100! Si to~110! Si at the trench edge. Both effects influence gate oxthickness, stress, and oxide charge. For curved surfacebird’s beak edges in LOCOS, or trench edges in STI, thcan be increased oxide charges. With shrinking devicemensions, these curved surfaces take up a higher percenof the transistor active area. Furthermore the local strainthese regions can alter the activation energy/dynamicsNBTI induced trap creation. We expect this to lead to pattdependent variation in circuit NBTI sensitivity and hencare must be taken for design and process interactions.

One intriguing method for getting around many of theissues is expected through the use of atomic oxidation mods. Saitoet al., have unambiguously demonstrated thatomic oxidation methods significantly improve interfa

FIG. 11. Device lifetime vs gate length with and without boron penetratiThe lifetime is defined as aVT5220 mV shift. The lifetimes were extrapolated from the temperature stress dependence. After Yamamotoet al.,Ref. 75.


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trap densities on~111! silicon, yielding an order of magnitude reduction inNit compared to conventional thermal oxidgrowth.82 They also demonstrated highly uniform oxidthickness including regions of oxide thickness growth at Sedges where~100! silicon surfaces change to~110! and~111!.

K. Holes

Why are holes required in NBTI? Blatet al. find noNBTI for n-channel MOSFETs and claim it is because thare no holes near the Si surface.71 This suggests that holeare required, but there is no clear equation that shows wholes do in the thermo–chemical reaction. Figures 8 anshow the role of holes qualitatively. This effect becomstronger for higher reverse body bias, which accelerates tmally generated holes towards the Si/SiO2 interface,25 thusincreasing NBTI sensitivity. On the other hand, circuits mnot see this accelerated condition sincen-well supply volt-ages are limited and hence ifVBS is increased, theVG poten-tial to the channel is decreased in the circuit, reducingoxide electric field. This inherent circuit bias constraint cpotentially offset the acceleratedVBS NBTI mechanisms. Ad-ditional work will be required to quantify the exact effecwith regard to realistic bias conditions encounteredp-MOSFETs, especially in dual- or multigate and multipVT devices.

L. Temperature

Higher temperature stress enhances NBTI. NBTI degdation is thermally activated@see Eqs.~16! and~17!# and,therefore, is sensitive to temperature. NBTI degrades mseverely the higher the temperature, as illustrated in Fig.As pointed out earlier, the activation energy of NBTI prcesses appears to be highly sensitive to the types of potereacting species and to the type of oxidation methods uThis sensitivity in activation energy is highly sensitive to ttemperature and variance in it will led to variance in tpredicted NBTI lifetime of different processes. High perfomance microprocessors and SOCs can have hot spotscircuit design leading to large temperature gradients acrochip. The net result is pattern dependent dispersion in

FIG. 12. Lifetime as a function of temperature. Nitridation done in NData after Kimizukaet al., Ref. 26.


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activation of NBTI processes and NBTI drift. If care is ntaken to understand these issues, timing degradation dedent paths can lead to accelerated circuit failures durburn-in or field operations. Detection of these failures mbecome difficult due to circuit complexity and hence leaderroneous data or output conditions.

Temperatures encountered during processing also plrole in the NBTI sensitivity. For example, it has been fouthat RTA processing and the ambient anneal environmenthave a significant effect on NBTI sensitivity, where NBTdepends strongly on the processing temperature and aning ambient.49 Oxygen ambient was found to worsen NBTwhile annealing in argon led to a reduction in NBTI sentivity. It is believed that the oxide growth temperature aannealing ambient can lead to changes in the oxide itsincluding the mechanical stress of the oxide, the composiof the oxide~silicon rich versus oxygen rich, the water cotent in the oxide, etc! and the total number of trapping centers and potential trapping centers that are passivatedSiH or SiD ~lower number of total traps leads to improveNBTI!.

Process temperatures should be limited to temperaless then 1100 °C.83 Although the effects of very high process temperatures have not been reported for nitridedoxides, it has been shown that temperatures at or abovevalue can lead to a significant generation of ‘‘nonreactivmobile hydrogen trapped in the gate oxide.83,84These resultsare also consistent with results that indicate N2O-grown ox-ides show significant reduction in charge-to-breakdo(QBD) when grown at higher temperature.85 This is in con-trast to pure oxides, which show increasedQDB with increas-ing oxide growth temperature up to approximately 1050 °

Another area effecting NBTI appears to be postmetazation anneal temperature and the forming gas annealperature. Resent results indicate that postmetallizationneals temperatures and FG anneals should be minimizetemperatures at or below 370 C to improve NBTI and iprove time-dependent dielectric breakdown~TDDB! in nar-row devices.86,87Finally, we point out that other anneals sucas the postsilicide anneal temperature, can impact the Nperformance and care must be taken to optimize all keyneals and the ambient of the anneals in a process.88

It was shown by Royet al. that it is beneficial to growthe gate oxide at a temperature above the SiO2 viscoelastictemperature.89 Growth stress incorporation in SiO2 is the re-sult of SiO2 viscosity decrease at high growth temperatuand its subsequent increase during cooling. A graded stture aids in stress relaxation, where a pre-grown oxide laprovides grading for the subsequent high-temperature olayer to grow below the pregrown seed SiO2 layer. This seedlayer acts as a sink for stress relaxation. With this procdesign, high-quality SiO2 interfacial layers, free from local-ized strain gradients, can be grown. They grew graded oxat typically 940– 1050 °C in a diluted oxidizing ambie~0.1% O! on a pregrown SiO2 layer, grown at 750– 800 °CThis pregrown oxide layer provides grading and stress reduring the cooling phase. Better than 33reduction in NBTIwas observed for the graded oxide when compared to c

.


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ventional oxides, attributed to the Si/SiO2 interfacial sub-structure and a reduced number of weak silicon–oxybond within the oxide layer.

Liu et al.measured the hydrogen redistribution in steagrown oxides by resonant nuclear reaction analysis.90 Theydid this for 25 nm thick oxides grown at 850 °C and alsooxides postoxidation annealed~POA! at T.1000 °C. Themeasurements showed that the POA sample had significalower hydrogen density, lowerD it , and lower Qf . AfterNBTI stress, the hydrogen density accumulated in anproximately 8 nm wide region near the SiO2 /Si interface,was significantly higher than the NBTI-inducedD it . POAclearly improved NBTI.

Bunyanet al. show that self heating in silicon on insulator ~SOI! MOSFETs can aggravate NBTI-induced flatbavoltage shifts and interface state density increases.91

M. Interconnects

Processing during backend-of-line~BEOL! metallizationappears to have a significant influence on NBTI sensitivData presented in joint work by Sony and Fujitsu87 indicatecopper metalization with typical dual damascene procesdegrades NBTI. The increased sensitivity of NBTI to coppmetalization was attributed to increased hydrogen presenboth the copper metalization and especially in the barmetal. Using TaN as the barrier metal compared to TiNimproved NBTI. These results are in contrast to earliersults, which indicated similar NBTI sensitivity in antennstructure obtained from Al metalization and from Cmetalization.92 The differences in these results may be duedifferences in the hydrogen or water content presentBEOL processing between the two fabrication facilities.

Clearly another area of significant importance withgard to NBTI and BEOL processing is the intermetal dieletric ~IMD !.87,93 Low-k IMD materials can introduce significant concentrations of water and hydrogen into the insulaMaterials of concern include spin on glass, SOD, plasenhanced chemical vapor deposition dielectrics, etc. Ascussed earlier, NBTI is strongly sensitive to H2O that canpenetrate the activep-MOSFET area in an IC. It has beefound that these low-k IMD materials may impose significant NBTI risk if hydrogen or water is present along wicatalytic anneals that appear to release and/or diffhydrogen/water to active regions ofp-MOSFETs causingsignificant NBTI degradation. Nitride liners may minimizthe impact of some of these issues but it is still possibleH/H2O to penetrate vias to the active devices and hencemust be taken to minimize the IMD from high levelsH/H2O.

The final area in BEOL processing to impact NBTI peformance is device antenna ratio and the potential for pladamage.93 Although forming gas anneals have been shownremove damage from unstressed devices, when stress ctions are applied, plasma damaged devices become sigcantly more sensitive to NBTI degradation with highly acelerated shifts in comparison to gate-protected structurestructures without antennas connected. Enhanced NBTIsitivity in p-MOSFET antenna connected structures has b


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found for both positive and negative plasma potentials94

Other than minimizing plasma-induced damage~PID! in pro-cessing equipment and through special gate protection stures, a simple method for immediate improvementthrough the use of conductive top films~CTFs! prior to usinghigh-density plasma for dielectric depositions. This has brecently demonstrated in a joint effort by Motorola and AMwhich clearly indicates that use of a thin undoped amorphsilicon CTF on top of the contact etch stop layer over silicresults in significantly reduced PID and significant improvment in NBTI lifetimes and improved electric fieldependences.95 The improvement in PID and NBTI performance was attributed not so much to the conducting abof the CTF but more to the photon absorption of this layfrom high energy photons generated in the plasma thatsuspected of damaging the gate oxide. The sensitivity ofeffect to antenna size remains somewhat unclear to us atpoint, but is expected to be related to asymmetric chageneration, electron/hole recombination times, and diffences in the barrier of the gate dielectric to electron aholes generated via the high energy PID photons.

N. Mechanical stress

Mechanical stress induced by either encapsulating fior by shallow trench proximity can have significant effecon the NBTI sensitivity of a device. Mechanical stress apears to interact with the amount of hydrogen and/or wapresent near the active regions of PMOS devices to caincreased NBTI sensitivity and even time-dependentelectric breakdown degradation.64,86,96Based on these resultit is important to minimize stress in IMD films and STI processing while also minimizing H/H2O content for improvingNBTI. Finally, although it has not been reported, we expthat IC packaging may become increasingly sensitiveNBTI degradation if the packaging material induces mchanical stress in encapsulated silicon chips, if stress isdeed a factor influencing NBTI. If true, this could becomeadditional concern for a SOC product that is destinedpackaged part burn-in, especially if significant amountsH/H2O remain in the IMDs of the IC chip. However, wagain point out this is speculation on our part and will rquire additional studies to verify if this is an issue.

O. Oxide electric field

Oxide electric field enhances NBTI. NBTI is very senstive to electric field as shown in Fig. 13 in terms of thapplied gate voltage for two different oxide thicknesses. Acording to Ogawaet al. the interface trap and fixed charggeneration show anEox

1.5 dependence.47 To determine the life-time dependence onEox , we write the oxide voltageVox as

VG5VFB1fs1Vox⇒Vox5VG2VFB2fs . ~21!

For thep1 poly-Si gate/n-substrate device,VFB'0.8 V andfs'2fF'20.6 V. The oxide electric field then becomes

Eox5Vox

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whereVG,0. Replotting the data of Fig. 13 in terms ofEox ,gives the plot in Fig. 14. The linear data on a semilog psuggest the lifetime expression

t5K exp~2Eox /E1!. ~23!

Fitting the data yields K52.331011 s and E1573105 V/cm for tox51.6 nm andK51.0731011 s and E1

55.73105 V/cm for tox52.9 nm.

P. Gate length

NBTI does not depend on lateral electric fields, unlihot carrier degradation, and should therefore not exhibitgate length dependence. Nevertheless, NBTI is sometienhanced with reduced gate length. It is not well understwhy that is the case. It may have to do with the closenesthe source and drain and the dielectric spacers to the achannel. As shown in Fig. 15, localized damage nearends of the channel and possible boron diffusion from souand drain into the gate oxide may play a role. Furthermolateral water diffusion into the gate oxide may be enhanfor shorter gate lengths. The threshold voltage shift depdence on gate length is shown in Fig. 16. For these dataMOSFET was totally or partially covered with silicon nitridto study the effect of water penetration. Clearly, the ‘‘

FIG. 13. Lifetime as a function of gate voltage. Data after Kimizukaet al.,Ref. 64.

FIG. 14. Lifetime as a function of oxide electric field.


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SiN’’ case allows the most water penetration and exhibitshighestVT shifts. On the other hand, if fluorine passivatioof interface traps is important, then shorter gate lengths mlead to reduced NBTI with reduced gate length, since F finit easier to diffuse to the SiO2 /Si interface. Although worseNBTI is most commonly associated with shorter channelvices, there are examples that show the opposite trend.97

VI. NBTI MINIMIZATION

To minimize NBTI, it appears to be necessary to hainitially low densities of electrically active defects at thSiO2 /Si interface and keep water out of the oxide. Duripoly-Si deposition, the water on the wafer surface is drivoff, leading to low water-containing oxides. The use ofsilicon nitride encapsulation layer has been found effectivekeeping water away from the active CMOS devices ahence improving NBTI performance.70 However, it is criticalto pattern the nitride film and optimize the geometry in ordto assure that hydrogen passivation of dangling bondsoccur while keeping the distance from the active region laenough to ensure that water cannot diffuse to the gate regAdditional studies have found that it is also importantminimize stress96 and hydrogen content,65 in these liner ni-trides covering the active PMOS devices. It appears to

FIG. 15. MOSFET cross section showing possible ‘‘leakage’’ pathsboron and water penetration into the gate oxide.

FIG. 16. Threshold voltage change as a function of gate length:~A! SiNall over the device and~B! SiN over gate only. Data from Sasadaet al.,Ref. 70.


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important to keep damage at the SiO2 /Si interface to a mini-mum during processing. The higher the initial interface trdensity, the worse is the subsequent NBTI. For examnitrogen introduction by ion implantation exhibits highNBTI than nitrogen introduction by nonimplanted means61

Plasma charging damage also degrades NBTI as showKrishnan et al. from Texas Instruments.92 This NBTI en-hancement with antenna structure was independent of mization, being observed in both dual damascene copperalization as well as traditional plasma etched aluminmetalization. The reason for this similarity is not understobut it is clear that antenna-charging effects are importanboth copper and aluminum technologies. Pagaduanet al.from Xilinx also show that plasma damage degrades NBTp-MOSFETs, but n-MOSFETs are not degraded.98 Thethreshold voltage degradation is consistent with their obvation that the rise time of the CMOS output signal, cotrolled by thep-MOSFET, is degraded. The fall time, controlled by then-MOSFET, is unchanged. It is believed thcharging damage results in higher interface trap densiAlthough these are passivated during subsequent ltemperature sintering, nevertheless, these higher initial Sdensities, lead to higher NBTI. Hence, this suggests thattial damage should be minimized, even if that damageannealed by postmetal annealing.

Deuterium is an effective way to improve both hot carier stress and NBTI. However, it is not trivial to get thdeuterium to the SiO2 /Si interface to form SiD bonds. If theMOSFET spacers consist of silicon nitride, deposited inpresence of hydrogen, most of the dangling bonds areready saturated with hydrogen and it is difficult to replathem with deuterium. Hence, the process needs to be altto ensure deuterium can get to the SiO2 /Si interface andpassivate dangling bonds or replace the hydrogen in exisSiH bonds with deuterium.

Nitrogen incorporation has given conflicting resulSome authors claim an NBTI improvement, while others oserve degradation. Degradation is more commonly obserNitrogen concentration plays a key role in NBTI sensitivespecially if it is located near the Si/SiO2 interface. Optimi-zation of the nitrogen profile in the gate oxide can signcantly improve NBTI sensitivity. Another key method to improve NBTI sensitivity is through the use of remote plasnitridation of N2O-grown oxides61,66 and DPNO oxides. Ni-trogen at the oxide/Si interface reduces the activatenergy.99 The higher the nitrogen concentration, the lowthe activation energy and bothQf and Qit exhibit the sameactivation energy. The location of the nitrogen is also imptant. The closer the nitrogen is to the oxide/Si interface,worse is NBTI.100

The method and chemistry of oxide growth appearshave significant effects on NBTI. It has been shown thatoxidation atmosphere has significant influence on NBwith wet oxides showing worse NBTI degradation then doxides. Fluorine, however, does lead to an improvemenhas also been clearly demonstrated that F implants or Fcentration in the gate oxides can significantly improve NBand 1/f noise performance.74 However, care must be takewhen using blanket F implants since detrimental effects


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be enhanced such as boron penetration orn-MOS perfor-mance degradation. Boron degrades NBTI.

As described earlier, the oxide electric field plays a snificant role in NBTI sensitivity. Buried channel devicehave been shown to reduce NBTI sensitivity, but they mnot be suitable for most advanced CMOS technologies.also expect NBTI sensitivity to be reduced by mid-gap wofunction gate materials, since the oxide electric field willreduced due to the work function difference and due toflatband voltage difference~lower doped channel region!.Based on these concepts, it is expected that fully-depleSOI should also offer improved NBTI immunity, becauseuses lower-doped channel regions resulting in lower gateide electric fields, which should lead to improved NBTI.

VII. CONCLUSIONS

NBTI is potentially a significant reliability issue inp-channel MOSFETs. Although it is not a ‘‘show stopperbecause it is possible to design around it, it does place ational onus on design and process engineers to take thisradation mode into account. While, the microscopic detaof NBTI are not completely understood with most of opresent knowledge based on empirical results, NBTI physand dynamics is gradually becoming clearer. From the liteture, it is clear there are many effects that interact with NBsensitivity in a process. Most of these effects are secorder and they modify the reaction dynamics or influenand shift the rate at which NBTI occurs within a given prcess and for a given device geometry. Probably the mimportant issue is the quality of the gate oxide and the sparegions sounding the edge of the gate. The number of tror weak spots in the oxide must be minimized to reduNBTI sensitivity. Passivation of these traps with hydrogena partial solution since bonds can be broken and procethat yield very low trap densities~less then 1010 cm22) arecritical.101 Minimizing this high-quality oxide to effects sucas antenna charging or other bond breaking process is lithe next most important issue. Passivation of remaining dgling bonds remains critical, but to minimize the sensitivof these bonds to NBTI induced degradation should benext level of focus.

Materials or process steps that reduce NBTI activatenergy should be minimized. Typical processing conditiothat affect the NBTI activation energy have been outlinedthis article, but in general the worst culprits for reducing Sand H interaction dynamics are nitrogen, water, and mchanical stress. Nitrogen, water and other chemical spethat lower NBTI activation energies can be minimized inprocess or one can tailor the profile in the oxides to lesthese materials at or near the Si/SiO2 interface. Mechanicalstress can be minimized by modifying the temperaturesgrowth conditions and strain in the oxide, STI or other delectric layers. Alternatively one may be able to relieve tstress in oxide by methods such as ion implantation innitride liner layers or stress compensating layers.102 Substi-tuting deuterium for hydrogen is the next best approach siD2 has high binding energies and diffuses slower than hydgen.


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Finally, to understand NBTI’s impact on SOC circuits,is critical to understand the distribution of NBTI tails inheent in advanced CMOS processes. Careful understandinthese issues along with close interaction with the descommunity on the impact of NBTI can lead to high yieldinproducts. To cross the road of NBTI to deep submicron Smanufacturing is the task of physicists, engineers, andprocess development and manufacturing communities.

ACKNOWLEDGMENTS

This work was partially carried out at the NationScience Foundation’s State/Industry/University CooperaResearch Centers’~NSF-S/IUCRC! Center for Low PowerElectronics~CLPE!. CLPE is supported by the NSF~GrantNo. EEC-9523338!, the State of Arizona, and the followincompanies: Conexant, Gain Technology, Intel CorporatiMicrochip Technology, Motorola, Inc., ON SemiconductoPhilips Semiconductors, Raytheon, Syncron TechnologLLT, Texas Instruments and Western Design Center. Thethors thank B. D. Choi from Arizona State University foassistance with some of the references, L. Anderson fTexas Instruments for illuminating discussions and insigand C. Bulucea from National Semiconductor for reviewithe paper and motivating us to enumerate NBTI processea clearer manner.

1G. E. Moore, IEEE IEDM, 1~1975!.2S. Thompson, P. Packan, and M. Bohr, Intel Technol. J.Q3, 1 ~1998!.3E. J. Nowak, IBM J. Res. Dev.46, 169 ~2002!.4T. H. Ning, IEEE CICC , 49~2000!.5R. R. Schaller, IEEE Spectrum34, 53 ~1997!.6G. D. Hutcheson and J. D. Hutcheson, Sci. Am.274, 54 ~1996!.7G. Kamarinos and P. Felix, J. Phys. D29, 487 ~1996!.8H. Iwai, IEEE J. Solid-State Circuits34, 357 ~1999!.9K. Hess, A. Haggag, W. McMahon, K. Cheng, J. Lee, and J. Lyding, IECircuits Devices Mag.17, 33 ~2001!.

10P. L. Levin and R. Ludwig, IEEE Spectrum39, 38 ~2002!.11R. C. Leachman and D. A. Hodges, IEEE Trans. Semicond. Manuf.9, 158

~1996!.12R. Doering and Y. Nishi, Proc. IEEE89, 375 ~2001!.13M. Makabe, T. Kubota, and T. Kitano, IEEE Int. Reliability Phys. Sym

38, 205 ~2000!.14B. S. Doyle, B. J. Fishbein, and K. R. Mistry, IEEE IEDM , 529~1991!.15Y. Nishida, H. Sayama, K. Oda, M. Katayama, Y. Inoue, H. Morimo

and M. Inuishi, IEEE IEDM , 869~2001!.16C. Bulucea and D. Kerr, Solid-State Electron.41, 1345~1997!.17Y. Chen, J. Zhou, S. Tedja, F. Hui, and A. S. Oates, IRW Final Rep.

41, 2001.18R. Thewes, R. Brederlow, C. Schlu¨nder, P. Wieczorek, A. Hesener, B

Ankele, P. Klein, S. Kessel, and W. Weber, IEEE IEDM , 81~1999!.19V. Reddy, A. T. Krishnan, A. Marshall, J. Rodriguez, S. Natarajan, T. R

and S. Krishnan, IEEE Int. Rel. Symp.40, 248 ~2002!.20A. Haggag, W. McMahon, K. Hess, K. Cheng, J. Lee, and J. Lyding, IR

Final Rep. No. 179, 2000.21B. E. Deal, M. Sklar, A. S. Grove, and E. H. Snow, J. Electrochem. S

114, 266 ~1967!.22B. E. Deal, J. Electrochem. Soc.121, 198C~1974!.23A. Goetzberger, A. D. Lopez, and R. J. Strain, J. Electrochem. Soc.120,

90 ~1973!.24K. Onishi, C. S. Kang, R. Choi, H. J. Cho, S. Gopalan, R. Nieh,

Dharmarajan, and J. C. Lee, IEEE IEDM , 659~2001!.25C. Schlunderet al., Microelectron. Reliab.39, 821 ~1999!.26N. Kimizuka, K. Yamaguchi, K. Imai, T. Iizuka, C. T. Liu, R. C. Keller

and T. Horiuchi, IEEE VLSI Symposium 2000, p. 92.27C. T. Sah, J. Y. C. Chen, and J. J. T. Tzou, Appl. Phys. Lett.43, 204

~1983!; S. T. Pantelides,ibid. 50, 995 ~1987!.28E. H. Poindexter and P. J. Caplan, Prog. Surf. Sci.14, 201–294~1983!.


ofn

Ce

e

,

s,u-

mt,

in

.

t,

.

.

29M. L. Reed and J. D. Plummer, J. Appl. Phys.63, 5776~1988!.30A. Stirling, A. Pasquarello, J. C. Charlier, and R. Car, Phys. Rev. Lett.85,

2773 ~2000!.31A. Stesmans and V. V. Afanas’ev, Microelectron. Eng.48, 113 ~1999!.32A. Stesmans and V. V. Afanas’ev, Phys. Rev.57, 10030~1998!.33P. Lenahan, IEEE 2002 Rel. Phys. Tutorial Notes, Adv. Rel. Topics, IE

IRPS , section 223~2002!.34T. D. Mishima and P. M. Lenahan, Appl. Phys. Lett.76, 3771~2000!; J. P.

Campbell and P. M. Lenahan,ibid. 80, 1945~2002!.35P. V. Gray and D. M. Brown, Appl. Phys. Lett.8, 31 ~1966!.36A. K. Sinha and T. E. Smith, J. Electrochem. Soc.125, 743 ~1978!.37K. Saminadayar and J. C. Pfister, Solid-State Electron.20, 891 ~1977!.38S. E. Rauch, III, IEEE Trans. Devices Mat. Rel.2, 89 ~2002!.39S. N. Rashkeev, D. M. Fleetwood, R. D. Schrimpf, and S. T. Pantelid

IEEE Trans. Nucl. Sci.48, 2086~2001!.40A. Stesmans, Phys. Rev. B61, 8393~2000!.41D. B. Brown and N. S. Saks, J. Appl. Phys.70, 3734~1991!.42C. G. Van de Walle and B. R. Tuttle, IEEE Trans. Electron Devices47,

1779 ~2000!.43B. Tuttle and C. G. Van de Walle, Phys. Rev. B59, 12884~1999!.44H. Katto IRW Final Rep. No. 54, 2001.45K. O. Jeppson and C. M. Svensson, J. Appl. Phys.48, 2004~1977!.46B. E. Deal, IEEE Trans. Electron DevicesED-27, 606 ~1980!.47S. Ogawa, M. Shimaya, and N. Shiono, J. Appl. Phys.77, 1137~1995!.48C.-H. Liu et al., Jpn. J. Appl. Phys., Part 141, 2423~2002!.49D. Lu, G. A. Ruggles, and J. J. Wortman, Appl. Phys. Lett.52, 1344

~1988!.50W. W. Abadeer, IEEE Trans. Dev. Mat. Rel.1, 60 ~2001!.51G. La Rosa, S. Rauch, and F. Guarin, IEEE 2002 Rel. Phys. Tuto

Notes, Rel. Fundamentals, , Section 133~2002!.52M. S. Krishnan and V. Kol’dyaev, IEEE Int. Rel. Symp.40, 421 ~2002!.53A. G. Revesz, J. Electrochem. Soc.126, 122 ~1979!.54J. Krauser, F. Wulf, M. A. Briere, J. Steiger, and D. Bra¨unig, Microelec-

tron. Eng.22, 65 ~1993!.55E. Takeda, E. Murakami, K. Torii, Y. Okuyama, E. Ebe, K. Hinode, and

Kimura, Microelectron. Reliab.42, 493 ~2002!.56K. Cheng, K. Hess, and J. W. Lyding, IEEE Electron Device Lett.22, 441

~2001!; K. Cheng, K. Hess, and J. W. Lyding,ibid. 22, 203 ~2001!.57M. M. Albert and N. H. Tolk, Phys. Rev. B63, 035308~2001!.58C. H. Lin, M. H. Lee, and C. W. Liu, Appl. Phys. Lett.78, 637 ~2001!.59T. G. Ference, J. S. Burnham, W. F. Clark, T. B. Hook, S. W. Mittl, K. M

Watson, and L. K. K. Han, IEEE Trans. Electron Devices46, 747 ~1999!.60W. F. Clark, T. G. Ference, S. W. Mittl, J. S. Burnham, and E. D. Adam

IEEE Electron Device Lett.20, 501 ~1999!.61C. H. Liu et al., IEEE IEDM , 861~2001!.62K. Saadatmand, E. McIntyre, S. Roberge, Z. Wan, K. Wenzel, R. R

mell, and J. Dykstra, IEEE International Conference on Ion Implant. Tenology Proceedings, edited by J. Matsuo, G. Takaoka, and I. Yam1999, Vol. 1, p. 292.

63P. Chaparalaet al., IRW Final Rep. No. 95, 2000.64N. Kimizuka, T. Yamamoto, T. Mogami, K. Yamaguchi, K. Imai, and

Horiuchi, IEEE VLSI Symposium, 1999, p. 73.65K. Ichinose, T. Saito, Y. Tanagida, Y. Nonaka, K. Torri, H. Sato, N. Sai

S. Wada, K. Mori, and S. Mitani, IEEE VLSI Symposium, 2001, p. 1066C. H. Liu et al., IEEE Int. Rel. Symp.40, 268 ~2002!.67A. Ono, K. Fukasaku, T. Hirai, M. Makabe, S. Koyama, N. Ikezawa,

Ando, T. Suzuki, K. Imai, and N. Nakamura, IEEE VLSI Symposium2001, p. 79.

68S.-S. Tan, T. Chen, C.-H. Ang, C.-M. Lek, W. Lin, J. Z. Zheng, A. See aL. Chan, IEEE International Symposium on Plasma/Process-InduDamage, 2002, p. 146.

69K. Imai and A. Ono, IEICE Trans. Electron.E85-C, 1057~2002!.70K. Sasada, M. Arimoto, H. Nagasawa, A. Nishida, H. Aoe, T. Dan,

Fujiwara, Y. Matsushita, and K. Yodoshi, Microelectron. Test Struct. , 2~1998!.

71C. E. Blat, E. H. Nicollian, and E. H. Poindexter, J. Appl. Phys.69, 1712~1991!.

72C. R. Helms and E. H. Poindexter, Rep. Prog. Phys.57, 791 ~1994!.73J. Ushio, K. Kushida-Abdelghafar, and T. Maruizumi, IEEE Semicond

tor Device Res. Symposium 2001, p. 158; K. Kushida-Abdelghafar,Watanabe, J. Ushio, and E. Murakami, Appl. Phys. Lett.81, 4362~2002!.

74T. B. Hook, E. Adler, F. Guarin, J. Lukaitis, N. Rovedo, and K. SchruefIEEE Trans. Electron Devices48, 1346~2001!.


e

g,uc

. R

a

m

d

Rtur

E

s.

OI

po-

g,

t.

lin,

pl.

c.

.


75T. Yamamoto, K. Uwasawa, and T. Mogami, IEEE Trans. Electron Dvices46, 921 ~1999!.

76D.-Y. Lee, H.-C. Lin, W.-J. Chaing, W.-T. Lu, G.-W. Huang, T.-Y. Huanand T. Wang, IEEE International Symposium on Plasma/Process-IndDamage, 2002, p. 150.

77S. Fang and J. P. McVittie, IEEE Electron Device Lett.13, 288 ~1992!.78G. J. Gerardi, E. H. Poindexter, P. J. Caplan, M. Harmatz, and W

Buchwald, J. Electrochem. Soc.136, 2609~1989!.79B. S. Meyerson, F. J. Himpsel, and K. J. Uram, Appl. Phys. Lett.57, 1034

~1990!.80T. O. Sedgwick and P. D. Agnello, J. Vac. Sci. Technol. A10, 1913~1992!.81H. S. Momose, T. Ohguro, K. Kojima, S. Nakamura, and Y. Toyoshim

IEEE VLSI Symposium, 2002, p. 156.82Y. Saito, K. Sekine, N. Ueda, M. Hirayama, S. Sugawa, and T. Oh

IEEE VLSI Symposium 2000, p. 176.83J. F. Zhang, C. Z. Zhao, G. Groeseneken, R. Degreave, J. N. Ellis, an

D. Beech, J. Appl. Phys.90, 1911~2001!.84K. Vanheusden, W. L. Warren, R. A. B. Devine, D. M. Fleetwood, J.

Schwank, M. R. Shaneyfelt, P. S. Winokur, and Z. J. Lemnios, Na~London! 386, 587 ~1997!.

85G. W. Yoon, A. B. Joshi, J. Kim, G. Q. Lo, and D.-L. Kwong, IEEElectron Device Lett.13, 606 ~1992!.

86E. Morifuji et al., IEEE VLSI Symposium, 2002, p. 218.87A. Suzukiet al., IEEE VLSI Symposium, 2002, p. 216.88M. Mehrotraet al., IEEE VLSI Symposium, 2002, p. 124.89P. K. Roy, Y. Chen, and S. Chetlur, IEEE Trans. Electron Devices48, 2016

~2001!.


-

ed

.

,

i,

C.

.e

90Z. Liu, S. Fujieda, K. Terashima, M. Wilde, and K. Fukutani, Appl. PhyLett. 81, 2397~2002!.

91R. J. T. Bunyan, M. J. Uren, J. C. Alderman, and W. Eccleston, IEEE SConference 1992, p. 130.

92A. T. Krishnan, V. Reddy, and S. Krishnan, IEEE IEDM , 865~2001!.93N. Matsunaga, H. Yoshinari, and H. Shibata IEEE International Sym

sium on Plasma/Process-Induced Damage, 2002, p. 142.94D.-Y. Lee, H.-C. Lin, M.-F. Wang, M.-Y. Tsai, T.-Y. Huang, and T. Wan

Jpn. J. Appl. Phys., Part 141, 2419~2002!.95S.-C. Songet al., IEEE VLSI Symposium 2002, p. 72.96E. Morifuji et al., IEEE VLSI Symposium, 2001, p. 117.97Y. H. Lee, K. Wu, T. Linton, N. Mielke, S. Hu, and B. Wallace, IEEE In

Rel. Symp.38, 77 ~2000!.98F. E. Pagaduan, J. K. J. Lee, V. Vedagarbha, K. Lui, M. J. Hart, D. Git

T. Takaso, S. Kamiyama, and K. Nakayama, IEEE Int. Rel. Symp.39, 315~2001!.

99S. S. Tan, T. P. Chen, C. H. Ang, and L. Chan, Appl. Phys. Lett.82, 269~2003!.

100S. S. Tan, T. P. Chen, C. H. Ang, Y. L. Tan, and L. Chan, Jpn. J. ApPhys.41, L1031 ~2002!.

101T. Ohmi, S. Sugawa, K. Kotani, K. Hirayama, and A. Morimoto, ProIEEE 89, 394 ~2001! ~see Fig. 20 in the article!.

102A. Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, HSato, and F. Ootsuka, IEEE IEDM , 433~2001!.


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