application to the automatic extraction of circuit shapes charles hymans modular analysis of a...
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Application to the automatic extraction of circuit shapes
Charles Hymans
Modular analysis of a circuit description
language by Abstract Interpretation
6 April 2002 Designing Correct Circuits 2
lfp F (lfp G)
Concrete semanticsfix-point of F
Galois connection (, ) linksconcrete D and abstract A domain
Sound abstract semanticsfix-point of G algorithm
A. I. design flowF
G
D
A
D
A
6 April 2002 Designing Correct Circuits 3
Shape analysis for RTL VHDL
A <= B or C;
A
B
C
or
A
B
C
6 April 2002 Designing Correct Circuits 4
Generic modules?
entity example generic(n : integer) port(A : bit_vector(1 to n), B : bit_vector(1 to 2*n))
for I in 1 to n A[I] <= not B[I + 1]; end;end;
No a-priori bound on
n !
6 April 2002 Designing Correct Circuits 5
Modular analysis
Semantics of a module?
Representation for infinite shapes?
A
B
1 ... n
n + 1
infinite !
6 April 2002 Designing Correct Circuits 6
Operational semantics Execution builds a circuit
State : (l, E, G, S)
VHDL command basic operators
7 basic operators modify (E, G)assert, create_int, connect ...
6 April 2002 Designing Correct Circuits 7
Trace semantics? Chopped semantics!
M
N
call return
M
N
6 April 2002 Designing Correct Circuits 8
Fix-point for chopped semantics
F(X)(g) = entry(g)
{s0 … sn+1 | s0 … sn X(g), sn sn+1 }
{s0 … sn+1 | s0 … sn X(g),
sn call(f), sn t0, t0 … tm X(f),
tm return, tm sn+1 }
6 April 2002 Designing Correct Circuits 9
Abstract domain
At each program point l
Possible values of integer variablesnumerical domain
Shapes built since module entrydecorated connection graph
6 April 2002 Designing Correct Circuits 10
Numerical domains
Intervals affine subspaces octagons polyhedra
X [aX, bX] Y [aY, bY]
aX + bY = c
X Y c
aX + bY c
Symbolic representation for numerical functions
6 April 2002 Designing Correct Circuits 11
Decorated connection graph
finite !
l + 1 = r
A
B
1 ... n
n+1
infinite !
A
B
for I in 1 to n A[I] <= not B[I + 1];end;
6 April 2002 Designing Correct Circuits 12
Abstract operators
Operational semantics expressed thanks to 7 basic operators
Design onlyabstract operatorsabstract module plug-in
sound operators sound analysis
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Example: wire connection
A[2*I + 1] <= not B[J];
left expression: l = 2*I + 1 environment: I = J right expression: r = J
resulting constraint: l = 2 * r + 1
6 April 2002 Designing Correct Circuits 14
Wire connection (cont.)
I J
l rresulting connection
environment
left right
6 April 2002 Designing Correct Circuits 15
Conclusion
Modular analysis Decorated connection graph Quickly applicable to other languages
Data-dependency: all VHDL Timed dependencies:
“B depends on A with a delay of 3 cycles”
Thank you for your attention!