application specific intelligent power modules -a novel approach to system integration in low power...
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Application Specific Intelligent Power Modules - A Novel Approach toSystem Integration in Low Power Drives
Eric R. Motto- Powerex Inc., Youngwood, Pennsylvania, USA
ABSTRACT
Abstract - This paper reviews the system requirements and key technologies driving the
development of highly integrated Application Specific Intelligent Power Modules (ASIPMs). New
ASIPMs with power circuit topologies, control functions and packaging optimized to meet the
performance, cost and size requirements of specific small motor control applications will be
presented.
I. INTRODUCTION
When used with an inverter, three phase AC motors are smaller, more efficient and more reliablethan the universal AC and brush type DC motors that are commonly used in light industrial and consumer
applications. In order to realize these advantages, the cost of the inverter must be offset by energy savings,
improved performance, and increased reliability. The widespread use of inverters in heavy industrial and
precision motion control applications is evidence that these advantages are being realized. On the other
hand, the use of inverters with small AC motors (100W - 2.2kW) is often limited by the cost and complexity
of the inverter. In addition, limited space often prevents the use of general purpose inverters with fixed
shape, size, and cooling requirements. For these applications, it is becoming increasingly desirable to
simplify and miniaturize the power section so that the physical size, form factor, and cost requirements can
more easily be met. This paper will examine the
system requirements of some typical small motor
drive applications and present five examples of
Application Specific Intelligent Power Modules
(ASIPMs) targeted to address these requirements.The examples illustrate how power circuit
topologies, integrated functions, and packaging can
be optimized to meet the requirements of specific
applications.
II. THE ASIPM CONCEPT
Conventional IPMs (figure 1a) integrating
power devices with low voltage ASICs (Application
Specific Integrated Circuits) to provide gate drive
and protection functions have been widely accepted
for general purpose motor drive applications rangingfrom 200W to more than 150kW [3][5][7]. Thesuccess of these modules is the direct result of
several technical advantages including: (1) Reduced
design time and improved reliability offered by the
factory tested, built-in gate drive and protection
functions; (2) Lower losses resulting from
simultaneous optimization of power chips and
protection functions; (3) Smaller size resulting from
User Supplied Interface
Power Chips
LV ASIC
Over Current,Over Temp.,Cotrol supplyfailure
Gate Drive
Temp. Sensor
LV ASIC
Over Current,Control supplyfailure
Gate Drive
Isolated Control
Signal Interface(Opto Couplers)
Isolated PowerSupplyC
PU
HVIC
LV ASIC
Power Chips
LevelShift
Gate Drive andProtection
Input signalconditioning
Protection, Fault Logicand Analog CurrentFeedback Processing
GateDrive
CPU
Isolated ControlSignal Interface(Opto Couplers)
Isolated PowerSupply
Current sensor(s)Temp. sensor
Figure 1a: Conventional IPM
Figure 1b: ASIPM
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the use of bare power chips and application specific control ICs. (4)
Improved manufacturability resulting from lower external component
counts.
Figure 2: HVIC Chip
Unfortunately, in spite of these advantages, the conventional
IPMs generic, general purpose, design does not provide enough
functional integration to meet the demanding cost and size
requirements of some small motor control applications. In thesecases, it is often desirable to increase the level of integration to
include functions such as level shifting, high side power supplies and
current sensing. The ASIPM shown in figure 1b has been developed
to address these requirements. The ASIPM takes the integration a
step farther than conventional IPMs by introducing HVIC (High
Voltage Integrated Circuit) technology. The ASIPMs described in this
paper utilize custom high and low voltage integrated circuits to
provide input signal conditioning, protection logic, analog current
feedback signal processing, level
shifting and gate drive for the
integrated power semiconductor
devices. A photo of a typical high
voltage integrated circuit (HVIC) isshown in figure 2.
III. SELECTING THE INTEGRATED
CONTROL AND PROTECTION
FUNCTIONS
The addition of HVIC
technology to the ASIPM makes it
possible to integrate a wide range of
sophisticated functions. Figure 3 is a
block diagram showing some of the
functions that can be implemented.
In general, the cost and size of the
ASIPM increases with increasing
complexity. To determine which functions should be integrated for a given application, it is necessary to
consider the fundamental trade-off between performance, size and cost illustrated in figure 4. The key to
developing a cost effective ASIPM is to integrate only the functions that provide both system and cost
advantages. Table 1 gives a breakdown of the required functions in four different applications. By examining
the requirements shown in table 1 and considering the trade-off of figure 4 an optimum combination of
integrated functions can be realized. Clearly, the optimum combination will be different for different
applications. To date, five families of ASIPMs have been developed to meet the needs of specific
applications. These devices will be described in more detail
NRS
GateDrive
GateDrive
SC Prot.
SC Prot.
LevelShift
Shoot-ThroughInterlock
BootStrapSupply
UnderVoltage
Lock-Out
FaultStatus
Feedback
TSOverTemp.
Current
Sensor(s)
UnderVoltage
Lock-Out
U,V,W
P
Control
Power
CPU/DSP
Control
n
Status
n
AnalogCurrent
n
Figure 3: ASIPM Integrated Functions
PerformanceEfficiency
Control PrecisionI/O Functions
Reliability
CostFunctional Value
Development TimeManufacturability
SizeSystem
RequirementsForm Factor
Figure 4: ASIPM Design Trade-off
Inverter
IGBTs & Free Wheel Diodes
Converter
DiodesBrake
IGBT & Diode
Figure 5: ASIPM Power Circuit Requirements
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Table 1: ASIPM Control and Protection Application Requirements
Control and Protection
Functions
High Performance
General Purpose
Industrial Inverter
Compact High Precision
AC Servo and Vector
Drives
Basic General Purpose
Industrial and
Commercial Speed
Control/Smart Motors
Low Cost Consumer
Appliance and
imbedded inverters
Gate Drive Required Required Required Required
Level Shift Required Required Required Required
Boot Strap Supply
Diodes
Required Required Required Required
P-Side Gate Drive
Under Voltage
Protection
Required due to unstable nature
of boot strap supplies
Required due to unstable nature
of boot strap supplies
Required due to unstable nature
of boot strap supplies
Required due to unstable nature
of boot strap supplies
P-Side Short Circuit
Protection
Desirable, but may not be
needed when high performance
output current sensors are used
with a high speed CPU
Desirable, but may not be
needed when high performance
output current sensors are used
with a high speed CPU
Desirable if low enough cost.
However, acceptable protection
can usually be achieved using
bus current sensors
Usually unnecessary in
imbedded inverter applications
N-Side Gate Drive
Under Voltage
Protection
Generally required for reliable
power up/down
Generally required for reliable
power up/down
Generally required for reliable
power up/down
Generally required for reliable
power up/down
N-Side Short Circuit
Protection
Desirable for low impedance
faults and shoot-through survival
Desirable for low impedance
faults and shoot-through survival
Desirable for low impedance
faults and shoot-through survival.
May be implemented using bus
current sensor.
Desirable for low impedance
faults and shoot-through survival.
May be implemented using bus
current sensor
Shoot Through InterlockGood safety feature. May be
required depending on users
design philosophy
Good safety feature. May be
required depending on users
design philosophy
Good safety feature. May be
difficult to justify cost
Desirable, but may not meet cost
requirements
Over Temperature Desirable Desirable Desirable if cost effective Usually unnecessary inimbedded inverter applications
Current Sensors and
Feedback
Three phase output current
feedback is required
Three phase output current
feedback is required
DC Bus current feedback signal
is usually sufficient
Current feedback signal is
usually not required
Fault Status Feedback Multiple diagnostic fault signalsare desirable
Multiple diagnostic fault signals
are desirable
Single fault status signal is
usually acceptable
Single fault status signal is
usually acceptable
in the following sections.
IV. SELECTING THE POWER CIRCUIT TOPOLOGY
The power semiconductor requirements in the inverter power stage also differ from application toapplication. Figure 5 shows the typical power devices that may be included in a small motor control. Table 2
gives a breakdown of the requirements in four different applications. For lowest cost, the power stage should
only include the necessary power devices. It can be observed from table 2 that the optimum power circuit
topology depends on the application requirements.
V. ASIPM EXAMPLES
Table 2: ASIPM Power Circuit Requirements
Power Circuit
Component
High Performance
General Purpose
Industrial Inverter
Compact High Precision
AC Servo and Vector
Drives
Basic General Purpose
Industrial and
Commercial SpeedControl/Smart Motors
Low Cost Consumer
Appliance and
imbedded inverters
Converter (Rectifier) Usually requires three phaserectifier
Required for stand alone units
Not required in DC feed multi
axis applications
Usually requires three phase
rectifier
May require three phase, single
phase, or doubler* configurations
Brake Usually required for rapiddeceleration
Braking function generally
required but may be
implemented in the bulk power
supply of DC fed systems and
size requirements vary widely
depending on the application
Usually not required Usually not required
Inverter Required - High PWMFrequency (5kHz - 20kHz)
Required - High PWM
Frequency (5kHz - 20kHz)
Required - High PWM
Frequency (5kHz - 20kHz)
Required - High and Low PWM
frequencies
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The following subsections present five
examples of actual ASIPMs that have been
optimized to meet the needs of specific
applications. In each example the power circuit
topology, package design and integrated functions
have been tailored to a specific class of small
motor control applications. At the same time carehas been exercised to keep the integrated
functions as generic as possible so that the
module is suitable for a wide enough range of
applications to take advantage of the
economies of automated mass production.
These examples each follow one of the
application categories outlined in tables 1 and
2.
Figure 6: PS212XX DIP ASIPM
A. ASIPM "DIP Series" For Consumer
Appliance Applications
The "DIP" ASIPM, PS212XX series, is
designed for basic speed control in consumer
appliance applications. For these applications,
the ASIPM must provide a small, low-cost,
efficient power stage that can be easily
integrated into the finished equipment. In order
to achieve these targets, a new transfer
molded package was developed. A photograph of the
new package is shown in figure 6 and a cross section
diagram is shown in figure 7. Low cost is achieved by
assembling bare power chips along with custom HVIC
and LVIC die on a lead frame like a giant integrated
circuit. The lead frame assembly is molded in epoxy resin
along with an aluminum heat sink to provide good
thermal characteristics. This process reduces cost and
manufacturing time by eliminating the need for separate
packaging of the power devices and control ICs. In
addition, the IMS (Insulated Metal Substrate) or ceramic substrate that is
used in conventional hybrid modules is not required. The transfer molded
package is also well suited for high volume, low cost mass production.
Aluminum Heat SinkMold Resin
Power Chips
IGBT, FWDi
Al Bond Wire Au Bond WireHVIC
Power Pins Control Pins
Figure 7: DIP ASIPM Package Cross Section
Table 3: DIP ASIPMsDIP ASIPM Inverter Rating
Line-up 400W 750W 1500W
Low
Frequency
Type
PS21204 PS21205
High
Frequency
Type
PS21213 PS21214
The input voltage for these applications is generally between
100VAC and 240VAC. To cover this range, IGBTs and free wheel diodes
with a 600V VCESrating were selected. Most of the target applications are
powered from a single phase AC source but flexibility to accommodate
three phase sources and voltage doubler (figure 8) topologies wasdesired. Due to these requirements and the limited capabilities of the lead frame design, it was determined
that the rectifier converter should not be integrated in the DIP ASIPM. The IGBT inverter section is a
standard three phase bridge containing six IGBT+FWDi pairs. For optimum system cost, the decision was
made to develop two different types of IGBT chips. High speed chips are used when the application requires
switching frequencies greater than 5kHz and low speed (low saturation voltage) chips are used when the
required switching frequency is less than 5kHz. At this writing, there are four DIP ASIPMs in production and
several additional types under development. Table 3 shows the typical application and type names of these
four devices.
330
VDC120VAC
Figure 8: Doubler Circuit
Figure 9 is a block diagram showing the DIP ASIPMs integrated control and protection functions
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under voltage lock out circuit. If the voltage of the control
supply falls below the UV level specified on the data sheet,
the low side IGBTs are turned off and a fault signal is
asserted. In addition, the p-side gate drive circuits have
independent under voltage lock out circuits to protect
against failure of the boot-strap power supplies.
The DIP ASIPM uses the voltage across anexternal shunt resistor inserted in the negative DC bus to
monitor the current and provide protection against overload
and short circuits. An RC filter with a time constant of 1.5 to
2s is inserted as shown in figure 9 to prevent erroneousfault detection due to di/dt induced noise at switching
events. When the voltage at the CIN pin exceeds the VSC
reference level specified on the device data sheet the lower
arm IGBTs are turned off and a fault signal is asserted at
the FO output. The IGBTs remain off until the fault time
(tFO) has expired and the input signal has cycled to its off
state. The duration of tFO is set by an external capacitor
CFO.
The DIP ASIPM has seven microprocessorcompatible input and output signals. All signals are 5V
TTL/CMOS compatible and referenced to the common ground
of the control power supply allowing direct connection to the
MCU. Figure 12 shows a typical external interface circuit. On
and off operations for all six IGBTs in the ASIPM are
controlled by the active low control inputs. Normally, these
inputs are pulled high to the 5V logic supply of the MCU with
an external resistor. The MCU commands the IGBT to turn on
by pulling the respective input low. Hysteresis is provided on
all inputs to prevent oscillations and enhance noise immunity.
The fault signal output is in an open collector configuration.
When a fault occurs the ASIPM pulls the fault line low.
(U,V,W)
GateDrive
(P)
(N)
GateDrive15V
Boot StrapSupply
Diode
+
Floating SupplyV(U,V,W)
+
+
ChargingPath
CIN(n)
CIN(n)
V(U,V,W)
Figure 11: Boot Strap Supply Operation
B. ASIPM "Version 3" For Basic General Purpose
Industrial Speed Control
(Smart Motors)
CPU/DSP
ASIPM
5V 15V
5.1K5.1K
6
+ +VD
UP, VP, WP,UN, VN, WN
FO
GND
Figure 12: DIP ASIPM
Interface Circuit
The version 3
PS1103X series of ASIPMs was
developed for applications such
as pumps, hoists, and conveyors
that require limited control
performance consisting primarily
of speed regulation. In theseapplications, it is often desirable
to miniaturize and simplify the
power stage so that the inverter
can be mounted on, or integrated into the motor. The version 3 series of ASIPMs consists of five types
designed for 0.2 to 2.2kW micro inverter applications. Table 4 summarizes the key characteristics of each of
the five module types in the PS1103X ASIPM family.
Table 4: Version 3 ASIPMs
Type Typical Motor
Rating (kW)
IGBT Rating
(IC/VCES)
Inverter Output
Current IO
(ARMS)
OC
Trip
(Amps)
Short Circuit
Level (SC)
(Amps)
PS11032 0.2/220VAC 4A/600V 1.5 5.3 8.0
PS11033 0.4/220VAC 8A/600V 3.0 10.6 16
PS11034 0.75/220VAC 15A/600V 5.0 17.7 30
PS11035 1.5/220VAC 20A/600V 7.0 24.7 40
PS11036 2.2/220VAC 30A/600V 11 39 60
The packaging selected for the version 3 ASIPM is a low profile design using an aluminum base
IMS (Insulated Metal Substrate) substrate. A photo of the version 3 ASIPM is shown in figure 13. A cross
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section diagram of the low profile IMS package is shown in figure
14. The power chips, control IC and support components are
assembled on the IMS substrate much like a conventional
surface mount printed circuit board. This process is easily
automated, low cost and quite flexible.
Figure 13: PS1103X
Version 3 ASIPM
A block diagram of the version 3 ASIPM is shown in
figure 15. Careful selection of integrated functions and advancedprocessing technologies allowed a single HVIC to be used for the
gate drive and protection of all six IGBTs. This single IC design
yields low cost and extremely compact size. The ASIPMs
integrated functions are powered from a single 15V control power
supply referenced to the negative DC bus.
Built-in, boot strap circuits supply power for the high side
gate drive circuits eliminating the need for separate isolated
power supplies. Incorporating
the high side power supplies
and level shifting into the
ASIPM reduces high voltage
spacing requirements on thecontrol PCB allowing a
significant savings in circuit
board space.
The PS1103X version
3 ASIPMs power circuit
consists of six rectifier diodes
forming a three phase bridge
and six IGBT, free wheel diode
pairs forming a three phase
inverter stage. The brake circuit is not required for most of the target applications so it was omitted to reduce
the size and cost of the module. A circuit diagram of the power circuit is included in figure 15. Openings are
provided in both the positive and negative DC bus connections. All of the IGBT and free wheel diodes are
the latest Mitsubishi/Powerex third generation technology utilizing shallow diffusion and 2~3m design rules[1].
Multi Layer Insulated
Metal Substrate Silicon
Chips
Gate Drive and Control
Circuits
Aluminum Bond
Wires
Plastic
CasePower Terminals Epoxy
Resin
Signal
Terminals
Figure 14: Cross Section of IMS ASIPM Package
Built in short circuit and over current protection allow maximum utilization of power device capability
while avoiding nuisance tripping. This is achieved using a time dependent fault trip level. Figure 16 shows
the time dependence of the
over current and short circuit
protection functions. When a
severe low impedance fault
causes the current to exceed
more than two times the
modules ICrating, short circuit
protection is activated and
shut down occurs very quickly
~2s. Under overload
conditions, the trip time
extends to 10s. Over current
protection is activated when
the peak current indicates that
the load current has exceeded
250% of the modules IO(RMS)
rating.
Gate Drive
UV Lock Out
Level Shift
Gate Drive
UV Lock Out
Level Shift
Gate Drive
UV Lock Out
Level Shift
Gate Drive
UV
Lock Out
SC
Protection
Analog Current
Feedback
Input Signal
Conditioning
Interlock
Fault Output
Logic
+VCC
HV-ASIC
P1
R
S
T
N1
P2
U
V
W
N2
VD
UPVP
WPUNVN
WN
FO
VAMP
GND
5V LogicInterfaceto MCU
15V
230VAC
Motor
Figure 15: ASIPM Version 3 Block Diagram
A buffered analog bus
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Typical ICWaveform
tW(s)0
2 10
ProtectionLevel
Short Circuittrip level
Over Currenttrip level
IC(A)
IC(rated)X 2
IORMS(rated)x
250% x 2
Figure 16: ASIPM Version 3 Short circuit
and over current protection function
VAMP(V)
1
0
3
4
5
2
0 100 200 300Bus Current (%) Normalized to IORMS(rated)x 2
Current Feedback Signal
Output Characteristic
Conditions:
VD=15V, Tj= 25C
VAMP(200%)
VAMP(100%)
Figure 17: ASIPM Version 3 Analog Bus
Current Feedback Signal Performance
VCIN(P)off
on
VCIN(N)
VGE(P)0
VGE(N)0
off
on
NormalOperation
N-Side erroneousnoise rejected
P-Side on commanddelayed until N-Side off
Active Low P-Sidecontrol input
Active Low N-Sidecontrol input
P-Side IGBT GateVoltage
N-Side IGBT GateVoltage
Figure 18: ASIPM Version 3 Shoot
Through Interlock Protectioncurrent feedback signal is provided for system
control. The signal is derived from a shunt that
measures the sum of the currents in the
emitters of the low side IGBTs (see figure 15).
The HVASIC amplifies the signal from the
shunt to provide a scaled analog feedback
signal of 4V when the peak load current
reaches a level equivalent to 200% of the
modules rated IO(RMS). Figure 17 shows the
characteristics of the analog feedback signal.
The HVASIC also provides shoot
through interlock logic for additional protection
against noise and control signal anomalies.
Figure 18 is a timing diagram showing theoperation of the interlock function. The interlock
function rejects input signals that command the
upper and lower IGBTs in a leg to be on
simultaneously. Operation of the interlock in the
version 3 ASIPM does not produce a fault
signal.
Table 5: Version 3 ASIPM Control SignalsSignal Name Designation Description
Control Inputs UP, VP, WP,
UN, VN, WN,
Inputs for controlling on/off
operation of the IGBTs in the IPM.
Fault Signal FO Fault output signal
Analog Current
Feedback
VAMP Analog current feedback signal
The module is protected from failure of
the 15V control power supply by a built in under voltage lock out
circuit. If the voltage of the control supply falls below the UV level
specified on the data sheet, the low side IGBTs are turned off
and a fault signal is asserted. In addition, the p-side gate drive
circuits have independent under voltage lock out protection to
protect against failure of the boot-strap power supplies.The PS1103X series ASIPM has eight microprocessor
compatible input and output signals. All signals are 5V
TTL/CMOS compatible and are referenced to the common
ground of the control power supply to allow direct connection to
the MCU. Table 5 summarizes the ASIPM's input and output
signal names and function definitions. Figure 19 shows a typical
external interface circuit for the version 3 ASIPM. On and off
operations for all six IGBTs in the ASIPM are controlled by the
CPU/DSP
ASIPM
5V 15V
5.1K5.1K
6
+ +
10K
0.1nF
VD
UP, VP, WP,UN, VN, WN
FO
VAMP
GND
Figure 19: ASIPM Version 3
Interface Circuit
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active low control inputs. Normally,
these inputs are pulled high to the 5V
logic supply of the MCU with an
external 5.1K resistor. The MCUcommands the IGBT to turn on by
pulling the respective input low.
Hysteresis is provided on all inputs toprevent oscillations and enhance noise
immunity. The fault signal output is in
an open collector configuration. When
a fault occurs, the fault line pulls low. If
the fault is caused by an SC or OC
condition, the output asserts a fixed
1.8ms pulse. In the case of a UV lock
fault the signal is maintained until the control supply
returns to normal. An example of a compact inverter
designed around the version 3 ASIPM is shown in
figure 20.
Figure 20: Miniature motor drive using Version 3 ASIPM
C. ASIPM "Version 2" For Precision Vector and
AC Servo Drives
The "Version 2" ASIPM, PS1102X series is
designed for miniature high performance servo and
vector drives. In these applications, it is desirable to
integrate sophisticated control functions such as a
current limit warning and three phase analog current
feedback. The increased integration simplifies the power
stage and reduces its cost. A simplified power stage also
helps to improve the reliability of complex multi-axis motion
control systems. The version 2 series of ASIPMs consists
of five types designed for 50 to 750W servo drives or 200 to
2200W high performance inverters. Table 6 summarizes the
key characteristics of these devices.
Table 6: Version 2 ASIPMs
Type Typical
Motor
Rating
(kW)
Inverter
Output
Current
(ARMS)
Peak Output
Current at
CL Warning
(AMPS)
Short Circuit
Protection
Level (SC)
(Amps)
PS11021 0.2 0.8 5.3 10
PS11022 0.4 1.5 10 20
PS11023 0.75 3.0 17 38
PS11024 1.5 5.0 25 40
PS11025 2.2 7.0 35 60
The packaging selected for the version 2 ASIPM is
the same low profile, aluminum base IMS utilized for version
3. A photo of the version 2 ASIPM is shown in figure 21.
A block diagram of the version 2 ASIPM is shown
in figure 22. In order to provide the sophisticated control
functions required for high performance applications, it was
necessary to use a LVASIC for the control and protection of
the low side IGBTs and a HVASIC for the level shift, gate
drive and protection of the high side IGBTs. Like the version 3
ASIPM the version 2 ASIPM has built in boot-strap supply circuitsand P and N side under voltage lock out.
Figure 21: PS1102X
Version 2 ASIPM
Figure 23: Matching Converter
Module for ASIPM
The version 2 ASIPM power circuit consists of six IGBTs
and six fast recovery free wheel diodes forming a three phase
inverter stage. The input rectifier was omitted because many of the
target applications are DC fed inverter modules for multiaxis
systems. For stand alone inverters a separate matching three
phase rectifier module is available. A photo of the matching rectifier
module is shown in figure 23. The braking circuit was not
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R
S
T
CU CV CW CL FO UN VN WN UP VP WP GND VD
T
S
Gate Drive
UV Lock Out
Gate Drive
UV Lock Out
Level
Shift
Gate Drive
UV Lock Out
U
V
W
CBU- CBU+ CBV- CBV+ CBW- CBW+
Motor230VAC
5V Logic Interface to MCUAnalog Current Feedback15V
Control UV Prot ection
OT
Fault Logic
Gate Drive & Short Circuit ProtectionAnalog
Current
Signal
Processing
Matching ConverterModule - RM**TN-H
Figure 22: ASIPM Version 2 Block Diagram
integrated because the requirements of the target applications range from no brake in the case of regulated,
DC fed, multi-axis systems to very large braking devices in systems with heavy regeneration. A circuit
diagram of the power stage is included in figure 22.
In the version 2 ASIPM the low side IGBTs are protected from short circuit conditions by circuits
that monitor the current mirror outputs on the IGBT chips. If the current through the device exceeds the SC
level shown in table 6, the IGBT is immediately but softly turned off. The soft turn off is used to help minimize
transient voltages that can occur during an emergency shut down. The SC level is set at about three times
the IGBTs nominal rating. At this current level the IGBT is in imminent danger of being damaged so an
immediate shut down is warranted. If the short circuit protection is activated the module will assert a faultoutput signal. The short circuit protection is automatically reset when the fault timer (tFOexpires) and the
control input signal of the IGBT involved returns to the off state.
If the current through any of the low side IGBTs or free wheel diodes exceeds the current limit level
shown in table 6, a warning signal will be asserted on the CL output of the module. At the CL level, the
device is not in imminent danger of being damaged so the power devices are not disabled and normal
inverter operation will continue. The CL signal is a warning that is intended to be used by the system control
to either stop inverter operation or attempt output current regulation depending on the requirements of the
application. The current limit warning is derived from the analog current feedback signals described below.
The version 2 ASIPM has a built in temperature sensor that monitors the base plate temperature
of the module. If the temperature exceeds the OT level specified on the device data sheet, all six IGBTs are
turned off and a fault signal is asserted. The temperature sensor is particularly useful for detecting conditions
such as cooling fan failure, extreme ambient temperatures, improper mounting or heat sink problems.
Normal operation of the module will resume when the base plate cools below the over temperature resetlevel. The built in temperature sensor simplifies manufacturing by eliminating the need for mounting and
calibrating external heat sink temperature sensors.
In many high performance applications inverter output current sensors are required for system
control. In order to simplify the power stage design and eliminate the need for hall current sensors, the
version 2 ASIPM integrates three phase current sensing and provides analog feedback signals
proportional to the inverter output currents.
The feedback signals are generated by sampling the low side arm currents and processing them to
create an analog voltage proportional to the output phase currents. The process for deriving these signals is
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illustrated in figure 24. The
current in the low side IGBT
and free wheel diode is
converted to a voltage
using the shunt RS. The
voltage across RS is then
amplified by amp 1 so that itswings 1.1V when theoutput current is at 200% of
the modules IO(RMS) rating.
The non inverting input of
amp 1 is supplied with a
2.25V reference that sets
the zero current output
voltage (VC0). The zero
current level is shifted up to
VC0so that the output signal
is always positive with
respect to logic common
and can be easilyconnected to the
microprocessor's analog
inputs. The output of AMP 1
is connected to a sample
and hold circuit that is
activated by a delayed low
side IGBT gate drive signal.
During the negative half
cycle the phase output
current is reconstructed
from the IGBT current
samples taken on every
high frequency PWM cycle. If gate drive signals are applied to the low side IGBT while its free wheel diode is
conducting the positive half cycle of the output phase current will also be reconstructed. The output of the
sample and hold circuit is buffered by AMP 2 to produce the analog current feedback signal VC. The
performance of the analog current feedback is
shown in figure 25. The version 2 ASIPM
provides analog current feedback signals for all
three output phases.
V
V
(U,V,W)
N
IC
V0
Delay
Chold
AMP 2
AMP 1RS
Gate Drive
VIN
VC
-
+
-
+
Vhold
IN
HOLD
IC
VC
off
on
Figure 24: Three phase
analog current feedback
VC(V)
1
0
3
4
5
2
0-100-200-300-400 100 200 300 400Load Current (%) Normalized to IORMS(rated)x 2
Current Feedback Signal Output Characteristic
Worst CaseError Band
150mV
Analog signal feedbackhold range
Conditions:VD=15V, TC= -20 ~ +100C
Figure 25: Three phase analog
current feedback performance
The version 2 ASIPM has 11
microprocessor compatible input and output
signals. All signals are referenced to the
common ground of the control power supply
allowing direct connection to a CPU. Table 7
summarizes the ASIPM's input and outputsignals. Figure 26 shows the recommended
interface circuit for the version 2 ASIPM. On
and off operations for all six IGBTs in the
ASIPM are controlled by the active low control
inputs. The fault signal and current limit warning
outputs are in an open collector configuration.
When a fault or current limit condition occurs
the respective output turns on and pulls the
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CPU/DSP
ASIPM
5V 15V
5.1K5.1K
6
+ +
10K
0.1nF
VD
UP, VP, WP,UN, VN, WN
FO, CL
CU, CV, CW
GND
Figure 26: ASIPM Version 2
Interface Circuit Table 7: Version 2 ASIPM Control SignalsSignal Name Designation Description
Control Inputs UP, VP, WP,
UN, VN, WN
Inputs for controlling on/off
operation of the six IGBTs
in the IPM.
Fault Signal FO Fault status output signal
Current Limit CL Current limit warningsignal
Analog
Current
Feedback
CU, CW, CV Analog feedback for
output phase currents
signal line low.
D. ASIPM "Version 1" and 1200V For compact high
performance general purpose motor drives
The "Version 1" PS1101X and 1200V PS1201X ASIPMs are designed for compact high
performance general purpose industrial motor drives. These modules have basically the same three phaseanalog current feedback, level shifting, and boot strap supply schemes as the version 2 ASIPM. The main
difference is that shoot through interlock and p-side short
circuit protection are added, multi output fault signaling is
provided, and the power circuits are more complete. These
additional functions make the version 1 and 1200V
ASIPMs the most complex of all types currently available.
Figure 27: PS1101X
Version 1 ASIPM
Table 8: Version 1 ASIPMs
Type Typical
Motor
Rating
(kW)
Inverter
Output
Current
(ARMS)
Peak Output
Current at
CL Warning
(AMPS)
Short Circuit
Protection
Level (SC)
(Amps)
PS11011 0.1 0.8 3.1 6.0
PS11012 0.2 1.5 5.8 12.0
PS11013 0.4 3.0 10.8 24.0
PS11014 0.75 5.0 17.3 43.0
PS11015 1.5 7.0 24.7 53.0
Figure 28: PS1201X 1200V ASIPM
Table 9: 1200V ASIPMs
Type TypicalMotor
Rating
(kW)
InverterOutput
Current
(ARMS)
Peak OutputCurrent at
CL Warning
(AMPS)
Short CircuitProtection
Level (SC)
(Amps)
PS12012 0.2 1.0 3.9 14.4
PS12013 0.4 1.6 5.8 14.4
PS12014 0.75 2.6 11.0 26.8
PS12015 1.5 4.0 15.6 38.0
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levels. Hysteresis is built into the UV and OV trip logic in order to prevent oscillations.
The version 1 and 1200V ASIPMs have 14 microprocessor compatible input and output signals.
All signals are referenced to the 5V logic power supply allowing direct connection to a CPU. Table 10
summarizes the ASIPM's input and output signals. Figure 31 shows a typical external interface circuit.
VI. CONCLUSION
ASIPMs (Application Specific Intelligent Power Modules) consisting of a combination of power
devices, low voltage ASICs and high voltage ASICs are effective for simplifying and miniaturizing the power
section of small motor drives. Maximum system benefit is achieved when the package design and integrated
functions are optimized to meet the requirements of specific applications. This paper has outlined these
system considerations and presented a series of examples demonstrating the effectiveness of this
technology.
VII. REFERENCES
[1] G. Majumdar, et al. "A New Generation High Speed Low Loss IGBT Module", ISPSD, May 1992
[2] J Yamashita, et al. "A Study on the Short Circuit Destruction of IGBT's" , ISPSD, May 1993[3] G. Majumdar, et al. "A New Generation High Performance Intelligent Module" PCIM Europe May
1992
[4] Powerex "IGBTMOD and IntellimodTM
Application and Technical Data Book" Second Edition,
PUB#9DB-200, 1998
[5] E. Motto, et. al. "A New Generation of Intelligent Power Devices for Motor Drive Applications" IEEE
IAS Conference October 1993
[6] E. Motto "Protecting High Current IGBT Modules From Over Current and Short Circuits" HFPC
Conference May ,1995
[7] John Donlon, et. al. "A New Converter/Inverter System for Windpower Generation Utilizing a New
600 Amp, 1200 Volt Intelligent IGBT Power Module" IEEE IAS Conference October 1994
[8] E. Motto, et. al. A New Intelligent Power Module With Microprocessor Compatible Analog Current
Feedback, Control Input, and Status Output Signals, 1996 IEEE IAS Conference Proceedings
[9] Eric R. Motto A New Ultracompact ASIPM with integrated HVASIC 1997 Powersystems World
conference proceedings
[10] G. Majumdar et. al. Novel Intelligent Power Modules for Low-Power Inverters 1998 IEEE PESC
Proceedings
[11] S. Noda et. al. A Novel Super Compact Intelligent Power Module 1997 PCIM Europe conference
proceedings