application of sige hetero structure

Applications of Silicon–GermaniumHeterostructure Devices

Series in Optics and Optoelectronics

Series Editors:

R G W Brown, University of Nottingham, UKE R Pike, Kings College, London, UK

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Series in Optics and Optoelectronics

Applications of Silicon–GermaniumHeterostructure Devices

C K Maiti and G A Armstrong

Indian Institute of Technology,Kharagpur 721302, India

andThe Queen’s University of Belfast,Belfast, Northern Ireland, UK

Institute of Physics PublishingBristol and Philadelphia

c© IOP Publishing Ltd 2001

All rights reserved. No part of this publication may be reproduced,stored in a retrieval system or transmitted in any form or by any means,electronic, mechanical, photocopying, recording or otherwise, withoutthe prior permission of the publisher. Multiple copying is permitted inaccordance with the terms of licences issued by the Copyright LicensingAgency under the terms of its agreement with the Committee of Vice-Chancellors and Principals.

British Library Cataloguing-in-Publication Data

A catalogue record for this book is available from the British Library.

ISBN 0 7503 0723 4

Library of Congress Cataloging-in-Publication Data are available

Consultant Editor: S C JainCommissioning Editor: Tom SpicerProduction Editor: Simon LaurensonProduction Control: Sarah PlentyCover Design: Victoria Le BillonMarketing Executive: Colin Fenton

Published by Institute of Physics Publishing, wholly owned by TheInstitute of Physics, London

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Typeset in LATEX using the IOP Bookmaker MacrosPrinted in the UK by J W Arrowsmith Ltd, Bristol

In memory ofDr Suva Maiti

CONTENTS

PREFACE xiii

1 INTRODUCTION 11.1 Evolution of bipolar technology 51.2 Heterojunction bipolar transistors 91.3 Development of SiGe/SiGeC HBT technology 131.4 Heterostructure field-effect transistors 161.5 Vertical heterostructure FETs 181.6 Optoelectronic devices 201.7 Applications of SiGe HBTs 211.8 Summary 25

Bibliography 25

2 FILM GROWTH AND MATERIAL PARAMETERS 322.1 Strained layer epitaxy 332.2 Deposition techniques 42

2.2.1 Wafer cleaning 432.2.2 Molecular beam epitaxy 442.2.3 UHVCVD 462.2.4 LRPCVD and RTCVD 472.2.5 Very low pressure CVD 482.2.6 Remote plasma CVD 482.2.7 Atmospheric pressure CVD 482.2.8 Solid phase epitaxy 492.2.9 SiGeC film growth 492.2.10 Strained-Si film growth 50

2.3 Thermal stability of alloy layers 512.4 Bandgap and band discontinuity 52

2.4.1 Si/SiGe 542.4.2 Si/SiGeC 562.4.3 Strained-Si 58

2.5 Mobility 592.5.1 Si/SiGe 592.5.2 Si/SiGeC 59

viii Contents

2.5.3 Strained-Si 632.6 Summary 64

Bibliography 65

3 PRINCIPLE OF SIGE HBTS 733.1 Energy band 753.2 Terminal currents in a SiGe HBT 773.3 Transit time 833.4 Early voltage 853.5 Heterojunction barrier effects 90

3.5.1 Effect of undoped spacer layers 923.6 High level injection 943.7 High-frequency figures-of-merit 96

3.7.1 Unity gain cut-off frequency, fT 963.7.2 Maximum oscillation frequency, fmax 98

3.8 Breakdown voltage, BVceo 993.9 Summary 100

Bibliography 100

4 DESIGN OF SIGE HBTS 1044.1 Device modelling 1064.2 Numerical methods 1084.3 Material parameters for simulation 110

4.3.1 SiGe: hole mobility 1124.3.2 SiGe: electron mobility 1134.3.3 SiGe: bandgap 1154.3.4 Recombination and carrier lifetime 117

4.4 History of simulation of SiGe HBTs 1184.5 Experimental SiGe HBTs 1194.6 Device design issues 121

4.6.1 Base design 1224.6.2 Emitter design 1264.6.3 Collector design 129

4.7 Small-signal ac analysis 1344.7.1 Small-signal equivalent circuit 1344.7.2 Evaluation of transit time 1394.7.3 ECL gate delay 141

4.8 Summary 145Bibliography 145

5 SIMULATION OF SIGE HBTS 1525.1 Epitaxial-base SiGe HBT (1995) 1555.2 Double polysilicon self-aligned SiGe HBT (1998) 1595.3 Energy balance simulation 1625.4 SiGe HBTs on SOI substrates 166

Contents ix

5.5 Low-temperature simulation 1725.5.1 Low-temperature SiGe HBTs 1735.5.2 Low-temperature simulation using ATLAS 175

5.6 I2L circuits using SiGe HBTs 1805.7 Noise performance 1825.8 Radiation effects on SiGe HBTs 186

5.8.1 Low dose-rate effects 1895.8.2 Simulation of radiation hardness 190


6 STRAINED-SI HETEROSTRUCTURE FETS 1966.1 Mobility in strained-Si 198

6.1.1 Theoretical mobility 1986.1.2 Experimental mobility 200

6.2 Band structure of strained-Si 2036.3 Device applications 204

6.3.1 Strained-Si n-MOSFETs 2066.3.2 Strained-Si p-MOSFETs 209

6.4 Simulation of strained-Si HFETs 2136.5 MODFETs 2176.6 Heterojunction Si/SiGe CMOS 2266.7 Summary 231

Bibliography 232

7 SIGE HETEROSTRUCTURE FETS 2387.1 HFETs: structures and operation 241

7.1.1 Experimental HFETs 2427.2 Design of SiGe p-HFETs 245

7.2.1 SiGe: MOS capacitor simulation 2457.2.2 Si-cap/oxide thickness variation 2467.2.3 Germanium mole fraction 2477.2.4 Choice of gate material 2497.2.5 Current–voltage characteristics 2507.2.6 δ-doped p-HFETs 252

7.3 SiGe p-HFETs on SOI 2547.4 SiGeC p-HFETs 2577.5 Devices using poly-SiGe 259

7.5.1 Poly-SiGe gate MOSFETs 2607.5.2 Poly-SiGe thin-film transistors 261

7.6 Vertical FETs 2637.6.1 Vertical SiGe HFETs 263

7.7 Noise in p-HFETs 2657.8 Summary 267

Bibliography 268

x Contents

8 METALLIZATION AND HETEROSTRUCTURESCHOTTKY DIODES 272

8.1 Deposition of metal films 2748.2 Fabrication of Schottky diodes 2768.3 Silicidation of group IV alloy films 2768.4 Silicidation with titanium 278

8.4.1 Rutherford backscattering characterization 2798.4.2 Auger electron spectroscopy characterization 2828.4.3 Sheet resistivity 284

8.5 Silicidation using Pt and Pd 2858.6 Heterostructure Schottky diodes 2878.7 Schottky diodes on strained-Si1−xGex 291

8.7.1 Barrier height and ideality factor 2938.7.2 Interface state density distribution 300

8.8 Schottky diodes on strained-Si 3038.9 Summary 305

Bibliography 307

9 SIGE OPTOELECTRONIC DEVICES 3109.1 Optoelectronic devices in silicon 315

9.1.1 p–n junction photodiode 3169.1.2 Schottky barrier photodiode 3179.1.3 p–i–n photodetectors 3189.1.4 Metal–semiconductor–metal photodetectors 318

9.2 Optical properties of SiGe and SiGeC films 3219.3 Optical devices using SiGe alloys 3259.4 Optical devices with SiGeC and GeC alloys 3349.5 Simulation of optoelectronic devices 336

9.5.1 PtSi/SiGe Schottky photodetectors 3389.5.2 SiGe p–i–n photodetectors 3419.5.3 MSM photodetectors 3459.5.4 SiGe/Si waveguide photodetectors 350


10 RF APPLICATIONS OF SIGE HBTS 35910.1 SiGe: perspective for wireless communication 36310.2 Technology comparison 36710.3 MOS versus bipolar 36910.4 SiGe BiCMOS technology 37510.5 RF circuits 378

10.5.1 Low-noise amplifiers 37810.5.2 Power amplifiers 38110.5.3 VCOs and frequency synthesizers 384

10.6 Passive components 386

Contents xi

10.7 Commercially available products 38810.7.1 TEMIC Semiconductors 38810.7.2 IBM 390


INDEX 397

PREFACE

Since the first report of SiGe heterostructure bipolar transistors (HBTs) in1987, there has been tremendous progress in SiGe research. The successfuldemonstrations of SiGe HBT technology, in both high-performance digitaland analogue circuit applications, are the results of over 15 years of steadyresearch progress from initial material preparations in 1984, through devicedemonstrations from 1987–1992 to large scale circuit fabrication in 1994and commercial products in 1998.

With the development of the ultrahigh vacuum chemical vapourdeposition (UHVCVD) system, which produces highly uniform SiGeheterostructures more rapidly than other methods, such as molecular beamepitaxy (MBE) or low-pressure CVD, only minor modifications to theprocess flow are required to incorporate the manufacture of SiGe HBTsinto a conventional bipolar or complementary metal–oxide-semiconductor(BiCMOS) line. Indeed, SiGe HBTs integrated with CMOS (BiCMOS)circuits have been shown to be substantially cheaper than III–V technology.Qualified full-scale production devices (with cut-off frequencies in the50–60 GHz range) and circuits using 200 mm wafers in a standard 0.5 µmCMOS line are now available.

SiGe HBTs are superior to Si bipolar junction transistors (BJTs) andcomparable to the best GaAs transistors, in that they are ideally suited forlow-voltage, low-power wireless communication applications. Promisingresearch results, combined with recent commercialization announcements,have generated considerable optimism. Silicon has been pushed to the1–2 GHz frequency domain. However, many new RF applications, such ashandheld and personal communication systems (PCS), direct broadcastTV, local multipoint distribution systems and wireless LANs, requirecircuit operation at frequencies up to 30 GHz.

High-speed digital communications (up to 40 Gbps) such assynchronous optical network (SONET) applications also require high-speed devices—typically with a maximum oscillation frequency, fmax inexcess of 100 GHz. It is now believed that, in many of these markets,SiGe will provide direct competition for GaAs on the grounds of costand design flexibility. Indeed, it is possible that SiGe technology may

xiii

xiv Preface

eventually be applicable in the frequency range above 30 GHz, where GaAsis currently well established, in projects requiring wireless technology fortraffic management and control, such as global positioning systems (GPS),sensor collision avoidance systems, road speed monitors and side airbagtriggers.

The application of strained-SiGe to heterostructure field-effecttransistors (FETs) is not as well developed as that of HBTs. In MOStechnology, scaling the gate length is impeded by lithographic techniquesand scaling device width is limited by the relatively low hole mobilityof a silicon p-channel metal–oxide-semiconductor field-effect transistor(p-MOSFET). When used in a heterojunction FET, strained-SiGe enhancesthe mobility of holes but not of electrons. Thus, the current drive ofthe p-MOSFET is improved, but not that of the n-MOSFET. However,strained-Si grown on a relaxed-SiGe buffer layer improves the electronmobility and current drive of an n-MOSFET. Other important researchtopics include synthesis of SiGeC, a carbon-containing alloy of SiGe and Si,and quantum-confined structures, which may ultimately offer an alternativeto lithographic techniques or serve as single-electron devices.

Integrated optoelectronics is another promising research field for SiGedevices, although development is hindered by the lack of a SiGe lightemitter. Detectors and waveguides have been demonstrated, and integratedSiGe and Si devices are possible. Work is underway on a graded bufferlayer—a virtual substrate—of SiGe that would permit III–V/SiGe/Siintegration. Possible photonic devices are under development including:low-loss optical waveguides, photodetectors for 1.3–1.6 µm, light emitters,long-wave infrared detectors, optical switches and photonic integratedcircuits.

In this textbook, we discuss the relevance of SiGe technology to allthe above application areas. The main focus of the book is on deviceapplications, backed up by an extensive survey of the literature. Chapter 1reviews the key developments in SiGe technology from the earliest researchto the present day, leading to a brief summary of the current status of SiGeproducts in the marketplace. Chapter 2 describes key technology issues forthe growth of stable strained-SiGe layers using different types of reactors.The effect of the Ge composition on strain and the consequent effecton bandgap and mobility is described. Chapter 3 gives the backgroundtheory of the HBT. Chapter 4 describes issues relating to optimal design ofSiGe HBTs and considers how device simulation can be used to determinekey indicators of device performance. Chapter 5 extends the concepts ofchapter 4 to give a number of examples of the use of device simulation tostudy a wide range of device structures involving application of SiGe.

Chapter 6 describes how growth of a strained silicon (strained-Si)layer on a relaxed-SiGe buffer layer has led to higher values of electronmobility with the resultant enhancement in the high-frequency performance

Preface xv

of heterojunction field-effect transistors (HFETs). Strategies for theenhancement of hole mobility using either MOSFET or modulation-dopedfield-effect transistor (MODFET) structures are given. The impact of bothstrained-Si MODFETs and MOSFETs as a basis for future deep submicronCMOS is considered. In chapter 7, an alternative approach to the formationof a p-HFET is described, involving growth of a strained-SiGe epitaxiallayer on a silicon substrate. Once again, the overall objective is a highermobility, in this case hole mobility, to improve both the transconductanceand bandwidth associated with the p-channel MOSFET.

Chapter 8 discusses design, characterization and application ofSchottky diodes, while chapter 9 considers the design and applicationof optoelectronic devices. Finally, chapter 10 assesses how SiGetechnology competes with other alternative technologies in the wirelesstelecommunications marketplace. It also focuses on how SiGe technologyhas rapidly matured, allowing its integration into a mixed signal BiCMOSprocess.

In summary, this book fills a gap in the literature in a rapidly evolvingfield, as it blends together wide ranging descriptions of SiGe technology,device physics and circuit applications. Where possible, the theoreticalmaterial is backed up by computer simulation. An extensive bibliographyis provided for each chapter, which helps the reader identify the key stagesin the development of SiGe from early research through to its integrationin high-performance BiCMOS.

We wish to extend special thanks to Professor S C Jain, ConsultantEditor, Institute of Physics Publishing, for his keen interest and valuablecomments. We are grateful to Tom Spicer, Commissioning Editor, for hispersonal support for this project. It was due to the skill and efforts ofhis colleagues, Simon Laurenson, Production Editor, and Sarah Plenty,Production Controller, that the project could be completed in a relativelyshort time. They deserve our sincere thanks. The help of the ProductionDepartment in removing the deficiencies in several figures is gratefullyacknowledged.

Finally, we must thank sincerely our families for their support andhelp during the preparation of this book.

C K MaitiG A Armstrong26 October 2000

Chapter 1

INTRODUCTION

Silicon is by far the most widely used semiconductor material and is likelyto remain so for the foreseeable future, although from the perspective of anintegrated circuit (IC) designer silicon is hardly a perfect semiconductor.Compared with other semiconductors, it is relatively poor in terms ofhow fast the charge carriers can move through the crystal lattice, whichlimits the speed at which silicon devices can operate. ‘Why is silicon stilldominant?’ The answer to this question is economics. Silicon is abundantin nature, non-toxic, strong and an excellent conductor of heat. It can begrown to a very high purity and very large diameter (with 12 inch nowbeing contemplated) wafers, and it readily forms a stable insulating film(SiO2 or Si3N4) of high quality. Properties of this kind make silicon anatural choice for IC manufacturing and, in fact, over the past 40 years orso, the performance of silicon ICs and the density of devices per unit areahave soared, while the cost per function has plunged (see figure 1.1). ICsare more difficult and more expensive to fabricate from III–V compoundsemiconductors such as GaAs/AlGaAs or InP. High-quality oxides arescarce in the III–V semiconductors, impeding device integration. High-purity, large diameter crystals are difficult to grow and yield is poor becauseof more defect density.

For decades, miniaturization has been the key to faster performanceof ICs. As the size of a transistor, whether field effect or bipolar,influences its speed of operation, designers have focused on creatingever smaller transistors. The strategy for enhancing the function of anelectronic device by reducing its critical dimensions is commonly referredto as scaling. Although scaling has led to improvement in the speedand flexibility of silicon-based electronics, the trend cannot continueindefinitely. Researchers are actively pursuing alternative approaches toboost the speed of electronic devices by introducing ‘bandgap engineering’.In silicon technology, two materials may be used in bandgap-engineeredtransistors: silicon carbide (SiC) and silicon–germanium (SiGe). Silicon

1

2 Introduction

Figure 1.1. Moore’s law: the gate length and cost of production lines as afunction of time. Source: National Technology Roadmap for Semiconductors,Semiconductor Industry Association, San Jose, USA, 1997. (After Paul D J 1999Adv. Mater. 11 191–204.)

carbide is a suitable emitter material, since it has a wider bandgap of2.2 eV, while SiGe is a suitable base material with a lower bandgap whichis dependent on the Ge content.

The evolution of SiGe technology has been very rapid. It has gonefrom laboratory research in less than eight years to a commercial reality.As an example, a 12-bit digital-to-analogue converter (DAC) has beendeveloped jointly by IBM and Analog Devices that processes data at1.0 Gbit s−1, which matches the speed of the best such circuits built usingGaAs technology and it operates on a fraction of the power they require.At present, aggressively designed SiGe transistors have cut-off frequenciesin excess of 130 GHz.

In recent years, SiGe transistors, and other devices based on SiGealloys, have been evident in an increasing number of products. SiGeheterojunction bipolar transistor (HBT) technology has the advantage ofrelatively simple integration with conventional complementary metal–oxidesemiconductor (CMOS) silicon circuits to form a SiGe BiCMOS technology,in which the Si bipolar devices and SiGe HBTs can be integrated for criticalhigh-speed analogue or digital functions. Silicon CMOS can serve for veryhigh density memory or compact on-chip signal processing functions, whichcannot be realized in other technologies.

The two most important devices used in silicon technology arethe bipolar and field-effect transistors, each having their strengths and

Introduction 3

Figure 1.2. Capacity of backbone network. (After Nakamura M 1998 IEEEISSCC Tech. Dig. pp 16–21.)

weaknesses. Bipolar transistors with their high transconductance havepredominantly been used in analogue applications, such as small-signalamplification, and in high-speed digital circuits, such as emitter coupledlogic (ECL). For digital circuit applications, CMOS technology dominatesbecause of its low power dissipation and high density of integration.The variety of bipolar transistors can, in general, be grouped intothose optimized to satisfy the requirements of two major industries:communications and computers.

As all activities of modern society have become information oriented,the need for high-speed and large capacity telecommunications systemsis rapidly increasing. The rapid growth in data transmission has alsocreated an urgent demand for increasing transmission capacity in backbonenetworks. Today, 10 Gb s−1 systems are in commercial use. Figure 1.2shows the predicted trend for optical fibre transmission capacity. Twomethods exist for achieving a higher transmission capacity:

(i) time division multiplexing (TDM), and(ii) wavelength division multiplexing (WDM).

Figure 1.3 shows the relationship between the bit rate and the requiredcut-off frequency (fT) of devices from differing technologies. A 10 Gb s−1

system with fT in the range 25–50 GHz can be satisfied using Si bipolartechnology, while a 40 Gb s−1 system, with corresponding fT in the range100–200 GHz, will require SiGe, GaAs or InP HBTs.

In communication applications, the increased importance oftransmitting, receiving and interpreting data transmissions at high speedshas generated a need for high-frequency precision analogue circuitry. With

4 Introduction

Figure 1.3. Electron devices for backbone network. (After Nakamura M 1998IEEE ISSCC Tech. Dig. pp 16–21).

internet host counts doubling every five to seven months, there is apressing need for high-speed interconnect circuits [1]. In these circuits,the high operating frequency, high transconductance, close matching of thedevice parameters and bandgap voltage referencing capabilities of bipolartransistors make them invaluable to the design of analogue circuits.

In the computer industry, the high-frequency performance and highcurrent drive capabilities of bipolar transistors enable the realization ofdigital circuits with very low gate delay and high fan-out compatibility. Theswitching delay of a bipolar circuit is made up of three major components.The importance of these two characteristics can be best illustrated bya graph of the ECL gate delay time versus the collector current of thebipolar transistors, as shown in figure 1.4. In the low collector currentrange, the gate delay is a function of the load resistance, RL, and the inputcapacitance of the gate, Cin, which is determined by the capacitance ofthe bipolar transistors as seen from the gate input. In the high collectorcurrent range, the gate delay decreases, approaching a minimum set bythe total forward transit time of the transistor, τF. At higher currents,the product of the combination of extrinsic and intrinsic base resistanceand the diffusion capacitance begins to dominate the propagation delay.As is evident from figure 1.4, the realization of low gate delays requiresthe use of increased collector currents. Thus, if the operating current pergate is a limiting factor, the design should be focused on the reduction ofparasitic capacitances. The delay contributed by each part of the transistoris different, depending on the type of circuit used.

Evolution of bipolar technology 5

Figure 1.4. Variation of delay components of a bipolar circuit versus collectorcurrent. At low currents, the gate delay is determined by the charging of thejunction capacitances. At high currents, the minority carrier storage associatedwith high-level injection prevails.

However, power consumption and dissipation restrictions in digitalbipolar circuits limit the collector current of the densely packed transistors.For high-speed digital applications, the challenges for designers of bipolarjunction transistors (BJTs) include an increased level of integration, loweroperating currents, reduction in base resistance and lower minimum gatedelays.

1.1. EVOLUTION OF BIPOLAR TECHNOLOGY

The design and study of a new semiconductor device structure hold promiseat both the device level, where the transistor’s electrical behaviour may leadto novel effects, and the circuit level, where the device characteristics maybe exploited to enhance functional performance. Since the revolutionaryinvention of the point-contact transistor at Bell Laboratories in 1947,numerous new transistor structures have been proposed and demonstrated.Of the many transistors demonstrated in the last fifty years, however, theIC market is dominated by just two devices: the BJT with a market shareof about 20%, and the metal–oxide semiconductor field-effect transistor(MOSFET) with 75%. BJTs and MOSFETs are the dominant high-performance devices in silicon technology. In this section, we shall presentan overview of the high-performance transistors in silicon.

6 Introduction

Figure 1.5. (a)–(g) The evolutionary continuum between bipolar and field-effecttransistors. A conventional FET is shrunk in lateral dimension (a), thenconverting to a stacking configuration (b). Rotating the structure by 90 produces(c). Reducing the vertical dimensions from (c) to (e) yields a permeable basetransistor. Replacing the grid with a sheet of metal produces a metal-basetransistor (f). Finally, replacing the metal base with a p-doped layer results inthe conventional bipolar transistor (g). (After Stoneham E B 1982 Microwaves55–60.)

Evolution of bipolar technology 7

The FET represents a class of devices (including MOSFETs, metal–semiconductor field-effect transistors (MESFETs) and junction field-effecttransistors (JFETs)) which operate on a principle substantially differentfrom that of the class of devices represented by the BJT. FETs representlateral geometries and spatial charge control (via depletion regions), whileBJTs represent vertical geometries and charge control. An ideal three-terminal device may be considered to move the charge within a finite time,when stimulated by some input voltage or current. Stoneham [2] has shownthat most new devices lie somewhere between the extreme cases of BJTsand FETs. By manipulating the geometries and translating lateral andvertical properties, the evolution of one device into the other is possible asshown in figure 1.5.

Although MOSFETs have constantly challenged the BJTs forperformance superiority, bipolar devices have consistently kept theiradvantage by evolving new and/or improved process and design. Thehistorical advantage of the bipolar device is the fact that its verticaldimensions are easier to control than the lateral MOS structure. Currentgain in a homojunction npn bipolar transistor is mainly determined by theratio of the density of electrons injected from the emitter into the base andthe density of holes reinjected from the base into the emitter, and results ina finite dc current gain. Many attempts have been made to design improvedemitter structures to minimize the disadvantages of the homojunction SiBJT with a heavily-doped emitter. Among these, polysilicon technologyis by far the most advanced but problems with contact resistance stillexist. Techniques to reduce contact resistance lead to reduced emitterefficiency [3, 4].

In a circuit environment, however, parasitics tend to dominate. Thebase–collector extrinsic junction and the base resistance prevent inputsignals from reaching the appropriate internal junctions until sufficientcharge has filled the depletion regions (in the case of the base–collectorcapacitance), while the base resistance reduces the voltage seen by theinternal emitter–base junction, lowering the effective transconductance.The steady improvement in performance of the BJT is the result oftechnology maturing sufficiently to build these scaled optimal structures.The evolution of new process technologies, such as silicon-on-insulator(SOI), trench isolation and epitaxial regrowth, provide techniques todrastically reduce the junction capacitances. These techniques have pushedthe evolution of the transistor to its technical limits. As lateral geometriescontinue to shrink, devices require vertical design modifications in order tomaintain higher performance.

Several alternative structures have been proposed in the literatureto extend the performance of silicon bipolar devices. The metal-basetransistor at one time held the most promise of all hot electron devices [5].The injection of electrons from the emitter occurs as in a BJT, but electrons

8 Introduction

entering the base from the emitter see a large band discontinuity. Thisaccelerates them to a large momentum in the vertical direction. Thebase being very narrow, electrons remain hot throughout the base region,resulting in a reduction in the base transit time. In addition, the use of ametal for the base reduces the base resistance. In principle, the metal-basetransistor should have a significant performance advantage over the BJT.Unfortunately, no metal-base transistor has yet achieved even unity currentgain.

Nishizawa [6] proposed a high-speed switching device known as thebipolar static induction transistor (BSIT) which may be thought of asa bipolar transistor with the intrinsic base region missing. Control ofcollector current in this device is only possible because the extrinsic p+

base regions are physically close together and current is controlled byforward biasing the base–emitter junction. A high transconductance isobtained compared to FETs of comparable dimensions and also leadsto faster switching times. Indeed, several types of circuits have beensuccessfully fabricated with the BSIT device [6, 7]. However, due to itsextreme sensitivity to process variations, the BSIT could hardly be usefulfor high levels of circuit integration.

Another interesting structure, a tunnel transistor, which is identicalto that of a p-channel MOSFET with a very thin (20 A) gate oxide layerhas also been proposed [8]. The thin oxide layer allows substantial electrontunnelling currents in the vertical direction. The gate can thus act asan emitter, the substrate as a collector and the source/drain regions asextrinsic base regions. The intrinsic base is replaced with a mobile holelayer or ‘inversion channel’ whose charge density modulates the electricfield strength across the oxide, and thus controls the electron tunnellingcurrents in the vertical direction. This hole charge density is controlled bythe extrinsic base potential. Using this concept, Simmons and Taylor [8]have theoretically and experimentally studied tunnel transistors built inthe AlxGa1−xAs/GaAs material system. GaAs was used as the emitterand the collector semiconductors and AlAs was used as a wide bandgapsemiconductor replacing the insulator. However, limited current densityand transconductance resulted in a much slower device.

Despite much research on alternative technologies, silicon integratedcircuits dominate mainstream electronics. Impressive improvements inhigh-speed Si bipolar technology have been made in the last few years.Self-aligned bipolar transistors having polySi base electrodes have beeneffective in reducing base resistance through their small resistance in thebase electrode and short length between the emitter and the base.

Si homojunction transistors with a maximum oscillation frequency,fmax above 80 GHz have been obtained using low base resistance self-aligned metal/IDP (SMI) technology. The base resistance is reduced to ahalf compared to conventional polySi technology and a 12.2 ps gate delay

Heterojunction bipolar transistors 9

Figure 1.6. Si and SiGe device performance over the past several years. In termsof device speed, SiGe has maintained about 50% advantage over Si devices.

time in an ECL ring oscillator at a voltage swing of 250 mV has beenachieved [9]. In 1999, Bopp et al [10] reported a near production, standardimplanted base silicon bipolar technology for mixed-signal applications.Applicability for mobile communications up to at least 6 GHz, and forhigh-speed data links in the range 10–40 Gbits s−1, was demonstrated.Transistors exhibited an fmax of 65 GHz, a minimum noise figure of 1.3 dBat 6 GHz and a 12 ps ECL gate delay.

Summarized in figure 1.6 are some of the reported results obtainedwith high-performance Si homojunction transistors. Although the datafor Si are only plotted up to 1997, the trend line shows that SiGe offersapproximately 50% advantage in overall device performance. By way ofcomparison, back in 1991, AlGaAs/GaAs MODFETs achieved an fT ofover 250 GHz [11] and exceeded the 400 GHz barrier for fmax. In aneffort to improve single chip functionality, it is not surprising that, despiteincreased process complexity, BiCMOS processes have been developed tocombine the advantages of CMOS and bipolar devices [12].

1.2. HETEROJUNCTION BIPOLAR TRANSISTORS

The idea of varying the bandgap in a bipolar transistor structure to increasethe emitter injection efficiency is almost as old as the bipolar junctiontransistor itself. Shockley described the idea in his application for apatent on the junction bipolar transistor [13]. The inherent performanceadvantages of HBTs over conventional bipolar junction transistors havebeen recognized and Kroemer [14] first explained the underlying principle

10 Introduction

of the heterojunctions. The heterojunction offers a larger set of deviceconfigurations and has become the basis for the so-called field of bandgapengineering [15].

The principle of operation of an HBT is identical to that of the BJT,except that the bandgap of the emitter region exceeds that of the baseregion by ∆Eg, typically of the order of 0.1–0.2 eV. The resultant e∆Eg/kT

exponential increase in current gain permits scaling of the base region tosmaller thicknesses and higher doping levels. Conceptually, the simplestway to incorporate a heterojunction into a silicon bipolar transistor processis to replace the polySi emitter of a standard bipolar process with awide bandgap material having a high-quality interface to the silicon base,thereby combining the minimized parasitic capacitances and resistancesof the device structure with the increased emitter injection efficiency ofthe wide bandgap emitter HBT. Several wide bandgap materials havebeen investigated, such as GaP [16–18], semi-insulating polycrystallinesilicon (SIPOS) [19–21], oxygen-doped silicon epitaxial films [22], epitaxialβ-SiC [23], polycrystalline β-SiC [24], amorphous silicon (α-Si) andmicrocrystalline (µc-Si) silicon [25–27]. Major problems encountered wereantiphase domains and cross doping (GaP), high bulk or contact resistance(α-Si and poly-β-SiC), and high processing temperature (single crystallineβ-SiC). Moreover, it seems difficult to realize ideal, or at least reproducible,base currents with these materials [26, 28]. β-SiC can now be grown at750 C, greatly improving its prospects for integration into Si HBTs withnarrow and heavily-doped bases.

A key point concerning wide bandgap emitter silicon HBTs is that theshape of the conduction band barrier in the base is identical to that of an Sihomojunction transistor. It is therefore impossible to obtain improvementsin transit time and output resistance associated with a bandgap gradingbetween the emitter and collector sides of the base leading to a built-indrift field for the minority carriers in the base. Some of these structuresmay prove useful for special applications. However, in general, these havenot been accepted by the semiconductor industry due to the difficulties inprocess optimization and reproducibility.

Although the performance advantages of HBTs over BJTs were wellunderstood, no fabrication technologies were available to produce high-quality heterojunctions until the 1970s. The emergence of two new growthtechniques, namely molecular beam epitaxy (MBE) [29] and metal–organicchemical vapour deposition (MOCVD) [30], sparked a thrust in the researchof high-speed HBTs. Most research has been on the AlGaAs/GaAssystem and related compound semiconductors. The high performancedemonstrated by HBTs is a result of not only the inherent advantagesof heterojunctions, but also the use of semiconductor materials with highermobilities and saturated drift velocities. For instance, implementation of anAlxGa1−xAs/GaAs HBT has yielded the lowest demonstrated gate delay of

Heterojunction bipolar transistors 11

1.9 ps, and an AlInAs/InGaAs HBT has given a unity current gain cut-offfrequency exceeding 200 GHz.

Despite the advances in HBT fabrication techniques, mostly usinggroup III–V and II–VI materials, silicon devices continue to dominatedue to the low cost and ease of manufacturability. Silicon readily formsa high-quality oxide which can be used to mask implants, diffusionand metallization. The isolation technique, chemical vapour deposition,diffusion, ion implantation, contact technology and etching methodsare highly developed in Si technology. GaAs and the other III–Vsemiconductors lack this important property.

It is well known that GaAs or InP technologies exhibit superior fTand fmax, compared to a SiGe device, for a specified geometry. Anexcellent comparison of the technologies has been presented by Konig andGruhle [31]. Plots from [31] of both fT and fmax as a function of basewidth are shown in figures 1.7 and 1.8. A further performance comparisonof a III–V material HBT with a SiGe HBT has been presented by Larson[32]. Clearly, if maximum bandwidth or speed is the only criterion, then

Figure 1.7. Comparison of cut-off frequency, fT, as a function of base widthfor SiGe HBTs and devices from III–V technologies. (After Konig U andGruhle A 1997 Proc. IEEE Cornell Conf. on Advanced Concepts in High SpeedSemiconductor Devices and Circuits pp 14–23.)

12 Introduction

Figure 1.8. Comparison of maximum frequency of oscillation as a function ofbase width for SiGe HBTs and devices from III–V technologies. (After Konig Uand Gruhle A 1997 Proc. IEEE Cornell Conf. on Advanced Concepts in HighSpeed Semiconductor Devices and Circuits pp 14–23.)

III–V technology is a superior option. In overall radio frequency (RF)system performance, including antenna interfacing, low noise and low poweramplifier performance and relatively high levels of integration, SiGe HBTtechnology offers significant advantages, as summarized in table 1.1.

Table 1.1. Technology comparison in the frequency range of 1–10 GHz. (AfterTemic Semiconductors, Germany.)

Si BJT SiGe HBT GaAs FET

Low-frequency noise + + −Low RF noise O + +Low voltage + + OHigh gain − + +High power − + +High efficiency − + +Analogue capability O + +Integration level + + OPower supply + + −

Development of SiGe/SiGeC HBT technology 13

1.3. DEVELOPMENT OF SIGE/SIGEC HBT TECHNOLOGY

As silicon BJTs reach their fundamental limits on speed because of thephysical properties of the semiconductor material, advanced high-speeddevices require heterojunction technology, as has been demonstrated inthe previous section. Although Ge had made its mark as the point-contactelectrode on the first transistor, Si eventually became the semiconductorof choice for its material properties. In 1957, Kroemer patented the firstheterojunction Si bipolar transistor and eighteen years later, Erich Kasperat Daimler–Benz (now Daimler–Chrysler) made the first SiGe strainedlayer [33]. With the advent of heteroepitaxy, the concept of strainedlayers has been extended to include other elemental semiconductors. Thesedevelopments set the stage for IBM’s development of SiGe HBTs in 1987using MBE. The use of the ultrahigh vacuum chemical vapour deposition(UHVCVD) tool for HBT and BiCMOS devices followed.

SiGe HBTs are particularly exciting because of their ability to takeimmediate advantage of highly developed silicon processing techniques.Impressive improvements in high-speed SiGe bipolar technology have beenmade through the growth of device quality strained-Si1−xGex layers. Thisstrain, which occurs because of a ∼4% difference in the lattice constantsof Si and Ge, is used to vary the bandgap energy, band discontinuitiesand other properties of the material. For any given Ge content, thereis a critical thickness of SiGe, above which dislocations cause severeperformance degradation, as discussed more fully in chapter 2. The thinbase layer of Si1−xGex, sandwiched between the Si collector and emitter,must be thin enough to prevent the formation of these dislocations. Ofadditional significance is the enhanced mobility in a strained layer whichoffers the possibility of improved performance in SiGe-based FET devices,as discussed in chapters 6 and 7, although much of this work is still in theresearch stage. Higher mobility in digital circuits permits a smaller voltageswing to switch between states, leading to both faster switching times andreduced power consumption.

Although the introduction of Ge in the base increases processintegration complexity, it offers an additional degree of freedom whichrelaxes a series of trade-offs affecting device design. Several key advantagesover conventional bipolar transistors include:

• reduction in base transit time—resulting in higher frequencyperformance;

• increase in collector current density and hence current gain;• lower intrinsic base resistance; and• increase in Early voltage.

The design of a SiGe HBT, for a particular technology generation, isoptimized by appropriate scaling of the emitter, base and collector regions

14 Introduction

and their associated doping profiles. A SiGe HBT offers additional designflexibility in that the bandgap of the base may be tailored by gradingthe Ge concentration. Reducing the width of the base region reduces thebase transit time with associated improvement in cut-off frequency, butinevitably increases overall base resistance with possible reduction in fmax.For effective design, it is thus essential to use an appropriate simulationtool. Many of the significant issues have been published in a number ofreports dealing with aspects of both numerical and analytical modelling ofSiGe HBTs [34–41]. In chapters 4 and 5 of this book, we discuss the designconsiderations for SiGe HBTs in terms of the following:

• optimization of base, emitter and collector doping profiles;• effect of Ge profile on the transit times;• prediction of cut-off frequencies, fT and fmax; and• design issues at low temperature.

Since the first report of SiGe HBTs in 1987, there have been numerousdemonstrations (see figure 1.6) of its impressive potential. For example,an early theoretical study [42] predicted a unity gain cut-off frequency inexcess of 300 GHz. Since then there have been a number of significantmilestones in the measured performance of SiGe HBTs, including fT inexcess of 130 GHz [43], fmax values of 160 GHz [44], ECL and currentmodel logic (CML) gate delay of less than 10 ps [45–47]. Recently, anSi/Si0.65Ge0.35 abrupt SiGe HBT with an fT of 213 GHz and fmax of115 GHz at 77 K has been reported [48]. Summarized in table 1.2 are someof the reported results obtained with high-performance SiGe HBTs, whichrelate to state-of-the-art performance in commercially available devices.

The addition of substitutional carbon to silicon–germanium thin films

Table 1.2. Some of the commercially available (as of 1998) device results fromvarious SiGe research groups.

Group IBM IBMparameter (1996) (BiCMOS) NEC HP Daimler–Benz

fT/fmax 48/60 48/60 60/50 40/– 59/90(GHz) 113/65

Rbi/Rb 7–9 k 7–9 k – 40k 380–780(Ohms/square)

Wb 700–1000 700–1000 – 500–600 150(A) w/spacers

Ge Profile 0–15% 0–15% 15% 16% 30%various various graded graded uniformshapes shapes

Development of SiGe/SiGeC HBT technology 15

leads to a new class of semiconducting materials (SiGeC) [49, 50]. Thisnew material can remove some of the constraints (such as the critical layerthickness) on strained-Si1−xGex and may help to open up new fields ofdevice applications for heteroepitaxial Si-based systems. The incorporationof carbon [51] can be used:

• to enhance the SiGe layer properties;• to obtain layers with new properties; and• to control dopant diffusion.

A summary of possible applications of C-containing Si and SiGe filmsare shown in table 1.3.

The incorporation of a low concentration of carbon (<1020cm−3) inthe SiGe region of SiGe HBTs can suppress boron out-diffusion caused bysubsequent processing steps [52]. This allows one to use higher boron doseswithin the SiGe base layer and/or narrower undoped SiGe spacers, leadingto a significantly improved transistor performance. For example, SiGeCHBTs have demonstrated excellent fT and fmax values [53] comparable tothe performance of state-of-the-art SiGe HBTs, as shown in figure 1.9.

The presence of carbon also relaxes technological process designconstraints by reducing the sensitivity of dopant profiles to subsequentprocessing steps. When compared with SiGe technologies, the additionof carbon offers a significantly greater flexibility in process designand a greater latitude in processing margins [54–56]. Basic growthtechniques, the mechanical and electrical properties of Si1−x−yGexCy layers

Figure 1.9. Cut-off and maximum oscillation frequencies versus collector currentfor SiGeC HBTs. (After Osten H J et al 1999 IEEE BCTM Proc. pp 109–16.)

16 Introduction

Table 1.3. Possible applications of C-containing Si and SiGe films. (AfterOsten H J et al 1998 Thin Solid Films 321 11–14.)

Material advantages Possible device applications

Increase performance andprocess margins for HBTsSuppress transient enhanceddiffusion of boronReduce undoped SiGe spacers HBT

Increase thickness, stability,Ge content of Si1−xGex p-Channel FET, npn HBT

Use strained-Si1−yCy on Siinstead of Si on relaxed buffer n-Channel FET, pnp HBT

Design new buffer conceptswith Si1−x−yGexCy

Use the reduction ofdislocation propagation Virtual substrates for hetero-FETs

Strain symmetrization on Si Superlattices on Si(001) for opticalapplications

grown pseudomorphically onto Si(001) and their applications have beencomprehensively reviewed by Osten [57].

1.4. HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS

The Semiconductor Industry Association (SIA) roadmap for CMOStechnology predicts that the minimum feature size will approach 10 nmby 2024. For the most aggressively scaled DRAM, the scale of integrationwill reach 64 Gbits in 2010. The slowing of the scaling rate noted inthe roadmap indicates several key technological hurdles that must besurmounted in order to attain the milestones of the roadmap. Thesechallenges encompass almost all aspects of device science, processingand integration architectures including interconnections and patterningtechnology.

The field-effect transistor (FET) is customarily a lateral structure,while the bipolar transistor discussed in the previous section is, in general,vertical. The first insulated gate field-effect transistor (IGFET) wasdemonstrated in 1960, a metal–oxide semiconductor FET (MOSFET)which uses silicon as the semiconductor and silicon dioxide as the insulator.A primary reason for the success of this device is the passivating effect thatthe silicon dioxide has on the underlying silicon interface. For this reason,

Heterostructure field-effect transistors 17

the most successful IGFETs are still silicon-based MOSFETs. MOSFETsusing an n-channel (i.e., with electrons rather than holes as the chargecarriers between n-type source and drain), are smaller than those of p-MOSdue to the higher electron drift velocity.

Because of the technical difficulty in passivating other semiconductormaterials, other successful FET structures which avoid the need forpassivation have also been proposed. In the metal–semiconductor FET(MESFET), the insulating layer is replaced with a Schottky contact. Theneed for passivation of column III–V semiconductors, such as GaAs, iscircumvented at the expense of substantially larger gate leakage currents.The high-performance MESFETs are generally n-channel due to the higherelectron drift velocity. In scaling down the classical planar MOS devicetowards deep submicron dimensions, the most important technologicallimit encountered is the definition of the channel length by lithographictechniques. From a physical point of view, the short channel effect,which translates into drain-induced barrier lowering (DIBL) and as suchinto threshold voltage roll-off and off-state leakage current, is the mostimportant limitation.

Heterojunction FETs (HFETs) can be pictured as a hybrid betweenthe MOSFET and MESFET and are the high performing junction FETs.Instead of a very wide bandgap oxide, a moderately wide bandgapsemiconductor is used as the insulator. Often this layer is doped withimpurities, but the resulting charge carriers are localized in the narrowerbandgap and therefore lower potential, second semiconductor. Due to theseparation of doping and charge carriers, the resulting FETs are frequentlyreferred to as modulation-doped field-effect transistors (MODFETs). Analternative name, high electron mobility transistors (HEMTs) is derivedfrom the much higher mobilities that result from modulation doping,since the physically segregated impurities are less effective in scatteringthe charge carriers. However, for high-performance short-channel devicesfabricated to date, the mobility plays only a small role, and it is thesaturated drift velocity which determines the channel transit time of anFET.

In the area of SiGe electronics, the bulk of the effort has concentratedon HBTs. However, the inherent capabilities of an Si/SiGe heterostructurecan also be applied to create SiGe-based modulation-doped FETs, aswell as being inserted into MOS structures to create heterostructurecomplementary metal–oxide semiconductor (HCMOS) transistors, in whichthe Schottky gate, used in a MODFET, has been replaced with a MOS-gate [58].

Typically, n-MODFETs use Si quantum wells (QW), whilep-MODFETs use a SiGe or a Ge QW, with both structures requiringthe growth of a thick SiGe buffer layer. Ismail [59] has reported on0.4 µm gate length n-MODFETs with a measured peak transconductance

18 Introduction

of 420 mS mm−1, which is about a factor of two higher than Sin-MOSFETs. This MODFET exhibited an fT and fmax of 33 and40 GHz, respectively. Introduction of the graded SiGe buffers dramaticallyincreases two-dimensional electron gas (2DEG) mobility values as high as180 000 cm2 V−1 s−1 at low temperature for n-MODFETs. However, whatis more important for device applications is room temperature mobility,which is found to range from 1000 to 3000 cm2 V−1 s−1—a factor of fourto six times greater than for Si-only MOSFETs. A 0.7 µm gate lengthSiGe p-MODFET has shown peak transconductance of 200 mS mm−1,while similar transconductance values for Si-only p-MOSFETs can only beachieved with gate lengths reduced to 0.2 µm or below. The p-MODFETsexhibited an fT and fmax of 10 and 18 GHz, respectively, along withroom temperature mobilities of 1400–1800 cm2 V−1 s−1—a factor of sixto nine times those above standard p-MOSFETs with comparable doping.Simulation studies on the performance of complementary MODFETstructures predict, for a 0.1 µm gate length device, peak transconductanceof 820 mS mm−1 for an n-MODFET, and 610 mS mm−1 for a p-MODFET,comparable to the performance achievable with III–V-based materials.

The application of strained-SiGe layers to FETs is not as welldeveloped as HBT applications. A fundamental limitation has been thatstrained-SiGe enhances the mobility of holes but not electrons. Thus,the current drive of p-FET devices is improved, but not that of n-FETs.However, strained-Si grown on a relaxed-SiGe layer improves electronmobility and n-FET device performance. Techniques for forming high-quality relaxed-SiGe on Si substrates have demonstrated performanceimprovements for both n- and p-HFETs [60–62].

Hartmann et al [63] have proposed that SiGeC alloys may offeran increased leverage in CMOS technology, just as SiGe has increasedthe performance of bipolar technology. It has been shown that bothelectron and hole confinement appear possible without the need of relaxedbuffer layers, making the SiGeC alloy a potential for CMOS technology.Recently, Quinones et al [64] have presented the evaluation of the strain-stabilizing capabilities of C in the SiGe material system by fabricatingSiGeC heterojunction p-MOSFETs over a range of Ge concentrations.Several excellent reviews on the possibilities and potential of the SiGe-channel MOSFETs for a submicron CMOS technology have also appeared[65–67].

1.5. VERTICAL HETEROSTRUCTURE FETS

Vertical MOS structures are being explored for increasing the integrationdensity and for incorporation of quantum effects into MOS devices.Vertical MOS heterostructures are expected to solve the scaling issuesof lithography, doping confinement and DIBL. Vertical devices will have

Vertical heterostructure FETs 19

small contact areas and will facilitate interconnects and minimize the viacontacts leading to a minimization of the area per function. Presentprojections, based on the operation of a 20 nm channel length verticaldevice at room temperature, result in an on-current of 20 000 µA µm−1,an off-state current less than 1 pA µm−2, a peak transconductance of morethan 3500 mS mm−1, a VT of less than 0.3 V at VDD of 1 V and an intrinsiccarrier transit time of less than 1 ps.

In establishing its potential advantages and assessing its performancewith respect to conventional transistors, a technology which providesdenser and faster structures, and uses the standard processing technologyand production equipment, research has been initiated. In fact, theSiGe technology has been implemented in the Si process lines by severalmanufacturers and is expected to facilitate a low-cost transfer of the newvertical SiGe heterostructure MOS into production. In addition, a CMOSpossibility also exists if the heterojunction is made by a SiGe/Si(p-MOS)or SiGe/Ge(n-MOS) combination. All these materials are compatible withSi technology and allow for an easy integration into production.

A vertical heterostructure MOS (VHMOS) has the followingadvantages.

• The device is not a lateral but a vertical one; source/channel anddrain regions are grown epitaxially. As such the device channellength is defined by the channel layer epitaxial growth and thus fullydecoupled from lithographic limitations. Therefore, much shorterchannel lengths (down to 20 nm) become feasible.

• At the source side of the device, a heterojunction is used which keepsthe barrier for conduction in the off-state constant and not affectedby the drain voltage. In order to have conduction in the on-state,the source side closest to the channel region is intrinsic. This allowsfor Fermi-level modulation by the action of the overlapping gate andthus conduction. The DIBL effect no longer exists [68].

The experimental evidence of the enhancement of out-of-plane holemobility in SiGe using a vertical p-MOSFET structure, fabricated byhigh-dose Ge implantation followed by solid phase recrystallization, hasbeen reported [69]. The structure combines the merits of a very shortchannel device without a critical lithography process and a higher holemobility in the channel region. Superior performance with respect toa homojunction structure has been demonstrated, especially for deepsubmicron dimensions. Although the p-MOS devices have been reportedso far, similar work is being performed on n-MOS devices with strained-Si/SiGe in the source/channel and drain regions. However, in this case, avirtual substrate consisting of a relaxed-SiGe layer is needed [68,70].

Up to this point, we have described the major application areas whereSiGe technology has become established. However, there are a number of

20 Introduction

other application areas in which SiGe devices may have a role to play.Bipolar inversion channel field-effect transistors (BICFETs) have beenstudied extensively theoretically [71] as well as experimentally in SiGematerials [72–74]. Taft and Plummer [71] implemented the concept inthe SiGe material system in order to take advantage of the establishedSi technology and showed that the SiGe BICFET could potentially fulfilboth the ends: high performance (due to its intrinsic speed advantage) andmanufacturability (due to the lower costs of silicon processing). Kasperand Reitemann [75] have explored the idea of a common device structurefor different functions by combining a SiGe HBT and a charge injectiontransistor (CHINT) on Si–SiGe–Si–SiGe [76]. It is a hot electron device;VDS accelerates the carriers, which cross the SiGe–Si barrier to be collectedat the real space transfer output as stated.

1.6. OPTOELECTRONIC DEVICES

The optoelectronics realm has traditionally been reserved to III–Vand II–VI compound semiconductors, due to the availability of directtransitions and heterostructures. However, the introduction of SiGe allowsheterostructures to be fabricated in traditional Si-only technologies, whichexpands the potential of Si optoelectronics. A conceptual integrated siliconchip of the future including CMOS, HBT/bipolar, SiGe quantum devices,SiGe detectors, SiGe waveguides and light emitter all on a chip is shownin figure 1.10. Integrated optoelectronics is another promising research

Figure 1.10. The integrated silicon chip of the future: CMOS, HBT/bipolar,SiGe quantum devices, SiGe detectors, SiGe waveguides and light emitter all ona chip. (After Paul D J 1998 Thin Solid Films 321 172–80.)

Applications of SiGe HBTs 21

field for SiGe devices, although development is hindered by the lack of aSiGe light emitter. Detectors and waveguides have been demonstrated, andintegrated SiGe and Si devices are possible.

Si-based heterostructures, such as Si/SiGe, offer the possibility ofimproving the standard Si device performances, particularly in high-frequency and low-noise applications, with the additional advantage ofstill being compatible with mainstream Si technology. Furthermore, SiGemicrostructures can also enable the integration of optical devices (LEDsand photodiodes) with silicon-based integrated circuits.

Research has been initiated on a graded buffer layer of SiGe—a virtualsubstrate—that would permit III–V/SiGe/Si integration and open the doorfor integrated optoelectronics [77]. The growth of device quality GaAsepitaxial layers on Si substrates is a long-range goal of electronic materialsresearch. The epitaxial growth of GaAs on Si substrates through the use ofa Ge/graded-Si1−xGex/Si buffer layer would allow monolithic integrationof GaAs-based optoelectronics with Si microelectronics [78].

1.7. APPLICATIONS OF SIGE HBTS

The revolution in wireless communications has been brought about bya combination of advances in digital integrated circuit technology, RFcomponents, digital communications and networking techniques [79]. RFcommunication systems can be broadly categorized in two market sectors,namely, ‘low-end’ such as pagers, cordless phones etc, and ‘high-end’such as personal communication service (PCS), GSM, IS-136 etc. SiGeHBTs are suitable for applications in the high-end applications wherethe best performance is essential, while CMOS technology will dominatethe low-end applications. Several excellent reviews of research in wirelesscommunications systems presently in use may be found in [32,80,81].

Figure 1.11 shows the present wireless system trends. The verticalaxis is a measure of mobility, and the horizontal axis is the informationrate. Analogue cellular systems are called first generation systems, andthe present digital cellular and digital cordless systems are called secondgeneration systems. The third generation systems, however, only representa midpoint in the planned development of mobile communication systems.Fourth generation systems will provide high bit rates of more than 2 Mbpsunder high mobility conditions.

The sell-off of rights to the spectrum by the US FederalCommunications Commission is creating a large market opportunity forSiGe in the USA, while the same trend is occurring elsewhere in the world.Components for PCS devices operating between 1.8–2.2 GHz are a fastgrowing market segment, along with pagers, beepers and wireless localarea networks. The implementation of a complete RF integrated circuit ona single silicon chip is a complicated task, as wireless circuits have a very

22 Introduction

Figure 1.11. Wireless system trends. (After Muraguchi M 1999 Solid-StateElectron. 43 1591–8.)

Figure 1.12. Selected high-frequency applications and allocated frequencybands between 1 and 100 GHz. The three market segments labelledcommunication, traffic and navigation will drastically expand in the next fewyears, mainly in the range up to about 10 GHz. (After Schaffler F 1998 ThinSolid Films 321 1–10.)

Applications of SiGe HBTs 23

broad range of requirements including noise figure, linearity, gain, phasenoise and power dissipation. The advantages and disadvantages of eachof the competing technologies Si CMOS, BJTs, Si/SiGe HBTs and GaAsMESFETs, HEMTs and HBTs have been examined by Larson in the lightof these requirements [79].

Wireless communication systems require very high efficiency poweramplifiers to extend battery life, simplify thermal design, and reduce thecost of handheld phones. In order to serve this new high volume market,faster and more powerful integrated circuit chips are required. For manyof these applications, as shown in figure 1.12, all-silicon transistors havebeen pushed to the 1–2 GHz frequency domain. However, many new

Table 1.4. Summary of several circuits reported in the literature using SiGeHBT technology.

Reference Circuit type Results

[10] Transceiver complete chip[82] Limiting amplifier 60 dB Gain

55 dB dynamic range 10 Gb s−1

[83] Optical receiver 40 Gb s−1 analogue IC[84] Mixer Conversion loss 6.5 dB,

LO power 10 dBm1/f noise corner frequency 3 kHz, 1mA

[85] Radio transceiver 900/1900 MHz, 2.7 V[86] 6.25 GHz LNA NF 2.2 dB, gain 20.4 dB

Dissipation 9.4 mW, 2.5 V supply[87] 1.88 GHz power amplifier Power gain 16 dB, PAE 53%[88] ECL inverter chain 16 ps/stage, 660 µA @ 3.3 V[88] 2.4 GHz downconverter LNA: gain 10.5 dB

(LNA + mixer) NF 0.95 dBMixer: +4 dBminput intercept 5 mA @ 1 V (total)

[88] Broadband amp Gain 8 dBBandwidth 17 GHz16.8 mA @ 2.5 V

[89] 12 GHz VCO 19 dBm, 5% tuning range,−80 dBc Hz−1 phase noise

[89] 12 GHz active mixer >0 dB gain @ +3 dBm LO,100 KHz IF BW, 30 dB isolation

[89] 12 GHz power amp >6 dB gain, 19 dBm output[90] 1/128 frequency divider 6.4–23 GHz, 1.5 W[91] RZ comparator 5 GHz, 1.5 V, 89 mW[92] Gilbert mixer Bandwidth 12 GHz GBW >22 GHz[93] 12-bit DAC 1.2 Gsps, 750 mW

24 Introduction

RF applications require circuit operation at frequencies up to 30 GHz,a regime well out of the realm of devices based solely on Si. A numberof circuit designs have been fabricated in SiGe technology in order todemonstrate its capability in the RF marketplace. Among the circuitsthat have been reported are: voltage controlled oscillators (VCOs), low-noise amplifiers (LNAs), power amplifiers (PAs), mixers and digital delaylines. Several reported circuit results are presented in table 1.4, and a morecomprehensive survey is included in chapter 10.

An exciting example of a communications application is the 10 Gbpsdata transmission system designed by Alcatel using advanced IBM SiGetechnology [94]. In this system, SiGe technology has made a significantcontribution toward the implementation of a cost effective transmission ona standard optical fibre, offering operators the advantage of upgrading theirexisting networks to terabit speed, without the time and cost of laying newcables.

Table 1.5. List of devices available in the SiGe BiCMOS technology. The maincharacteristics are provided for each device which are available to the designersto make a full custom design. (After Brenner et al 1999 IBM MicroNews 5 1–4.)

Device Parameter

1 npn SiGe HBT fT = 47 GHzfmax = 65 GHz

2 npn Higher breakdown SiGe HBTfT = 27 GHz, fmax = 55 GHz

3 n-FET ID,sat = 485µA/µmLeff min=0.39 µm

4 p-FET ID,sat = 213µA/µmLeff min=0.39 µm

5 Gated lateral pnp β = 107, VA = 67 V6 Spiral inductor L = 10 nH, Q = 6 at 1 GHz7 Varactor 1.4 fF µm−2

8 Schottky barrier diode Vf = 0.31 V @ 100 µA for 5× 5 µm9 Substrate contact 330 Ωs (p+ subs.) for 2× 10 µm10 Polysilicon resistor (RP) 220 Ω/square11 Polysilicon resistor (XN) 340 Ω/square12 Reach-through implant resistor (RN) 23.5 Ω/square13 n+-subcollector resistor (RS) 8 Ω/square14 Ion implanted resistor (RI) 1750 Ω/square15 Metal–insulator–metal capacitor 0.7 fF µm−2

16 Decoupling capacitor 1.5 fF µm−2

17 p–i–n diode 6 Ω for a 2× 10 µm18 ESD protective device 2000 V HBM

Summary 25

An excellent review of the application-driven origins of SiGetechnology, how it has evolved and how the limitations of conventionalsilicon bipolar scaling have enhanced its adoption in the semiconductorindustry, has been written by Meyerson [95]. This review demonstratesthat SiGe HBTs are superior to Si BJTs and comparable to the bestGaAs transistors and ideally suited for low-voltage and low-power wirelesscommunication applications. In some aspects, such as low noise and lowpower consumption, SiGe HBTs have advantages over III–V HBTs, andapproach the performance of some HEMTs, at least below 10 GHz.

So far, Si BJT performance has been the main barrier for siliconto penetrate wireless RF front-ends. While SiGe HBTs have removedthe barrier, RF isolation and system cost issues still remain. Sincesilicon substrates are conductive, it is not practical to build high-qualitypassive elements on-chip. However, much of the cost in current RFsystems using discrete components comes from the passive elements. Inaddition to the SiGe HBT, recent progress in passive component designon silicon substrates, listed in table 1.5, now gives the RF designers a richenvironment to realize applications for the wireless marketplace.

1.8. SUMMARY

This introductory chapter has described the evolution of SiGe technologyfrom early materials research to its current established position inthe marketplace. The evolution of bipolar technology has led to thedevelopment and application of a SiGe transistor through utilization ofstrained layers. SiGe HBT technology has the potential to revolutionizehigh-frequency transceiver design in a way comparable to the revolutionin digital integrated circuit technology brought about by CMOS. Itsunique combination of outstanding high-frequency performance, lowmanufacturing cost and high yield will provide abundant opportunities fornew architectures and new systems in the near future. Subsequent chaptersin this book describe the basis of SiGe technology in much more detail.

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[4] Patton G L, Bravman J C and Plummer J D 1986 Physics, technology

26 Introduction

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28 Introduction

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30 Introduction

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Chapter 2

FILM GROWTH AND MATERIALPARAMETERS

Silicon-based heterostructures have come a long way from the use ofstrain as a parameter for bandgap engineering, to the present state ofdevices/circuits with enhanced performance compared to those obtainedin bulk-Si and competing III–V compound semiconductors. Apart fromthe inherent performance enhancement, undoubtedly the main attractionof high mobility Si/SiGe, SiGe/strained-Si and Si/SiGeC heterostructuresis their basic compatibility with standard Si processing. For any material,issues important to the device designer include bandgap difference, bandalignments and mobility. The first two properties determine the class ofdevices that can be fabricated. For example, quantum confinement ofelectrons cannot occur without a conduction band discontinuity.

It is the purpose of this chapter to consider the recent developments ingrowth techniques and the performance levels achieved to date in group IValloy systems, to address the problems related with film development andprocess integration and to discuss alternative routes that could circumventthe use of strain adjusting epilayers, which are presently the bottleneckfor an introduction of these promising materials (such as strained-Si andSiGeC) into a production environment. We shall discuss various growthand doping techniques and strain-induced material properties of differentgroup IV alloy layers. The electronic properties of Si/SiGe, Si/SiGeC andstrained-Si films will be presented.

Semiconductor heterostructure devices rely on the differences in theelectronic bandstructure of the two semiconductors used to fabricate adevice. In the beginning of heterostructure devices, the emphasis was onfinding a pair of semiconductors with different bandgaps but with nearlythe same lattice constants. This was necessary so that a good epilayerof one semiconductor could be grown on the other. In lattice matchedheterostructures, one can obtain an interface of high quality without

32

Strained layer epitaxy 33

defects, so that as a free carrier approaches a heterostructure boundary,it would be influenced only by the potential gradients and is not trappedor artificially scattered at the heterostructure boundary.

Heterostructures based on column III–V and II–VI compoundsemiconductors, such as AlAs and GaAs, can be easily fabricatedsince there are direct structural and chemical matches among thesesemiconductors. On the other hand, for silicon-based heterostructures thisis not the case as silicon has no natural semiconductor partner with respectto the configuration of its atomic lattice and chemistry, although siliconand germanium are completely miscible over the entire compositionalrange and give rise to alloys with a diamond crystal structure. At roomtemperature, the lattice constants for silicon and germanium are 5.43 A and5.65 A, respectively, leading to a 4.2% lattice mismatch. Clearly, the largemismatch between silicon and germanium precludes depositing epitaxialgermanium directly on silicon. The miscibility of silicon and germanium,however, allows deposition of epitaxial Si1−xGex, without adhering tostoichiometric ratios, on silicon. As a result, the lattice mismatch betweensilicon and Si1−xGex is lessened. Because a significant lattice mismatchstill exists, Si1−xGex on silicon can range from a fully strained to a fullyrelaxed state. Normal heterostructures of Si and Ge thus grow with highdislocation densities that were believed to be incompatible with most deviceapplications. In the early 1980s, however, the situation changed when itwas demonstrated that by utilizing strained layer epitaxy, defects couldbe eliminated in thin silicon-based heterostructures. In strained alloysof Si and Ge, Si1−xGex, it was found that heterostructure effects weremuch stronger than expected, making them very attractive for deviceapplications.

2.1. STRAINED LAYER EPITAXY

Before we discuss the deposition and properties of strained layers, webriefly discuss the properties of the relevant bulk materials as given intable 2.1. Ge has been known to be produced with extremely poor impurityconcentrations and large mobilities with both p- and n-type conductivity.Both the n- and p-type high-quality Ge samples exhibit mobilities of about2 000 000 cm2 V−1 s−1 at about 4 K. On the other hand, high-purity Siexhibits electron mobilities slightly in excess of 500 000 cm2 V−1 s−1 at4 K.

As the atomic spacing of germanium is 4.2% larger than that of silicon,when the first few atomic layers of Ge are deposited, it is energeticallydesirable that they maintain full bonding with the silicon by compressingtogether. In the fully strained case, the larger Si1−xGex horizontal latticecompresses to match the silicon substrate and the Si1−xGex vertical latticeconstant expands to accommodate the horizontal compression as shown

34 Film growth and material parameters

Table 2.1. Room-temperature materials data of selected group IV elements.

Element C Si Ge α–SnLattice Diamond Diamond Diamond DiamondLattice constant, ao (A) 3.5668 5.431 5.657 6.489Density, g cm−3 3.515 2.329 5.323 7.285TCE, α (10−6 K−1) 1.0 2.56 5.9 4.7Bandgap, Eg (eV) 5.48 1.11 0.664 –Dielectric constant, ε 5.7 11.9 16.2 24Electron mobility,µe(cm2 V−1 s−1) 1800 1450 3900 1400

Hole mobility,µh(cm2 V−1 s−1) 1600 450 1900 1200

Effective mass m∗

Electron, m∗e(⊥) – 0.19 0.08 0.024

Electron, m∗e(‖) – 0.92 0.64 0.2–0.45

Light-hole, m∗h(l) 0.7 0.15 0.043 –

Heavy-hole, m∗h(h) 2.18 0.54 0.28–0.38 –

Figure 2.1. A schematic diagram of strained-Si1−xGex crystal latticesillustrating two types of strain. In both cases, the epitaxial film is constrainedby the substrate along two axes, as indicated by the arrows.

in figure 2.1. The higher energy state of strained-Si1−xGex is sustainedbecause the activation energy for the dislocation formation has not beenreached. Since the Si substrate lattice is both much thicker and stiffer, itremains essentially undistorted. The growth of Si1−xGex on silicon beginsas a strained layer, but when the thickness or germanium concentrationof the layer exceeds a critical value, the layer relaxes. Since the lattice


Figure 2.2. Lattice constant for an Si1−xGex alloy as a function of x. Vegard’slaw is a linear interpolation between aSi and aGe.

constants of Si1−xGex alloys are larger than that of Si, pseudomorphicSi1−xGex layers grown on silicon have biaxial in-plane compression of thealloy and an extension normal to the interface. If layers are grown on agermanium substrate the reverse is the case. In both cases the layers suffera tetragonal distortion.

In fully relaxed Si1−xGex on silicon, the lattice constant returnsto the bulk value. The lattice constants of bulk-Si1−xGex alloys havebeen measured and the results obey Vegard’s law to a very goodapproximation. Assuming Vegard’s law applies, the bulk-Si1−xGex latticeconstant (aSi1−xGex

) is a function of the silicon and germanium latticeconstants (aSi and aGe) and the mole fraction of germanium, x inequation (2.1). The lattice constant of Si1−xGex alloys varies linearly, asshown in figure 2.2 obeying Vegard’s rule:

a(Si1−xGex) = aSi + x(aGe − aSi). (2.1)

Due to the relatively large lattice mismatch between SiGe and silicon,commensurate (defect-free) SiGe alloy films cannot be grown on siliconsubstrates without introducing large amounts of strain.

As the thickness of the SiGe layer increases, so does the integratedstrain energy and at some point this configuration will reach a thickness,which is known as the ‘critical layer thickness’, beyond which the totalenergy becomes larger and results in ‘misfit dislocations’ or periodic arraysof incompletely bonded atom rows. Misfit or threading dislocations appearat the interface in both the relaxed and partially relaxed cases. Threadingdislocations affect the heterojunction by acting as a pathway for enhanced


dopant diffusion. This leads to increased junction leakage current. Misfitdislocations located inside a heterojunction depletion region result inan increased space-charge layer recombination and generation current.For most device applications, dislocations are deleterious and should beavoided.

Since the dangling bond can become a trap or leakage site, suchdislocations must be avoided within the active volume of a heterostructuredevice. This implies that active device areas must not lie at the interfaceof the Si1−xGex and Si layers. This is possible in certain devices but,unfortunately, there are also segments of dislocations that thread from theheterostructure interface up to the surface of the crystal. A number ofstrategies have been suggested to minimize the impact of such threadingdislocations [1].

The first possibility is extending the dislocation plane either to the edgeof the wafer or at least to the boundary of a device die where threadingdislocations would be irrelevant. Alternating thin layers can also be grownso that dislocations do not form and instead the atomic spacings of one orboth materials shift to accommodate one another. This occurs naturallyin very thin layers (e.g., 10–100 atoms thick) and can persist in muchthicker layers (100–1000 layers) if a low-temperature growth technique isused, where dislocations do not have enough energy to form and grow.In some recent applications, however, the use of thick relaxed-Si1−xGexlayers as a starting substrate for strained silicon (strained-Si) depositionhas been made. Relaxed-Si1−xGex layers can be grown thick enough tocause threading dislocations to loop around. As a result, the surface isnearly defect-free. Alternating layers of silicon and Si1−xGex may also beused to filter out threading dislocations.

Contrary to the simplistic view given above, the transition from thestrained to the relaxed case is not abrupt and is not clearly defined. Varyingdegrees of strain relaxation can exist [2]. Figure 2.3 shows three regimes(stable, metastable and relaxed) in the plot of Si1−xGex layer thickness onsilicon versus germanium mole fraction. The germanium concentration isdirectly related to the lattice mismatch according to Vegard’s law. Theterm ‘critical thickness’ was initially defined to denote the transition froma strained to a relaxed-Si1−xGex layer. Van der Merwe [3, 4] calculatedthe critical thickness as a function of increased lattice mismatch, byminimizing the sum of the interfacial and strain energy. However, mostof the published literature accepted the mechanical equilibrium theory ofMatthews and Blakeslee [5, 6] as defining the transition from the stable tometastable regimes. Mechanical equilibrium theory assumes the existenceof a threading dislocation. The energy required to glide a threadingdislocation into a misfit dislocation is balanced with the strain energy fromthe lattice mismatch to define the critical thickness as a function of latticemismatch. When the strain energy exceeds the misfit dislocation forms to


Figure 2.3. Critical layer thickness versus Ge content showing stable, metastableand relaxed ranges of Si1−xGex layers on Si. (After Schuppen A et al 1995J. Mater. Sci., Mater. Electron. 6 298–305.)

relieve the strain energy. A simplified Matthews–Blakeslee critical thicknesscalculation (hc) where angular dependences have been ignored [7], is givenby equation (2.2)

hc 1f

b

4π(1 + ν)

(lnhcb

+ 1)

(2.2)

where ν is Poisson’s ratio (0.3), b is the slip distance (0.4 nm), f is themismatch between the film and substrate and for Si1−xGex on silicon, f is0.042x. For a detailed derivation of the critical thickness, the reader mayrefer to an excellent review by Jain and Hayes [8].

Although the Matthews–Blakeslee equilibrium theory is widely cited,strained-Si1−xGex layers have been deposited much thicker than the theorypredicts. Bean et al [9] deposited strained layers by molecular beam epitaxyat 550 C with the thickness an order of magnitude or more above theMatthews–Blakeslee curve, as shown by the solid curve in figure 2.3. Thedashed curve demarcates the metastable and dislocation regimes. Abovethe dashed curve, strained-Si1−xGex layers were impossible to deposit.Between the solid mechanical equilibrium curve and the dashed curve,the layers are labelled metastable. Layers in the metastable regime are


strained, even though the layers are above the Matthews–Blakeslee criticalthickness. However, metastable layers relax with subsequent annealing.

People and Bean sought to reconcile these differences by includingthe kinetics of relaxation in their calculation [10]. Their critical thicknessprediction fits their data, but their theory has not been widely acceptedby other researchers. Many other researchers have also contributed withcritical thickness theories based on energy, mechanical equilibrium andkinetics of dislocations [11–13]. The critical thickness theories basedon dislocation formation are disputed by some researchers because otherfactors, such as wafer preparation and particulate contamination, may playa much larger role in determining misfit dislocations [14]. Furthermore,methods for determining whether a layer is strained or relaxed may nothave enough sensitivity to detect the onset of dislocation formation [15].As a result, dislocation techniques with poor resolution overestimate thecritical thickness. Determination of the critical thickness curve depends onthe deposition methods and characterization methods used. Nonetheless,most researchers concur that the Matthews–Blakeslee equilibrium curvedistinguishes the point where strained-Si1−xGex layers cannot sustainextended thermal processing.

When a thin film with a larger lattice constant (e.g., Si1−xGex)is grown on a smaller lattice constant substrate (e.g., silicon), the filmmaintains an in-plane lattice constant of the substrate and is undera biaxially compressive strain. Since layer sequences with well-definedelectrical and optical properties require coherence of the in-plane latticeconstant, biaxial strain is always present in such heterostructures. Thisasymmetry of the strain with respect to the (001) growth direction leadsto a splitting of the sixfold degenerate conduction band and also of theheavy-hole/light-hole valence band degeneracy. The band ordering in thisheterosystem is therefore strongly strain dependent, and a type I bandalignment is obtained where the entire band offset occurs in the valenceband (figure 2.4(a)) while the band offset in the conduction band is verysmall. This type of structure is favourable for hole confinement and hasbeen exploited in several novel heterostructure devices, namely buriedchannel p-MOSFETs, p-MODFETs and HBTs (see for example, a reviewby Konig and Daembkes [16]).

Similarly, a smaller lattice constant silicon epilayer (strained-Si) willbe under biaxial tension when grown on a larger lattice constant relaxed-Si1−xGex substrate. In this case, type II band offset occurs (figure 2.4(b))and the structure has several advantages over the more common type Iband alignment. A large band offset is obtained in both the conductionand valence bands, relative to the relaxed-Si1−xGex layer [7]. This allowsboth electron and hole confinements in the strained-Si layer, making ituseful for both n- and p-type devices for strained-Si/SiGe-based CMOStechnology. The ability to achieve both n-MOS and p-MOS devices


Figure 2.4. Band alignments for (a) Si0.8Ge0.2 on (001)Si, (b) strained-Sion (100)Si0.8Ge0.2 and (c) Si0.6Ge0.4/Si heterostructure on (001)Si0.8Ge0.2substrates.

using strained-Si provides a promising alternative for next generationhigh-performance SiGe CMOS technology (see for example, reviews byMaiti et al [17] and Schaffler [18] and references therein). Since strained-Si provides both larger conduction and valence band offsets and does notsuffer from alloy scattering, a significant improvement in carrier mobilitycan be achieved. However, strained-Si is more difficult to grow comparedto strained-Si1−xGex, as the growth of thick relaxed-Si1−xGex is difficultwithout forming a large concentration of defects due to dislocation, and atotal thickness of several microns leads to non-planarity, high defect densityand surface roughness.


To fully exploit strain as an additional parameter for bandgapengineering, it is necessary to have substrates available that provide thedesired in-plane lattice constant for the subsequent pseudomorphic layers.For this purpose, strain-relaxed SiGe buffer layers on an Si substrate areused. In an effort to extend the Si1−xGex strained layer technology and tosearch for new materials, experimental work on Si1−xCx and Si1−x−yGexCyalloys was started in the early 1990s and recently on Ge1−yCy alloys.A different concept for strain adjustment has been suggested by addingcarbon into the Si/SiGe material system [19, 20] indicating that theaddition of carbon is a promising way for new relaxed buffer concepts withlow threading dislocation densities. As the lattice parameter of carbon(3.546 A) is much smaller than that of Si and Ge, C may be used as asubstitutional impurity in the SiGe to decrease the lattice mismatch ofthe SiGe system. In the case of a ternary alloy such as Si1−x−yGexCy,assuming Vegard’s law and for a fully relaxed film, the lattice parametercan be written as

aSiGeC = aSi + x (aGe − aSi) + y(aC − aSi) (2.3)

where ai is the lattice parameter of the ith component. The third termbeing negative, it is possible to adjust composition of the alloy to cancelthe second and third term leading to an alloy with exactly the Si latticeparameter (i.e., zero net strain). According to equation (2.3), for about12% Ge in Si and 1% C in silicon, the mismatch is equal and opposite anda strain symmetrized structure with average zero strain may be obtained.

Addition of substitutional carbon to the Si1−xGex material systemcan provide an additional design parameter in band structure engineeringon Si substrates. Since large bandgap variations from 5.5 eV (diamond)to 0.66 eV (Ge) exist, the Si1−x−yGexCy system may result in anincrease in the bandgap to values greater than those of SiGe and Si,in addition to other interesting properties such as the highest knownthermal conductivity (diamond), high hole mobility (Ge) and maturedprocessing technology (Si). The incorporation of C, however, presentsdifficult challenges due to the large lattice mismatch between C and Si, lowsolubility of carbon in Si and silicon carbide precipitation. Attempts havebeen made to form strained layers on Si or Ge substrates containing Sn as aconstituent. Synthesis of dislocation-free Siy(SnxC1−x)1−y [21] and growthof quaternary Si1−x−y−zGexCySnz alloy have also been announced [22].

For the last few years, experimental studies on strained-SiGe materialshave resulted in a significant progress in the understanding of strainrelaxation kinetics and optimization of graded buffer layers with respectto relaxation and surface morphology [23–27]. These parameters areof crucial importance as they are interdependent and are affected bygrowth temperature, grading rate and composition. It appears that thecompetition between dislocation nucleation and propagation determines


Figure 2.5. Cross-sectional transmission electron micrograph and secondary ionmass spectrometry profile of a graded SiGe buffer layer on an Si substrate. (AfterSchaffler F 1998 Thin Solid Films 321 1–10.)

the final threading dislocation density in the film. The compositionalgrading is believed to promote propagation while suppressing nucleationof dislocations and leading to reduced amounts of surface strain, thusallowing higher growth temperature [28,29]. Figure 2.5 shows the secondaryion mass spectrometry (SIMS) profile together with a cross-sectionaltransmission electron micrograph (TEM) micrograph of a graded SiGebuffer layer grown at 750 C by MBE. It is interesting to note that,close to the substrate interface, the misfit dislocation segments appearquite irregular with respect to spacing and length, whereas long-stretchedmisfits can be observed in the upper part of B1. B2 remains free of misfitdislocations, as expected, because once B1 is fully relaxed, B2 becomes


strain-free. In fact, the use of a compositionally graded, relaxed, Si1−xGexbuffer layer has been advocated as ‘virtual substrate’ and allows the strainin the film to be tailored at will. (For a detailed discussion on strainadjustment in SiGe buffer layers see, for example, excellent reviews bySchaffler [18,30].)

In the following sections, we discuss the technology of growth ofSiGe, SiGeC and strained-Si films. Only a brief review is given for well-established results, and readers are referred to the original publicationsfor more detail. We shall examine the deposition of heteroepitaxial filmsusing various reactors in greater depth. As the reactor configurations differsubstantially, the advantages and disadvantages of each system are alsocompared. For a detailed discussion, the reader may refer to a review byMaiti et al [31].

2.2. DEPOSITION TECHNIQUES

Many methods exist for depositing low-temperature silicon and Si1−xGexon silicon. These can be broadly categorized into physical deposition andchemical vapour deposition (CVD) methods. To cope with the difficulties ofgrowing SiGe alloys, molecular beam epitaxy was used at first to producethin, device quality films. MBE is a physical vapour deposition methodand is mostly used for the deposition of III–V compound semiconductorsbecause of the excellent control of layers. Pioneering studies in the mid-1980s at AT&T Bell Laboratories, IBM Thomas J Watson Research Centerand Daimler–Benz Research Laboratories, Germany, British Telecom, UK,Hitachi and NEC, Japan, among others, used molecular beam epitaxyto show that SiGe alloys could be bandgap-engineered controllably andsuccessfully used to realize a host of novel electronic and photonic devices.MBE allows the fabrication of moderately defect-free heterojunctions.However, MBE not being a production tool, they are only used fordemonstration devices.

On the CVD side, Gibbons et al [32] at Stanford were one of thefirst groups to demonstrate high-quality Si1−xGex on silicon. Towardscommercialization of SiGe technology, the development of UHVCVD byMeyerson et al [33] at IBM has been a key step forward which appearedat nearly the same time in the mid-1980s as limited reaction processingCVD (LRPCVD). The UHVCVD reactor combines a standard diffusionfurnace with an ultrahigh vacuum and has made the most significantimpact in the fabrication of Si/Si1−xGex HBTs. An excellent review ofthis technique, and of the devices fabricated using this method of growth,has been published [34]. Other CVD techniques have also been used togrow device quality SiGe layers [35]. Results of Si1−xGex film depositionsat atmospheric pressure CVD by ASM, the only commercial entry in thelate 1980s, have been published. These atmospheric CVD results may

Deposition techniques 43

be the most promising for widespread application of Si1−xGex on siliconheterostructures in a production environment.

In the following, we briefly discuss several reactors, the wafer cleaningmethod, reactor kinetics such as Ge incorporation control, dopant controland selective deposition, and compare the performances of various reactors.Focus is placed on systems that have successfully demonstrated devices andthe discussion of the reactors proceeds in order of increasing base pressure.

2.2.1. Wafer cleaning

Perhaps the most important issue in silicon-based heteroepitaxy is waferpreparation and in situ cleaning prior to epitaxial growth. Poor surfacecleaning results in defects at the epitaxial interface that are independentof the lattice mismatch between Si and Si1−xGex. Conventional siliconhomoepitaxial reactors use an in situ high-temperature hydrogen orhydrogen chloride (HCl) ambient to ensure that the surface is free ofoxide prior to epitaxial growth. Several approaches to the cleaningproblem have been made in the low-temperature deposition of Si1−xGexon silicon: retaining the high-temperature step and using an ultrahighvacuum to desorb oxide; using a lamp-heated system to rapidly changefrom the cleaning temperature to the deposition temperature; usingion bombardment to physically remove the oxide; or using the uniqueproperties of silicon wafers after dipping in liquid hydrofluoric (HF) acid foran H2-terminated surface. Carbon and oxygen contamination is a commonproblem in epitaxy. Having a very low base pressure reduces the oxygenand carbon contamination and prevents the formation of a native oxide.Using a load-lock during the wafer load and unload is an additional methodof keeping the deposition chamber free of oxygen and carbon from theatmosphere.

In silicon homoepitaxy, emphasis is placed on obtaining a high growthrate for high throughput and reducing the autodoping from deposition. Inlow-temperature silicon and Si1−xGex epitaxy, autodoping is not a problemand desired layer thicknesses are of the order of 100 nm or less. Precisecontrol of the germanium and dopant concentration profiles becomes moreimportant than high growth rates. Certain device applications needbandgap grading, so Ge incorporation control down to 1–2% is desirable.High and moderate levels of dopants of both types are needed to formdifferent device structures. Quick transitions from high to low and lowto high dopant and Ge concentrations are also desired for the formationof lightly-doped spacers for modulation-doped structures. Control of insitu doping profiles down to 50 nm and formation of dopant profileswith peaks below the surface are extremely important for precise verticaldopant profiles and lower junction capacitance. As ion implantationcannot produce these types of profiles, in situ doping is a necessity.


For CVD techniques, gas chemistry and gas purity are very importantissues. Silane (SiH4) is more reactive than dichlorosilane (SiH2Cl2),so a lower deposition temperature is possible. Even lower depositiontemperatures can be achieved by using disilane (Si2H6).

2.2.2. Molecular beam epitaxy

Molecular beam epitaxy is the growth technique most widely used to growpseudomorphic Si1−xGex layers on Si. This is a growth technique wherethe thermally evaporated molecules of the desired species impinge on anatomically clean heated substrate to form a crystalline solid. The growthtechnique is intrinsically clean due to UHV growth environment (basepressure ∼10−11 Torr). Cryopumps provide an oil-free evacuation system.MBE is specially suited for the growth of heterostructures requiring precisecontrol of alloy composition, layer thickness and doping. The maincharacteristics of the MBE growth technique are as follows:

• very low growth pressure (∼10−9 Torr) allowing atomic layer by layergrowth on a atomically clean surface;

• low growth temperature (350–600 C) which minimizes solid statediffusion and autodoping;

• slow growth rate (0.1–5 A s−1) which permits atomically thin-layergrowth and better uniformity;

• multilayer growth capability that allows growth of quantum well andsuperlattice structures;

• in situ surface analysis capability such as high-energy electrondiffraction (RHEED), Auger electron spectroscopy (AES) and x-rayphotoelectron spectroscopy (XPS).

Most MBE systems retain some type of high-temperature cleaningor anneal cycle. The resistively heated substrate can be lowered to thedeposition temperature without worry of surface recontamination becauseof the very low partial pressures of oxygen and carbon in the processchamber. Argon sputter cleaning has been used to etch 10 nm from thesurface of the wafer. The etch is followed by a 850 C anneal before loweringdown to the deposition temperature, between 500–750 C. But sputtercleaning leads to degradation in the minority carrier lifetime by heavymetal contamination sputtered from the chamber onto the surface of thewafer [36]. Because of the UHV conditions, medium temperature (<850 C)bakeouts are sufficient to cause native oxide and other contaminants todesorb from the surface of the wafer [37]. The success of using HF dipsas a cleaning method in UHVCVD has also spread to MBE, allowingsilicon homoepitaxy at a temperature down to 370 C without any high-temperature anneals [38].


Molten pools of extremely pure elemental sources such as siliconand germanium at the base of the MBE apparatus provide a source ofatoms, with beams of these atoms directed at the substrate to producethe desired film. The atoms strike the silicon substrate and accumulatein a crystalline manner (epitaxial growth). The deposition kinetics aresimple in MBE, since a chemical reaction does not take place. Theheated substrate provides the surface mobility necessary to epitaxiallyalign the impinging molecules. Deposition rate is controlled by the fluxof the evaporated molecules and the substrate temperature. Depositionrates of up to 600 nm min−1 for silicon are possible. However, typicalSi1−xGex deposition rates are in the 30 nm min−1 range for greater profilecontrol [39].

Also, extremely abrupt compositional profile control is possible by theuse of mechanical shutters. To minimize the strain that results from latticemismatch, generally SiGe alloys layers containing less than 30% Ge aregrown. Bean et al [39] found that the maximum germanium incorporationbefore the occurrence of non-planar growth depends on the depositiontemperature, as shown in figure 2.6. At 750 C, the maximum germaniummole fraction is 10%, whereas at 550 C 100% germanium is possible [9,39].

Figure 2.6. Temperature dependence for planar Si1−xGex growth as a functionof Ge concentration. It is noted that for the Ge fraction more than 0.5, thegrowth temperature must be lower than 550C.


A limited range of dopant incorporation by coevaporation is possiblein MBE, specifically for n-type dopants, because of low sticking coefficientsof Sb and As and surface segregation. Low-energy implantation duringdeposition may solve these problems, but increases the complexity andthe cost of MBE. Wafer uniformity is another limitation. Rotating thesubstrate partially circumvents the problem, but large wafers (>125 mm)may present an insurmountable problem from a uniformity stand point.The inability to in situ dope n-type dopants and to deposit selective layershas been surmounted by using gas source MBE (GSMBE) [37,40–42].

In GSMBE, Si2H6, germane (GeH4), diborane (B2H6) and phosphine(PH3) are introduced into the deposition chamber instead of evaporatingelemental sources. The deposition is controlled by the chemical reactionof the gaseous radicals at the surface of a heated wafer. GSMBE may bedescribed as a hybrid MBE/CVD system, but the deposition pressure is anorder of magnitude or more below other CVD systems. At these depositionpressures, gas phase equilibrium may not be achieved, so standard CVDkinetics may not apply.

2.2.3. UHVCVD

Chemical vapour deposition systems utilize precursor gases thatincorporate the desired atoms to the substrate surface. This technique,which has been well known for decades, is in many ways simpler than MBE.CVD is the most advantageous process because it is a high throughputprocess and also it has in situ doping capabilities. An ultrahigh vacuumchemical vapour deposition reactor consists of a diffusion furnace underultrahigh vacuum, as shown in figure 2.7. Since the base pressure iscomparable to MBE at 10−9 Torr, the advantages of low contamination

Figure 2.7. A schematic cross section of a UHVCVD reactor.


and prevention of native oxide after loading are similar to MBE. UHVCVDdoes not use an in situ cleaning step, but relies on the passivation of thesurface immediately after an HF dip [43]. A load-lock is also used toprevent exposing the deposition chamber to the atmosphere. The gasesSiH4, GeH4, B2H6 and PH3 provide the sources for CVD of p-type andn-type silicon and Si1−xGex. The deposition pressure is about 1–2 mTorr,with deposition rates around 1–2 nm min−1. The control of the wafertemperature in a diffusion furnace is extremely good. As a result, a surfacerate-limited reaction results in a very uniform layer.

2.2.4. LRPCVD and RTCVD

Limited reaction processing CVD for silicon homoepitaxy and Si1−xGexheteroepitaxy was first developed at Stanford University. The uniquefeature of this system is that the surface reaction is temperature driven,and the temperature of the substrate acts as a switch either to initiatea reaction, terminate a reaction or to change the reaction rate. Thistechnique employs rapid isothermal processing, and the temperature ofthe substrate (hence the reaction rate) can be rapidly varied (as fast as350 C s−1). In this system, the base pressure is about 1 mTorr andthe gas flows are established at low temperature. Typical gases usedinclude SiH2Cl2, GeH4, B2H6, AsH3 and PH3 as source gases. Thelamps are turned on to raise the substrate temperature and initiatethe deposition, hence the terminology limited reaction processing. Asa result of the rapid temperature transitions, the high-temperature insitu cleaning step occurs with hydrogen or hydrogen chloride in a shorttime, thus reducing the total thermal budget compared to commercialepitaxial deposition systems. Many other research groups have usedsimilar configurations and have adopted the name rapid thermal chemicalvapour deposition (RTCVD) instead of LRPCVD because they use gasswitching rather than lamp heating to control the reaction. However, rapiddoping and compositional transitions are possible by using the lamps asa thermal switch to control the reaction. In situ doping and selectivesilicon and Si1−xGex heteroepitaxy have been demonstrated. Si1−xGexlayers need to be deposited at a lower temperature to avoid relaxationand three-dimensional growth problems. The deposition temperature usedfor Si1−xGex is about 625 C and is increased to 850 C for silicon caplayer deposition, if required. One of the major problems with reducing thetemperature, however, is increased oxygen incorporation in the Si1−xGexlayers. The oxygen incorporation problem may be reduced with the use ofa load-lock and point-of-use filtration of SiH2Cl2.


2.2.5. Very low pressure CVD

The very low pressure CVD (VLPCVD) deposition tool follows the moreconventional CVD method with some differences and was first developed atMIT. The deposition chamber is a quartz tube evacuated by a turbopumpto a base pressure of 10−8 Torr when cold. The susceptor and wafer areheated by a bank of quartz halogen infrared lamps up to a temperature of800 C. The base pressure increases to about 10−7 Torr when the chamberis heated to 800 C. Process gases during deposition include silane (SiH4),germane (GeH4), diborane (B2H6), arsine (AsH3) and phosphine (PH3) asthe semiconductor and dopant gas sources. Unlike MBE or UHVCVD, thebase pressure in VLPCVD is not low enough to prevent the formationof oxide in the reaction chamber. Therefore, in situ plasma cleaningtechniques are needed to prepare the surface for epitaxial deposition. TheVLPCVD reactor resembles the UHVCVD deposition kinetics because ofthe mTorr deposition pressure and SiH4 gas chemistry. Deposition of insitu doped n- and p-type layers of up to 1020 cm−3 dopant concentrationsand the deposition of selective epitaxial layers using VLPCVD have beendemonstrated [44–46].

2.2.6. Remote plasma CVD

Remote plasma enhanced CVD (RPCVD) has also been used for the Siand Si1−xGex epitaxy [47]. It is a low-temperature process and has beensuccessfully employed for silicon homoepitaxy and Si1−xGex heteroepitaxyin the temperature range of 150–450 C. The epitaxial process employsan ex situ wet chemical clean, an in situ remote hydrogen plasma clean,followed by a remote argon plasma dissociation of silane and germane togenerate the precursors for epitaxial growth. Boron doping concentrationas high as 1021 cm−3 has been achieved in the low-temperature epitaxialfilms by introducing B2H6/He during growth. The growth rate of epitaxialSi can be varied from 0.4–50 A min−1 by controlling the RF power. Thewide range of controllable growth rates makes RPCVD an excellent tool forapplications ranging from superlattice structures to more conventional Siepitaxy. Defect densities below the detection limits of TEM (∼105 cm−2 orless) have been reported. The RPCVD process also exploits the hydrogenpassivation effect at a temperature below 500 C to minimize the adsorptionof C and O during growth. Low oxygen content ∼ 3 × 1018 cm−3 hasbeen achieved by RPCVD. Silicon and Si/Si1−xGex films with boronconcentrations ranging from 1017 to 1019 have been achieved.

2.2.7. Atmospheric pressure CVD

Atmospheric pressure reactors hold the greatest promise for widespreadcommercial use of Si1−xGex heteroepitaxy of silicon. CVD of epitaxial SiGe


films from SiH4–GeH4–HCl–H2 gas mixtures in an atmospheric pressureCVD process has been reported [48]. IBM [49,50] and ASM [51–53] depositsilicon and Si1−xGex at atmospheric pressure using SiH2Cl2 and GeH4.Layer depositions are carried out in a horizontally arranged, induction-heated and air-cooled conventional epitaxy reactor. RCA precleaned siliconwafers were treated in situ in hydrogen at 1070 C for 10 min and then HClgas-etched for a further 10 min. Gas purifiers and load locks are essential inboth cases to reduce the oxygen and carbon incorporation. The IBM systemuses a silicon carbide susceptor, whereas the ASM system uses a quartzsupport plate. The deposition kinetics appear similar to the LRPCVDor RTCVD systems since SiH2Cl2 and GeH4 are used. The IBM systemdeposited smooth Si1−xGex layers with up to 44% germanium at 550 C;they speculate that the chlorine-based gas chemistry suppresses islandingat high germanium concentrations. Unfortunately, no in situ doping dataor Si1−xGex device results have been reported using atmospheric CVD.

2.2.8. Solid phase epitaxy

From the viewpoint of the compatibility with conventional siliconprocessing, it may be difficult and extremely costly to merge MBEtechniques within a standard bipolar/BiCMOS process. An alternativeapproach to forming the SiGe layer, is to implant high-dose Ge ions on thesilicon substrate using solid phase epitaxy (SPE) [54–56]. This producesan amorphous SiGe layer on the silicon substrate and subsequent thermalannealing is required to induce crystallization. Residual implantationdefects due to high-dose germanium implantation may be removed bysequential RTA. This method is fully compatible with the conventionalsilicon IC manufacturing process and is relatively simple. SPE growth ofa SiGe alloy using Ge ion implantation and prolonged furnace anneal hasbeen reported [57–60]. Carbon has a very low bulk solubility in Si and Ge.It is known that the incorporation of elements into Si at concentrationsfar in excess of their bulk solubility limit is possible by SPE. Thus, SPEprovides another possible synthesis route for forming metastable Si1−yGeyor Si1−x−yGexCy layers.

2.2.9. SiGeC film growth

SiGe grown on Si(001) is compressively strained due to the larger latticeconstant of germanium compared to silicon. This causes limitations suchas a critical thickness for planar pseudomorphic growth. Adding a smallamount of carbon into the SiGe material system allows strain adjustmentdue to the small lattice constant of carbon. Exactly strain compensatedSiGeC structures have been shown to exhibit a smaller bandgap thansilicon with a considerable valence band offset [61–64]. Si1−yCy and


Si1−x−yGexCy alloys in which C is incorporated substitutionally offerconsiderably greater flexibility compared to that available in Si/Si1−xGexheterostructures. In particular, the growth of Si1−x−yGexCy alloys witha Ge:C ratio of about 8:1 offers the possibility of fabricating group IVheterostructure devices lattice matched to Si.

Due to the smaller lattice constant of carbon, synthesis of carbon-containing alloys with high electronic quality is challenging in part becauseof the low equilibrium solubility of carbon on the Si lattice. A numberof research groups have investigated the maximum amount of carbon thatcan be incorporated in Si1−x−yGexCy by MBE and CVD [62, 65, 66] andalso studies have been carried out to determine the fraction of the totalcarbon concentration that is substitutional on the lattice. An MBE system,equipped with an electron beam evaporator for silicon, a pyrolytic graphitefilament for carbon and effusion cells for germanium and boron, has beenused for the growth of Si1−x−yGexCy samples with Ge contents up to 6%and carbon concentrations up to 0.55% at 450 C on a thick Si buffer layer.High-quality Si/Si1−x−yGexCy heterojunctions have been grown [67] byRTCVD using dichlorosilane (Si2H2Cl2), germane (GeH4) and methylsilane(SiCH6) as the precursors of Si, Ge and C, respectively.

Using a cold-wall, ultrahigh vacuum, stainless steel chamber withsingle-wafer-processing capability, epitaxial SiGeC films have been grownat 550 C with 1–20 sccm of Si2H6, 0.1–2 sccm of GeH4 and 0.8–1.6 sccm of CH3SiH3. Carbon incorporations of 2.6 atomic wt.% in Si and1.4 atomic wt.% in SiGe were obtained [68]. Photoluminescence studiesof Si1−x−yGexCy and electrical measurements on the Si1−x−yGexCy-basedbipolar transistors [69] indicate that the incorporation of substitutional Cincreases the bandgap of Si1−x−yGexCy pseudomorphically grown on anSi(100) substrate, with the bandgap increasing by 21–25 meV when 1% Cis added.

2.2.10. Strained-Si film growth

High-quality completely lattice-relaxed SiGe buffer layers have been grownon Si(001) using MBE in the temperature range of 750 and 900 C andcompositional grading of the order of 10% µm−1 or less with final Geconcentrations of about 30%. Xie et al [1] have grown compositionallygraded relaxed-Si1−xGex buffer layers on Si with various compositiongradients and temperatures. The authors reported a threading dislocationdensity in fully relaxed-SiGe buffer layers grown using both MBE andRTCVD in the range of 105–106 cm−2 [70]. GSMBE [71,72] has also beensuccessfully employed for the growth of high-quality completely lattice-relaxed step-graded SiGe buffer layers on Si(001) in the temperaturerange of 750 and 800 C. A more abrupt compositional transience of theSiGe/Si interface is expected in GSMBE-grown QWs, owing to reduced Ge

Thermal stability of alloy layers 51

segregation at the heterointerface [73], than in those grown by solid sourceMBE where Ge segregation has been recognized as an important issue [74].Another advantage of GSMBE is that uniform thickness and compositioncan be obtained without sample rotation. However, GSMBE is associatedwith autodoping of doping gas impurities, which would affect the devicecharacteristics.

2.3. THERMAL STABILITY OF ALLOY LAYERS

Since most of the low-temperature grown strained layers are metastablein nature, at a high processing temperature these coherently strainedlayers can relax by forming misfit dislocations. Even for sub-criticallystrained (i.e., thermodynamically stable) epilayers, interdiffusion can beimportant at a high temperature. Since standard silicon processing steps,such as implantation annealing and thermal oxidation, typically exceed thestrained layer deposition temperature, thermal stability of strained layersis of utmost importance. The Matthews–Blakeslee curve imposes severelimitations on stable strained-Si1−xGex layer thickness and germaniumconcentration. Understanding the relaxation processes of metastable layersis imperative if thicknesses and germanium concentrations greater than theequilibrium curve are needed. Relaxation processes from thermal cyclingcan be categorized into three mechanisms: temperature dependence ofthe threading dislocation glide force [75]; dislocation multiplication [76];and germanium diffusion [77]. In an advanced very large scale integration(VLSI) process, there are two high-temperature steps: (i) thermal oxidationto grow gate oxide and (ii) post implant anneal after ion implantation.For gate oxidation, a temperature between 850–950 C is typically used,whereas for rapid thermal implant anneal a temperature as high as 1050 Cis used depending on the dopant and dose. These high-temperatureprocess steps impose serious limitations on the thermal budget that canbe used to fabricate a device based on these metastable films. Thecharacterization methods used vary due to the detection limits of eachtechnique. Detection methods include plan-view TEM, in situ plan-viewTEM, Raman spectroscopy, double crystal diffractometry (DCD) anddefect etching.

X-ray diffraction analysis is not very sensitive to study dislocationdefect densities device grade materials. Capacitance–voltage (C–V )measurements can be employed to study the carrier confinement in the QW.The SiO2/Si/SiGe/Si MOS low-frequency capacitance shows a plateauregion in inversion. This property of the low-frequency capacitance canbe used to qualitatively study the degradation of the material propertiesdue to high-temperature process steps. The plateau in the C–V curve issensitive to the band offset in the valence band at the Si/SiGe interface [78].This band offset in the valence band is reduced if the quality of the


heterointerface is degraded either due to the creation of misfit dislocationdefects or due to interdiffusion.

A few general trends may be established from the published literatureon thermal stability of the strained layers:

• layers below the Matthews–Blakeslee equilibrium curve appear stable;• relaxation of uncapped layers ranges from 600–700 C;• unstrained silicon cap layers improve the thermal stability by

extending the point of relaxation to 800 C. A silicon cap suppressesdislocation nucleation and propagation; and

• interfacial contaminants play a major role in the number of as-deposited dislocations.

2.4. BANDGAP AND BAND DISCONTINUITY

Theoretical calculations based on the electronic structure of heterointer-faces, involving a variety of SiGe layers on Si and Ge substrates, havebeen employed to predict the band offset [7, 79]. Computations are gen-erally based on local density functional theory, [80], phenomenologicaldeformation potential theory [81] and self-consistent ab initio pseudo-potential [82]. Experimental determination of the valence band offset be-tween strained-Si1−xGex and Si (type I band alignment) has been reportedby several workers using different techniques such as x-ray photoelectronspectroscopy (XPS) [83], admittance spectroscopy [84], deep-level transientspectroscopy (DLTS) [85], capacitance–voltage and temperature-dependentcurrent–voltage (I–V ) characteristics [86–88].

In the case of a p-type Si/Si1−xGex MOS capacitor, as the gate bias isswept negative, holes will accumulate first in the buried Si1−xGex potentialwell formed by the valence band offset ∆Ev, rather than at the silicon/oxideinterface. Carrier accumulation in the buried well produces a bias regionover which there is little change in the capacitance as a function of gatebias. As the gate bias continues to be swept to negative voltage, holeswill eventually begin accumulating at the silicon/oxide interface. Thecapacitance then rises towards the maximum value of Cox, as is usualfor an Si MOS capacitor. Band offsets can be extracted by fitting theshape of simulated MOS capacitance–voltage curves in the plateau regionto measurements at different temperatures, typically ranging from 100–300 K [87].

To extract band offsets from C–V measurements of p-MOSFETs,threshold voltages at heterointerface (VTH) and SiGe/SiO2 interface (VTS)are measured both from the ID–VG characteristics and a plot of ID/

√gm

versus VG curve of a MOS device [89]. The relationship between threshold

Bandgap and band discontinuity 53

voltages and valence band offset (∆Ev) is given by [90]

VTH = VFB + φTH − qNBxdm

(tSiεSi

+toxεox

)(2.4)

and

VTS = VFB + φTS − qNBxdmCox

√1 +H(φH) (2.5)

where

φTH = 2φF +∆Evq

(2.6)

H(φH) = ho exp(φTH − φHkT/q

)(2.7)

where

ho = 2εSiNBkT/ (qNBxdm)2 (2.8)

where VFB is the flatband voltage, φTH is the potential at threshold at thetop Si/Si1−xGex interface, φTS is the potential at Si/Si1−xGex interface,φF is the Fermi potential, q is electronic charge, NB is the effective dopingconcentration in the bulk of the semiconductor, xdm is the maximumdepletion layer width in strong inversion, tSi is the Si cap layer thickness,tox is oxide thickness, εox is the oxide permittivity, k is the Boltzmannconstant, T is temperature and ∆VT = VTH − VTS.

By subtracting equation (2.5) from equation (2.4) and rearranging, asystem of two nonlinear equations (2.9) and (2.10) with ∆Ev and φH asunknown is obtained:

∆Ev=φH−2φF+kT

qln

[([1 + Cox

tSiεSi

+Cox (∆VT − ∆Ev)

qNBxdm

]2−1

)(ho)−1

]

(2.9)and φH is given by

φH = φTH − kTq

ln

[([εSi(φH − 2φF)qNBxdmtSi

]2− 1

)(ho)

−1

]. (2.10)

For an Si/SiGe heterostructure, an experimental valence band offset(∆Ev) is obtained by iterating equations (2.9) and (2.10) using thevalues of doping concentration and threshold voltages obtained fromthe experimental high-frequency apparent doping versus gate voltagecharacteristics [89], as shown in figure 2.8.


Figure 2.8. Apparent doping versus distance from the Si/SiO2 interface. Dataobtained from the high-frequency C–V measurements.

2.4.1. Si/SiGe

The electronic properties of SiGe materials depend on the substratematerial on which they are grown, the germanium mole fraction in the film,and the quality of the film and interface. Although SiGe can be grown onsilicon, germanium or even SiGe substrates, the fabrication of SiGe HBTsrequires SiGe growth on silicon substrates. When a thin film with a largerlattice constant (e.g., Si1−xGex) is grown on a smaller lattice constantsubstrate (e.g., silicon), the film maintains the in-plane lattice constantof the substrate and is under a biaxially compressive strain. Figure 2.4,described earlier, shows the band offset between a strained-Si0.8Ge0.2 filmgrown on silicon and strained-Si on a relaxed-SiGe layer.

A discussion of strain-induced splittings within the framework ofdeformation potential theory has been given by van de Walle andMartin for strained-SiGe [79]. Depending on the composition, thebandgap of Si1−xGex alloy varies from 1.1–0.7 eV, corresponding to thewavelength range of about 1–1.5 µm. This is a very useful range fordiscrete optoelectronic devices and for integrated optoelectronics on silicon.Figure 2.9 shows the bandgap difference compared to bulk-Si of unstrainedSi1−xGex [91] and the calculated values of strained-Si1−xGex [92] at roomtemperature. The strained-Si1−xGex curve splits into two lines becauseof uncertainty in some of the parameters used in the calculations. The


Figure 2.9. Germanium mole fraction and strain-dependent bandgap ofSi1−xGex. The bandgap reduction for compressive (strained-SiGe), tensile(strained-Si) and relaxed cases are shown. (After People R 1986 IEEE J.Quantum Electron. 22 1696–710.)

calculated strained value lies in between the two dotted curves. Thecalculations for the bandgap of strained-Si1−xGex were confirmed byLang [93] using photocurrent spectroscopy. The bandgap depends on thegermanium fraction in both cases, but strained-Si1−xGex experiences afaster drop in bandgap than the unstrained case due to splitting of thevalence band degeneracies. Figure 2.9 indicates that strained-Si1−xGexlayers need less germanium to achieve the desired bandgap difference.

The bandgap alignment for strained-Si0.8Ge0.2 on silicon appears infigure 2.9 based on pseudopotential and deformation potential calculationsby van de Walle [82] and People [81]. Since the conduction banddiscontinuity is much smaller than the valence band discontinuity,researchers often ignore the conduction band discontinuity. Quantumconfinement of electrons at the Si–strained-Si1−xGex heterointerface isdifficult because of the small conduction band discontinuity. However, the


state of the initial substrate plays a major role in determining the bandoffsets, as shown in figure 2.9. In fact, calculations show virtually anybandgap alignment is possible [14].

2.4.2. Si/SiGeC

Present knowledge about the band structure of tensilely strained-SiGeCternary alloys on Si〈001〉 is limited. Assuming an average band structurefor Si1−x−yGexCy alloys, Soref [94] has suggested an empirical interpolationbetween Si, Ge and diamond (C) for the bandgap which increases in thefundamental gap of Si1−x−yGexCy layers with increasing y. This resulthas been contradicted by Demkov and Sankey [95] who have shown thatthe fundamental gap is reduced when a small percentage of carbon isadded to the silicon lattice. This reduction in bangap is in agreementwith the photoluminescence measurement data. To describe adequatelythe observed energy shifts for pseudomorphic carbon-containing layers,strain-induced effects and effects due to alloying should be considered[96]. An estimation for the band offsets and the fundamental bandgapfor Si1−x−yGexCy alloys (containing up to 3% carbon and 30% Geconcentration) tensile or compressive strained has been reported by Osten[97]. This estimation considers both the band alignment at the interface oftwo different materials, as well as strain effects.

Figure 2.10 summarizes the results for the highest valence bandfor different tensile and compressive strained-Si1−x−yGexCy layers onSi〈001〉. The plot shows ∆Ev as a function of the effective Ge or C

Figure 2.10. Valence band offsets for compressively strained Si1−xGex andSi1−x−yGexCy (x = 10%, 20% and 30%, y varies between 0% and 3%) and tensilestrained Si1−yCy and Si1−x−yGexCy (y = 1%, 2% and 3%, x varies between 0%and 30%) plotted as a function of the effective lattice mismatch—expressed in‘effective’ Ge or C concentrations, respectively. (After Osten H J 1998 J. Appl.Phys. 84 2716–21.)


concentration for the compressive or tensile strained layers, respectively.The effective concentration corresponds to the concentration needed foridentically strained binary layers. The valence band offset betweencompressive strained layers and Si is generally much larger than thatat the tensile strained layer/Si interface. Photoluminescence studiesof Si1−x−yGexCy sandwiched between Si layers [62, 63] and electricalmeasurements on the Si1−x−yGexCy-based bipolar transistors [69] indicatethat the incorporation of substitutional C increases the bandgap ofSi1−x−yGexCy pseudomorphically grown on an Si(100) substrate, with thebandgap increasing by 21–25 meV when 1% C is added.

Analysis of n- and p-type MOS capacitors indicates that most of theband offset is in the valence band for Si/Si1−x−yGexCy heterojunctionswith carbon contents less than or equal to 0.8 at.%, i.e., no capacitanceplateau region is observed for n-type Si/Si1−x−yGexCy/Si capacitors.Figure 2.11 summarizes the extracted valence band offsets as a functionof the mismatch to Si for Si/Si1−x−yGexCy capacitors with Ge contentsof 20 and 30% and carbon contents up to roughly 1 at.%. From thedata it is seen that the extracted valence band offset decreases as carbonis added to Si1−x−yGexCy. This is consistent with the widening of theSi1−x−yGexCy bandgap with the increasing carbon content that has been

Figure 2.11. Summary of valence band offsets extracted from MOScapacitance–voltage characteristics for p-type Si/Si1−x−yGexCy capacitors. Theoffset is extracted by fitting C–V simulations to the measured data. (AfterHoyt J L et al 1998 Thin Solid Films 321 41–6.)


observed by photoluminescence measurements [63, 98]. It is also observedfrom figure 2.11 that, for a given mismatch to Si, the valence band offsetsappear to be slightly higher for Si/Si1−x−yGexCy than for Si/Si1−xGexheterojunctions.

XPS has been used to measure the conduction and valence bandoffsets in thick, relaxed Ge-rich Si1−x−yGexCy alloys grown by solidsource molecular beam epitaxy on (100) Si substrates [99]. It was shownthat addition of C increased the valence band maximum of SiGeC by+48 meV %C−1. The bandgap energies were obtained from opticalabsorption, and were combined with the valence band offsets to yieldthe conduction band offsets. For SiGeC/Si heterojunctions, the offsetswere typically 0.6 eV for the valence band and 0.38 eV for the conductionband, with a staggered type II alignment. These offsets provide significantelectron and hole confinement for device applications.

Admittance spectroscopy has been used to measure valence bandoffsets in Si/Si1−xGex and Si/Si1−x−yGexCy heterostructures grown byMBE. The Si/Si1−xGex and Si/Si1−x−yGexCy samples consisted of 250 ASi1−xGex or Si0.796Ge0.20C0.004 alternating with 350 A Si for ten periods,and both layers were doped p-type with dopant concentrations of 7.4 ×1016 cm−3 and 1 × 1017 cm−3, respectively. These heterostructureswere grown on a 2000 A Si buffer on Si substrates and capped with2000 A Si. Measurements of conductance and capacitance as functions oftemperature at various frequencies were used to determine the activationenergy for thermal excitation over the Si barriers in the p-type multiplequantum well (MQW) structures; band offsets were then obtained fromthe measured activation energies. For Si/Si0.75Ge0.25 and Si/Si0.80Ge0.20heterostructures coherently strained to Si, valence band offsets of 198± 12and 160 ± 20 meV, respectively, were obtained. For a Si0.796Ge0.20C0.004heterostructure, the valence band offset was 118 ± 10 meV. This valueis slightly lower than the valence band offset of approximately 135 meVexpected in a Si/Si0.833Ge0.167 heterojunction, for which the latticemismatch is the same as in the Si/Si0.796Ge0.20C0.004 heterojunction.

2.4.3. Strained-Si

The heterojunction band offsets (∆Ec, ∆Ev) in a strained-Si/SiGeheterostructure have been determined from the measurement of thresholdvoltages of surface channel strained-Si p-MOSFET structures [89, 100].The extracted experimental valence band offset ∆Ev was found to be160 meV. Using the valence band offset value, the conduction band offsetwas obtained from the following equation

∆Ec = Eg (Si1−xGex) + ∆Ev (Si1−xGex/Si) − Eg(strained-Si) (2.11)

Mobility 59

where Eg (strained-Si) is given by [7, 101]

Eg = 1.11 − 0.4x (2.12)

where x is the Ge concentration in the top part of a completely relaxedSiGe buffer cap. The conduction band offset ∆Ec was found to be 126 meVfor a Ge concentration of 0.2 at the top of the relaxed-SiGe layer.

2.5. MOBILITY

Strain not only modifies the bandgap energy and band alignments but alsolowers the effective mass at the band edges and higher mobilities may beexpected [102]. In the following, we discuss some experimental work usedto determine mobility in strained layers. A more comprehensive discussionof the electron and hole mobility on strain level and the band structure willbe given in chapter 4.

2.5.1. Si/SiGe

Calculations have been made for strained and unstrained Si1−xGex thathave shown an increased electron mobility perpendicular to the growthinterface and increased hole mobility parallel to the growth interface forstrained layers with increasing Ge content. If an Si1−xGex strained epilayeris grown on (100) Si, the splitting of the conduction band minimum dueto strain reduces the effective mass and improves the electron mobility ina direction perpendicular to the interface by about 50% [103, 104]. Theseresults, however, have been contradicted by other simulations showing thatthe mobility peaked and then decreased with increasing Ge concentration[105, 106]. If the epilayer is grown on a thick relaxed-Si1−xGex bufferlayer with a higher Ge concentration than in the epilayer, the mobilityperpendicular to the layer is reduced while the mobility parallel to theinterface increases [107]. As the doping concentration in the semiconductorincreases, the strict periodicity of the lattice is disturbed by the existenceof the impurity atoms, and various heavy doping effects occur. Besides thedependence of carrier mobilities on the doping concentration and electricfield, in alloy semiconductors, mobilities also depend on the composition.It is well known that heavy doping of a semiconductor can reduce thebandgap. In SiGe alloys and strained layers, the combined effect of strainand heavy doping on the bandgap and bandgap narrowing have beenreported [8, 108].

2.5.2. Si/SiGeC

Given the potential of Si/Si1−x−yGexCy, it is imperative to know its carriertransport properties and compare them with those in the Si/Si1−xGex


system. Two-dimensional modulation-doped hole gases can in principlebe fabricated since the band offset at the Si/Si1−x−yGexCy interfaceis predominately in the valence band [109, 110]. To date, however,there are very few reports on the transport properties of holes in theSi/Si1−x−yGexCy interface and reports of transport properties are limitedto the temperature range of 77–300 K. In the following, we discuss thetransport properties of a two-dimensional hole gas in an Si/Si1−x−yGexCymodulation-doped structure.

Using modulation-doped p-type Si1−x−yGexCy QWs, transportproperties of boron-doped tensile strained, perfectly strain compensatedand compressively strained-Si1−x−yGexCy alloy layers on Si(001)substrates have been studied by Duschl et al [111]. The layer sequenceof the p-type modulation-doped Si0.85−yGe0.5Cy QWs is 200 nm undopedsilicon, 20 nm Si0.85−yGe0.5Cy, 10 nm Si spacer, a 30 nm thick 2×1018 cm−3

boron-doped Si layer and a 30 nm Si cap. The mobility and chargecarrier density were determined in a temperature range 40–300 K usingthe standard van der Pauw technique at a magnetic field of 0.3 T.

At room temperature, acoustic and optical phonon scattering isdominant. However, with the freeze-out of phonons at cryogenictemperatures, ionized impurity scattering becomes dominant in moderatelydoped semiconductors. In Si1−x−yGexCy layers, alloy scatteringcontributes as a further mechanism. The carrier mobility also dependson the amount of ionized impurities, the germanium and carbon contents.In the following, we discuss the effect of the addition of carbon andgermanium on the hole mobility of strained and exact strain compensatedSi1−x−yGexCy layers.

Figure 2.12 shows the room temperature mobility and hole densitydata. Besides a silicon reference layer (solid square), the first (open squares)starts with the compressively strained Si0.94Ge0.06. By adding carbon,while leaving the germanium content constant, the strain is subsequentlyreduced until exact strain compensation is reached (C = 0.55%). Thenthe amount of Ge is reduced leading to tensile strained Si0.995−xGexC0.0055and finally to Si0.995C0.0053. The second sequence (open circles) starts withSi0.96Ge0.04 and ends at Si0.996C0.0037.

Considering the Hall mobility (figure 2.12(a)) it is quite evident thatadditional germanium and carbon reduces the mobility as compared topure silicon. A general trend is that the room temperature mobility on thecompressive strain side is nearly independent of the carbon content. Onthe other hand, the hole density (figure 2.12(b)) decreases from compressiveto tensile strain.

Figure 2.13 shows the temperature dependence of the Hall mobility.The reduced mobility of the Si1−x−yGexCy alloys compared to puresilicon at room temperature agrees well with the results published in theliterature [18, 112, 113]. The reasons for the drop in mobility are the

Mobility 61

Figure 2.12. Room temperature mobility (a) and hole density (b) of pure Si(solid square) and two sample sequences. The first sequence (open squares)starts with Si0.94Ge0.06. By adding carbon, while leaving the germanium contentconstant, the strain is subsequently reduced until strain relaxation is reachedSi0.935Ge0.06C0.055 then the amount of germanium is reduced leading finallyto Si0.995C0.0053. The second sequence starts with Si0.96Ge0.04 and ends withSi0.996C0.004. (After Duschl R et al 1998 Thin Solid Films 336 336–9.)

alloy scattering and the enhancement of optical phonon scattering withincreasing germanium incorporation due to the smaller optical phononenergy of germanium compared to silicon. But the theoretically predictedand experimentally observed small decrease of the effective mass due tothe germanium incorporation, which should lead to a higher mobility,cannot compensate these effects. However, at a low temperature, theSi1−x−yGexCy layers show a higher mobility than the silicon due to thelower carrier concentration which leads to a lower effective mass and minorrole of the optical phonon scattering at a low temperature. It is seen that


Figure 2.13. Temperature dependence of the hole mobility for the compressivelystrained Si0.94Ge0.06, exact strain compensated Si0.935Ge0.06C0.055 and tensilestrained Si0.995C0.053 layers. (After Duschl R et al 1998 Thin Solid Films 336336–9.)

the room temperature mobility decreases with C and Ge alloy concentrationcompared to pure Si from 180 to 120 cm2 V−1 s−1, which is due to theincreasing alloy scattering and enhanced scattering at optical phonons. Attemperatures below 100 K, a higher mobility is measured for the samplescontaining C, due to the lower carrier concentration and because ionizedimpurity scattering becomes dominant.

Figure 2.14 shows the mobility and carrier density of a two-dimensionalhole gas in the Si1−x−yGexCy channel from room temperature to 10 K.The initial decreasing and eventual saturation of hole density indicate thefreeze-out of parallel conduction paths and the gradual transfer of holes tothe Si1−x−yGexCy channels as temperature is decreased. In contrast, thehole mobility increases with decreasing temperature. This is evidence ofthe formation of two-dimensional hole gas in the Si1−x−yGexCy channels.The hole mobility at a low temperature decreases as C is incorporated. Forexample, at 10 K the mobility with no C is 1800 cm2 V−1 s−1 comparedto 1500 and 800 cm2 V−1 s−1 with C levels of 0.3% and 0.6%, respectively.It is not clear if the decrease in hole mobility is due to enhanced alloyscattering with the addition of C, or other factors, such as increasedinterface roughness or C-related defects. The carrier density saturates at∼1012 cm−2 at a low temperature, suggesting a complete hole transfer,as intended, from the Si dopant layer to Si1−x−yGexCy channels. Thevariation in the carrier density may be due to imperfect doping controlduring growth and is not thought to result from a change in the valenceband.

Mobility 63

Figure 2.14. Hole density and mobility as a function of temperature forSi/Si1−x−yGexCy modulation-doped heterostructures. (After Chang C L et al1998 Thin Solid Films 321 51–4.)

2.5.3. Strained-Si

Low-temperature Hall mobility measurements are commonly used todetermine the overall quality of a heterostructure and are used tooptimize the growth parameters. At low temperature, where the thermaleffects and scattering by phonons are dramatically reduced, the electronmobility becomes very sensitive to residual scattering mechanisms due tobackground charge impurities, roughness and dislocation. Experimentalelectron mobility data from strained-Si/SiGe modulation-doped structuresmay be divided into two categories: (i) data from devices with the uniformcomposition buffer and (ii) devices with the compositionally graded buffer.A detailed discussion on the mobility of electrons and holes in strained-Simay be found in [17].

At room temperature, strained-Si electron mobility values are between2000 and 2800 cm2 V−1 s−1 for n-channels [118,119], which exceed those inbulk-Si MOSFETs by a factor of four to six. High hole mobilities in excessof 9300 cm2 V−1 s−1 at 4 K in p-type modulation-doped Si/Si0.87Ge0.13/Siheterostructures have been reported by Whall et al [120]. For p-MOSFETs,room temperature values between 1400 and 1800 cm2 V−1 s−1 have beenreported [121], a factor of six to nine above those of conventional Si p-MOSFETs. The dependence of low-field electron and hole mobility onstrain level is shown in table 2.2. A more comprehensive discussion of thedependence of low-field electron and hole mobility on strain level and theband structure will be given in chapter 6.


Table 2.2. Experimental low-field electron and hole mobility: dependence onstrain level.

Ge concentration Strain in Si Temperature Mobilityin the buffer (%) (%) (K) enhancement factor Ref.Electron

10 0.4 300 1.45 [114]20 0.8 1.6729 1.3 1.7529 1.3 77 1.35

Hole

29 1.33 300 1.2 [115]18 0.8 300 1.4 [116]18 0.8 77 2.025 1.0 300 1.5 [117]

2.6. SUMMARY

In this chapter we have given the background for growing different strainedlayers using various types of reactors. Basic Si1−xGex properties anddeposition systems have been briefly covered. A variety of methods existto deposit high-quality alloy layers. In addition to depositing layers withgermanium concentrations of at least 15%, control of the germanium profileto within 1% is desirable for bandgap grading. The use of Si/Si1−xGexheteroepitaxial structures for heterojunction devices is hindered by thelattice mismatch between the two materials. However, strained-Si1−xGexlayers can be deposited on silicon at or above the Matthews–Blakesleecritical thickness curve without interfacial dislocations. Typical bandgapengineering applications may require up to 150 meV bandgap difference.Therefore, the deposition technique must be able to deposit Si1−xGexlayers with germanium concentrations of at least 20%. Layers depositedabove the Matthews–Blakeslee curve must contend with thermal relaxationduring thermal processing. Unfortunately, the Matthews–Blakeslee criticalthickness at 20% germanium is only about 20 nm, and is a limitationfor applications requiring higher Ge mole fractions. Partially strain-compensated or fully strain-compensated SiGeC films may extend theapplication areas.

Differences in the reactor design, base pressure, gas chemistry anddeposition temperature do not appear to limit the ability to deposit devicequality group IV alloy layers. MBE is commonly used as a researchtool due to its low wafer throughput. UHVCVD appears to have the

Bibliography 65

most advantages in terms of material quality and throughput. Researchusing LRP/RTCVD reactors have demonstrated device quality material.Extension of the LRP/RTCVD reactor concept to commercial atmosphericCVD reactors holds promise, but additional work in characterizingatmospheric reactors is needed. Furthermore, the throughput of thesesingle wafer atmospheric CVD reactors needs to be examined.

The experimental determination of valence band and conduction bandoffsets (∆Ev, ∆Ec) in a heterostructure, from the measured thresholdvoltages (VTH and VTS) of a p-MOSFET have been discussed. A review ofexperimental work to determine the variation of mobility in SiGe, SiGeCand strained-Si layers on strain, doping and temperature has also beendescribed.

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Chapter 3

PRINCIPLE OF SIGE HBTS

In chapter 2, the technologies involved in SiGe layer growth and theelectronic properties of strained-Si1−xGex layers have been described withspecial emphasis on those properties which are related to their use as anarrow bandgap material in the base of a heterojunction bipolar transistor(HBT). In this chapter, we examine the underlying physics of the npn SiGeHBT, with particular emphasis on the fundamental differences between theoperations of the SiGe HBT and the Si BJT.

The concept of a bipolar transistor in which the emitter has a greaterbandwidth than the base dates back to the time of Shockley’s originalpatent on the junction bipolar transistor [1]. A detailed theoretical analysisof the potential performance advantages of this type of device, commonlyknown as a heterojunction bipolar transistor, was presented by Kroemer in1957 [2]. However, it was not until 1987 that a functional HBT employinga base layer was demonstrated. The introduction of Ge into the base ofan npn Si BJT reduces the bandgap of the SiGe alloy in the p-dopedbase, relative to Si in the n-doped emitter and collector regions. Thisbandgap discontinuity creates the heterojunctions needed for the enhancedperformance of a SiGe HBT.

Before discussing heterojunction action in a bipolar transistor we startby recapping well-established Si BJT fundamentals [3]. If the effect ofcarrier recombination is initially ignored, the electron and hole injectioncurrents in a forward biased pn junction can be expressed as

In =qADnb

Lnbnp0

(expqVbekT

− 1)

(3.1)

Ip =qADpe

Lpepn0

(expqVbekT

− 1)

(3.2)

where Vbe is the applied bias, A is the area of the junction, Dnb and Dpe arethe minority carrier diffusion constants, Lnb and Lpe are minority carrier

73

74 Principle of SiGe HBTs

diffusion lengths, and np0 and pn0 are the equilibrium minority carrierconcentrations in the neutral base and emitter, respectively.

In conventional homojunction transistors, the doping concentration inthe emitter is considerably higher than in the base, in order to obtain ahigh injection efficiency. For a typical gain of 100, the emitter must bedoped 100 times more heavily than the base. As the doping concentrationincreases to more than 1018 cm−3, bandgap narrowing due to heavy dopingbecomes significant [4].

The following substitutions can be made in equations (3.1) and (3.2)

np0 =n2ioNb

(3.3)

pn0 =n2ieNe

(3.4)

n2ie = n2io exp

∆EbgnkT

(3.5)

where nio is the intrinsic carrier concentration and ∆Ebgn represents thebandgap reduction in the emitter due to heavy doping.

When bandgap narrowing is included, the current gain β becomes

βSi =NeLpeDnb

NbLnbDpeexp(−∆Ebgn

kT

). (3.6)

In an HBT with a narrow bandgap base, the bandgap of the emitteris larger than the base and therefore the injection efficiency can be madevery high, even if the base is doped more heavily than the emitter [2, 5].In a SiGe HBT, a narrow bandgap SiGe base is used and the bandgapdifference between the emitter and base is ∆Eg(x) = Eg,Si − Eg,SiGe(x).Due to its smaller bandgap, the intrinsic carrier concentration in the SiGebase increases.

The difference between the HBT and BJT is that the concentration ofthe injected electrons is much higher (several orders of magnitude) into thebase due to lower conduction band barrier. The current gain for a SiGeHBT becomes

βSiGe = βSi exp(∆Eg(x)kT

). (3.7)

This means that the collector current will be much higher than ina similarly doped BJT, by a factor of exp(∆Eg(x)/kT ), while the basecurrent is not affected. In a SiGe HBT, the bandgap difference ∆Eg(x)can be made much larger than kT . For example, a Ge fraction x = 0.2in the base yields a bandgap difference of more than 170 meV. Therefore,the current gain of the HBT can be made large, irrespective of the dopingratio in the emitter and the base. However, the real advantage of the HBT

Energy band 75

is not to achieve a very high current gain, but to trade it against a highbase doping, necessary to reduce the base resistance.

High values of maximum oscillation frequency and low values of gatedelay τd (for digital switching applications) can be obtained in HBTs [6,7].Base resistance is an important parameter in determining fmax. In a well-designed HBT, a value of 50 for β is usually sufficient, so emitter injectionefficiency can be traded for increased doping in the base. Increased basedoping gives rise to reduced base resistance which is also desirable in helpingto avoid punch-through as the base–collector voltage is increased.

High base doping may contribute to the onset of tunnelling current atthe emitter–base junction. This can be avoided by deliberately reducingthe doping concentration in the emitter. Indeed, in the HBT, it is inprinciple feasible to consider the possibility of interchanging collector andemitter, providing additional advantage in some digital circuits. Many ofthe specific issues involved in transistor design are more fully covered inchapter 4. For the remainder of this chapter, we focus in more detail ondevice physics, showing how the incorporation of germanium significantlychanges the physics of the base region and the emitter–base and base–collector junctions.

3.1. ENERGY BAND

The first step in understanding how a heterostructure device will operateis to consider the energy band diagram. For homostructures, the electronaffinity and bandgap are position independent, and there is no need toworry about the reference level. But for heterostructures, a reference level isessential, normally taken to be the field-free vacuum level. To draw energyband diagrams for devices with a position-dependent alloy composition, itis essential to know how the bandgap varies with position and also the bandline up at compositional junctions.

Figure 3.1 shows the band diagram of an npn bipolar transistor. Inforward active mode, the emitter–base junction is forward biased by theinput voltage Vbe, and the base–collector junction is reverse biased by theoutput voltage Vbc. The collector current Ic consists of electrons which areinjected from the n-emitter into the thin p-base, move through the base bydrift and diffusion, and are collected in the n-collector layer (a drift fieldin the base can be caused by either a doping or a bandgap gradient). Thenumber of electrons injected into the emitter side of the base is determinedby the height of the potential barrier, ∆Vn, in the conduction band betweenthe emitter and the base, which can be controlled by the input voltage Vbe.The dominant component of the base current Ib consists of holes which areinjected from the p-base into the n-emitter (no holes are injected into then-collector in forward active mode because the base–collector junction isreverse biased). The number of holes injected into the emitter is determined


Figure 3.1. Simulated band diagram of an npn bipolar transistor. (AfterPrinz E J 1992 Base transport and vertical profile engineering in Si/Si1−xGex/Siheterojunction bipolar transistors PhD Dissertation Princeton University.)

Figure 3.2. Simulated band diagram of a narrow bandgap base npnheterojunction bipolar transistor. (After Prinz E J 1992 Base transport andvertical profile engineering in Si/Si1−xGex/Si heterojunction bipolar transistorsPhD Dissertation Princeton University.)

Terminal currents in a SiGe HBT 77

by the potential barrier ∆Vp in the valence band between base and emitter,which is also controlled by the input voltage Vbe.

The key idea of an HBT is to lower the potential barrier seen bythe carriers responsible for the output current (electrons in npn devices)compared with the one seen by the carriers constituting the input current(holes in npn devices), thereby increasing the ratio of output to inputcurrent, the common emitter current gain of the HBT [5]. This is doneby fabricating the emitter and the base using materials having differentbandgaps. Depending on the layer in which the bandgap is changedcompared to a homojunction device, two HBT configurations can bedistinguished:

(i) in a narrow bandgap base HBT, the bandgap in the base is loweredthereby increasing the collector current, whereas

(ii) in a wide bandgap emitter HBT, the bandgap in the emitter isincreased compared to the base, resulting in a lower base current.

In both cases, the common emitter current gain is increased by afactor proportional to exp(∆Eg/kT ) if spike and notch effects at theheterojunctions are neglected. Note that in an HBT, where the emitterbandgap is larger than that in the base, the current gain β shouldincrease when the temperature is lowered, making it possible to operatethe transistors more effectively at cryogenic temperature.

3.2. TERMINAL CURRENTS IN A SIGE HBT

In this section we consider a comparison of a SiGe HBT with the equivalentSi BJT. For the purpose of comparison, it is assumed that both the siliconbipolar and the SiGe HBT are identical, other than the fact that germaniumis present in the SiGe HBT. Figure 3.3 shows how the base bandgap changesare brought about by the incorporation of Ge into the base.

In thermal equilibrium, the Fermi level, EF, is constant across thejunction. Therefore, for an abrupt Si/SiGe interface, the difference inbandgap between the emitter and base causes discontinuities to exist atthe conduction and valence bands, shown in figure 3.3 as ∆Ec and ∆Ev,respectively. Also, the total discontinuity, ∆Ec+∆Ev, is equal to the basebandgap difference between the silicon emitter and SiGe base, ∆Ec−bg . InSiGe, the valence band discontinuity, ∆Ev, tends to be considerably largerthan the conduction band discontinuity, ∆Ec.

Figure 3.4 shows the band diagram in forward active mode, wherein this more general case, the germanium concentration is graded linearlyacross the base, increasing from emitter towards the collector. With thepresence of germanium, the electron injection barrier from emitter to base,ψn, is reduced and there will be greater electron injection from emitter tobase. This means an increase in the collector current. However, the hole


Figure 3.3. Effect of strained-SiGe layer on the bandgap of emitter–basejunction for an abrupt Si/SiGe interface. (After Tang Y T 2000 Advancedcharacteristics and modelling of SiGe HBTs PhD Thesis University ofSouthampton.)

injection barrier from base to emitter, ψp, remains the same as in a siliconbipolar transistor. Therefore, the hole current from base to emitter, whichis the main contributor to base current, remains the same. Hence, siliconbipolar transistors and SiGe HBTs tend to have approximately the samebase current.

The following derivations [8], used to show enhancements resultingfrom Ge incorporation in the base, closely follow derivations containedin [9]. We consider the most general case of germanium grading and showhow constant grading may be treated as a particular case for which thetheoretical treatment is still valid. The collector current of a graded SiGeHBT can be obtained by altering the collector current equation of a siliconbipolar transistor. Assuming uniform base doping for the device, the siliconbipolar collector current density, Jc,Si, for uniformly-doped base can be


Figure 3.4. Bandgap energy diagram across a graded SiGe HBT in forwardactive mode of operation. Of and Wf are the electrical boundaries of the neutralbase region on the emitter and collector sides of the base, respectively. (AfterTang Y T 2000 Advanced characteristics and modelling of SiGe HBTs PhD ThesisUniversity of Southampton.)

written using the Moll–Ross relation [10]

Jc,Si = q (exp (qVbe/kT ) − 1)

[∫ Wf

Of

Nb(x)dxDnb(x)n2ie(x)

]−1

(3.8)

=qDnbn

2io

WbNbexp(∆Eapp

gb /kT)[exp (qVbe/kT ) − 1] (3.9)

where q is the charge on an electron, Vbe is the forward biased emitter–base voltage, k is the Boltzmann constant, T is temperature, Of and Wfare the base electrical junction positions at the emitter and collector sideof the neutral base, in forward active mode, Wb is the neutral base width,Nb(x) is the positional-dependent base doping concentration, Dnb(x) andnie(x) are the positional-dependent base electron diffusion coefficient andeffective intrinsic carrier concentration, respectively, nio is the intrinsic


carrier concentration in the absence of heavy doping effects, Nb is thebase doping, and ∆Eapp

gb is the base apparent bandgap narrowing due tothe heavy doping effect.

In equation (3.8), nie(x) accounts for the effective intrinsic carrierconcentration across the base and is a function of the bandgap. For a gradedSiGe HBT, bandgap changes across the base, as depicted in figure 3.4, canbe accounted for [9]

n2ie(x) = γn2io exp

(∆Eapp

gb

kT+

∆Eg,SiGe(grade)(x/Wb)kT

+∆Eg,SiGe(Of)

kT

)

(3.10)where [11]

γ =(NcNv)SiGe(NcNv)Si

≈ 0.4 (3.11)

and neutral base width,Wb =Wf−Of . The term Eg,SiGe(grade) representsthe bandgap difference across the neutral base. The term ∆Eg,SiGe(Of)represents the bandgap difference at the emitter side of the neutral base,Nc and Nv are the density of states in the conduction and valence bands,respectively.

Putting equations (3.8) and (3.10) together and integrating, themost general form for the SiGe HBT collector current density, Jc,SiGe,incorporating both bandgap offset and grading, can be written as [9]

Jc,SiGe = ζ γqDnbn

2io

WbNb

[exp

(∆Eapp

gb

kT+qVbekT

)− 1

](3.12)

× ∆Eg,SiGe(grade)kT

exp(∆Eg,SiGe(Of)/kT

)1 − exp

(− ∆Eg,SiGe(grade)/kT)

where

ζ =(Dnb)SiGe(Dnb)Si

> 1 (3.13)

where the symbol ‘–’ refers to a position averaged quantity. The ratio of(Dnb)SiGe to (Dnb)Si accounts for the strain enhancement of the minoritycarrier electron mobility with increasing germanium content [12].

Taking the ratio of Jc,SiGe to Jc,Si, the collector current enhancementdue to bandgap engineering can be estimated by,

Jc,SiGeJc,Si

≈ ζ γ∆Eg,SiGe(grade)kT

exp (∆Eg,SiGe(Of)/kT )1 − exp (−∆Eg,SiGe(grade)/kT )

(3.14)

where we can draw important conclusions by considering the magnitudesof the terms in the above equation in giving rise to collector currentenhancement, i.e.,


• ζ > 1 defines the effect of the difference in diffusivity/mobilitybetween SiGe and Si;

• exp(∆Eg,SiGe(Of )

kT

)> 1 defines the effect of basic heterojunction action

due to bandgap shrinkage in the base; and

• ∆Eg,SiGe(grade)/kT1−exp(−∆Eg,SiGe(grade)/kT

) > 1 defines the effect of bandgap grading

across the base.

It should be pointed out that equation (3.12) applies in the generalcase. In the limiting case, where there is no grading, the latter term tendsto unity as ∆Eg,SiGe(grade) tends to zero, and the overall expression forcollector current is still valid in a much simplified form.

Even though γ < 1 [11], exp(∆Eg,SiGe(Of)/kT ) increases the SiGeHBTs collector current exponentially for a finite germanium content. Fora SiGe HBT having a germanium concentration varying from 4% at theemitter–base junction to 12% with a trapezoidal shape across the base (seefigure 3.5), a collector current enhancement by a factor of 4.5 has beenreported [9].

The base current in a bipolar transistor, consists of severalcomponents. In the emitter, holes can recombine with electrons at the

Figure 3.5. Uniform (flat), triangle, and trapezoid Ge profiles in the base ofa SiGe HBT. (After Harame D L et al 1995 IEEE Trans. Electron Devices 42455–68.)


emitter surface, in the neutral emitter, or in the wide bandgap part of theemitter–base space-charge region. In the narrow bandgap base, electronscan recombine with holes in the narrow bandgap part of the emitter–base space-charge region, or in the neutral base. An additional sourceof collector and base current consists of electron–hole pairs created byavalanche multiplication or thermal generation in the base–collector space-charge region. The various base current components can be distinguishedby their dependence on emitter–base voltage, base–collector voltage, andtemperature. If both base and emitter material have a high minoritycarrier lifetime, which is usually the case in SiGe HBTs, the base current isdominated by emitter surface recombination current or the current in theneutral emitter.

Since the boundary conditions for the injected minority carriers intothe emitter remain the same as in the homojunction, the reverse injectedhole current can be written as

Jp =qDpen

2ie,Si

NdeWe

(eqVbe/kT − 1

). (3.15)

Equation (3.15) assumes a short, uniformly-doped emitter. For emitterswith a short minority carrier lifetime, We is replaced by the diffusionlength Lpe =

√Dpeτp where Dpe and τp are the respective minority carrier

diffusivity and lifetime in the emitter region, giving

Jp =qDpen

2ie

NdeLpeeqVbe/kT (3.16)

where Nde and Lpe are the emitter doping density and hole diffusion length,respectively. Equation (3.16) implies that Jp has an ideality factor of unity.

The potential barrier for hole injection into the emitter is the samefor both the homojunction and the narrow bandgap heterojunction device,which implies that this component of the base current should be identicalin the two devices, if they have similar emitters. This has indeed beenobserved in experimental SiGe HBTs and is evident from figure 3.6.

Auger recombination deals with the heavy doping effects. This band-to-band recombination mechanism occurs at dopant concentrations beyond1019 cm−3 [13]. One of the main objectives in SiGe HBT design is to lowerthe base resistance by increasing the base doping concentration. The lowerbase resistance improves high-frequency performance. In the highly-dopedemitter of a BJT, the net effect of Auger recombination is a lower effectivelifetime in the emitter, leading to a shortened diffusion length and increasedbase current. In a device simulator this effect is easily included as an extraterm in the current continuity equations.

Figure 3.6 shows the collector and base currents of a flat-base SiGeHBT (x = 0.2) compared to the corresponding Si homojunction device.

Transit time 83

Figure 3.6. Room temperature Gummel plots of a flat-base SiGe HBT andsilicon control device with similar base sheet resistances, and emitter areas,showing the increased collector current due to the narrow bandgap base. (AfterPrinz E J 1992 Base transport and vertical profile engineering in Si/Si1−xGex/Siheterojunction bipolar transistors PhD Dissertation Princeton University.)

In the Gummel plot, the collector current of an ideal bipolar transistorshould be proportional to eqVbe/kT , corresponding to an inverse slope ofapproximately 60 mV per decade of collector current at room temperature.The ∼50× increase in the collector current (and the current gain) of theHBT compared to the homojunction transistor is due to the narrowerbandgap in the base, since both the devices have the same integrated basedopant concentration. Since the base current of silicon and SiGe HBTsare virtually identical, the current gain enhancement due to germaniumincorporation is similar to the collector current enhancement. Therefore,the superior current gain potential of a SiGe HBT can be traded off for anincreased fmax and reduced base resistance, leading to higher power gain,faster switching speed and a lower noise figure.

3.3. TRANSIT TIME

Bandgap grading across the base creates a drift electric field that acceleratesthe electron minority carriers through the base. The graded electric fieldreduces the amount of base stored charge per unit collector current. Thisreduces the energy and time required to move charge in and out of the baseduring transients. As a result, the base transit time, τb, decreases.


In any bipolar transistor, the base transit time for constant base dopingcan be written as [10]

τb =Qb

Ic=∫ Wf

Of

n2ie(z)Nb(z)

[∫ Wf

z

Nb(y)dyDnb(y)n2ie(y)

]dz (3.17)

where Qb is the total base stored charge and Ic is the collector current.Putting equation (3.10) into (3.17) and integrating, τb,Si [13,14] and τb,SiGe[9] become:

τb,Si =W 2

b

2Dnb(3.18)

τb,SiGe =W 2

b

ζDnb

kT

∆Eg,SiGe(grade)(3.19)

×[1 − kT

∆Eg,SiGe(grade)

(1 − exp

(−∆Eg,SiGe(grade)kT

))].

Taking the ratio of τb,SiGe/τb,Si gives:

τb,SiGeτb,Si

=2ζ

kT

∆Eg,SiGe(grade)(3.20)

×[1 − kT

∆Eg,SiGe(grade)

(1 − exp

(−∆Eg,SiGe(grade)kT

))].

For a finite germanium grading of more than 1% at room temperature,τb,SiGe/τb,Si will be less than 1 and therefore the SiGe HBT base transittime will be shorter than the silicon bipolar. The cut-off frequency, fT of abipolar device, as explained in section 3.7, is a function of base transit time,implying that bandgap grading will also increase the usable frequency ofoperation of the device.

An additional benefit of incorporating Ge into the base is a reductionin emitter transit time τe, compared to a silicon BJT. Since τe is inverselyproportional to the collector current, for a given base doping profile, theenhancement in τe, is obtained from the inverse of (3.14) as

τe,SiGeτe,Si

≈ Jc,SiJc,SiGe

=1 − e−∆Eg,SiGe(grade)/kT

ζ γ∆Eg,SiGe(grade)

kT e∆Eg,SiGe(0)/kT. (3.21)

The emitter transit time can potentially be a limiting factor in HBTs whichinclude a low-doped emitter region to avoid tunnelling current from baseto emitter. Such structures are discussed in chapter 4. The effect of baseand emitter transit times on ac performance is more fully discussed insection 3.7.

Early voltage 85

3.4. EARLY VOLTAGE

For analogue circuit applications, a high value of the product of currentgain and Early voltage (βVA) is desirable. There are several physical effectswhich cause the collector current to increase with collector–emitter voltagefor a constant base current. The most important of these is the increase ofthe collector current caused by a decrease of the width of the neutral basewith base–collector reverse bias [15].

Output conductance is a measure of collector current variation withbase–collector reverse bias. In figure 3.8, the base–collector depletionregion widens and reduces the neutral base width as the reverse biasedbase–collector voltage increases, while keeping a fixed emitter–base voltage.Reduction of the neutral base width leads to an increase in the gradientof the injected electron distribution in the p-type base. Since the electrondiffusion current across the base is directly proportional to this gradient,the collector current will increase. A low output conductance is desirableto achieve invariant output current in low-frequency analogue applications.

The Early voltage, VA, an indicator of the extent of base widthmodulation, can be obtained by extrapolation of the output characteristics.With reference to figure 3.7, the Early voltage (ignoring recombination inthe base) is given by

VA ≈ Jc ∂Vce∂Jc

= Jc/( ∂Vce∂Wb

∂Wb

∂Jc

). (3.22)

The rate of change of the neutral base width Wb with respect to the

Figure 3.7. Definition of the Early voltage VA. The linear parts of the outputcharacteristics of a bipolar transistor are extrapolated to zero collector current.


Figure 3.8. Minority carrier distribution in an npn transistor for increasingbase–collector reverse bias voltage in forward active mode. np(x) is the electronconcentration in the p-type base. (After Tang Y T 2000 Advanced characteristicsand modelling of SiGe HBTs PhD Thesis University of Southampton.)

base–collector voltage, for constant emitter–base voltage, is given by

∂Wb

∂Vbc= − Cjc

qNb(Wb)(3.23)

and the change of the collector current density with respect to the basewidth is

∂Jc∂Wb

= −JcNb(Wb)/

(n2ie(Wb)Dnb(Wb)

)∫Wb

0

(Nb(x)/ (n2ie(x)Dnb(x))

)dx. (3.24)

For a constant base profile, combining equations (3.23) and (3.24) one gets

VA =qn2ie(Wb)Dnb(Wb)

Cjc

∫ Wb

0

(Nb(x)/

(n2ie(x)Dnb(x)

) )dx (3.25)

where n2ie(Wb) denotes the intrinsic carrier density at the end of the neutralbase on the collector side. Combining equation (3.25) with the standardequation for bipolar current gain

β =q

Jb0

[∫ Wb

0p(x)/(n2ie(x)Dn(x)

)dx

]−1

(3.26)

Early voltage 87

and assuming p(x) = Nb(x) yields an important figure-of-merit for bipolartransistors, βVA, given by

βVA =q2

Jb0Cjc

(n2ie(Wb)Dn(Wb)

). (3.27)

The following three points are significant:

• βVA is a strong function of Ge concentration at the end of the neutralbase (base–collector junction);

• βVA is larger in SiGe than in silicon due to the larger n2io(Wb) valuein SiGe; and

• to maximize βVA, the base–collector junction capacitance should beas low as possible.

Harame et al [9] showed that Early voltage enhancement of a gradedSiGe HBT can be expressed as

VA,SiGeVA,Si

≈ exp(∆Eg,SiGe(grade)

kT

)[1 − exp (−∆Eg,SiGe(grade)/kT )

∆Eg,SiGe(grade)/kT

].

(3.28)

Combining equations (3.28) and (3.14), the enhancement in βVA atconstant emitter–base voltage can be shown as

βVA,SiGeβVA,Si

≈ γζe∆Eg,SiGe(Of )/kT e∆Eg,SiGe(grade)/kT (3.29)

which is significantly greater than unity for a profile with finite Ge content.For finite germanium grading, ∆Eg,SiGe(grade), of more than 1% across thebase, τb,SiGe/τb,Si, ratio will be larger than 1. Therefore, grading Ge acrossthe neutral base improves not only base transit time, but also Early voltage.Furthermore, since current gain is essentially enhanced by the difference inbandgap at the emitter–base junction and Early voltage by Ge gradingacross the base, respectively, the composite product βVA is significantlyenhanced by up to two orders of magnitude.

Figure 3.9 shows the SiGe/Si ratio for the three parameters ofinterest—current gain, Early voltage, and the product of current gain timesEarly voltage [9]. This figure needs to be interpreted with some care, asthe integrated Ge dose across the base has been kept constant in order toprovide a meaningful comparison. In this figure, when ∆Eg,Ge(grade) = 0,a pure Ge box profile of 8.4% Ge is implied, while ∆Eg,Ge(grade) =125 meV, (the x-axis limit in figure 3.5), implies a purely triangular profilefrom 0–18.6% Ge. Any other grading between these limits indicates thecorresponding trapezoidal Ge profile. The triangular profile has the largestEarly voltage and gain–Early voltage product. The Ge box profile has an


Figure 3.9. Early voltage and current gain Early voltage products. (AfterHarame et al 1995 IEEE Trans. Electron Devices 42 455–68.)

exponentially increased current gain, by the factor exp(∆Eg,SiGe(Of)/kT ),but the same Early voltage. The βVA product is strongly influenced bybase–collector capacitance Cbc, but there is always a trade-off between theseparate terms. If β is increased, by reducing the base doping, VA willdecrease, so it is therefore not desirable to have excessively high currentgain.

In a SiGe HBT with a box Ge profile, the improvement in βVA islimited by critical thickness considerations. For example, for a base widthof about 500 A, the Matthews–Blakeslee theory predicts a maximum Geconcentration of about 7% corresponding to a bandgap difference of 55 meVcompared to Si. This bandgap difference translates into ∼5× improvementin the βVA product. In a graded base SiGe HBT, insertion of a verythin Si1−xGex region between base and collector will reduce base–collectorcapacitance and increase Early voltage, while leaving the current gainvirtually unchanged [16]. The thickness of this Si1−xGex layer has to besufficient to include the base edge of the base–collector depletion regioneven at maximum reverse bias Vbc. Since the equilibrium critical thicknessdecreases with increasing Ge concentration in a strained-Si1−xGex layer,the improvement possible in the βVA product of a graded-base HBT isgreater compared to that of β alone in a box profile HBT.

A simple structure to investigate the β versus VA trade-off in gradedbase HBTs is a stepped base transistor, where the base consists of twoseparate p-doped layers with constant bandgap in each layer. Figure 3.10shows the calculated band diagrams and measured collector current

Early voltage 89

Figure 3.10. Calculated band diagrams and measured collector currentcharacteristics showing the effect of the position of the biggest bandgap regionin the base on the output resistance of SiGe HBTs. The devices had anemitter area of 62 × 62 µm. (After Prinz E J 1992 Base transport and verticalprofile engineering in Si/Si1−xGex/Si heterojunction bipolar transistors PhDDissertation Princeton University.)

characteristics for two stepped-base devices. Both devices had similarcurrent gains because of the similar width and height of the highest barrierfor electrons in the base. The output resistance of device in which thenarrow gap layer was located at the base–collector junction, however, wasvastly increased compared to device which had its narrow gap layer atthe emitter–base junction. Prinz and Sturm [16] have experimentallydemonstrated βVA products of 168 000 using a two step 14–28% germaniumbase. State-of-the-art silicon bipolar processes have a βVA product of6000. The effects of base dopant out-diffusion leading to a base–collector


heterojunction barrier on the Early voltage have also been reported [17].A more complete discussion on the effects of parasitic barriers is given inthe following section.

3.5. HETEROJUNCTION BARRIER EFFECTS

The computed conduction band offset in the silicon to strained-Si1−xGexheterojunction is small (typically 20 meV) [18]. If a significant conductionband offset exists, a reduction in the gain may result. In a heterostructure,compositional grading across the heterojunction may be used to eliminatethe conduction band spike. In the case of an Si/SiGe/Si system, theconduction band spike is not a severe problem if the emitter dopantconcentration is larger than the base doping concentration, as the bandbending appears on the side with lower doping. In an npn transistor anysmall conduction band spike may be disregarded. However, it is not true forthe pnp transistor, as the spike will be large in this case because valenceband offsets are much larger than the conduction band offsets. At highcurrent densities or high forward bias, the transport of carriers is stronglyinfluenced by the potential barrier that develops due to alloy gradingpotential of the heterojunction. A retrograde Ge profile near the collectorjunction also creates a barrier to the flow of the minority carriers [19].

Another type of parasitic barrier arises due to the boron out-diffusionfrom the base. Extension of base dopant beyond the Si1−xGex regionoccurs during thermal cycling, or improper control of the as-depositedprofile [20, 21]. Even small amounts of boron out-diffusion from a heavily-doped Si1−xGex base into the Si emitter and collector cause parasiticbarriers in the conduction band which can drastically reduce the collectorcurrent enhancement.

Shafi et al [22] fabricated a SiGe HBT with a very narrow base widthof 214 A, doped with a boron concentration of 5 × 1019 cm−3 and a Geconcentration of 15%. The width of emitter was 0.3 µm doped with auniform As concentration 1018 cm−3, while the doping in the collector was3 × 1016 cm−3. The collector current enhancement factor was 13, whilethe base current was also found to increase sixfold. The authors attributedthis increase in base current to a either very low lifetime near the collectorregion in the base, or a parasitic barrier at the base–collector junction.Shafi et al [23] have also reported the collector current degradation dueto out-diffusion of boron and creation of parasitic barriers. The minoritycarrier concentration in the base increases due to the barriers and this willincrease the recombination and base current, irrespective of the value ofthe lifetime of the minority carriers.

Out-diffusion of boron into the collector results in the formation ofa parasitic conduction band barrier, as illustrated in figure 3.11, wherean exponential out-diffusion tail region of varying diffusion length, LD,

Heterojunction barrier effects 91

Figure 3.11. Simulation of band diagram and electron concentration for a SiGeHBT with the doping profile of (a). Note the exponential dopant out-diffusiontail (diffusion length LD) into the Si collector region. The band diagram (b) showsthe parasitic conduction band barrier at the Si1−xGex/Si interface. (c) and (d)show conduction and valence bands, respectively, at the base–collector junctionfor various diffusion lengths LD. (e) The parasitic conduction band barriercauses a deviation from the triangular electron profile in the base leading toincreased minority carrier charge storage in the base even as Ic decreases. (AfterPrinz E J 1992 Base transport and vertical profile engineering in Si/Si1−xGex/Siheterojunction bipolar transistors PhD Dissertation Princeton University.)


Figure 3.12. Simulation of normalized collector current enhancement versusinverse temperature for various values of LD. (After Prinz E J 1992 Basetransport and vertical profile engineering in Si/Si1−xGex/Si heterojunctionbipolar transistors PhD Dissertation Princeton University.)

extending into the Si collector region, has been superimposed upon anSi0.8Ge0.2 base with a constant doping of 1019 cm−3. Even a smallamount of boron out-diffusion (LD ∼ 30 A) causes a large parasitic barrierfor electrons at the base–collector junction (barrier height ∼85 meV), asshown in figure 3.11(c). This barrier leads to increased minority carrierstorage in the base significantly impeding electron diffusion through thebase, increasing neutral base recombination and degrading the collectorcurrent, as shown in figure 3.11(e). The parasitic barriers thereby reducethe potential enhancement in current gain once the diffusion length exceeds11 A, as shown in figure 3.12.

With increased minority carrier charge storage in the base, as shownin figure 3.11(e), the parasitic barriers increase the base transit time, τb,because of the increase in electron charge and the decrease in collectorcurrent Ic, as the ideal triangular electron profile for electron concentrationin the base is replaced by a trapezoidal profile. This effect, demonstratedby simulation, was experimentally observed by Pruijmboom et al [24] inhigh-frequency measurements of SiGe HBTs.

3.5.1. Effect of undoped spacer layers

The deleterious effect of base dopant out-diffusion from the Si1−xGexbase into silicon emitter and collector can be limited by inserting thinundoped Si1−xGex layers on both sides of the base [20, 21]. These

Heterojunction barrier effects 93

Figure 3.13. Doping profile of HBT structure with undoped SiGe spacerlayers. (After Prinz E J 1992 Base transport and vertical profile engineering inSi/Si1−xGex/Si heterojunction bipolar transistors PhD Dissertation PrincetonUniversity.)

Figure 3.14. Simulated boron doping profile (SUPREM III) for various anneals.If the Si1−xGex layer thickness is increased by adding 150 A thick intrinsicSi1−xGex spacer layers on both sides of the base, the diffused boron profile isstill contained inside the Si1−xGex layer for a temperature below 800 C. (AfterPrinz E J 1992 Base transport and vertical profile engineering in Si/Si1−xGex/Siheterojunction bipolar transistors PhD Dissertation Princeton University.)


spacers have to be wide enough to contain the tail regions of the boronout-diffusion. Inevitably, this change increases the overall width of thestrained-Si1−xGex layer, making the structure more likely to relax byforming misfit dislocations at the interface.

To demonstrate the effect of thermal cycle on SiGe HBT performance,consider the device structure shown in figure 3.13 with a base doping of5×1019 cm−3, a base width of 300 A and box Ge profile (x = 0.18), leadingto a base sheet resistance of ∼800 Ω/square. The 1017 cm−3 collectordoping represents a trade-off between breakdown voltage BVceo and theonset of high level injection in the collector (Kirk effect) [25, 26]. If thebase is doped above 2 × 1018 cm−3 a lightly-doped n-Si spacer has to beinserted between base and emitter to prevent tunnelling leakage in theemitter–base junction [27].

Figure 3.14 shows calculated doping profiles for a 10 min anneal atvarious temperatures and figure 3.15 the corresponding band diagrams for astructure (a) without and (b) with 150 A thick spacers. Note the absence ofparasitic barriers in the device with spacers up to an annealing temperatureof 850 C. However, increase in the thermal budget of the process leads to astrong degradation of the collector current. The intrinsic spacers, therefore,substantially improve the tolerance of the device structure for the thermalbudget of the process. These simulations show that in the design of a SiGeHBT process, intrinsic Si1−xGex spacer layers on both sides of the base,should be considered according to the thermal budget of the process. Thecritical thickness limitation of the strained-Si1−xGex layer, however, limitsthe total permissible thickness of the base including the spacer layers.

3.6. HIGH LEVEL INJECTION

In a bipolar transistor, two different type of high level injection (HLI)can occur. The first occurs in the base region from the large number ofelectrons injected at high emitter–base voltage. The effect was analysedfor Si BJTs by Webster [28]. Since the reverse injected base current retainsan eqVbe/kT dependence, the current gain falls off inversely proportional toIc [3]. In general, this effect does not appear in HBTs if the base dopantconcentration is high.

The other HLI effect occuring in the collector region is the Kirkeffect [25] which arises as the base–collector depletion width spreads intothe collector at high current levels due to electron velocity saturation. Theeffect of velocity saturation at large collector current densities dependson the relative base and collector doping concentrations. Forward bias ofthe internal base–collector junction increases the base current due to holeinjection into the collector and results in a rapid drop in dc current gain.In a SiGe HBT, the valence band offset prevents the injection of holes intothe collector and subsequently the collector current saturates at densities

High level injection 95

Figure 3.15. Simulated band diagrams for a structure (a) without and (b)with 150 A thick spacers for a 10 min anneal at different temperatures. (AfterPrinz E J 1992 Base transport and vertical profile engineering in Si/Si1−xGex/Siheterojunction bipolar transistors PhD Dissertation Princeton University.)

less than the classical Kirk effect. In addition, excess charge is stored inthe base, which results in decreased current gain and fT.

Cottrell and Yu [29] and Yu et al [30] attempted to model the valenceband barrier effects at high collector current densities for a SiGe HBT.The authors noted that the valence band barrier effect appears at highcurrent densities for npn and at all current densities for pnp devices. Otherresearchers [31, 32] examined the effect of two-dimensional lateral carrierdiffusion on the gain. In this case, the electrons accumulating in the


base–collector space-charge layer (SCL) diffuse laterally before collection,resulting in an increased effective collector area. Recently, a comprehensiveinvestigation of the impact of the Ge profile shape as well as the scaling ofbase and collector doping on high injection heterojunction barrier effectshas been described [33] over a wide temperature range. The onset of theKirk effect in a SiGe HBT was shown to expose the Si/SiGe heterojunctionwhich blocks the flow of holes into the collector under the Kirk effectand hence induces an electron barrier in the conduction band. Thecombined effect reduces collector current, increases base current and rapidlydegrades fT. Various strategies to simultaneously reduce the impact of theconduction band barrier, and increase fmax and BVceo were discussed.

Experimental evidence of the valence band barrier in a pnp SiGe HBThas been confirmed [19, 34, 35]. The knee current (at which Ic × β ismaximum) which increases with applied base–collector bias, is found tobe much stronger than can be explained by the Kirk effect. Similarly, thegraph of unity gain cut-off frequency fT versus collector current densityalso shows a strong dependence on the base–collector bias. From theexperiments, the knee current density was found to be much less thanthe current density calculated by accounting solely for velocity saturation.

3.7. HIGH-FREQUENCY FIGURES-OF-MERIT

For high-frequency ac operation, bipolar transistors are often assessedaccording to two figures-of-merit. The first is known as the unity gaincut-off or transition frequency, fT. The second is known as the maximumoscillation frequency. While both figures-of-merit may not necessarily besuitable for all applications of SiGe HBTs, both are still widely quoted,particularly in device research publications.

3.7.1. Unity gain cut-off frequency, fT

fT is defined as the frequency at which the common emitter short circuitac current gain is unity [13]. It is related physically to the bipolar device,as the total delay for the minority carrier across the device from emitterto collector, τec [3]. The total delay consists of the minority carrier storedcharge delay and the junction capacitance charging delay, and is oftenrelated to fT through the equation:

fT =1

2πτec(3.30)

where the total transit time τec comprises of a number of components:

τec = τe + τeb + τb + τbc + τje + τc. (3.31)

High-frequency figures-of-merit 97

The major components, due to minority carrier stored charge, are τe for theneutral emitter and τb for the neutral base region (as previously discussedin section 3.3). The term τeb represents minority carrier transit time in theemitter–base depletion region, and is often small enough to be included inthe emitter transit time term. The transit time τb, the delay due to theexcess minority carrier storage in the base, is generally the most significantterm in equation (3.31) and the relevant expressions for a SiGe HBT andthe effect of Ge grading have been given in equations (3.19)–(3.20).

The delay term τbc is known as the collector depletion layer transittime. It can be approximated as [13,36]

τbc =Wjc

2vscl(3.32)

where Wjc is the base–collector depletion layer width, vscl is the carrierscattering limited velocity which is approximately equal to 1×107 cm s−1 atroom temperature for silicon [37]. For high-speed devices, as the base widthis consistently scaled down, τb reduces, and τe and τbc become progressivelymore significant.

The delay term τje is the total charging time associated with emitter–base and base–collector depletion layers and is given by [3]

τje =kT

qIc(Cje + Cjc) (3.33)

where Cje and Cjc are the emitter–base and the base–collector depletioncapacitances. As the collector current increases, it is often assumed thatthis transit time component becomes negligible. However, for low powerdevices, the effect of low Ic on τje becomes more significant, emphasizingvery clearly the importance of minimizing the junction capacitances Cjeand Cjc.

The delay term τc is the collector charging time [3]

τc = RcCjc. (3.34)

In a well-designed transistor, Rc is usually quite small and therefore τcis usually not very significant. By combining all equations, fT can beconveniently formulated as

fT =12π

(kT

qIc(Cje + Cjc) +

W 2b

αDnb+ τe + τeb +

Wjc

2vscl+RcCjc

)−1

.

(3.35)Figure 3.16 shows the typical variation of fT with collector current. Fromequation (3.33), it is clear that τje is dominant at low collector current, andtherefore fT tends to increase with increase in Ic. However, the influenceof τje reduces drastically as the collector current continues to increase. At


Figure 3.16. Variation of fT with collector current in a SiGe HBT.

peak fT, τe, τb and τbc are usually the dominant terms for an optimaltransistor design [13]. Therefore, to improve the peak value of fT, all threeterms need to be minimized. Eventually high injection occurs and the basetransit time increases at high collector current, causing the reduction in fTas shown in figure 3.16.

3.7.2. Maximum oscillation frequency, fmax

The unity gain cut-off frequency provides a good indication of the intrinsicdelay associated with a bipolar transistor. However, it is not a realisticparameter for a circuit environment, as it assumes that the output isshort circuited. In addition, it is independent of base resistance and hencedoes not take the base resistance base–collector depletion capacitance timeconstant into account. These are important parameters for determiningthe transient behaviour of bipolar circuits. Therefore, another morepractical and widely accepted figure-of-merit, fmax, is commonly used,which characterizes the power transfer in and out of the bipolar device.fmax is defined as the frequency at which the unilateral power gain becomesunity. Here the output is essentially isolated from the input by anappropriate external matching circuit comprising reactive and resistivecomponents. The load that it drives is also assumed to be conjugatelymatched to the transistor output impedance. It can be shown [38] that:

fmax =

√fT

8πCjcRb(3.36)

Breakdown voltage, BVceo 99

where Rb is the base resistance. Equation (3.36) shows that it is notsufficient to obtain a high value of fT, by decreasing base width, but thatbase resistance and base–collector capacitance must also be minimized.However, as base width decreases rapidly to achieve high fT, Rb willincrease unless the doping is increased. To counter that effect, the baseneeds to be more highly doped, which means that emitter doping has tobe lowered to prevent emitter–base junction tunnelling for very high basedoping levels. The increased current gain capability of a SiGe base enableslowering of emitter doping without jeopardizing sufficient current gain.

An alternative figure-of-merit, the ECL gate delay (see section 4.7.3)has been used to characterize the effects of transistor parameters at highfrequency [39]. Unlike the frequencies fT and fmax, there is no standardexpression for the switching time or the propagation delay. The gate delaydepends not only on the intrinsic characteristics of the transistor but alsothe circuit configuration and the values of load resistance and capacitance.In all cases, base resistance and base–collector capacitance appear in theexpressions. Even though fmax does not accurately represent the deviceperformance at high frequencies, the qualitative effect of reducing baseresistance and base–collector capacitance is apparent. A further discussionon the computational aspects of determining the various components of fTfrom device simulations will be presented in chapter 5.

3.8. BREAKDOWN VOLTAGE, BVCEO

Although several breakdown voltages are defined for a bipolar transistor,the most important is the collector–emitter breakdown voltage, BVceo,as it determines the maximum supply voltage that can be applied. Thecollector–emitter breakdown is limited by two different reverse bias junctionbreakdown mechanisms: Zener and avalanche. Zener breakdown occurswhen both sides of a junction have high dopant concentrations. Avalanchebreakdown occurs when a large electric field appears across the depletionregion causing an impact ionization and generation of electron–hole pairs.BVceo, limited by avalanche breakdown, occurs when the product of theavalanche multiplication factor and dc current gain approaches unity. Fordesign purposes it is often approximated by [40]

BVceo BVcbom√β

(3.37)

where BVcbo is the base–collector breakdown voltage with emitter open-circuited and m ranges from 2–3 for silicon [41].

In general, the optimization of breakdown voltages for a homojunctiontransistor and an HBT does not differ. However, extension of the Ge profileinto the collector region to avoid the parasitic heterojunction barriers maylead to increased impact ionization. But simulations of carrier energy


seem to indicate that impact ionization is more likely to occur deeper intothe collector than originally thought [42]. Therefore, a narrow bandgapSi1−xGex-base may not affect the breakdown voltage. A trade-off existsbetween the breakdown voltage and the collector velocity saturation effects.Increases in breakdown voltage for both emitter–base and base–collectorjunctions have been obtained by placing lightly-doped spacers on both sidesof the heavily-doped base without incurring collector velocity saturationeffects [43–45].

3.9. SUMMARY

The objective of this chapter has been to describe the basic physics ofSiGe HBTs. Use was made of energy band diagrams in deriving theexpression for collector current in the most general case of a graded baseSiGe HBT. It was evident that significant enhancement in current gain,base transit time and Early voltage is possible with the incorporation ofgermanium in the base region. The way in which the resultant reductionof emitter and base transit times leads to a corresponding enhancementin high-frequency performance measures such as fT and fmax was clearlyindicated. The onset of a parasitic conduction band barrier at the base–collector junction through out-diffusion of boron from the base was shownto be undesirable, since it increases minority carrier storage in the base,and reduces both collector current and fT. Consequently, the advantage inuse of thin undoped SiGe spacer layers between base and emitter and baseand collector was discussed.

BIBLIOGRAPHY

[1] Shockley W 1951 US Patent Specification 2569347[2] Kroemer H 1957 Theory of a wide-gap emitter for transistors Proc. IRE 45

1535–7[3] Sze S M 1981 Physics of Semiconductor Devices 2nd edn (New York: Wiley)[4] Slotboom J W and de Graaff H C 1976 Measurement of bandgap narrowing

in Si bipolar transistors Solid-State Electron. 19 857–62[5] Kroemer H 1982 Heterojunction bipolar transistors and integrated circuits

Proc. IEEE 70 13–25[6] Vaidyanathan M and Roulston D J 1995 Effective base–collector time

constants for calculating the maximum oscillation frequency of bipolartransistors Solid-State Electron. 38 509–16

[7] Vaidyanathan M and Pulfrey D L 1999 Extrapolated fmax of heterojunctionbipolar transistors IEEE Trans. Electron Devices 46 301–9

[8] Tang Y T 2000 Advanced characteristics and modelling of SiGe HBTs PhDThesis University of Southampton

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[9] Harame D L, Comfort J H, Cressler J D, Crabbe E F, Sun J Y-C,Meyerson B S and Tice T 1995 Si/SiGe epitaxial-base transistors—part I:materials, physics and circuits IEEE Trans. Electron Devices 42 455–68

[10] Kroemer H 1985 Two integral relations pertaining to the electron transportthrough a bipolar transistor with a nonuniform energy gap in the baseregion Solid-State Electron. 28 1101–3

[11] Slotboom J W, Streutker G, Pruijmboom A and Gravesteijn D J 1991Parasitic energy barriers in SiGe HBTs IEEE Electron Device Lett. 12486–8

[12] Kay L E and Tang T-W 1991 Monte Carlo calculation of strained andunstrained electron mobilities in Si1−xGex using an improved ionized-impurity model J. Appl. Phys. 70 1483–1488, 1991.


[14] Lindmayer J and Wrigley C 1961 The high injection level operation of drifttransistors Solid-State Electron. 2 79–84

[15] Early J M 1952 Effects of space-charge layer widening in junction transistorsProc. IRE 40 1401–6

[16] Prinz E J and Sturm J C 1991 Current gain-Early voltage products inheterojunction bipolar transistors with nonuniform base bandgaps IEEEElectron Device Lett. 12 691–3

[17] Prinz E J and Sturm J C 1991 Analytical modelling of current gain-Earlyvoltage products in Si/Si1−xGex/Si heterojunction bipolar transistorsIEEE IEDM Tech. Dig. pp 853–6


[19] Harame D L, Stork J M C, Meyerson B S, Crabbe E F, Scilla G J,de Fresart E, Megdanis A C, Stanis C L, Patton G L, Comfort J H,Bright A A, Johnson J B and Furkay S S 1990 30 GHz polysilicon-emitterand single-crystal-emitter graded SiGe-base pnp transistors IEEE IEDMTech. Dig. 33–6

[20] Prinz E J, Garone P M, Schwartz P V, Xiao X and Sturm J C 1989 Theeffect of base-emitter spacers and strain-dependent densities of states inSi/Si1−xGex/Si heterojunction bipolar transistors IEEE IEDM Tech. Dig.pp 639–42

[21] Prinz E J, Garone P, Schwartz P, Xiao X and Sturm J 1991 The effects ofbase dopant out-diffusion and undoped Si1−xGex junction space layers inSi/Si1−xGex/Si heterojunction bipolar transistors IEEE Electron DeviceLett. 12 42–4

[22] Shafi Z A, Gibbings C J, Ashburn P, Post I R C, Tuppen C G andGodfrey D J 1991 The importance of neutral base recombination incompromising the gain of Si/SiGe heterojunction bipolar transistors IEEETrans. Electron Devices 38 1973–6

[23] Shafi Z A, Ashburn P, Post I R C, Robbins D J, Leong W Y, Gibbings C Jand Nigrin S 1995 Analysis and modelling of base currents of Si/Si1−xGexheterojunction bipolar transistors fabricated in high and low oxygencontent material J. Appl. Phys. 78 2823–9

[24] Pruijmboom A, Slotboom J W, Gravesteijn D J, Fredriksz C W,


van Gorkum A A, van de Heuvel R A, van Rooij-Mulder J M L,Streutker G and van de Walle G F A 1991 Heterojunction bipolartransistors with SiGe base grown by molecular beam epitaxy IEEEElectron Device Lett. 12 357–9

[25] Kirk C T 1962 A theory of transistor cut-off frequency fT falloff at highcurrent densities IRE Trans. Electron Devices 9 164–74

[26] Poon H C, Gummel H K and Scharfetter D L 1969 High injection in epitaxialtransistors IEEE Trans. Electron Devices 16 455–8

[27] Matutinovic-Krstelj Z, Prinz E J, Schwartz P V and Sturm J C 1991Reduction of p+–n+ junction tunnelling current for base currentimprovement in Si/SiGe/Si heterojunction bipolar transistors IEEEElectron Device Lett. 12 163–5

[28] Webster W M 1954 On the variation of junction-transistor currentamplification with emitter current Proc. IRE 42 914–20

[29] Cottrell P and Yu Z 1990 Velocity saturation in the collector ofSi/GexSi1−x/Si HBTs IEEE Electron Device Lett. 11 431–3

[30] Yu Z, Cottrell P E and Dutton R 1990 Modelling and simulation of high-levelinjection behaviour in double heterojunction bipolar transistors IEEEBCTM Proc. pp 192–4

[31] Gao G-B, Fan Z-F and Morkoc H 1991 Analysis of cut-off frequency roll-offat high currents in SiGe double-heterojunction bipolar transistors Appl.Phys. Lett. 58 2951–3

[32] Mazhari B and Morkoc H 1991 Effect of collector-base valence-banddiscontinuity on Kirk effect in double-heterojunction bipolar transistorsAppl. Phys. Lett. 59 2162–4

[33] Joseph A J, Cressler J D, Richey D M and Niu G 1999 Optimization ofSiGe HBTs for operation at high current densities IEEE Trans. ElectronDevices 46 1347–54

[34] Harame D L, Stork J M C, Meyerson B S, Crabbe E F, Patton G L,Scilla G J, de Fresart E, Bright A A, Stanis C, Megdanis A C, Manny M P,Petrillo E J, Dimeo M, McIntosh R C and Chan K K 1990 SiGe-base pnptransistors fabricated with n-type UHV/CVD LTE in a ‘No Dt’ processDig. Symp. on VLSI Technol. pp 47–8

[35] Harame D L, Meyerson B S, Crabbe E F, Stanis C L, Cotte J, Stork J M C,Megdanis A C, Patton G L, Stiffler S, Johnson J B, Warnok J, Comfort J Hand Sun J-C 1991 55 GHz polysilicon-emitter graded SiGe-base pnptransistor Proc. Symp. VLSI Tech. pp 71–2

[36] Meyer R G and Muller R S 1987 Charge-control analysis of the collector-basespace-charge-region contribution to bipolar transistor time constant τtIEEE Trans. Electron Devices 34 450–2

[37] Smith P, Inoue M and Frey J 1980 Electron velocity in Si and GaAs at veryhigh electric fields Appl. Phys. Lett. 37 797–8

[38] Pritchard R L 1955 High-frequency power gain of junction transistors Proc.IRE 43 1075–85

[39] Asbeck P M 1990 Bipolar transistors High Speed Semiconductor Devicesed S M Sze (New York: Wiley) pp 335–97

[40] Werner Jr R M and Grung B 1983 Transistors: Fundamentals for theIntegrated-Circuit Engineering (New York: Wiley)

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[41] Roulston D J 1990 Bipolar Semiconductor Devices (Singapore: McGraw-Hill)

[42] Patton G L, Stork J M C, Comfort J H, Crabbe E F, Meyerson B S,Harame D L and Sun J Y-C 1990 SiGe-base heterojunction bipolartransistors: physics and design issues IEEE IEDM Tech. Dig. pp 13–16

[43] Comfort J H, Patton G L, Cressler J D, Lee W, Crabbe E F, Meyerson B S,Sun J Y-C, Stork J M C, Lu P-F, Burghartz J N, Warnock J, Scilla G,Toh K-Y, D’Agostino M, Stanis C and Jenkins K 1990 Profile leveragein self-aligned epitaxial Si or SiGe base bipolar technology IEEE IEDMTech. Dig. pp 21–4

[44] Tang D D and Lu P F 1989 A reduced-field design concept for highperformance bipolar transistors IEEE Electron Device Lett. 10 67–9

[45] Lu P F, Comfort J H, Tang D D, Meyerson B and Sun J Y-C 1990 Theimplementation of a reduced-field profile design for high-performancebipolar transistors IEEE Electron Device Lett. 11 336–8

Chapter 4

DESIGN OF SIGE HBTS

As semiconductor technology continues to evolve, numerical modelling ofthe electrical behaviour of advanced devices has become vital. Numericaldevice modelling based on the self-consistent solution of the fundamentalsemiconductor equations dates back to the famous work of Gummel in1964 [1]. In Gummel’s one-dimensional (1D) discretization, the Poissonequation and the current continuity equations are decoupled and solvedsequentially until convergence. Gummel’s approach was later extended byde Mari [2] and applied to transient simulations of a 1D p–n junction. Avery important breakthrough in the discretization of the current transportequations was reported by Scharfetter and Gummel in 1969 [3]. TheScharfetter–Gummel (SG) discretization scheme has since been used byall important device simulation programs.

During the 1970s and 1980s, several 1D and 2D programs weredeveloped, and made freely available to the research community. Examplesinclude SEDAN [4] for 1D simulations, MINIMOS [5] for 2D MOStransistor simulations, BAMBI [6] for arbitrary semiconductor structuresand PISCES [7], a 2D finite-element simulator, which rapidly became anindustry standard and formed the basis of future commercial products suchas Silvaco–ATLAS [8], Avant–Medici [9] and PISCES–2ET [10].

In 1977, Sutherland and Hauser [11] were the first to use numericaltechniques to analyse heterojunction devices. They showed that the basicformulation for homojunction devices could easily be generalized to includethe effects of a position-dependent band structure. The formulation wasfurther developed [12] to include field-dependent mobility to fit the steady-state velocity field characteristics, and later expanded to treat degeneratesemiconductors via Fermi–Dirac statistics [13–15].

HQUPETS [16] was an early 2D simulation tool developed for SiGeHBTs, and has been extensively used for device design [17]. Severaladvanced 1D simulators, specific to SiGe HBTs, such as a simulatorfor cryogenic research and silicon–germanium bipolar device optimization

104

Design of SiGe HBTs 105

(SCORPIO) [18] and PROSA [19], have been reported.Although the drift–diffusion (DD) model is the most widely used

and understood tool for semiconductor device simulation, it unfortunatelyfails to predict non-stationary transport effects. As a derivative ofthe Boltzmann transport equation (BTE), it also fails to reflect thequantum mechanical nature of carrier transport. The continuous pushtoward smaller devices has led to a need to address these shortcomings,and to the development of more sophisticated physical models, such asthe hydrodynamic and energy transport models [20, 21], the sphericalharmonics expansion method [22] and the Monte Carlo technique [23–27].Unfortunately, since the Monte Carlo method involves keeping statistics ona large number carriers undergoing random collisions, it is very expensivein terms of computer time. The simulation of a complete transistor requirestracking a prohibitive number of carriers in order to attain statisticalsignificance. This typically limits the Monte Carlo technique to use anaid in studying only part of the transistor, for instance the emitter–basejunction.

In the hydrodynamic or energy transport model, the first threemoments of the BTE are taken, yielding the particle, momentum andenergy conservation equations [20]. To solve these equations, it is generallynecessary to make many assumptions (for instance invocation of therelaxation time approximation). As the drift–diffusion model is pushedto its limits, more people are trying the hydrodynamic method of solution.A complete hierarchy of approaches and analyses has been reviewed byRavaioli [28]. However, the increased rigour of such models comes at theexpense of increased CPU time, so for the simulations reported in thisbook we confine our discussion almost exclusively to the drift–diffusionmodel. Regardless of the modelling methodology used, the ultimateresponsibility will always rest on the user of the simulator to intelligentlyinterpret the results and know when the assumptions inherent to themethod are being violated. Otherwise, as was pointed out by Tangand Laux [29], ‘. . . computationally sophisticated 2D or even 3D devicesimulations are rendered merely expensive, and perhaps misleading, curve-fitting programs’.

The aim of this chapter is to give some insight into the formulationof a physical device model for a SiGe HBT and to show how it canbe applied for HBT transistor design. The model equations account forthe position-dependent variation of energy bandgap, the dependence ofmobility on different scattering mechanisms, carrier velocity saturation,doping-dependent carrier lifetime and heavy doping effects. The resultingHBT model corresponds closely to that implemented in the Silvaco–ATLASdevice simulator [8], which has been used in a number of the examplesconsidered. A number of studies are presented where model prediction iscompared to measured data.

106 Design of SiGe HBTs

4.1. DEVICE MODELLING

Physically based device simulation predicts the electrical characteristicsassociated with a specified physical structure and bias conditions. Thisis achieved by mapping the structure onto a two-dimensional or three-dimensional grid consisting of a number of grid points called nodes. Byapplying a set of partial differential equations, derived from Maxwell’sequations to this grid, the transport of carriers can be simulated. Byspecification of appropriate boundary conditions, dc, ac and transientmodes of operation can be modelled. Physical simulation has twoimportant characteristics. It is much quicker and cheaper than performingexperiments. In addition it provides information that is difficult orimpossible to measure. The main drawback is that all the relevant physicsmust be incorporated into the simulator. The user must specify the problemto be solved by defining:

• the physical structure;• the physical models; and• the bias conditions for which electrical characteristics are required.

A basic requirement for a successful physical simulation of asemiconductor device is a mathematical model describing its operation.The model is characterized by a set of fundamental equations which linkthe electrostatic potential and the carrier densities within some predefinedsimulation domain. These equations are derived from Maxwell’s laws andconsist of Poisson’s equation and the continuity equations for electrons andholes. Poisson’s equation relates variations in electrostatic potential to thespace-charge density and is given by,

∇ · (ε∇ψ) = −q (p− n+N+D −N−

A

)− ρs (4.1)

where ψ is the electrostatic potential, ε is the local dielectric permittivity,q is the charge of an electron, p and n are the hole and electronconcentrations, ND and NA are the ionized donor and acceptor impurityconcentrations and ρs is the surface charge density.

The continuity equations, which describe the way that electron andhole carrier densities evolve as a result of transport processes, generationand recombination processes, are given by,

∂n

∂t=

1q∇ · 5Jn + (G−R) (4.2)

∂p

∂t= −1

q∇ · 5Jp + (G−R) (4.3)

where Jn and Jp are the electron and hole current densities, and G and Rare the generation and the recombination rates, respectively. The above

Device modelling 107

equations provide the general framework for device simulation. However,further secondary equations are necessary to specify particular physicalmodels for current density, generation recombination rates. The currentdensity equations are usually obtained by applying approximations andsimplification to the BTEs. These assumptions can result in a number ofpossible transport models such as the drift–diffusion model [30], the energybalance and the hydrodynamic models [20]. The choice of transport modelcan impact on the choice of generation and recombination model. By farthe simplest and most commonly used model in device simulation is thedrift–diffusion model. Until recently this model was adequate for nearlyall semiconductor devices but it tends to become less accurate for smallfeature sizes [28].

In the drift–diffusion model, the current densities are expressed interms of quasi-Fermi levels Φn and Φp as

5Jn = −qµnn∇φn (4.4)

5Jp = −qµpp∇φp (4.5)

where µn and µp are the electron and hole mobilities. Using Boltzmannapproximations, the quasi-Fermi levels may be related to the carrierconcentrations and the potential as given by

n = nie exp[q (Ψ − φn)kTL

](4.6)

p = nie exp[−q (Ψ − φp)

kTL

](4.7)

where nie is the effective intrinsic carrier concentration and TL is the latticetemperature. These two equations may then be rewritten as

Φn = ψ − kTLq

lnn

nie(4.8)

Φp = ψ +kTLq

lnp

nie. (4.9)

By substituting these equations into the current density expressions,one obtains

5Jn = qDn∇n− qnµn∇Ψ − µnnkTL∇ (ln(nie)) (4.10)

5Jp = −qDp∇p− qpµp∇Ψ+ µppkTL∇ (ln(nie)) (4.11)

where the last term accounts for the gradient in the effective intrinsic carrierconcentration, taking into account bandgap narrowing effects. Effectiveelectric fields are given by

5En = −∇(ψ +

kTLq

lnnie

)(4.12)


5Ep = −∇(ψ − kTL

qlnnie

). (4.13)

From the above and using Einstein relationships, the familiar drift–diffusionexpressions are as follows:

5Jn = qµn 5En + qDn∇n (4.14)

5Jp = qµp 5Ep − qDp∇p. (4.15)

In the case of Boltzmann statistics, Dn and Dp are given by

Dn =kTLqµn (4.16)

Dp =kTLqµp. (4.17)

In the case of the energy balance (EB) model, a higher-order solution tothe generalized BTE is necessary to include an additional coupling of thecurrent density to the carrier temperature (energy). Then the currentdensity and energy flux densities are expressed as

5Jn = qDn∇n − µnn∇Ψ+ qnDTn ∇Tn (4.18)

5Sn = −Kn∇Tn −(kδnq

)5JnTn (4.19)

5Jp = qDp∇p − µpp∇Ψ+ qpDTp ∇Tp (4.20)

5Sp = −Kp∇Tp −(kδpq

)5JpTp (4.21)

where Kn,p and δn,p are respective transport coefficients for electrons andholes that depend on the corresponding carrier temperatures Tn and Tp.Sn and Sp are the flux of energy (or heat) from the carrier to the lattice.Full details of the formulation are given in [31].

4.2. NUMERICAL METHODS

Several different numerical methods can be used to solve the semiconductorequations. In general, there are three approaches: decoupled (Gummelmethod), fully coupled (Newton method) or a combination method. Thedecoupled method will solve for each unknown in turn keeping othervariables constant, repeating the process until a stable unchanging solutionis achieved. Fully coupled techniques, such as the Newton method, solve thetotal system of unknowns together. The combined method will only solvesome of the equations fully coupled. The Newton method is the preferred

Numerical methods 109

method as it offers quadratic convergence, provided a suitable initial guesscan be estimated. Because of this constraint, it is always advisable to usesmall incremental changes to the applied voltage.

In performing a simulation, the device starts with zero bias on allelectrodes. Solutions are obtained by stepping the bias on electrodes fromthis initial equilibrium condition, using small steps in voltage. Once asolution is obtained, the current flowing through each electrode is calculatedby numerical integration. Internal quantities, such as carrier distributionsand electric field throughout the device, can then be computed or presentedgraphically.

There are several ways to predict the small-signal and large-signalhigh-frequency properties of semiconductor devices. A review of thesedifferent techniques has been given by Laux et al [32]. Frequency domainperturbation analysis is used to calculate the small-signal characteristics,while Fourier analysis is required for a large-signal response. InATLAS, frequency domain perturbation of a dc solution can be usedto calculate small-signal characteristics at any frequency. Variables arerepresented as the sum of a known dc component and an unknownsinusoidal ac component. The semiconductor equations are expanded withdifferentiation in time becoming equivalent to multiplication by jω. Thedc solution is subtracted, and what remains is a complex linear systemwhose unknowns are the ac components. Solving this linear system givesthe small-signal y-parameters. If the Newton method is used for the dcsolution, then the Jacobian matrix associated with the dc operating pointcan be used directly in the small-signal analysis without recomputation. Ifthe semiconductor device is treated as a two port network, with definedinput and output ports, then knowledge of the y-parameters permits allother small-signal parameters to be calculated. The advantage of thisapproach is that the determination of y-parameters is based solely onthe physical structure, and hence does not rely on any predefined lumpedelement equivalent circuit model.

These y-parameters can then be used to find different power gains [33].Among the various power gains described so far in the literature several,such as maximum available gain (MAG), maximum stable gain (MSG)and maximum available unilateral gain (MAUG), have found widespreaduse. Additionally, a figure-of-merit that has been used extensively formicrowave characterization is Mason’s invariant U (or Mason’s gain).These quantities are calculated from the measured small-signal scatteringparameters because of the ease of measurement at high frequencies.

All the above mentioned gains can be conveniently expressed iny-parameters as follows:

MSG =∣∣∣∣y21y12∣∣∣∣ (4.22)


MAG =∣∣∣∣y21y12∣∣∣∣ (k −√k2 − 1)

(4.23)

where

k =2Re(y11)Re(y22) −Re(y12y21)

|y12y21| (4.24)

U =|y21 − y12|2

4[Re(y11)Re(y22) −Re(y12)Re(y21)] (4.25)

MAUG =|y21|2

4Re(y11)Re(y22). (4.26)

Maximum available gain is obtained when both input and output aresimultaneously conjugately matched. MAG exists only when the deviceis unconditionally stable when k > 1. As can be seen from equations (4.25)and (4.26), U equals MAUG only if the device is unilateral, i.e., y12 = 0.MAG and MSG are equal to each other once the device is unconditionallystable. The frequency at which MAG becomes unity is often defined asfmax. However, a full discussion on the interpretation of fmax is givenin [34]. Since common-emitter microwave transistors may have power gainwith no impedance transformation, they can have useful gain when insertedinto a 50 Ω system. This gain is identical to |s21|2.

ATLAS has an option to easily convert y-parameters obtained fromac analysis, to s-, z- or h-parameters. The unity gain cut-off frequencyis extracted from extrapolation of the high-frequency asymptote of a plotof the magnitude of h21 in dB versus log (frequency). Most BJT devicesat a sufficiently low frequency can be represented as single pole devices.This assumption is equivalent to a high-frequency asymptote with a slopeof −20 dB per decade. However, both Cbe and Cbc capacitances are biasdependent, and so is the cut-off frequency. From the MAG (in dB) versuslog (frequency) plot, fmax is extracted at the point where MAG becomes0 dB.

4.3. MATERIAL PARAMETERS FOR SIMULATION

Electrons and holes in a device are accelerated by electric fields but losemomentum as a result of various scattering processes. These scatteringmechanisms include lattice vibrations, impurity ions, other carriers,interfaces and material imperfection. To simplify these mechanisms formodelling purposes, mobility is usually defined as a function of latticetemperature, local electric field and doping concentration. In a devicesimulator, a mobility model is further subdivided into

• low-field behaviour,

Material parameters for simulation 111

• high-field behaviour,• bulk semiconductor regions, and• inversion layers.

In the low-field region, mobility is principally dependent on phononand impurity scattering, both of which tend to decrease the low-fieldmobility. High-field behaviour shows that carrier mobility decreases withelectric field. The mean drift velocity no longer increases linearly withincreasing electric field, but rises more slowly. Eventually the velocitysaturates at a constant velocity commonly denoted by the symbol vsatwhich is principally a function of lattice temperature. Modelling mobilityin bulk material involves characterizing µn0 and µp0 as a function of dopingand lattice temperature and describing the transition between low-field andhigh-field regions. Modelling carrier mobility in inversion layers presentsadditional complications due to surface scattering and quantum mechanicaleffects. These effects are important for accurate simulation of MOS devices.The transverse electric field is often used to characterize mobility variationwithin inversion layers.

In ATLAS, a wide (and somewhat baffling) range of different siliconmobility models is available. Full details are given in the ATLAS manual[8]. The low-field mobility can be characterized in five different ways: userdefined; a lookup table as a function of doping; an analytic function ofdoping and temperature [35]; a carrier scattering model relating mobilityto carrier concentration and temperature; or a unified model dependent onimpurity, lattice and carrier–carrier scattering and temperature [36,37]. Forbipolar device simulation, the latter model is recommended as it applies aunified description of minority and majority carrier mobilities. The modelshows excellent agreement with available experimental data.

As carriers are accelerated in an electric field, their velocity will beginto saturate at a high electric field. This effect has to be accounted for bya reduction of effective mobility, since the drift velocity is the product ofmobility and electric field in the direction of current flow. The followingexpression [38] is used to implement a field-dependent mobility for bothholes and electrons, that provides a smooth transition between low-fieldand high-field behaviour,

µ(E) = µo

[1/1 +(µoE

vsat

)β] 1β

(4.27)

where µo is the low-field mobility, E is the electric field parallel to thedirection of current flow, β is a constant, and vsat is the saturation velocity.The coefficient β is one for holes and two for electrons. The saturationvelocity vsat is calculated by default from the temperature-dependent


model,

vsat(T ) =2.4 × 107

1 + 0.8 exp (T/600)(4.28)

but specific values for holes and electrons can be specified, if required.The incorporation of germanium significantly changes the properties

of the base region and the emitter–base and base–collector junctions in aSiGe HBT. While silicon has been well characterized over the past 40 years,still not nearly as much is known about strained-SiGe. Many simplifyingassumptions are made in the SiGe material parameters. The addition ofGe reduces the bandgap of Si, leading to the narrow bandgap SiGe base ofthe HBT, as discussed in chapter 3. The lattice constant of the strained-Si1−xGex alloy differs considerably from that of Si. The incorporationof Ge also modifies the energy band structure, and density of states inthe conduction and valence bands. In addition, carrier mobilities anddiffusivities change owing to changes in the effective masses and alloyscattering. Finally, the dielectric constant, built-in potentials and depletionwidths in the p–n heterojunctions depend on the Ge concentration. As allthe device simulations reported in this book have been carried out usingthe Silvaco–ATLAS simulator [8], we consider in the following section, thematerial parameters used in the simulations.

4.3.1. SiGe: hole mobility

There have been few reports on the measurements of mobility in strained-Si1−xGex alloys. Mansevit et al [39] reported enhanced electron mobilitiesat room temperature, but the Ge mole fraction of the samples was notaccurately known. Monte Carlo simulations of electron mobility heavily-doped SiGe at room temperature indicate that µn will be almost 50% higherthan for silicon due to the smaller effective mass in SiGe [40]. Enhancedlow-temperature mobilities have been also observed for both holes andelectrons [41]. In addition to phonon, impurity and alloy scatteringmechanisms, strain is expected to play a major role in determining carriermobility. Due to strain effects, mobilities in SiGe are different for carrierstravelling parallel and perpendicular to the direction of growth.

In ATLAS version 5.0, there is no specific SiGe mobility modelincorporated, but a separate user specified model can be created bywriting specific functions in the C programming language, which are theninterpreted when running the simulation. For this purpose, a hole mobilitymodel may be based on a model developed by Mau [42] originating froman empirical fit to experimental data. The electron mobility model may bebased on theoretical computations by Manku and Nathan [43].

The composition, temperature and doping dependent hole mobility isgiven by:


(i) for majority carriers

µp = 49.0(T

300

)−0.45

+480.0 (T/300)−2.2 − 49.0 (T/300)−0.45(1.0 + (T/300)−2.4

)(Ntot/1.7 × 1017)0.74

(4.29)

(ii) for minority carriers

µp=

([122.3(T

300

)−0.45

+480.0(T/300)−2.2 − 122.3(T/300)−0.45

(1.0 + (T/300)−2.4) (Ntot/1.4 × 1017)0.7

]ρ

)

×(1.0 +

1.00.5 + (7.2 × 1020/Ntot)

2

)−1

(4.30)

where

ρ =(µmin(x) +

(µmax(x) − µmin(x))1 + (Ntot/2.35 × 1017)0.88

)

×(µmin(0) +

µmax(0) − µmin(0)1 + (Ntot/2.35 × 1017)0.88

)−1

(4.31)

whereµmin(x) = 68.7 exp

(51.2x3 − 34.2x2 + 8.7x

)(4.32)

andµmax(x) = 461.9 exp

(32.5x3 − 22.2x2 + 6.4x

). (4.33)

4.3.2. SiGe: electron mobility

The alloy scattering limited electron mobility components for coherentlystrained Si1−xGex, along directions perpendicular and parallel to thegrowth direction are given by [43]

µalloy⊥ =5.5 × 1018T

22.0Ncx(1 − x)m2t

(4.34)

µalloy‖ =5.5 × 1018T

4.0Ncx(1 − x)m2l

(4.35)

where Nc is the effective density of states for silicon.It may be noted that the alloy mobility decreases with increasing Ge

content. At low doping levels, alloy scattering and phonon scatteringpredominate, both of which have an E1/2 dependence. At high dopinglevels, impurity scattering becomes important, and it too has the sameenergy dependence. Since the conduction band of SiGe for x < 0.3 issimilar to that of silicon, and all the predominant scattering rates have an


E1/2 dependence, the individual parallel and perpendicular componentsmay be defined.

The parallel component of electron mobility in SiGe can thus beobtained by using Mathiessen’s rule

1µSiGe‖

=1µSi‖

+1

µalloy‖(4.36)

and the corresponding perpendicular component becomes

1µSiGe⊥

=1µSi⊥

+1

µalloy⊥(4.37)

where the mobility of silicon for parallel and perpendicular to the growthplane is expressed as [43]

µSi⊥ =3.0µSi

(mt/ml + 2.0)(4.38)

µSi‖ =3.0µSi

2.0(ml/mt) + 1.0(4.39)

where ml and mt are longitudinal and transverse density of state massesin silicon.

At very high concentrations, the Caughey–Thomas relationship [38]no longer suffices to describe the carrier mobility. The effect of ultrahighconcentrations on mobility have been analysed by Klaassen [36], and themodified expression for majority and minority mobility for electron in sili-con is given by:

(i) for majority carriers

µSi =

[74.5(T

300

)−0.45

+1430.0(T/300)−2.3 − 74.5(T/300)−0.45

(1.0 + (T/300)−2.6(Ntot/8.6 × 1016)0.77

]/Z

(4.40)(ii) for minority carriers

µSi =

[200.0(T

300

)−0.45

+1430.0(T/300)−2.3) − 200.0(T/300)−0.45

(1.0 + (T/300)−2.6)(Ntot/5.3 × 1016)0.68)

]

(4.41)where

Z = 1.0 +1.0

0.21 + (4.0 × 1020/Ntot)2(4.42)

where Ntot is the total doping and the ‘clustering’ function Z(N) is fittedanalytically.


To evaluate the mobility of strained-SiGe, alloy scattering as well asenergy shifts in the conduction band have to be included. The shiftsare taken into account through the electron concentration, since thetotal mobility is given by a weighted average of the unstrained electronconcentration of the ith conduction band, with the corresponding strainedelectron concentration.

The components of the total electron mobility of strained-SiGe, for thegrowth plane µxx, and plane parallel to the growth direction µzz, can berepresented as [43]

µxx =

(µSiGe⊥ + µSiGe‖

)exp(−∆Ex/kT ) + µSiGe⊥ exp(−∆Ez/kT )

2.0 exp(−∆Ex/kT ) + exp(−∆Ez/kT )(4.43)

µzz =2.0µSiGe⊥ exp(−∆Ex/kT ) + µSiGe‖ exp(−∆Ez/kT )

2.0 exp(−∆Ex/kT ) + exp(−∆Ez/kT )(4.44)

where ∆Ex = −0.21x and ∆Ez = 0.42x are the splitting energies due tothe shift in the [001], [010] and [100] bands.

Despite the apparent complexities of the latter model, a morestraightforward model has been proposed in the 1D SCORPIO simulator[18], which describes the mobility enhancement of both carriers in SiGe asa linear function

µSiGe(x) = (1 +K.x)µSi (4.45)

where K is a fitting constant taken to be 10. Although there are conflictingreports concerning the degree of SiGe mobility enhancement which occursin a HBT, Richey et al [18] conclude that their much simpler model givesexcellent agreement with measured data.

4.3.3. SiGe: bandgap

The most significant material parameter to be specified in the simulationof SiGe HBTs is the bandgap narrowing induced by incorporation of aGe fraction x. A number of different models have been put forward.Polynomial fits by Bludau et al [44] describe the temperature dependenceof the energy bandgap of pure silicon at or below room temperature. Thehigh-temperature model from Sze [45] is slightly modified to match theroom temperature value and is given by

Eg(T ) = 1.170+1.059×10−5T −6.05×10−7T 2 0 ≤ T ≤ 170 K (4.46)

Eg(T ) = 1.1785 − 9.025 × 10−5T − 3.05 × 10−7T 2 170 ≤ T ≤ 300 K(4.47)

Eg(T ) = 1.170 − 4.73 × 10−4T 2

T + 624.93T ≥ 300 K. (4.48)


An empirical a fit to the data provided by People [46] for the bandgapof strained-Si1−xGex alloys on Si(100) substrates is given by

Eg(x) = 1.124 − 1.22x+ 0.88x2 x ≤ 0.6. (4.49)

A linear fit is used for 0.6 < x < 1.0, which assumes that the bandgap ofstrained pure Ge on (100) Si is 0.6 eV. Note that the bandgap of strained-SiGe is considerably smaller than that of bulk-SiGe.

In ATLAS, to give increased accuracy, the SiGe bandgap is modelledby a complex piecewise linear function of x, as defined in full in the ATLASmanual. For values of x likely to be encountered in a SiGe HBT (x < 0.245),the following equation applies

Eg(x) = 1.08 + x(0.945 − 1.08)/0.245. (4.50)

In ATLAS, an alternative temperature dependence of the bandgap Eg(T )for SiGe is given as

Eg(T ) = Eg(0) − αT 2

T + β= Eg(300) + α

[3002

300 + β− T 2

T + β

](4.51)

where the composition dependences of α and β are given by:

α = (4.73(1 − x) + 4.77x)10−4

β = 636.0(1 − x) + 235.0x.

The electron affinity of SiGe is assumed to be independent of thecomposition x and equal to 4.07 eV, identical to that of Si.

In a BJT model, the intrinsic carrier concentration nio, which dependson the effective density of states in the conduction and valence bands andthe bandgap, plays an important role. The effective conduction and valenceband density of states in silicon are given by the well-known expressions:

Nc = 2(2πm∗

nkT

h2

)3/2Nv = 2

(2πm∗

pkT

h2

)3/2(4.52)

where h is Planck’s constant, and m∗n and m∗

p are the effective masses ofthe electron and hole density of states.

The effective density of states decreases with increasing Ge content,because the amount of degeneracy in both the valence and conductionband decreases [43, 47]. In ATLAS, an empirical function used to give thecomposition dependence of densities of states for SiGe is given by:

Nc = 2.8 × 1019 + x(1.04 × 1019 − 2.8 × 1019) (4.53)

Nv = 1.04 × 1019 + x(6.0 × 1018 − 1.04 × 1019). (4.54)


By using equations (4.53) and (4.54), one can calculate the intrinsic carrierconcentration as a function of the Ge content

n2io(x) = NcNv exp(

−Eg(x, T )kT

). (4.55)

In addition to the Ge-induced bandgap narrowing, the high doping in thebase induces additional bandgap narrowing, similar to that observed insilicon. Although several bandgap narrowing and mobility models havebeen proposed for silicon [48–50], little information is available in theliterature for Si1−xGex [51]. The default model in ATLAS version 5.0assumes that the bandgap narrowing due to heavy doping is the sameas that in silicon. This approach has the advantage that any differencesin the simulation of Si BJT and SiGe HBTs can then be unambiguouslyattributed to heterojunction action (due to Ge incorporation), rather thandifferences in model parameters. This assumption of equal values of doping-induced bandgap narrowing in silicon and Si1−xGex is reasonably good forbase doping concentrations up to approximately 1 × 1019 cm−3 [51], butfor higher concentrations there is some evidence [52] to suggest that thebandgap narrowing in Si1−xGex is lower than that in silicon.

Bandgap narrowing effects due to heavy doping are modelled byreplacing the intrinsic carrier concentration nio with an effective carrierconcentration nie(x, y) where

nie(x, y) = nio exp

qa12kT

ln N(x, y)

a2+

((lnN(x, y)a2

)2+ a3

)1/2

(4.56)

where a1 = 0.00692, a2 = 1.3 × 1017 cm−3 and a3 = 0.5 are modelparameters. In ATLAS, the dielectric constant of SiGe as a function ofcomposition is given by

ε = 11.9 + 4.1x. (4.57)

4.3.4. Recombination and carrier lifetime

The dominant recombination processes in bulk-Si are Shockley–Read–Hall(SRH) and Auger recombination. Radiative recombination is negligiblesince silicon is an indirect bandgap semiconductor, and recombinationinvolving excitons and shallow-level traps is only important at lowtemperature. The total recombination rate due to Auger and SRHrecombination can be written as:

R =[Ann+App+

1τn(p+ p1) + τp(n+ n1)

] (np− n2ie

). (4.58)


In equation (4.58), An and Ap are the electron and hole Augerrecombination coefficients and nie is the effective intrinsic carrierconcentration including bandgap narrowing effects. τn and τp are theminority carrier SRH lifetimes and n1 and p1 are constants which dependon the energy of the deep-level traps. Commonly used (default) values forthe radiative and Auger recombination coefficients are An = 5.0×10−32 andAp = 9.9 × 10−32 for silicon [53]. Since strained-SiGe is similar to siliconin band structure, exactly the same recombination model is assumed forSiGe.

The minority carrier lifetimes in silicon are doping-dependent. Fordoping concentrations up to 1019 cm−3, an empirical fit to experimentaldata gives

τ(N) =τ(0)

1 +N/N0(4.59)

for both electrons and holes. τ(0) is the minority carrier lifetime in lightly-doped silicon and N0 is the reference doping. A good fit to experimentaldata is achieved by setting N0 = 7.1 × 1017 cm−3 for both n- and p-type silicon, τ(0) = 3.95 × 10−4 s for holes and τ(0) = 1.70 × 10−5 s forelectrons [54]. However, τ(0) is very much process dependent. Studieson the determination of minority carrier lifetime in SiGe have shown thatthe lifetimes are believed to be somewhat shorter than silicon minoritycarrier lifetimes (in the nanosecond range), due to the large number ofmisfit dislocations.

4.4. HISTORY OF SIMULATION OF SIGE HBTS

Numerous papers have appeared in the literature on both the numericaland analytical modelling of the SiGe HBTs [40, 55–61]. Much of the earlywork on simulation of SiGe HBTs was carried out over a decade ago andsignificant improvements in performance have since been achieved.

Smith and Welbourn [40] reported that for a SiGe transistor with a0.15 µm thick strained layer base (with 15% Ge, ∆Ev = 170 meV and 50%enhancement of electron mobility due to strain) an fT of 20 GHz shouldbe realizable before the onset of base widening. The value of fmax wasestimated to be 40 GHz. This represented a threefold increase of speedover the homojunction devices at that time. Pejcinovic et al [56] simulatednumerically the small-signal performance of a SiGe HBT. The heavy dopingeffect in SiGe was assumed to be the same as in Si, and effects of strain andalloy scattering on the mobility were included in the model. The dopingconcentrations in the emitter, base and collector were 7×1019, 2×1019 and4.5 × 1017 cm−3, respectively. The authors found that for the Ge fractionx = 0.2, the turn-on voltage of the HBT was smaller by 0.12 V as comparedto an otherwise identical Si homojunction transistor. The frequency fT wastwice as large as in the Si transistor and fmax was even larger.

Experimental SiGe HBTs 119

In early 1989, Won and Morkoc [60] examined theoretically the high-speed capability of the SiGe HBTs. They included alloy scattering andstrain effects on the mobility in the model. Several doping concentrationswere considered. The collector and base doping concentrations wereoptimized by making a compromise between speed and breakdown voltage.If the parameters are optimized to obtain an fT of 75 GHz, the estimatedfmax value is 35 GHz at a current density of 1×105 A cm−2 and Vbc = 5 V.The theoretical work done during this period showed that the HBTs hadgreat promise, once technological problems encountered in their fabricationwere resolved.

Hueting et al [61] have optimized a SiGe HBT design for high-frequency performance and claimed that a box type Ge profile with theleading edge approximately in the middle of the base is optimal. Thedoping concentrations in the emitter, base and collector were 2 × 1021,2.2 × 1018 and 1 × 1017 cm−3, respectively, while the Ge concentration inthe base was 11.5%. An fT value of 45 GHz for a base thickness of 600 Awas obtained. Hueting et al studied the effect of grading the Ge profilein the base and concluded that (in their opinion) the grading of Ge in thebase is of minor importance. Several other simulation techniques such asMonte Carlo [62–64], energy transport [19,65] have also been employed forthe simulation studies of SiGe HBTs.

4.5. EXPERIMENTAL SIGE HBTS

Since the introduction of SiGe into conventional Si technology, variousresearch groups have demonstrated high-performance SiGe base HBTs withdiffering approaches to forming the Ge profile in the base. While the IBMgroup uses graded Ge profiles, the Daimler–Benz group focuses on SiGeHBTs with a uniform Ge box profile. The epitaxial growth of active deviceregions in Si-based technology is a significant departure from past devicefabrication, where epitaxy had been used solely for the controlled substrateformation. Epitaxial base technology has many advantages over an ion-implanted technology.

A box-like profile provides independent control over base width anddoping concentration. Thus, a base width as small as 30 nm, with avery high doping concentration, can be obtained. Even for these smallthicknesses, the base resistance is acceptable and punch-through is avoided.This allows reduction of charge storage in the emitter and independentcontrol of base resistance and base transit time. By tailoring the baseprofile, low values of emitter–base and base–collector capacitance, Cbe andCbc, can be obtained. The design can also be tailored for optimum ECLperformance in a digital circuit by obtaining high fT at low base resistance.

Epitaxial base technology provides the opportunity to independentlycontrol each of the delays defined in equation (3.31). Transit time is


reduced by both vertical scaling and Ge grading in the base. Self-alignedepitaxial base technology also allows reduction of extrinsic capacitancesand resistance to reduce the gate delays [66, 67]. Harame et al [68] havedeveloped a high-performance SiGe BiCMOS HBT process. During theemitter formation, considerable out-diffusion of boron takes place as thediffusion coefficient of boron is considerably larger than that of arsenic.The problem of boron out-diffusion can be avoided, and narrow bases canbe formed, if arsenic is replaced by phosphorus for doping the emitter [69].The diffusivity of phosphorus is much larger than that of arsenic and isclose to that of boron. In the devices designed and fabricated by Crabbeet al [69], phosphorus-doped emitters were used. The epitaxial SiGe baseswere grown by UHVCVD [70] at 550 C. The Ge profile was graded from0% at the emitter–base junction to 15% at the base–collector junction.The collector doping was 4 × 1017 cm−3 to avoid base widening at highcurrent densities. Lightly-doped spacers were placed in the emitter–baseand base–collector junctions to maintain reasonable values of BVebo andBVceo. The narrow base width reduced the intrinsic transit time from2.1 ps to 1.9 ps [71]. The cut-off frequency was 73 GHz at a collectorcurrent density of 2 mA µm−2. The peak fmax was only 26 GHz, dueto high extrinsic base resistance caused by insufficient activation of boronbecause of low emitter anneal temperature.

Gruhle et al [72] fabricated a high-performance MBE-grown SiGetransistor. Ge concentrations of 21–28% and boron concentrations of upto 2 × 1020 cm−3 were used to obtain simultaneously high current gainsand low base resistance. The SiGe HBT with the highest fmax (in 1995)was reported by Schuppen et al [73]. This transistor used a relatively thick(60 nm) base and heavy doping to minimize the intrinsic base resistance.The base transit time was reduced by a strong electric field with 0–15%Ge grading. The SiGe base was grown selectively by using a self-alignedCVD technology. The performance achieved was an fmax of 160 GHz anda gate delay of 19 ps in an ECL circuit. In the same year, Meister et al [74]reported a SiGe HBT with a 74 GHz fmax, resulting in a record CML gatedelay (at that time) of 11 ps.

Recently, a 0.2 µm self-aligned selective epitaxial growth (SEG) SiGeHBT, with shallow-trench and dual deep-trench isolations and Ti–salicideelectrodes, has been developed. The process, except for the SEG, is almostcompletely compatible with well-established silicon BiCMOS technology.The SiGe HBTs exhibited a peak fmax of 107 GHz and a record minimumECL gate delay of 6.7 ps [75]. An Si/Si0.65Ge0.35 abrupt HBT with transitfrequencies fT of 133 and 213 GHz at 300 and 77 K, respectively, hasbeen announced recently [76]. The corresponding maximum oscillationfrequencies are 81 and 115 GHz. A detailed analysis of the intrinsic delaytimes has shown that the base transit time plays the dominant role.

Device design issues 121

4.6. DEVICE DESIGN ISSUES

In the following sections, important parameters of SiGe HBTs (fT, fmaxand VA) will be considered in detail and attempts are made to illustratehow simulation has been used to optimize the device design for circuitapplications. Base, emitter and collector profile design issues at roomtemperature will be discussed. All the simulations have been performedusing the Silvaco–ATLAS device simulator as described in sections 4.1 and4.2, using default material parameters.

Figure 4.1. Doping profile and Ge profile (flat or box) of a SiGe HBT.


4.6.1. Base design

We consider a uniform (flat or box) Ge profile (x = 0.12) in the base.The device structure and the doping concentration used for simulation isshown in figure 4.1. A simulated band diagram comparing SiGe and Sitransistors is shown in figure 4.2. As can be seen in figure 4.3, the uniformGe box profile produces the sevenfold increase in β for 12% Ge at 300 K,since the enhancement depends exponentially on the bandgap reductionat the emitter–base junction. In the conventional Si BJT, β is inversely

Figure 4.2. Schematic band diagrams of a homojunction (Si BJT) and aheterojunction (SiGe HBT) bipolar transistor.


Figure 4.3. Comparison of dc current gain of an Si BJT and a flat base SiGeHBT.

proportional to the integrated base charge. Since base doping cannot beincreased indefinitely while maintaining adequate β, the flat Ge profile isparticularly useful in realizing a transistor with either a very high β, or amoderate β with lower intrinsic base resistance.

However, any significant enhancement in peak fT of a SiGe HBT overan Si BJT, depends principally on the utilization of Ge grading across thebase. The simulated peak cut-off frequency of 42 GHz for a uniform Geprofile is shown in figure 4.4.

Now we consider a graded Ge profile (defined for reference purposesas triangular) having 0% Ge at the emitter–base junction and 12% Ge


Figure 4.4. Simulated cut-off frequency of an Si BJT and a flat base SiGe HBT.

at the collector–base junction, as shown in figure 4.5. The Ge grading(0–12%), is effective for reducing τb, and thus increasing fT. In thistype of Ge profile design, there is no Ge-induced bandgap reduction atthe emitter–base junction, and the β is reduced compared to the flat Geprofile. However, as the β enhancement depends approximately linearly onthe Ge grading when there is no bandgap reduction at the emitter–basejunction, an enhancement in β of approximately 5 has been simulated. Inhigh-speed analogue applications, which require a high βVA product, thetriangular Ge profile would appear to offer a superior design [77]. Becauseβ is still enhanced for the triangular Ge profile, it is still possible to trade β


Figure 4.5. Doping profile and Ge profile (triangular) of a SiGe HBT.

for lower base resistance. Using this approach, both fT and base resistancecan be tailored to significantly increase fmax. It is seen from figure 4.6 thatfor a graded Ge profile in the base, fT has increased from 42 GHz (Ge boxprofile) to 63 GHz, but the gain has dropped from 360 to 200, as shown infigure 4.7.

A trapezoidal profile would appear to be a logical compromise betweenthe two previous Ge profiles. This type of profile was used successfullyto realize the first 1.0 Gb s−1 12-bit digital-to-analogue converter [77].Figures 4.8 and 4.9 show a simulation of a trapezoidal profile where the Gemole fraction at the emitter–base edge is 5% and it has been graded to reacha maximum Ge concentration of 15% at the base–collector junction. It isseen that the trapezoidal grading results in a good compromise betweenpeak current gain of 200, and fT of 50 GHz.


Figure 4.6. Comparison of peak cut-off frequency of a graded base versus a flatbase SiGe HBT.

4.6.2. Emitter design

An ideal emitter should provide low emitter saturation current density,low emitter resistance, low charge storage, low emitter–base depletioncapacitance, and good passivation at the perimeter of the emitter. Thepolysilicon emitter contact used in conventional Si technology meets mostof these requirements. The polysilicon–silicon interface also provides abarrier-to-hole injection into the emitter. An alternative approach to thepolysilicon emitter contact is to use single-crystal emitter. Such a structure


Figure 4.7. Comparison of dc current gain of a graded base and a flat base SiGeHBT.

is ideal to decouple the base from the emitter, thereby allowing arbitrarilyhigh base dopant concentrations. Furthermore, it allows a reduction inemitter–base capacitance, leading to higher fT at lower collector currentdensity, as long as the delay associated with minority carrier charge storagein the quasi-neutral emitter can be minimized by maintaining sufficientcurrent gain. A high–low emitter profile, consisting of a heavily-dopedpolysilicon contact on top of a thin epitaxial emitter cap addresses bothrequirements [78]. The emitter cap thickness should be small to minimizecharge storage and is typically 200–300 A. The highly-doped polysiliconcontact ensures low total emitter resistance.


Figure 4.8. Comparison of dc current gains of flat, graded (triangle andtrapezoid) base SiGe HBTs.

Three different thicknesses of low-doped emitter, namely 100, 200 and300 A, have been used for simulation as shown in figure 4.10. The peakvalue of Ge fraction x is 0.08. As expected, fT decreases marginally from30 GHz as the emitter cap thickness is increased from 100 to 300 A. Thelocation of the Ge profile with respect to the metallurgical emitter–basejunction plays a key role in the dc and ac characteristics of the HBT. Foran HBT with a linearly graded Ge profile and with a poly emitter contact,locating the emitter–base metallurgical junction right at the bottom ofthe Ge ramp is a good compromise to ensure moderate current gain while


Figure 4.9. Comparison of cut-off frequency of flat base, graded trapezoidalbase SiGe HBTs.

taking full advantage of the Ge grading to minimize the base transit time.The slope of the Ge profile at the edge of the emitter–base space-chargeregion on the base side can affect the ideality of the collector current [79].

4.6.3. Collector design

The design of the collector is dictated by conflicting requirements tosimultaneously achieve high breakdown voltage BVceo, low base–collectorcapacitance, low base–collector signal delay τbc, and a high value of


Figure 4.10. Emitter with different low-doped spacer layers. Ge and Boronprofiles in the base are also shown.

the knee current density at which fT decreases. The collector dopingprofile determines two critical performance parameters of the transistor:the base–collector delay time τbc, which is a significant component ofthe total intrinsic delay τec, and the intrinsic base–collector capacitancewhich governs circuit performance. A conventional approach to suppressbase widening is simply to utilize a thin highly-doped epitaxial collectorlayer. Consequently, base widening is suppressed at the expense of BVceodegradation. One of the methods to increase BVceo, while suppressing basewidening, is to introduce a retrograde collector profile [80].

In determining HBT performance, it should be recalled that thecollector–emitter breakdown voltage BVceo is directly related to the


Figure 4.11. Different collector doping profile and Ge profile (triangular) of aSiGe HBT.

cut-off frequency, according to the theoretical ‘Johnson limit’, and fallsmonotonically for increasing values of fT [81]. A 50 GHz transistorcorresponds to a breakdown voltage of 3.3 V. In general, therefore, somedegree of optimization is always required to yield the appropriate higherfT for a lower BVceo.

Increasing the peak collector doping density (Ncoll) above 1 ×1017 cm−3 improves the frequency performance in two ways:

(i) a reduction in transit time τbc giving increase in fT; and(ii) a delay onset of Kirk effect permitting operation at higher collector

current density since the Kirk (knee) current density (Jk) isproportional to the collector doping.


In simulations, as a compromise, we have assumed a minimum collectorconcentration of 5 × 1016 cm−3 at the base–collector junction, and haveramped the doping as shown in figure 4.11. Profiles 1, 2, and 3 correspondto peak values of 1.5 × 1017 cm−3, 2 × 1017 cm−3 and 4 × 1017 cm−3 ata depth of 0.4 µm. The effects of the different collector profiles on fT areshown in figure 4.12.

As expected, profile 3 (highest doping) produces the highest fT of49 GHz. Early work on achieving high fT with SiGe HBTs utilized collectorconcentrations in the range 2 to 6 × 1017 cm−3 [82, 83]. These highercollector dopings led to unacceptably high values of Cbc for most circuit

Figure 4.12. Effect of collector doping (ramping) on cut-off frequency.


applications, as they increase the input capacitance of the device via theMiller effect. Optimizing the collector profile consists therefore in tradingan increased transit time τec, arising from an increase in τbc with reducedcollector doping, for a reduction in the base–collector capacitance. Thispoint is considered again in chapter 5 where two variants of a process areconsidered: one to achieve very short ECL gate delay by using a relativelylow collector doping and the other using a much higher collector doping toachieve fT of more than 100 GHz. Figure 4.13 shows the effect of collectordoping on the simulated output characteristics. It is evident that the profilewith the highest fT yields the lowest BVceo.

Figure 4.13. Effect of collector doping on BVceo.


4.7. SMALL-SIGNAL AC ANALYSIS

A useful outcome of physical device simulation is the opportunity to usethe results to extract parameters which can be used in a compact modelfor circuit simulation. The particular virtue of device simulation in thiscontext is the ability to visualize how changes to a particular process orstructure affect the overall circuit performance. The whole field of compactmodelling for bipolar transistors is extensive, with the Gummel–Poonmodel, and recently the vertical bipolar inter-company (VBIC) model,widely used [84, 85]. A detailed consideration of these models is beyondthe scope of this book. However, by way of illustration, we present anexample showing how device simulation can yield component values for arudimentary small-signal lumped element model. In addition, a method ofdetermining the different components of the transit time by integration ofthe carrier distribution is also discussed.

4.7.1. Small-signal equivalent circuit

By treating the bipolar transistor as a two port network, it has beenexplained in section 4.2 that a device simulator such as ATLAS hasthe capability to determine all small-signal parameters. It is thereforepossible to use these parameters to extract the components of the hybrid-π small-signal equivalent circuit as shown in figure 4.14. This equivalentcircuit represents a somewhat idealized representation of the transistor andneglects distributed effects of minority carrier storage in the quasi-neutralemitter and base regions [86]. It assumes that all parasitic componentsassociated with resistance, inductance and capacitance of probes, pads and

Figure 4.14. Simplified hybrid-π model of a SiGe HBT.

Small-signal ac analysis 135

interconnects have been successfully de-embedded. In this model, Cbe is theemitter–base capacitance (representing the sum of diffusion and depletioncapacitance), rbe is the dynamic emitter resistance, Cbc is the base–collector capacitance, rbb is the base resistance, rcc the collector resistanceand ree the emitter resistance. The small-signal transconductance isexpressed as [87]

gm = gmo exp (−jωτd) (4.60)

where gmo is the low-frequency intrinsic transconductance and τd is thetransit time phase delay of transconductance.

To determine series resistance, it is most convenient to use small-signalz-parameters, where it can be shown [87]

Z11 = rbb + ree +Zπ

1 + gmZπ(4.61)

Z12 = ree +Zπ

1 + gmZπ(4.62)

Z21 = ree +Zπ

1 + gmZπ

[1 − gm

jωCbc

](4.63)

Z22 = rcc + ree +1

jωCbc

11 + gmZπ

+Zπ

1 + gmZπ(4.64)

whereZπ =

rbe1 + jωrbeCbe

. (4.65)

If small-signal ac simulations are carried out at relatively high frequency(typically in the range 0.02–0.1 fT), then since gmo ≥ 1/|Zπ|

ree = Re (Z12) − 1gmo

(4.66)

rbb = Re (Z11 − Z12) (4.67)

rcc = Re (Z22 − Z21) − CbegmoCbc

. (4.68)

The method of extraction of rbb and ree appears to work well, butextraction of rcc is problematic, because rcc is expressed as the smalldifference between the real parts of Z22 and Z21, and a further termrepresenting the high-frequency ac output resistance. This latter term,involving a ratio of capacitance, tends to be much larger than the unknownvalue of rcc, so it proves very difficult to obtain a consistent value ofrcc which is independent of the frequency at which it is evaluated. Inaddition, the accuracy of the second term is dependent on the accuracyof the evaluation of the other three parameters Cbe, Cbc and gmo. None


of these parameters are known with absolute certainty and have to beextracted using either y- or h-parameters using

Cbc = −Im(y12)ω

(4.69)

Cbe =Im(y11)ω

(rbb + rbe)2

r2be− Cbc (4.70)

and rbe can be reliably obtained from

rbe =1 −Re(y11)(rbb + ree)

Re(y11)(4.71)

at a frequency low enough that the reactance of Cbe does not affect Re(y11).Figure 4.15 shows how the value of base resistance, extracted using

equation (4.67), varies with frequency, as collector current is increased.The well-established mechanism of reduction in base resistance at highercollector current due to current crowding is evident in this figure. Thechoice of frequency is important in so far as one would like to evaluatethe base resistance at a frequency where the extracted value is relativelyinsensitive to the choice of frequency. Based on the pattern of variationseen in figure 4.15, it would appear that extraction of rbb at a frequencyof around 1 GHz, significantly below fT would appear to be a reasonablechoice.

Figure 4.15. Variation of rbb = Re(Z11 − Z12) with frequency.


Figure 4.16. Extraction of input resistance using (a) h-parameters and(b) z-parameters.

Figure 4.17. Extraction of output resistance using (a) h-parameters and(b) z-parameters.


Figure 4.16 shows that the equations (4.67) and (4.68) for rbb andrcc based on z-parameters are relatively independent of frequency in therange 1–8 GHz and it is clear that while rbb can be relatively accuratelydetermined from z-parameters (rather than h-parameters), the small valueof rcc, believed to be of the order of 20 ohms from sheet resistancecalculations, is masked by the much higher value of more than 200 ohms ofthe additional term involving the ratio of capacitance. This point is furtherillustrated in figure 4.17, which shows that the total output resistance canbe estimated by two methods: one using z-parameters, the other usingh-parameters. As indicated on the figure, both expressions nominally givethe same value. Neither equation however, is exact. Both involve a degreeof approximation, and the expected value of rcc is of the same order as thelikely error in using either of the two expressions. This example highlightsthe difficulty which can occur in determining collector series resistance fromsmall-signal parameters.

To evaluate gm, it transpires that the most appropriate method is touse h-parameters, rather than y-parameters. It has been shown that forthe small-signal equivalent circuit shown [34]

gm =Re(h21)Re(h11)

. (4.72)

Figure 4.18 shows that the above equation involving the ratio of

Figure 4.18. Extraction of gm using (a) y-parameters and (b) h-parameters.


h-parameters is more reliable in estimating the transconductance, gm. Useof Re(y21)/ω always underestimates gm, because it takes no account of theeffect of the voltage divider ratio due to rbb and rbe. This correction ofcourse requires accurate values of rbb and rbe so the computation usingh-parameters is always liable to be more reliable.

4.7.2. Evaluation of transit time

While small-signal analysis is useful in extracting fT from |h21|, it doesnot permit insight into the magnitude of the individual components thatcomprise the total transit time τec. To find the individual components of τecfrom device simulation, it is necessary to integrate the carrier concentrationwithin defined regions of the transistor, according to the analysis givenin [88]. When the semiconductor equations are solved numerically, thecarrier concentration is known at every node in the structure. Hence, it isrelatively straightforward to integrate the carrier concentration numericallyto give the individual components of transit time. The total transit timeis given by

τec =q

∆Jc

[∫ xeb

0∆n(x)dx+

∫ xbc

xeb

∆n(x)dx+∫ L

xbc

∆n(x)dx

]. (4.73)

Here we define the individual components by the incrementalrelationships:

• emitter–base depletion charging time

τeb =q

∆Jc

∫ xeb

0(∆n(x) − ∆p(x)) dx (4.74)

• base–collector depletion charging time

τbc =q

∆Jc

∫ L

xbc

(∆n(x) − ∆p(x)) dx (4.75)

• emitter transit time

τe =q

∆Jc

∫ xeb

0∆p(x)dx (4.76)

• base transit timeτb =

q

∆Jc

∫ xbc

xeb

∆n(x)dx (4.77)

• collector transit time

τc =q

∆Jc

∫ L

xbc

∆p(x)dx. (4.78)


In the formulation given, the integration is implicitly defined as one-dimensional through the active transistor region, where x = 0 defines theemitter contact, and x = L the collector contact. In this analysis, forsimplicity, the parameters xeb and xbc define the respective positions ofemitter–base and base–collector metallurgical junctions. A more rigorousdefinition of these two points, as the points of intersection of dp/dJc anddn/dJc, is given in [88]. This definition is, however, difficult to implementin a 2D device simulator and has not been used.

The values of differential carrier densities ∆n(x) and ∆p(x) can becomputed by perturbing the dc bias by a small amount, to induce asmall change in collector current density ∆Jc. The value of emitter–collector transit time τec, computed using this method, is comparable (butnot exactly identical) to the value of the SPICE parameter τF obtainedfrom the y-intercept of the graph of 1/(2πfT) versus 1/Ic as defined inequation (3.31) [89].

However, it should be borne in mind that all components of τec willvary to some extent with bias condition, whereas τF is an absolute valuedefined as 1/Ic → 0. Both emitter and base transit times are relativelyinsensitive to collector current but increase as expected at the onset ofhigh injection leading to a fall in fT [90].

Figure 4.19 shows the relative magnitudes of the components of transittime based on a simulation of a state-of-the-art HBT with a base widthof 40 nm, a Gaussian base doping profile with peak 1.5 × 1019 cm−3 anda low-doped emitter of 1018 cm−3. The transit times were evaluated as afunction of bias condition using equations (4.74)–(4.78).

The simulated maximum unity gain cut-off frequency for this transistorbased on h21 is 38 GHz, while the corresponding value of τF from figure 4.20is 3.6 ps. For comparison, if transit times are computed directly the

Figure 4.19. Variation of transit time components with collector current.


Figure 4.20. Extraction of SPICE parameter, τF from variation of fT withcollector current.

minimum value of τec before onset of high injection is 3.75 ps at a collectorcurrent of 7 mA. It should also be pointed out that, while the y-intercept ofthe extrapolated straight line in figure 4.20 gives τF, its slope represents thesum of the depletion capacitance Cje + Cjc as defined in equation (3.35).This represents an alternative method for the determination of parasiticcapacitance to the use of y-parameters.

4.7.3. ECL gate delay

Unlike the frequencies fT and fmax, there is no standard analyticalexpression universally accepted for the propagation delay of an ECL gate.This gate delay, which normally represents a performance measure fordigital circuits, depends not only on the intrinsic characteristics of thetransistor, but also on the circuit configuration and the values of loadresistance and capacitance. The unloaded ECL gate delay exhibits asimilar sensitivity to intrinsic device transit time, parasitic resistance andcapacitance as fmax. At low switching current levels, the gate delay isdominated by the base–collector capacitance, which is dependent on thedevice structure and layout geometry, whereas at high current levels thedelay is more strongly coupled to the total base resistance and the transittime of the device.

Approximate expressions for the gate delay for specific circuits havebeen used by Kroemer [91] and by Shafi et al [92] for the ECL circuitsemploying SiGe HBTs. The expression used by Kroemer is given by

τdel =52rbbCbc +

rbbRLτF + (3Cbc + CL)RL (4.79)


where RL is the load resistance and CL is the load capacitance of thecircuit. The importance of reducing the base resistance to improve thespeed is obvious from this equation (4.79). It is clear that a reduction inrbb will improve the switching time until the first two terms become smalland the final term involving RL dominates. Further improvement can onlybe obtained by reducing base–collector capacitance. The importance of theabove result lies not in the actual numerical values of different terms butin that it demonstrates the relative importance of the various transistorparameters in determining its speed.

Shafi et al [92] have used a different approach to calculate the gatedelay in an ECL circuit. Their calculations are based on the weightingfactors developed by Fang [93]. The calculations using this method werecompared with direct SPICE simulations and the two results agreed within5% for the specific technology considered. The propagation delay isexpressed as a sum of RC time constants and stored charge elements:

τdel =∑i

KiRiCi +Kjτec (4.80)

where summation over i includes all the resistances and capacitances of thelogic gate and those associated with the emitter, base and collector of allthe transistors in the circuit.

Shafi et al [92] calculated the numerical values of gate delay for SiGeHBTs and compared these with similar computations for homojunctiondevices. A Ge concentration of 12% was shown to be required in the SiGebase to provide sufficient gain enhancement to allow the reversal of theusual emitter and base doping concentrations. This results in a transistorwith a low base resistance and low emitter–base depletion capacitance. Fora fully optimized device, predicted propagation delays were 15 ps for theSiGe HBT and 29 ps for the Si BJT. Subsequently, as SiGe technologyhas developed over the last decade, bipolar scaling to ultrathin base and0.2 µm self-aligned technology has given rise to a propagation delay as lowas 6.7 ps by a research group from Hitachi [75].

In order to simulate ECL delay, circuit simulation using SPICE mustbe used. If the two-dimensional structure of the transistor is known, devicesimulation can be used to extract key SPICE parameters such as τF, Cje, Cjcand rbb from small-signal ac analysis, as illustrated in the previous section.These SPICE parameters can then be used in a circuit simulation to predictvariation in ECL gate delay with collector current. The advantage of thisapproach is that it provides insight into how the process can affect thecircuit performance.

Table 4.1 presents a representative sample of key SPICE parametersextracted for a scaled SiGe HBT process based on silicon-on-insulator (SOI)technology [94]. The technology, outlined more fully in chapter 5, utilizesan epitaxial base and lightly-doped emitter. To allow for effects of boron


out-diffusion the base profile is assumed to be Gaussian. In table 4.1, twosets of process parameters are considered. In the set labelled (a) the emitterdoping is 1018 cm−3, while in the set labelled (b), the emitter doping isreduced to 1016 cm−3.

The key issue illustrated by table 4.1 is to examine whether use ofa lower doping density in the emitter spacer layer can improve ECL gatedelay. A more lightly-doped emitter will of course degrade the overalltransit time and hence fT, but does yield a significantly lower emitter–base junction capacitance. This lower junction capacitance gives a markedimprovement in ECL gate delay particularly at lower collector currents,

Table 4.1. SPICE parameters for a SiGe HBT.

Transistor parameters (a) (b)

Base dose 1.2× 1013 cm−2 1.2× 1013 cm−2

Emitter doping (n-type) 1× 1018 cm−3 1× 1016 cm−3

Collector doping 1× 1017 cm−3 5× 1016 cm−3

Mask alignment tolerances 0.25 µm 0.25 µmGe fraction x 0.1 0.1Low-doped emitter width Wepi 0.05 µm 0.03 µmBase width Wb 0.038 µm 0.045 µm

Extracted SPICE parameters

Forward current gain (β) 356 190Transit time τF 3.0 ps 4.2 psBase resistance rbb at 1 mA 81 Ω 68 ΩCollector resistance rcc 42 Ω 63 ΩEmitter junction capacitance Cje 50.8 fF 14.7 fFCollector junction capacitance Cjc 13.5 fF 10.0 fFCollector substrate capacitance Cjs 2.2 fF 2.2 fFEarly voltage VA 75 V 101 V

Extracted small-signal parameters

Cut-off frequency fT from h21 38 GHz 29 GHzMaximum oscillation frequency fmax(MAG) 48 GHz 56 GHz

SPICE circuit simulations

Cut-off frequency fT at Ic = 5 mA 36.2 GHz 31.0 GHzMaximum oscillation frequency fmax SOI 35.1 GHz 38.3 GHzMaximum oscillation frequency fmax Si 29.8 GHz 30.6 GHzECL gate delay at 0.5 mA 39.0 ps 24.3 psECL gate delay at 1 mA 21.7 ps 16.7 psECL gate delay at 5 mA 18.4 ps 15.5 ps


Figure 4.21. Dependence of fmax on emitter–polySi length.

well below the current level at which peak fT is predicted. In addition, thecreation of the bipolar transistor in an SOI rather than a silicon substrateyields approximately 20% improvement in fmax due to lower collector–substrate capacitance in the SOI substrate, as shown in figure 4.21. In thisfigure, circuit simulation using SPICE parameters extracted from ATLAShas been used to determine fmax.

With the simulated values of base resistance as an input parameterfor SPICE, ECL gate delays have been computed as a function of baseresistance and are tabulated in table 4.2. It is seen that, as expected, theECL gate delay decreases with the decrease in rbb and the minimum valueis comparable to the experimentally reported values for a SiGe HBT ofcomparable dimensions [95].

Table 4.2. The dependence of ECL gate delay on base resistance. SPICEparameters used: VAF = 130 V, Cje = 7.5 pF, Cjs = 13 pF, Cjc = 5.5 pF.

Base resistance Gate delay (ps)

200 17.1100 14.750 13.325 12.5

Summary 145

4.8. SUMMARY

This chapter has considered how a SiGe HBT can be modelled in a devicesimulator. The relevant equations, relating to current flow in a structurewhere the bandgap is varying, were considered. Basic concepts employedin a simulation program were given. Key material parameters for SiGe,in so far as they differ from silicon, were outlined. A more accuratestrained layer SiGe mobility model should be used to take into account thedifferent mobilities (parallel and perpendicular to the growth direction) ofthe strained-SiGe layer.

The way in which ac simulation can be utilized to determine small-signal y-parameters was considered. Knowledge of y-parameters thenpermits any other small-signal parameter to be evaluated. In this way,both fT and fmax can be determined. A specific study of the design of anHBT with a base width of approximately 60 nm was fully described. Base,emitter and collector profile design issues were discussed in detail. HighβVA product necessary for analogue applications is of special interest, asit is achievable using SiGe HBTs. Devices with three different Ge profiles(flat, triangular and trapezoid) were considered. The optimum Ge profile inthe base was shown to be a trapezoidal profile. A retrograde collector profileallowed the condition fT = fmax to be optimized, whilst still achievingacceptable BVceo.

The significance of the ECL gate delay and the way in which devicesimulation can be used to predict ECL gate delay was outlined. Gatedelays of ECL circuits involving SiGe HBTs were computed using SPICEparameters extracted using small-signal analysis.

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[87] Lee S, Ryum B R and Kang S W 1994 A new parameter extraction techniquefor small-signal equivalent circuit of polysilicon emitter bipolar transistorsIEEE Trans. Electron Devices 41 233–8

[88] Van den Biesen J J H 1986 A simple regional analysis of transit times inbipolar transistors Solid-State Electron. 29 529–34


[90] Roulston D J 1990 Bipolar Semiconductor Devices (Singapore: McGraw-Hill)

[91] Kroemer H 1982 Heterojunction bipolar transistors and integrated circuitsProc. IEEE 70 13–25

[92] Shafi Z A, Ashburn P and Parker G J 1990 Predicted propagation delay ofSi/SiGe heterojunction bipolar ECL circuits IEEE J. Solid-State Circuits25 1268–76

[93] Fang W 1990 Accurate analytical delay expressions for ECL and CMLcircuits and their applications to optimizing high-speed bipolar circuitsIEEE J. Solid-State Circuits 25 572–83

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[94] Schiz J FW, Bonar J M, Lamb A C, Cristiano F, Ashburn P, Hemment P L Fand Hall S 1999 Leakage current mechanisms associated with selectiveepitaxy in SiGe heterojunction bipolar transistors Proc. ESSDERC’99pp 344–7

[95] Washio K 1999 SiGe HBTs and ICs for optical-fiber communication systemsSolid-State Electron. 43 1619–25

Chapter 5

SIMULATION OF SIGE HBTS

In chapter 3, we discussed the operating principle of a SiGe HBT, whilein chapter 4 we focused on the basics of physical device simulationand gave some examples of its application. In particular, it has beenshown that 2D simulations may be used with confidence for an accurateprediction of device performance. In this chapter, we develop thisconcept further by considering the simulation of some state-of-the-art SiGeHBTs, concentrating on those that have given particularly noteworthyperformance. As SiGe technology continues to develop with device scaling,performance will naturally tend to improve, so we are only endeavouringto present particular examples in some detail.

In section 5.2, we consider the device described by Meister et al[1]. This device was noteworthy in 1995 as the epitaxial-base (epi-base)bipolar technology was extended to SiGe technology, leading to a maximumoscillation frequency of 74 GHz and a CML gate delay time of 11 ps.In section 5.3, a later generation device [2] is simulated. In this device,particular attention has been paid to reproducing the two-dimensionalstructure. Excellent agreement in both fT and fmax has been achieved. Insection 5.4, we show how, in a transistor with a very thin base, conventionaldrift–diffusion simulation tends to overestimate the transit time and ahydrodynamic simulation can in principle give a more accurate result for atransistor when fT exceeds 100 GHz.

If SOI material is used as a substrate in a bipolar transistor,significant reduction in collector–substrate capacitance can be achievedwith consequent improvement in fmax [3]. However, self-heating of thesilicon island in which the HBT is formed can be problematic [4, 5]. Insection 5.5, a thermal simulation of a SiGe HBT fabricated in an SOIsubstrate is presented.

Problems encountered for the low-temperature operation of Si BJTscan be solved effectively by using heterojunction technology. Section 5.6describes examples of low-temperature simulation. Because of its bandgap-

152

Simulation of SiGe HBTs 153

engineered base, the SiGe HBT is particularly suitable for operationat cryogenic temperature [6–12]. Since the bandgap of the emitter islarger than that of the base, therefore the current gain increases at lowtemperature. Since doping in the base of an HBT can be very high, carriersdo not freeze at low temperature.

While most digital applications involve the use of ECL technology,SiGe technology offers the potential for reducing the delay of an integratedinjection logic (I2L) gate. I2L is a low-power bipolar technology suitablefor VLSI which traditionally has suffered from a relatively poor dynamicperformance. There has been renewed interest in I2L, motivated by theimpressive performance reported for SiGe HBTs [13,14]. The gate delay ofI2L circuits is primarily determined by stored charge in parasitic diodes

Figure 5.1. Doping profile and Ge profile (graded base) of a SiGe HBT.

154 Simulation of SiGe HBTs

associated with the extrinsic base region [15]. The lower bandgap ofSiGe therefore has a great impact on the propagation delay of integratedinjection logic. It is shown by simulation in section 5.7 that thatSiGe I2L may be a useful technology in high-performance and low-powerapplications, such as portable electronic systems [16].

As SiGe HBT technology appears to be exceptionally promising for RFand microwave analogue applications, the low-frequency noise performance,a key figure-of-merit, needs to be studied in detail. Section 5.8 presentsa comprehensive study on the noise performance of SiGe HBTs with

Figure 5.2. Gummel plot of a graded base SiGe HBT.

Epitaxial-base SiGe HBT (1995) 155

comparison to AlGaAs/GaAs HBTs and conventional Si BJTs fabricatedin different technologies. Finally, in section 5.9, the potential for SiGetechnology in a radiation intensive environment is considered.

5.1. EPITAXIAL-BASE SIGE HBT (1995)

In chapter 4, we established that, to design a high-performance HBT, it wasdesirable to use a low-doped emitter, thin base with a graded Ge profile andretrograde collector profile. In this section, the accuracy of the simulationis assessed, by comparison with devices recently reported in the literature.To optimize the high-frequency performance of a device, a nominal targetof fT ∼ fmax was used.

Figure 5.3. The dc current gain of a graded base SiGe HBT.


Epi-base technology has many advantages over ion-implantedtechnology. An implantation tail can be avoided and the resultant box-likedoping profile provides independent control over base width and dopingconcentration. Using epi-base technology, Meister et al [1] have reportedan experimental SiGe HBT. A base width of about 500 A and a peak basedoping concentration (6× 1018 cm−3) were used. The structure, includingthe Ge and doping profiles used in simulation, is shown in figure 5.1. TheGe concentration in the base has been graded from 0% at the emitter–basejunction to 12% at the centre of the base.

Figure 5.4. Typical output characteristics of a graded base SiGe HBT as afunction of collector doping.

Epitaxial-base SiGe HBT (1995) 157

Figure 5.2 shows the simulated Gummel plot and it is seen that almostideal base current characteristics are observed, with a peak dc current gainof approximately 210, as shown in figure 5.3. A unilateral power gain of22 dB at 10 GHz was achieved at a base–collector voltage of 2 V. Evenfor a base width of about 500 A, a high base doping (> 6 × 1018 cm−3)maintains a low base resistance and avoids punch-through.

In particular, the high fmax of 74 GHz originates from the integrationof the SiGe base, providing high cut-off frequency at low intrinsic baseresistance. The design can be tailored for optimum ECL or CMLperformance by obtaining high fT at low base resistance leading to a CMLgate delay time of 11 ps.

The effect of collector doping on the Early voltage obtained fromthe simulated output characteristics is shown in figure 5.4. Thesecharacteristics are obtained by utilizing a constant base current, (Ib =15 nA), as opposed to the more usual fixed base voltage boundaryconditions. It is seen that as the collector doping concentration increases,the Early voltage decreases. This reduction in Early voltage with theincrease in collector doping density is expected from the consideration ofequation (3.25) in chapter 3, as a higher collector concentration gives ahigher base–collector capacitance and hence lower Early voltage. The Earlyvoltage for the lowest collector doping of 5 × 1016 cm−3 is 110 V, leadingto a βVA product of 22 000. A Ge fraction of 12% at the base–collectorjunction has helped to provide a high Early voltage.

The dependence of cut-off frequency on the collector current is shownin figure 5.5 for two different base–collector voltages, while figure 5.6 shows

Figure 5.5. Effect of base–collector reverse bias voltage on the cut-off frequencyof a graded base SiGe HBT.


Figure 5.6. Cut-off frequency versus Ic of a graded base SiGe HBT.

a comparison of simulated and measured fT with collector current. It isevident that while the overall match is good, indicating good agreementof emitter–base and base–collector capacitance, the simulated values areslightly below the measured values. It is believed that this may be due to asmall inaccuracy in the drift–diffusion model in predicting base transit timein thin base transistors. This point is more fully discussed in section 5.3.A direct comparison of major experimental and simulated figures-of-meritis shown in table 5.1. While excellent agreement has been obtained forfT, the simulation overestimates fmax, possibly due to an underestimate ofbase resistance.

Table 5.1. Comparison of simulated device parameters.

Parameter Experimental [1] Simulation

Emitter size, Ae 0.27× 2.5 µmCurrent gain, β 220 210Breakdown voltage, BVceo 3.0 3.0Early voltage, VA 130 V 120 VCut-off frequency, fT 61 GHz 57 GHzMaximum frequency oscillation, fmax 74 GHz 105 GHz

Double polysilicon self-aligned SiGe HBT (1998) 159

5.2. DOUBLE POLYSILICON SELF-ALIGNED SIGE HBT (1998)

In this section we consider an alternative SiGe HBT, discussed by Kondoet al [2]. The device structure is illustrated in detail in figure 5.7. It hasthe same structure as a conventional double polysilicon bipolar transistor.A borophosphosilicate (BPSG) refilled trench is used for isolation. Sincethe dielectric constant of BPSG is about one third that of silicon, substratecapacitance is therefore minimized. A wedge-shaped CVD silicon dioxideisolation structure below the p+-polySi base electrode helps reduce base–collector capacitance. Both SiGe base and polySi SiGe contact are self-aligned on the n-collector and p+-polySi SiGe sidewall inside the window.Hence, the width of the base–collector junction has been reduced to thatof the 0.5 µm emitter window.

The intrinsic base consists of a 200 A undoped SiGe layer, a 300 Ap−-type graded SiGe layer and a 150 A undoped silicon layer. A SIMSplot is shown in figure 5.8. For ATLAS simulation, the peak emitterdoping of 1020 cm−3 (n+-type), the peak base doping of 5 × 1018 cm−3

(p-type) and the collector doping of 5×1016 cm−3 (n-type) were considered.The characteristic length of the Gaussian base profile is 0.0145 µm. Thegermanium fraction x is graded linearly, from a peak value of 0.145, downto zero at the emitter–base junction. Full details of the simulation are givenin [17].

Figure 5.7. Schematic cross section of the ultra low-power SiGe base bipolartransistor with a wedge-shaped CVD-SiO2 isolation and a BPSG-refilled trench.(After Kondo M et al 1998 IEEE Trans. Electron Devices 45 1287–94.)


Figure 5.8. A SIMS impurity profile of the emitter and the base in the intrinsicregion. (After Kondo M et al 1998 IEEE Trans. Electron Devices 45 1287–94.)

Figure 5.9. Comparison of Gummel plot for a SiGe HBT. (After Hamel J S andTang Y T 2000 Proc. ESSDERC pp 620–3.)

The Gummel plot simulated by ATLAS is shown in figure 5.9, alongwith the published result for comparison. Since great care has beentaken to model both the doping profile and two-dimensional structure,excellent agreement has been achieved for the collector current. The higher

Double polysilicon self-aligned SiGe HBT (1998) 161

Figure 5.10. Comparison of simulated and experimental fmax and fT as afunction of collector current. (After Hamel J S and Tang Y T 2000 Proc.ESSDERC pp 620–3.)

base current simulated by ATLAS could be due to lower hole lifetime inthe emitter, but insufficient detail regarding the polysilicon interface isavailable in the original paper [2] to enable more precise modelling.

The respective simulated and published values of fT and fmax havebeen compared in figure 5.10. The agreement is excellent with thesimulation showing a peak fmax of 70 GHz and a peak fT of 40 GHz ataround 200 µA. It would appear therefore that inaccuracy in the simulatedbase current does not affect the accuracy of the high-frequency modelling.Subsequently, this transistor has been used as the basis of a simulationstudy which offers a comparison between vertical and lateral HBTs [18].The simulation predicts a potential twofold improvement in fmax, andat significantly lower bias current compared to the vertical SiGe HBT,for a given minimum lithography. The relevant comparison is shown infigure 5.11. The improved fmax is attributed to an order of magnitudeimprovement in the rbbCbc time constant in the lateral HBT. Althoughspecific device structures were utilized, the same active region profilesand identical minimum lithography ensured a meaningful comparison.The factor of two improvement predicted for lateral SiGe HBT on SOItechnology gives a general indication as to how bipolar technology is likelyto evolve over the next decade. As minimum lithography decreases, theSOI layer thickness in the lateral HBT can be made thinner to continue toprovide improvement in performance.


Figure 5.11. Comparison of frequency performance versus dc collector currentbetween vertical and lateral SiGe HBTs. (After Hamel J S and Tang Y T 2000Proc. ESSDERC pp 620–3.)

5.3. ENERGY BALANCE SIMULATION

As discussed in chapter 4, the drift–diffusion approximation can lead toinaccuracy in the prediction of device characteristics, particularly when thewidth of the base is reduced below 30 nm. In this instance, it is necessaryto perform a simulation involving energy balance [19], where the equationsfor current flow must be modified as given in equations (4.18)–(4.21).

The conventional drift–diffusion model of charge transport neglectsnon-local transport effects such as velocity overshoot, diffusion associatedwith carrier temperature gradients and dependence of ionization rateson carrier energy distribution. The drift–diffusion approximation is alow-order approximation of the Boltzmann transport equation (BTE).Device simulation based on the solution of the full BTE is possiblebut requires significant computing resources. A simpler intermediatelevel approximation, which offers potential for improved accuracy, istherefore attractive. Essentially, the energy balance model predictsvelocity overshoot relative to the carrier saturation velocity defined inequation (4.28). Velocity peaks occur in regions of the device where carriertemperature is a maximum e.g., base–collector junction. High velocity givesrise to reduced transit time compared to the drift–diffusion model.

The device considered for simulation [20] is a state-of-the-art SiGeHBT, designed to give a very high fT by incorporating a high dose selectivecollector implant of peak concentration of the order of 1018 cm−3. The

Energy balance simulation 163

Figure 5.12. Germanium and doping profile for a SiGe HBT with 15% Gecontent. (After Oda K et al 1997 IEEE IEDM Tech. Dig. pp 791–4.)

SIMS profile of the transistor, with a 15% graded Ge profile is shownin figure 5.12. This profile has been accurately reproduced in the inputdatafile for ATLAS simulation. This transistor is very similar to thatdescribed in the previous section. It only differs in two respects: a muchhigher doping density in the collector and the location of the peak collectordoping lying closer to the base–collector. It was reported that the measuredpeak fT ranges from 110 GHz for a peak Ge content (x = 0.1) to 130 GHz(x = 0.25), as shown in figure 5.13.

The simulated maximum cut-off frequency has been plotted as afunction of peak collector doping in figure 5.14. It is clear that the drift–diffusion model predicts a maximum fT of less than 100 GHz, irrespectiveof the value of peak collector doping. It seems that in order to predictan fT of more than 100 GHz to match the measured value, the energybalance model appears to be required. This conclusion is in line with theobservations in figure 5.6, where once again the simulated fT is less thanthe measured value.

The differences between the energy balance and drift–diffusion modelson emitter and base transit times are shown in figure 5.15. It is clearthat the EB model predicts significantly lower values of base transit times,sufficient to account for the higher measured values of fT.

A comparison of extracted carrier velocity for the DD and EB models,


Figure 5.13. Maximum cut-off frequency as a function of Ge content. (AfterOda K et al 1997 IEEE IEDM Tech. Dig. pp 791–4.)

Figure 5.14. Cut-off frequency versus peak collector doping in a graded baseSiGe HBT.

Energy balance simulation 165

Figure 5.15. Simulated emitter and base transit time of a SiGe HBT, as afunction of collector current for both drift–diffusion and energy balance modelsfor Ge mole fraction x = 0.1.

Figure 5.16. Extracted carrier velocity using drift–diffusion and energy balancemodels.


Figure 5.17. Simulated electron temperature in a SiGe HBT.

as a function of base bias, for two Ge fractions (x = 0.1 and 0.2), is shown infigure 5.16. The EB model shows a significant overshoot in the saturationvelocity, sufficient to account for the lower base transit time in figure 5.15,while the maximum velocity possible with the DD model is limited bythe saturation velocity, vsat = 8 × 106 cm s−1. A plot of the simulatedelectron temperature in figure 5.17, taken as a one-dimensional sectionthrough the active device, shows the expected carrier heating associatedwith the high-field region at the base–collector junction. The maximumof the temperature profile is, however, shifted into the collector region,as the carriers are accelerated through the high-field region to reach themaximum temperature. Velocity overshoot occurs in the base region, wherethe electric field is high and the temperature is only beginning to rise.

5.4. SIGE HBTS ON SOI SUBSTRATES

In Si bipolar technology, the two well-known disadvantages are: highpower dissipation and low density. High power dissipation is a resultof the high parasitic junction capacitance associated with using siliconas the substrate. Previously, silicon-on-insulator has been used forhigh-performance deep submicron CMOS, as discussed more fully insection 10.3. The advantages of utilizing a composite substrate comprisinga monocrystalline semiconductor layer, such as silicon, epitaxially deposited

SiGe HBTs on SOI substrates 167

on a supporting insulating substrate, are well recognized. Major advantagesinclude the substantial reduction of parasitic capacitance between chargedactive regions and the substrate, and the effective elimination of leakagecurrents flowing between adjacent active devices. Modern communicationdevices also present greater difficulties in high level integration becausethey require digital computing capability (logic and memory) along withanalogue and RF circuitry. The need to reduce power consumption inbattery powered wireless communication systems is a need which has notpreviously been met. While bipolar transistors fabricated on SOI substrateshave been shown to offer lower parasitic capacitance [21], they do have agreater susceptibility to self-heating [4, 5].

Investigations on the impact of self-heating on transistor performanceand effect of introduction of thermal vias to reduce temperature rise havebeen performed by Armstrong and Gamble [22]. Lattice heating in theSiGe HBT has been simulated by coupling the solution of the heat flowequation along with the semiconductor equations:

C∂TL∂t

= ∇ (κ∇TL) +H (5.1)

where TL represents the lattice temperature, C the heat capacitance perunit volume and κ the thermal conductivity. The Joule heating termH, which provides the coupling between the heat flow equation and thesemiconductor equations, is given by

H =J2nqµnn

+J2pqµpp

(5.2)

where Jn,p and µn,p represent current density and carrier mobility ofelectrons and holes, respectively. The temperature dependence of κ inthe semiconductor is modelled by [23]

κ =1

a+ bTL + cT 2L(5.3)

where for silicon and polysilicon, a = 0.03, b = 1.56×10−3, c = 1.65×10−6,while for silicon dioxide κ = 0.014.

The SiGe HBT transistor considered for simulation (see figure 5.18) isbased on SiGe technology developed at Southampton University [24]. Thenovel feature of this technology is selective growth of a silicon collector inan anisotropically etched oxide window, followed by non-selective growthof a SiGe base and low-doped SiGe emitter in the same growth sequence.A key aspect of the technology is the very low junction capacitance at bothemitter–base and base–collector junctions. In addition, the fabrication ofthe transistor in a bonded substrate offers the possibility of including aburied silicide layer to reduce collector resistance. Simulations indicate


Figure 5.18. Structure of a SiGe HBT on SOI used for simulation.

Figure 5.19. SiGe HBT doping profile used for simulation.


Figure 5.20. A schematic diagram of a SiGe HBT showing different regions.(After Armstrong G A and Gamble H S 1999 Silicon-on-Insulator Technology andDevices IX, Electrochemical Society Proceedings Series vol 99-3, ed P L Hemment(Pennington, NJ: Electrochemical Society) pp 249–54.)

that the predicted performance of an optimized Si0.9Ge0.1 heterojunctiontransistor produced in SOI material utilizing minimum lithography is fmaxin excess of 100 GHz and ECL gate delay of less than 10 ps. To achievethis level of performance, a minimal feature size with an emitter polysiliconwidth of 0.25 µm and 0.125 µm mask alignment is required. A typical basedoping considered for simulation is shown in figure 5.19.

Figure 5.20 illustrates a simplified structure, representative of the oxideisolated technology, with extended base and collector regions. The buriedcollector is shown to be thinner than would normally be used, to emphasizeany potential heating effect due to collector resistance. Electrical boundaryconditions are applied at the emitter, base and collector contacts in thenormal way. The substrate (not shown below the oxide) is assumed to beheld at a fixed ambient temperature. Figure 5.20 also shows the inclusionof a thermal via through the buried oxide. This via, which is created priorto bonding, acts as a heat conduction path. A thermal boundary condition


Figure 5.21. Simulated Gummel plot with and without inclusion of the heatequation. (After Armstrong G A and Gamble H S 1999 Silicon-on-InsulatorTechnology and Devices IX, Electrochemical Society Proceedings Series vol 99-3,ed P L Hemment (Pennington, NJ: Electrochemical Society) pp 249–54.)

is defined at all three electrical contacts such that

−κ∂TL∂n

=1Rth

(TL − Text) (5.4)

where Rth represents thermal resistance in K mW−1.Figure 5.21 shows the Gummel plots, with and without the inclusion

of the heat equation for the lattice heating modelling. Due to poor thermalconductivity in the buried oxide, the junction temperature rises, leading toa deviation from linearity. In the lower curve, heating has caused a 25 Krise in temperature above the ambient. The consequent increase in collectorcurrent is consistent with that value of collector current, which would occurfor the same increase in ambient temperature. A comparison between themaximum temperature rise in a transistor on an SOI substrate, with twodifferent thicknesses of buried oxide, and the maximum temperature riseon a silicon substrate is shown in figure 5.22.

For different thermal boundary conditions (Rth ranging from2–20 K mW−1), the sensitivity of the maximum temperature rise tothermal resistance, for a buried oxide of 0.4 µm, and a collector voltageof 3 V, is shown in figure 5.23. The impact of the thermal via in providinga heat conduction path through the buried oxide is shown in figure 5.24.


Figure 5.22. Comparison of heating effect between SOI and silicon substrates.(After Armstrong G A and Gamble H S 1999 Silicon-on-Insulator Technology andDevices IX, Electrochemical Society Proceedings Series vol 99-3, ed P L Hemment(Pennington, NJ: Electrochemical Society) pp 249–54.)

Figure 5.23. Dependence of maximum temperature rise on thermalresistance in a SiGe HBT fabricated in a bonded SOI substrate. (AfterArmstrong G A and Gamble H S 1999 Silicon-on-Insulator Technology andDevices IX, Electrochemical Society Proceedings Series vol 99-3, ed P L Hemment(Pennington, NJ: Electrochemical Society) pp 249–54.)


Figure 5.24. Contour plots of temperature in a SiGe HBT. (AfterArmstrong G A and Gamble H S 1999 Silicon-on-Insulator Technology andDevices IX, Electrochemical Society Proceedings Series vol 99-3, ed P L Hemment(Pennington, NJ: Electrochemical Society) pp 249–54.)

The peak temperature occurs, as expected, within the active area of thetransistor. However, it is clear that the thermal via is effective in providinga heat conduction path to the silicon substrate.

Although an attempt has been made to predict the thermal behaviourof HBT transistors fabricated on SOI substrates, absolute accuracy isdifficult to achieve because of the error in estimating the degree ofexternal heat loss, which has been approximated using a thermal resistanceboundary condition at the electrical contacts. The variation in temperaturewithin the transistor and the dependence of the maximum temperaturerise on thermal resistance have been demonstrated. The reduction intemperature, which occurs if a thermal via is included, depends on itsalignment relative to the active area.

5.5. LOW-TEMPERATURE SIMULATION

The outstanding performance advantages of a SiGe HBT for low-temperature operation have been demonstrated experimentally in a state-of-the-art silicon bipolar process [7–10]. However, the design andoptimization issues associated with the low-temperature operation of SiGe

Low-temperature simulation 173

HBTs remain unclear. Because of its bandgap-engineered base, a SiGeHBT is particularly suitable for operation at cryogenic temperature,where the exponential gain enhancement factor becomes very large. Inaddition, the built-in drift field in the base is more effective at lowtemperature, compensating for the degradation in base diffusivity, resultingin improvement in the cut-off frequency. It has been demonstrated [7] thatpresent SiGe technology is capable of providing transistors with highercurrent gain at 77 K than at room temperature, and unloaded ECL circuitswhich are as fast at 77 K as they are at room temperature. The key designissues for the low operation of SiGe HBTs may be identified as follows [25]:

• minimization of carrier freeze-out in the base;• control of increased parasitic emitter–base tunnelling current at low

temperature;• design of collector profile to leverage the increase in Kirk knee current

density with cooling; and• effect of Ge grading on current gain and cut-off frequency.

Low-temperature semiconductor device simulation is a difficult taskbecause parameters, often assumed constant in conventional simulators,may actually be complex functions of temperature. Phenomena uniqueto low-temperature operation, such as carrier freeze-out, are typically notaccounted for in simulators designed for room temperature use. In addition,the system of equations to be solved for low temperature is much more ill-conditioned numerically than at room temperature, due to terms havingstronger exponential temperature dependency. For these reasons, availablesimulation programs can have difficulty in converging to a solution at77 K [26,27].

5.5.1. Low-temperature SiGe HBTs

Patton et al [28] studied the low-temperature operation of a SiGe HBTfabricated in a poly-emitter bipolar process. The devices showed improvedlow-temperature behaviour with extremely high current gains of 1600 at77 K for devices having 7.5 kΩ/square base resistivity. Crabbe et al [6]investigated the low-temperature behaviour of Si BJTs and SiGe HBTsfabricated and optimized for room temperature operation. The authorsdemonstrated that introducing a spacer layer in the emitter–base junctionreduced the low level parasitic emitter–base tunnelling (leakage current) atlow temperature, but gave rise to carrier freeze-out and increase of baseresistance at 77 K. The respective current gains were 20–40 for an Si BJT,and 100–140 for a SiGe HBT for the temperature range from 77–300 K. Thegraded Ge profile in the base improved both the low-temperature currentgain and base transit time, resulting in a peak cut-off frequency of 94 GHzat 85 K, compared to 75 GHz at 298 K.


A much improved low-temperature SiGe HBT [29], specificallydesigned for low-temperature operation, was fabricated using self-alignedepi-base technology [30]. Lightly-doped spacers were used at both thejunctions to reduce the electric field. The base width was approximately59 nm and the peak concentration of the graded Ge profile was 9%. For ahigh-power design (about 10 mW), the ECL gate delay at 84 K was 28.1 ps,roughly the same as at 310 K, yet a factor of two better than the best valueobtained at that time with a low-temperature Si BJT. Low power ECLcircuits showed a power delay product of 112 fJ at 84 K. The measured gatedelays were in reasonable agreement with the theoretical predictions [31].At that time, these results represented a significant advance in performanceof silicon-based bipolar technology at 77 K.

During the 1990s, the research group at IBM [7, 9, 10] reportedprogressive further improvements in the low-temperature performance ofSiGe HBTs. A low thermal budget allowed a sharp transition from a low-doped emitter to a heavily-doped base, making the base immune to carrierfreeze-out at 77 K. At 84 K, transistors showed a current gain of 500, fTof 61 GHz and ECL gate delay of 21.9 ps, 3.5 ps faster than at roomtemperature. Typical parameters and performance of the transistors at310 and 84 K for the epitaxial emitter-cap (no spacer) design and an i–p–i(with spacers) design, are given in table 5.2.

The effect of introducing lightly-doped spacer layers at both theemitter–base and base–collector junctions was studied in detail [9]. The

Table 5.2. Typical SiGe HBT parameters at 310 and 84 K at the wafer level.(After Cressler et al 1994 IEEE Electron Device Lett. 15 472–4.)

Temperature 310 K 84 K 310 K 84 K

SiGe profile Emitter-cap design i–p–i design

βmax 102 498 105 82β at 1.0 mA 94 99 96 34Peak gm (mS) 62 113 74 83Rbi(kΩ/square) 7.7 11.0 8.2 15.9Re (Ω) 14.3 11.0 82 15.9Ieb (nA) 8.44× 104 1.91× 103 2.89 1.11BVceo (V) 3.1 2.1 3.2 3.2BVcbo (V) 10.8 9.6 10.8 9.5Cbe (fF µm−2) 5.47 5.13 6.30 5.90Cbc (fF µm−2) 0.46 0.40 1.04 0.93Peak fT (GHz) 43 61 53 59Peak fmax (GHz) 40 50 37 48ECL delay (ps) 25.4 21.9 26.0 30.4


spacer layer reduced the low level parasitic base leakage but gave rise tocarrier freeze-out and an increase of base resistance at 77 K. However, it wasshown that a thin abrupt base profile attainable with epitaxial processing isparticularly useful for low-temperature operation since the resultant profileis less sensitive to base freeze-out than ion-implanted profiles. The authorsalso fabricated homojunction Si BJTs and showed that properly designedhomojunction transistors also have sufficient current gain and switchingspeed at 77 K for many digital applications. In several applications,however, the flexibility offered by using SiGe for base layer yields greatbenefits.

Gruhle et al [12] have reported a high-performance SiGe HBT,fabricated using MBE, having a base doping of 2 × 1019 cm−3, largelyexceeding the emitter impurity level and a base sheet resistance of about1 kΩ/square. The device exhibited an Early voltage of 500 V, a maximumroom temperature current gain of 550 rising to 13 000 at 77 K. Devicesbuilt on buried-layer substrates exhibited an fmax of 40 GHz and an fT of42 GHz.

Sturm et al [32] also fabricated high-quality SiGe HBTs using rapidthermal chemical vapour deposition. Both graded-base and uniform Geprofiles in the base were considered. In a transistor with 20% uniform Geconcentration in the base, currents gain of about 2000 at room temperatureand 11 000 at 133 K were observed. The performance of SiGe HBTs atliquid helium temperature has been reported by Joseph et al [8]. Thecurrent gain of a self-aligned, UHVCVD-grown SiGe HBT showed anincrease in current gain from 110 at 300 K to 1045 at 5.85 K, althoughparasitic base current leakage limits the useful operating current to aboveabout 1.0 µA at 5.84 K. A very high base doping (peak at 8× 1018 cm−3)was used to suppress the base freeze-out at 4.48 K and resulted in a basesheet resistance of 18.3 kΩ/square.

5.5.2. Low-temperature simulation using ATLAS

In order to understand the impact of the Ge profile and base doping in thedesign of a low-temperature SiGe HBT, simulations were performed usingATLAS 2D device simulator on two separate base doping profiles, and twodifferent Ge profile shapes:

(i) a box Ge profile (uniform Ge content, x = 0.20, not shown)(ii) a graded Ge profile (see figure 5.25).

Figure 5.26 shows Gummel plots at 300 and 100 K, respectively, forconstant Ge concentration. The simulated collector current characteristicis ideal over more than ten decades of current. As the temperature islowered, the intrinsic carrier concentration decreases exponentially, and foran observable current to flow at low temperature, the emitter–base voltage


Figure 5.25. Doping profile and Ge profile (graded case) in a SiGe HBT.

must be increased substantially, as may be seen from figure 5.26. As thedc current gain depends exponentially on the bandgap narrowing presentat the emitter edge of the neutral base [33], the box Ge profile (x = 0.2)produces a larger enhancement in β, in figure 5.27, than the graded profilein figure 5.25. In the former diagram, a peak dc current gain as high as11 000 is predicted at 100 K, compared to the more moderate enhancementfor the graded Ge. In the latter case, the predicted current gain at 150 Kof 900 is more than adequate for successful circuit operation at such alow temperature. A contributory factor to the high current gain at lowtemperature is the low level of bandgap narrowing in the relatively lightly-doped 5 × 1018 cm−3 single-crystal emitter.

Richey et al [34] have shown close agreement with measurements forlow-temperature SiGe HBT simulations, using a calibrated doping profilebased on SIMS data. The authors have used the 1D simulator SCORPIOto examine the effects of Ge profile shape and base profile scaling ontemperature. Some of these results are presented below. It has been


Figure 5.26. Gummel plots of a SiGe HBT (flat base) at 300 and 100 K.

shown in chapter 4 that a triangular Ge profile in the base produces moreenhancement in cut-off frequency and βVA product than a box Ge profile.The bandgap grading associated with the triangular Ge profile induces adrift field that helps accelerate electrons across the base, decreasing thebase transit time. Figures 5.28–5.30 show dependence of cut-off frequencyfT, relative improvement in fmax and βVA product on temperature, forbox and graded Ge profiles, at different dc bias points. Three separatesets of base doping profile are used and, for each set, two Ge profiles—abox profile and a linearly graded profile—are considered. Each Ge profilehas the same stability point as defined by Matthews and Blakeslee [35,36],i.e. the integrated Ge concentration is held constant. Three stability pointsare referenced. Stability point 1 refers to a state-of-the-art device, with aneffective Ge thickness of 120 nm and a base width of 90 nm. For the secondstability point, the base profile has been scaled by one half while base


Figure 5.27. The dc current gain of a flat base SiGe HBT at differenttemperatures. For comparison, dc current gain at 150 K for a graded basetransistor is shown.

Figure 5.28. Cut-off frequency comparisons over temperature. (AfterRichey D M et al 1997 IEEE Trans. Electron Devices 44 431–40.)


Figure 5.29. Enhancements in maximum oscillation frequency. (AfterRichey D M et al 1997 IEEE Trans. Electron Devices 44 431–40.)

Figure 5.30. Current gain–Early voltage product enhancements. (AfterRichey D M et al 1997 IEEE Trans. Electron Devices 44 431–40.)


doping is increased to maintain the same pinched base resistance. Stabilitypoint 3 is identical to the previous case, except that the Ge content isdoubled. For all three scaled profiles, both the collector profile and emitterdepth are unaltered.

For all parameters, the enhancement factor increases significantly asthe temperature is reduced. The relative improvement for the graded Geprofile at low temperature is due to the greater effectiveness of the drift fieldin compensating for degradation in diffusivity. The simulation suggests thatfor low-temperature operation, a box Ge profile may be used for maximizingdc current gain and fT, but this is a more sensitive function of temperaturethan the triangular profile. In conclusion, the box Ge profile producesthe greatest enhancement in β, fT and fmax over temperature, while thetriangular Ge profile produces the greatest enhancement in βVA product.

5.6. I2L CIRCUITS USING SIGE HBTS

High-performance bipolar logic circuits are usually realized using emittercoupled logic (ECL) which has a relatively low packing density and highpower dissipation. The gate delay of I2L circuits is primarily determinedby stored charge in parasitic diodes associated with the extrinsic baseregions of the I2L gate [15]. SiGe technology offers the prospect of usingbandgap engineering to minimize the stored charge in the parasitic diodesassociated with the I2L gate. Hence, the use of a heterojunction can addhigh speed to the other well-known advantages of I2L technology, namelyhigh packing density, low voltage and low power dissipation. Experimentalresults on SiGe integrated injection logic circuits (surface-fed and substrate-fed variants) have been reported [16].

Figure 5.31(a) shows the cross section of an I2L gate and figure 5.31(b)a circuit diagram. The cross section shows the merged structure of the I2Lgate, with the SiGe layer used both as the base of the npn transistor andthe collector of the pnp transistor. The npn switching transistor operates

Figure 5.31. Schematic cross-section (a) and circuit diagram (b) of an I2L.(After Wainwright S P et al 1996 Proc. ESSDERC pp 649–52.)

I2L circuits using SiGe HBTs 181

in the inverse mode, which allows multiple collectors to be produced usingn+-polySi contacts to the top n-type silicon layer. A polysilicon contact isalso used to connect to the base of the pnp injector transistor. The emitter(injector) of the pnp transistor is formed in the top 300 nm n-type siliconlayer using a BF2 implant through a 50 nm screen oxide. This SiGe I2Ltechnology therefore uses a vertical pnp transistor in contrast to the lateralpnp transistor used in conventional silicon I2L technologies.

A Gummel plot of a 3 µm npn switching transistor, operated in upwardmode in an I2L gate with three collectors, gave a maximum current gainof 14. The collector current characteristic was ideal over several decadesof current, while the ideality factor of the base current was 1.28. Themeasured output characteristic is shown in figure 5.32 and indicates abreakdown voltage BVceo of about 2.9 V. A low gain of 1.4 for the pnptransistor was not deemed to be important for the operation of the I2Lgate, provided that the ratio of saturation currents for the pnp and thenpn transistors was much greater than unity. Figure 5.33 compares themeasured and modelled [37] switching time as a function of injector currentper gate. The measured and modelled values agree quite closely, with themeasured values being about 40% faster.

For optimization of SiGe integrated injection logic (I2L) circuits, aquasi two-dimensional stored charge model has been developed [16]. It has

Figure 5.32. Output characteristics (upward mode) of the npn SiGe HBT.(After Wainwright S P et al 1996 Proc. ESSDERC pp 649–52.)


Figure 5.33. Comparison of measured and modelled I2L gate delay. (AfterWainwright S P et al 1996 Proc. ESSDERC pp 649–52.)

been shown that at low injector currents, the use of SiGe offers only amarginal benefit, since the switching speed is dominated by depletion regioncharge. However, at high injection currents, where the switching speedis dominated by stored minority carrier charge, the use of SiGe in I2Ltechnology has been shown to have important benefits. The inclusion of16% Ge in the substrate-fed I2L gate leads to a decrease in the dominantstored charge by a factor of more than ten, which suggests that gatedelays well below 100 ps should be achievable, even at a geometry of3 µm. The model has also been applied to predictions of the performanceof a self-aligned structure, specifically optimized for SiGe I2L. For a Geconcentration of 16% in the base, a maximum delay of 34 ps was predictedusing 1.4 µm design rules.

5.7. NOISE PERFORMANCE

Different types of noise mechanisms are found to be present insemiconductors [38]. Among them the low-frequency noise, typicallyobserved to exhibit a dependence on frequency, is very important foranalogue and mixed-signal applications. Low-frequency noise is knownto degrade the spectral purity of nonlinear radio frequency (RF) and

Noise performance 183

microwave circuits, such as oscillators and mixers, where the low-frequency,baseband noise generates noise sidebands around the RF or microwavecarrier signal [39].

Low-frequency noise in UHVCVD-grown Si and SiGe bipolartransistors has been studied by Vempati et al [40]. The authors havemade a comprehensive study by comparing different technologies andhave demonstrated that the SiGe devices have excellent noise propertiescompared to AlGaAs/GaAs HBTs and conventional Si bipolar junctiontransistors. Low-frequency noise has been characterized as a function ofbias, geometry and temperature [41,42].

The transistors used were fully integrated, self-aligned devices, withshallow and deep trench isolation, silicided extrinsic base and contacts,two levels of metallization and a conventional poly-emitter contact. Twodifferent bias configurations were used to distinguish the various noisesources contributing to noise in the Si and SiGe bipolar transistors. Thedevices were biased in low injection (Ib ∼ 2.25 µA) in order to eliminateany second-order parasitic resistance effects and spurious noise due toweak impact ionization. The collector current was also limited to severalmilliamps, so that the shot noise due to the collector current was negligiblecompared to the base current shot noise. Common-emitter configurationwith high input impedance was used for measuring the base noise. Inorder to determine the collector noise and the contributions, if any, of theparasitic series resistances, the devices were biased in the common-collectorconfiguration.

Typical curves of the equivalent input-referred base current noisespectra for Si and SiGe devices are shown in figure 5.34. At low frequencies,the noise rises over the shot noise and thermal noise background andexhibits an expected spectrum for frequencies below 1 kHz. Within thescatter of data (approximately 50 devices for both Si and SiGe combinedwere measured) the slope of the spectrum varies as 1/f . The roll-off of thespectra above 10 kHz is due to the Miller capacitance associated with thedevice and packaging.

As temperature excursions are important in analogue applications,noise measurements were made over the range of −55 C to 85 C.Figure 5.35 shows the temperature dependence of the noise spectra of Siand SiGe transistors at a fixed base current of 2.25 µA. It is observedthat the noise spectral density exhibits a clear 1/f behaviour withoutany anomalous behaviour in the slope across this temperature range.The noise spectra for Si and SiGe devices are similar, and have nosignificant temperature dependence. The authors concluded that thecombination of an inverse of area dependence on geometry and near-quadratic dependence on base current suggests that the noise sources arehomogeneously distributed over the entire emitter area and not restrictedonly to the emitter periphery. Comparisons with different technologies


Figure 5.34. Equivalent input-referred base noise current spectral density at abase current of 2.25 µA for multi-stripe Si and SiGe transistors with an emitterarea 3× 0.5 µm and comparable doping profiles. The inferred 1/f to shot noisecorner frequencies are 480 Hz and 373 Hz for Si and SiGe transistors, respectively.(After Vempati L S et al 1996 IEEE J. Solid-State Circuits 31 1458–67.)

Figure 5.35. Noise spectral density at two different temperature points (358and 218 K) of Si and SiGe devices of an emitter area of 3 × 0.5 µm. (AfterVempati L S et al 1996 IEEE J. Solid-State Circuits 31 1458–67.)

Noise performance 185

demonstrate that the Ge incorporated in the base does not degrade thenoise performance and that SiGe HBTs have better noise performance thanAlGaAs/GaAs HBTs and conventional ion-implanted Si BJTs.

Even though SiGe HBTs have demonstrated better noise performanceover Si BJTs at low frequency, even better high-frequency noisecharacteristics may be expected if the Ge profile is optimized specificallyto address this issue. The SiGe HBT design issues associated withminimization of broadband noise have been considered by Ansley et al [43].Using the 1D simulator SCORPIO, the effect of the Ge profile in the base onthe minimum noise figure at high frequency was theoretically investigated.The analysis was based on an equivalent circuit noise model originallyformulated by Hawkins [44], as shown in figure 5.36. The model accountsfor thermal noise in the source (vs), base resistance (vb), shot noise in theemitter (ve) and collector partition noise (icp). The resulting expressionfor noise factor may be approximated with sufficient accuracy by

F 1 +RbRs

+Re2

[(1 − (2πf)CjeXs)2

Rs+((2πf)C2

je)Rs

]

+(1 + (2πf)2τ2b

α0− 1)(

Rs2Re

+X2s

2ReRs

)(5.5)

where Rs is the source resistance, Xs is the source reactance, Re is thedynamic emitter resistance (thermal voltage divided by emitter current)and Cje is the emitter–base depletion capacitance, α0 is the common basedc current gain and f is the frequency at which the noise factor is evaluated.This formulation helps in determining the relative contribution of each ofthe terms which control the noise factor. As a guide, the presence of Ge

Figure 5.36. Equivalent circuit schematic of Hawkin’s noise model for bipolartransistors. (After Hawkins R J 1977 Solid-State Electron. 20 191–6.)


reduces the noise factor by decreasing τb, decreasing base resistance Rband allowing the possibility of increased current gain. The minimum noisefigure, NFmin is given by 10 log(F) when Rs is set to the optimum sourceresistance Ropt which may be approximated as

Ropt ≈√

2RbRea

+(R2e

2−X2

opt

)(5.6)

and the optimum source reactance Xopt is given by

Xopt ≈ (2πf)2CjeR2e

a(5.7)

where

a ≈ 1β+

((2πf)τb)2

α0+

((2πf)τje)2

α0. (5.8)

When considering the Ge profile, the best noise performance is achievedwith the greatest amount of Ge in the neutral base region, subject tothe maximum acceptable β and the strained layer stability constraints.In what was essentially a theoretical study, a novel optimized Ge profileto achieve minimum noise figure was developed, as shown in figure 5.37,which compares the new profile with a traditional trapezoidal profile ofthe same average Ge content. Simulations using this profile at 10 GHzindicated an improvement of almost 1 dB in the minimum noise figure overan equivalent Si BJT control, and 0.4 dB over the equivalent SiGe HBTwith the traditional profile.

Base doping has a direct impact on β, intrinsic base resistance Rbiand fT, with all values decreasing as doping increases. The decrease inβ and fT (with increases in both base and emitter transit time) wouldgive the impression that NFmin will increase. However, the decrease in thebase resistance suggests there may be a decrease in NFmin. Figure 5.38shows the effect of increasing base doping on the major components ofnoise factor, as a function of collector current, for a 90 nm base HBTwith the calibrated Ge profile of figure 5.37. An additional extrinsic basesheet resistance of 500 ohms/square has been included in the calculation.It is apparent that an increase in base doping increases NFmin because βdecreases and τb increases. Even though an increase in doping reduces Rb,Ropt also decreases which partially offsets the impact of reduction in basethermal noise.

5.8. RADIATION EFFECTS ON SIGE HBTS

In the following, we describe briefly the effects of proton and gammaradiation on SiGe HBTs fabricated in IBM SiGe BiCMOS technology.

Radiation effects on SiGe HBTs 187

Figure 5.37. Ge profile which allows optimization for NFmin compared to theconventional graded Ge profile. Emitter and base carrier concentrations areshown for reference from polySi interface in emitter to base–collector junction(at right edge). (After Ansley W E et al 1998 IEEE Trans. Microw. TheoryTech. 46 653–60.)

Figure 5.38. Effect of base doping level on the noise factor sources for thescaled base profile using a base link sheet resistance of 500 ohms/square. (AfterAnsley W E et al 1998 IEEE Trans. Microw. Theory Tech. 46 653–60.)


Dose-rate effects and proton energy effects have been studied in detail forthis technology, mainly by Cressler and his group [45–47]. Characteristics ofproton and gamma irradiated SiGe HBTs and gated lateral pnp transistors(GLPNPs) have been reported [48].

MOS devices respond to ionizing radiation in several ways, dependingon whether the damage occurs in silicon or in the oxide. In the oxide,charge-generation in the gate/oxide interface or the oxide/silicon interfacecauses changes in the threshold voltage (VT), transconductance (gm), andthe leakage current. Two kinds of charges are observed: oxide trappedcharge and interface trapped charge, each having different effects on deviceparameters. The major effects of radiation-induced interface states onMOS devices are lowering of transconductance and distortion of I–Vcharacteristics. The generation of electron–hole pairs after a radiationburst is not a long-lived phenomenon because the electrons tunnel intothe bulk of the device and the trapped hole charge can lead to significantdevice degradation.

For most bipolar devices, the effects of radiation and subsequentperformance degradation due to surface states are not as catastrophic as forMOSFETs. Bipolar transistors are, in general, more radiation tolerant thanCMOS as they depend on junctions for operation, while MOSFETs dependon surface effects and the interfaces. Also, bipolar transistors are dopedup to three orders of magnitude higher than MOSFETs. When irradiated,degradation of current gain and an increase in leakage current are found tooccur in the case of bipolar devices. Gain degradation occurs mainly dueto the atomic displacement in the bulk of the device. The displacementresults in an increase in the number of recombination centres, which reducesthe minority-carrier lifetime, and therefore an increase in the base currenttakes place. The other cause of gain degradation is due to the ionizationof the oxide passivation layer, mainly in the emitter–base junction regionwhere charge trapping and the generation of new interface traps occur.The trapped surface charge and the interface states cause an increase inminority-carrier surface recombination velocity, which reduces the gain.

Another important effect in bipolar transistors is the increase in thejunction leakage currents resulting from ionization in the surface oxide,mainly the region over the base–collector junction. This increase in base–collector leakage current (typically ∼1 nA) is usually due to charge build-upin the oxide layer over the junction producing a surface channel whichconducts strongly. Figure 5.39 shows a schematic device cross sectionof a SiGe HBT and sources of degradation. The SiGe HBT has beensuccessfully integrated with conventional Si CMOS technology to realizea SiGe BiCMOS technology. This technology is more fully discussed inchapter 10.


Figure 5.39. Schematic cross section of a self-aligned UHVCVD SiGe HBT.Sources of degradation are shown in the structure. (After Banerjee G 1999Master’s Thesis Auburn University.)

5.8.1. Low dose-rate effects

Low dose-rate (LDR) effects have been investigated in the state-of-the-artSiGe HBTs (see figure 5.39) which were fabricated using a self-aligned,planar structure with deep and shallow trench isolation and a conventionalpoly-emitter contact. These SiGe HBTs have 70 GHz fmax frequencyresponse and have been fully integrated into a 0.35 µm SiGe BiCMOStechnology for system-on-a-chip applications [49].

The LDR effects on these vertical SiGe HBTs were contrasted withhigh dose-rate (HDR) data, as well as data from gated lateral pnptransistors from this SiGe BiCMOS process, in order to shed light on thedamage mechanisms. In contrast to reports of strongly enhanced LDRdegradation in conventional Si bipolar transistors, LDR effects in the SiGeHBTs were found to be nearly non-existent [50]. Figure 5.40 shows thedependence of dc current gain on the energy of protons. A peak β of about105 is observed which degrades to 100 for 44 MeV and 95 for 196 MeV.Clearly, the β degradation is much larger for the higher energy. It hasbeen observed that an increase in the base current occurs when collectorcurrent is more or less independent of radiation. However, the degradationin current gain is not as large in the high current region of the transistor,where it will be biased for most of the high-frequency and high-power RFapplications. The LDR effects have been found to be very technology-dependent.


Figure 5.40. Current gain degradation as a function of energy. (AfterBanerjee G 1999 Master’s Thesis Auburn University.)

5.8.2. Simulation of radiation hardness

The effects of proton radiation in a gate-assisted lateral pnp (GLPNP) inan advanced SiGe BiCMOS technology have been studied by Niu et al [48].The GLPNP is essentially a p-MOSFET whose source and drain serve asthe emitter and collector of the lateral bipolar transistor. These transistorsavoid the current gain limitation by combining both MOSFET and bipolaroperational modes, and thus are commonly used in BiCMOS circuits [51].Radiation-induced surface and bulk traps were electrically probed using acombination of dc measurements and 2D simulation. Figure 5.41 showsthe schematic top view and cross section of a GLPNP, along with the SiGeHBT in the BiCMOS process studied.

To understand the physics underlying radiation degradation, extensive2D simulations using MEDICI [52] were performed by the authors, byplacing positive charges in the oxide and introducing a thin surface layerof traps. The simulations show that the radiation-induced thresholdvoltage increases and the carrier lifetime at the surface decreases. Differentcombinations of trap density and spatial distributions of traps were used,and only those with higher surface trap densities can reproduce theexperimentally observed data. Figure 5.42 shows the evolution of thesimulated electron and hole densities versus depth with VGB change atVbe = 0.45 V.


Figure 5.41. Device cross section for the gated lateral pnp transistor and SiGeHBT. (After Niu G et al 1998 IEEE Trans. Nucl. Sci. 45 2361–5.)

Figure 5.42. Simulated electron (solid curve) and hole (dashed curve) densitiesversus depth with VGB (gate-to-base bias) change at Vbe = 0.45 V. (After Niu Get al 1998 IEEE Trans. Nucl. Sci. 45 2361–5.


5.9. SUMMARY

In this chapter, further examples of device simulation employing SiGe HBTtechnology have been considered. Attention has been given to simulationof various advanced technologies leading to high cut-off frequency and/orlow transit time. Good agreement between simulation and measurementprovides confidence in the use of device simulation for future development.Simulation of the low-temperature operation of a SiGe HBT has beenshown to be applicable for a wide range of applications in low-temperatureelectronics. Other more specialist applications of SiGe technology in I2Lcircuits and radiation hard environment have been considered.

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Chapter 6

STRAINED-SIHETEROSTRUCTURE FETS

In conventional Si technology, the complementary metal–oxide semi-conductor dominates the integrated circuit market. Its popularity comesfrom the simplicity in processing, as well as high input impedance.However, p-channel devices are inferior to n-channel ones in terms ofcurrent drive capability and speed performance. This is a consequence ofthe lower mobility of holes compared to electrons in Si. In order to matchthe current drive capability of n-channel (n-MOS), p-channel (p-MOS)devices are designed to be about 2–3 times larger than that of n-MOS.This adversely affects the level of integration and device speed.

In order to improve the speed of VLSI/ULSI circuits, new materialsand device structures are being proposed. The advances in the growth ofstrained silicon (strained-Si) layers on relaxed-SiGe buffer layers, combinedwith higher values of both the hole and electron mobilities in strained-Si,have led to increased interest in silicon-based heterojunction field-effecttransistors (HFETs) using conventional Si-processing technology.

Heteroepitaxy of semiconductor materials has been an active area ofresearch for the last two decades. Interest is driven by the possibilityof creating novel electronic and optical devices, as well as integratingexisting devices in different material systems, leading to the productionof integrated circuits with increased functionality and lower cost. Thefoundation of heteroepitaxy was laid by two important contributions. Thefirst, by Frank and van der Merwe in 1949 [1], showed theoretically that ifa lattice mismatched layer is grown on a thick substrate, the layer willbe pseudomorphic, provided that the mismatch is small and thicknessof the layer is not large. The second by Shockley [2] suggested the useof semiconductors of different bandgaps for fabrication of heterostructuredevices.

The lattice mismatch in the SiGe material system is 4.2%, resulting ina very high misfit and threading dislocation density. Most of the research

196

Strained-Si heterostructure FETs 197

Figure 6.1. Band alignments between Si and Si0.70Ge0.30 on two substrates:(a) Si and (b) Si0.70Ge0.30.

has concentrated on devices having strained layers with thicknesses belowthe critical thickness. Si1−xGex strained layer heterostructure devices werefabricated on an Si substrate only in the late 1980s. The key features ofthe growth and electronic properties of the strained-SiGe alloy system andtheir applications have been described in chapter 2 of this book, and alsoin more detail in several excellent reviews [3–7].

When a thin film with a larger lattice constant (e.g., Si1−xGex) isgrown on a substrate with a smaller lattice constant (e.g. silicon), the filmmaintains the in-plane lattice constant of the substrate and is under abiaxially compressive strain. Figure 6.1 shows the band offset between astrained-Si0.7Ge0.3 film grown on silicon. This is known as the type I bandalignment where virtually all the entire band offset occurs in the valenceband (figure 6.1(a)) with minimal band offset in the conduction band. Thistype of structure, favourable for hole confinement, has been exploited inseveral novel heterostructure devices, namely buried channel p-MOSFETs,p-MODFETs and HBTs (see, for example, excellent reviews by Paul [8]and Konig and Daembkes [9]).

Similarly, a smaller lattice constant silicon epilayer will be underbiaxial tension when grown on a larger lattice constant relaxed-Si1−xGexsubstrate. Figure 6.1(b) shows the band offset for a strained-Si epilayergrown on a relaxed Si0.70Ge0.30. In this case, type II band offset occursand the structure has several advantages over the more common type I bandalignment, as a large band offset is obtained in both the conduction andvalence bands, relative to the relaxed-Si1−xGex layer [10]. This allows bothelectron and hole confinements, making it useful for both n- and p-typedevices for strained-Si/SiGe based CMOS technology. Since strained-Siprovides both larger conduction and valence band offsets and does not sufferfrom alloy scattering (mobility degradation) [11], a significant improvementin carrier mobility can be achieved. Strained-Si is more difficult to grow ascompared to strained-Si1−xGex, since an Si1−xGex substrate is currentlynot available and, until recently, the growth of relaxed-Si1−xGex withoutforming a large concentration of defects due to dislocation was difficult.

198 Strained-Si heterostructure FETs

Studies of the incorporation of a small amount of C atoms into the Si/SiGematerial system to develop new types of buffer layers with reduced misfitdislocations may be useful [12].

However, the ability to achieve both n-MOS and p-MOS devicesusing strained-Si provides a promising alternative for next generation high-performance SiGe CMOS technology (see, for example, reviews [5, 13] andreferences therein). Strained-SiGe channel p-MOSFET designs are morefully covered in chapter 7. In this chapter, we discuss the present trendsand applications of strained-Si films in SiGe-based CMOS technology. In-depth discussion will cover the film growth, electronic properties of thestrained-Si layers on virtual substrates, design and simulation of strained-Si channel HFETs and MODFETs. Recent progress made in integrationissues and the future prospects of strained-Si/SiGe-based high-performanceHFETs, which may be integrated into Si VLSI/ULSI production, are alsodiscussed.

6.1. MOBILITY IN STRAINED-SI

Optimum semiconductor device design is ultimately based upon a fullunderstanding and accurate modelling of charge-carrier transport insemiconductors. Due to their relevance for both basic understanding andfor device applications, there has always been a strong interest in accuratemodel descriptions of the mobility as a function of strain, temperatureand dopant concentration. For the estimation of maximum theoreticalmobilities that can be achieved in strained-Si/SiGe heterostructures,several theoretical studies incorporating various scattering mechanismshave been reported [14–16]. The main scattering mechanisms to beconsidered in the strained-Si/SiGe material system are [17]:

(i) lattice scattering;(ii) ionized impurity scattering;(iii) neutral impurity scattering; and(iv) alloy scattering.

In addition, the strain distribution in the lattice mismatched SiGelayer affects the relative importance of intra- and inter-valley scattering,due to strain-induced changes in the conduction and valence bands.

6.1.1. Theoretical mobility

Stern and Laux [14] considered the dependence of electron mobilityon remote doping and background doping in the channel, as well asthe contribution of interface roughness and interface charges. Theirresults are in good agreement with the experimental data whenrealistic background acceptor densities between 1014 and 1015 cm−3 were

Mobility in strained-Si 199

considered [18–20]. Monroe et al [21] have studied the limitations ofvarious parameters including scattering from remote dopants, backgroundimpurities, interface roughness, alloy fluctuations, strain, morphology andthreading dislocations on the mobility. Considering all potential scatteringmechanisms which are reasonable, the authors predicted a low-temperatureelectron mobility over 1 000 000 cm2 V−1 s−1, which is comparable to thosereached in GaAs/AlGaAs heterostructures.

Several other workers have calculated the expected electron mobilityenhancements in strained-Si layers relative to bulk-Si [22–24, 26, 27].Vogelsang and Hofmann [23] have calculated the in-plane electron driftvelocities and mobilities in strained-Si for 300 and 77 K. High-field driftvelocities were calculated by Monte Carlo (MC) simulations and low-fieldmobilities by the numerical solution of Boltzmann’s equation includingintra- and inter-valley phonon and impurity scattering mechanisms. Amobility enhancement of 74% was obtained at 300 K, compared to 36% at77 K, and a significant improvement of the drift velocity relative to bulk-Siwas reported. Yamada et al [27] have reported a Monte Carlo study ofthe low-temperature mobility of electrons. For a device structure having2×1018 cm−3 doping, mobility values of 2.5×105 cm2 V−1 s−1 at 4.2 K and3.1× 105 cm2 V−1 s−1 at 1.5 K for an electron density of 7.5× 1011 cm−2

were obtained. Peak mobility values of 5.0×105 cm2 V−1 s−1 at 4.2 K and7.6× 105 cm2 V−1 s−1 at 1.5 K were predicted for a lower channel electrondensity.

Rashed et al [22] have studied electron transport in the inversionlayer of strained-Si channel n-MOSFETs using an MC tool, taking intoaccount scattering mechanisms, namely phonon, surface roughness andalloy scattering. Table 6.1 shows the computed low-field electron mobilityenhancement factors for strained-Si, along with some reported experimentaldevice data. For a low level of strain at low electric field, the electronmobility increases with increasing strain.

High-field velocity saturation and overshoot of electrons in strained-Si [24] show only a slight increase in the saturation velocity at both roomtemperature and 77 K. As the electric field parallel to the current flow isincreased, the drift velocity of the electron increases and approaches thesaturation velocity. These high electric fields are common in short-channeldevices, and thus the saturation velocity, rather than low-field mobility,may ultimately limit the performance of scaled devices [23,28].

Electron velocity overshoot in strained-Si/Si1−xGex MOSFETs hasalso been studied using an MC simulator by Gamiz et al [29] for steady-state and non-steady-state for high longitudinal field transport regimes.It was concluded that at high longitudinal fields, the electron velocityovershoot effects, due mainly to the reduction of the inter-valley scatteringrates as the Ge mole fraction increases, improve MOSFET drain currentand transconductance.


Table 6.1. Low-field electron mobility: dependence on strain level in Si.

Ge concentration Strain in Si Temperature Computed mobilityin the buffer (%) (%) (K) enhancement factor Ref

10 0.4 300 1.6 [22]20 0.8 1.830 1.33 1.9

2.5 0.1 300 1.14 [23]5 0.2 1.2710 0.4 1.515 0.6 1.6520 0.8 1.7325 1 1.742.5 0.1 77 1.285 0.2 1.3610 0.4 1.36

16.6 0.66 300 2.67 [24]33.3 1.33 2.6716.6 0.66 77 1.3533.3 1.33 1.35

Experimental mobilityenhancement factor

10 0.4 300 1.45 [25]20 0.8 1.6729 1.3 1.7529 1.3 77 1.35

However, the progress in the study of hole mobility in strained-Si hasbeen relatively slow. Nayak and Chun [11] have calculated the low-fieldhole mobility of strained-Si. At room temperature, in-plane hole mobilitieswere found to be 1103 and 2747 cm2 V−1 s−1 for Ge content of 10%and 20%, several times higher than that of bulk-Si. Table 6.2 shows thecomputed low-field hole mobility for strained-Si, along with some reportedexperimental hole mobility enhancement factors obtained from device data.

6.1.2. Experimental mobility

Low-temperature Hall mobility measurements are commonly used todetermine the overall quality of a heterostructure and are used tooptimize the growth parameters. At low temperature, where thermaleffects and scattering by phonons are dramatically reduced, the electron

Mobility in strained-Si 201

Table 6.2. Low-field hole mobility: dependence on strain level in Si.

Ge concentration Strain in Si Temperature Computed mobilityin the buffer (%) (%) (K) cm2 V−1 s−1 Ref

10 0.4 300 1100 [11]15 0.6 195020 0.8 270025 1 3500

Experimental mobilityenhancement factor

29 1.33 300 1.2 [30]

18 0.8 300 1.4 [31]18 0.8 77 2.0

25 1.0 300 1.5 [32]

mobility becomes very sensitive to residual scattering mechanisms due tobackground charge impurities, roughness and dislocation.

Experimental electron mobility data from strained-Si/SiGe modulation-doped structures may be divided into two categories:

(i) data from devices with the uniform composition buffer, and(ii) devices with the compositionally graded buffer.

Figure 6.2 shows the range of values for Hall mobility [18, 28, 33–38]using both uniform composition and graded buffer layers. In the case of theuniform composition buffer [33, 36, 38], strain relief is a function of bufferlayer thickness. In order to achieve a strain level of 1% in Si, a partiallyrelaxed 0.2 µm Si0.68Ge0.32 uniform composition buffer is required [39].For an effective strain level of 1% in Si on a uniform composition buffer,record high electron mobilities of 1280 cm2 V−1 s−1 at 300 K [38] and17 000 cm2 V−1 s−1 at 1.5 K [36] have been reported. In this type ofbuffer, mobility is limited by the presence of a large number of defects(109–1010 cm−2) in the buffer layer. The effect of dislocations on electronmobility has been reported by Ismail [40]. It has been found that electronmobility is sensitive to threading dislocations when their density exceeds3×108 cm−2, and decreases by two orders of magnitude when the threadingdislocation density is 1 × 1011 cm−2.

The introduction of graded buffer layers has made a great impacton the electron mobility enhancement. The upper curve in figure 6.2represents very high (around 200 000 cm2 V−1 s−1) low-temperaturemobilities but underestimates the two-dimensional electron gas mobility


Figure 6.2. Measured electron Hall mobility versus temperature inmodulation-doped strained-Si. The solid symbols are for strained-Si grown onhigh-quality, graded Si1−xGex buffer layers, while the open symbols refer to filmswith constant Ge content. (After Maiti C K et al 1998 Semicond. Sci. Technol.13 1225–46.)

at room temperature. This is due to parasitic parallel channels of lowmobility and an unknown carrier concentration, which freeze out at a lowtemperature, but lead to a reduced average value of the Hall mobility at ahigher temperature. By carefully designing the doping concentration in aseries of samples, Nelson et al [41] could separate the contribution of the2DEG at room temperature, and extracted room temperature mobility inexcess of 2500 cm2 V−1 s−1 for the limiting case of a vanishing parasiticchannel. The room temperature mobility enhancement factor is almosttwice that of bulk-Si, and a factor of more than three greater than that ofan Si-MOSFET.

The extremely high electron mobility obtained in modulation-dopedlayered structures, grown using MBE and UHVCVD, indicates thata similar buffer layer quality has been obtained. By optimizing themodulation-doped layer sequence and thickness of strained-Si well [42], thehighest mobility values between 300 000 and 400 000 cm2 V−1 s−1 have been

Band structure of strained-Si 203

obtained. Additional wave functioning by front and back gating of someof the structures led to a record low-temperature (0.4 K) electron channelmobility beyond 500 000 cm2 V−1 s−1 [43, 44], which is an improvementof more than a factor of ten compared to the best Si MOSFETs reported.Typical values of room temperature mobility, however, are between 2000and 2800 cm2 V−1 s−1 for n-channels [28,45], which exceed those in bulk-SiMOSFETs by a factor of four to six.

A high hole mobility in excess of 9300 cm2 V−1 s−1 at 4 K ina p-type modulation-doped Si/Si0.87Ge0.13/Si heterostructure has beenreported by Whall [46]. At room temperature, values between 1400 and1800 cm2 V−1 s−1 are more typical, still a factor of at least six to nineabove that of a bulk-Si p-MOSFET [47].

6.2. BAND STRUCTURE OF STRAINED-SI

The effect of both strain and alloying on the bandgap of the strained-Si/SiGe material system has been reported in detail by People [10]. Inparticular, the computed conduction and valence band discontinuities havebeen based on the calculations of van de Walle and Martin [48]. Theextracted valence and conduction band offsets between the strained-Si andrelaxed-Si1−xGex layers [49] are plotted against theoretically estimatedvalues in figure 6.3, showing a good match, particularly at low Geconcentration. Substituting the extracted conduction and valence bandoffset values, the overall bandgap of the strained-Si can be obtained and isshown in figure 6.4, along with the theoretical calculations of People [10].

The heterojunction band offsets (∆Ec, ∆Ev) in a strained-Si/SiGeheterostructure have also been determined from measurement of thethreshold voltages of a surface channel strained-Si p-MOSFET structure(see figure 6.5(a)) [50]. To determine the threshold voltage at the strained-Si/SiGe interface (VTH) and the threshold voltage at the strained-Si/SiO2interface (VTS), the zero current intercept of the IDS–VGS and IDS/

√gm

characteristics were used. The measured values of threshold voltages VTHand VTS were −1.0 V and −1.7 V, respectively [50, 51]. The extractedexperimental valence band offset ∆Ev was found to be 160 meV. Usingthe valence band offset value, conduction band offset was obtained fromequations (2.11) and (2.12) where x is the Ge concentration in the top partof a completely relaxed-SiGe buffer cap. The conduction band offset ∆Ecwas found to be about 126 meV for a Ge mole fraction x = 0.18 in therelaxed-SiGe layer, and agreement with reported results was found to begood [10,33].


Figure 6.3. Band offsets: (a) valence band and (b) conduction band forstrained-Si to relaxed Si1−xGex. Calculated curves are from People R 1986 IEEEJ. Quantum Electron. 22 1696–710 and the data are from Braunstein et al 1958Phys. Rev. 109 695–710.

6.3. DEVICE APPLICATIONS

Silicon complementary metal–oxide semiconductor transistors are the mostimportant building blocks in digital integrated circuits due to low powerconsumption and mature technology. The use of strained-Si/SiGe materialspromises to improve the speed-power performance of CMOS by offeringhigher electron and hole mobilities. Device applications of strained-Si/SiGewith special emphasis on heterostructure metal–oxide semiconductor field-effect transistors are described in this section, while the alternativeapproach of a Schottky gate modulation-doped field-effect transistor isdiscussed in section 6.5.

Device applications 205

Figure 6.4. Bandgap of strained-Si grown on a relaxed-Si1−xGex buffer layer.Calculated curves are from People R 1986 IEEE J. Quantum Electron. 221696–710 and the data are from Braunstein et al 1958 Phys. Rev. 109 695–710.

Figure 6.5. Device structures for strained-Si MOSFETs with (a) Si on thesurface, (b) Si buried and (c) dual strained-Si channels.


6.3.1. Strained-Si n-MOSFETs

Very high electron mobilities demonstrated in strained-Si layer suggest agreat potential for this material in high transconductance n-MOSFETs.To date, in-plane electron mobilities approaching 3000 cm2 V−1 s−1

have been reported in long-channel MOSFETs with both surface andburied channels [52]. Figure 6.5 shows the schematic diagrams of severalpossible configurations of strained-Si MOSFETs. All the structures havethick, relaxed-Si1−xGex buffer layers, consisting of a layer with linearly-graded Ge, followed by a constant Ge layer. The surface channel device(figure 6.5(a)) has a single layer of thin strained-Si grown on top of therelaxed buffer layer. This layer is oxidized to form a gate oxide. The buriedstrained-Si channel device (figure 6.5(b)) has a layer of strained-Si buriedbeneath a thin layer of relaxed Si1−xGex. An additional layer of strained-Siis necessary to form a gate oxide on top of the Si1−xGex, but ideally thisadditional Si layer (sacrificial layer) should be consumed during oxidation.If this sacrificial layer is not consumed fully, then a very thin layer of Si,left between the gate oxide and the Si1−xGex barrier layer (figure 6.5c) canact as a parallel conducting channel, strongly affecting device performance.Depending on the dopant type in the layers, these structures can be usedfor n- or p-MOSFETs.

Welser et al [52, 53] have fabricated both p- and n-MOSFETs usingall these device structures and some of their results on n-MOSFETs arepresented below. Long-channel (L ×W = 10 µm × 168 µm) surface andburied n-MOSFET devices fabricated on relaxed-Si0.7Ge0.3 buffer layershave shown well-behaved output characteristics. The effective low-fieldmobilities for these device structures are shown in figure 6.6. For thesurface-channel strained-Si device µeff is enhanced compared to the bulk-Sicontrol device and has a similar dependence on the effective electric field.The peak mobility is 1000 cm2 V−1 s−1, which shows an 80% enhancementover Si-control (550 cm2 V−1 s−1). The peak mobility value for the buriedchannel device is over 1600 cm2 V−1 s−1, which is almost three times thatof Si-control device. Room temperature effective mobility versus electricfield curves of surface-channel, strained-Si n-MOSFETs with different Gecontent in the buffer layer are shown in figure 6.7, along with the mobilityextracted from a bulk-Si control device. Strained-Si mobility increases withincreasing strain (more Ge content in the relaxed buffer layer) and has littledependence on the effective electric field.

Rim et al [54] have reported measurements on deep submicron(0.1 µm) strained-Si n-MOSFETs. An electron mobility enhancement by75%, compared to typical Si MOSFET mobilities, has been reported inspite of the high channel doping and vertical effective field present in thedevice. The ac measurements, used to reduce self-heating effects, haveshown an extrinsic transconductance increase by 45% for a channel length


Figure 6.6. Effective low-field mobility versus effective field for differentn-MOSFETs. The surface channel strained-Si mobility shows a fairly constantmobility enhancement compared to that of the control-Si device, while theburied strained-Si mobility peaks at low fields, but decreases rapidly at higherfields. (After Welser J J 1994 The application of strained-silicon/relaxed-silicongermanium heterostructures to metal–oxide semiconductor field-effect transistors(Stanford University).)

Figure 6.7. Effective mobility of surface-channel, strained-Si n-MOSFETsat room temperature. Strained-Si mobility increases with increasing strain(more Ge content in the relaxed buffer layer). (After Welser J J 1994 Theapplication of strained-silicon/relaxed-silicon germanium heterostructures tometal–oxide-semiconductor field-effect transistors (Stanford University).)


Figure 6.8. Effective mobility, µeff versus vertical effective field, Eeff . Forhigh Eeff , µeff is enhanced by 75% for strained-Si compared to the epi control-Sidevice and state-of-the-art universal MOSFET mobility. Data from Welser J etal 1994 IEEE IEDM Tech. Dig. pp 373–6, Takagi S et al 1994 IEEE Trans.Electron Devices 41 2357–62. (After Rim K et al 1998 IEEE IEDM Tech. Dig.pp 707–10.)

of 0.1 µm. In figure 6.8, the effective mobility µeff , measured on largedevices, is shown as a function of vertical effective field Eeff . Even for highEeff (>0.5 MV cm−1), the effective mobility µeff for the strained-Si deviceis enhanced by ∼75% compared to the epi control-Si.

Electron mobility enhancements observed at lower Eeff [25] are thussustained at higher effective fields, as predicted theoretically for thephonon-limited mobility in strained-Si MOS inversion layers [16]. Themeasured µeff for strained-Si (peak µeff ∼ 575 cm2 V−1 s−1) is alsoenhanced over the state-of-the-art n-MOSFET mobility [55]. These resultsdemonstrate that, unlike conventional Si which is constrained to theuniversal MOSFET mobility curve (figure 6.8, dotted curve), strained-Siprovides mobility improvement at a given Eeff . Such an enhancement in µeffat high channel doping and Eeff enables fabrication of high mobility, deepsubmicron devices with channel doping suitable to counter short-channeleffects (SCE).


6.3.2. Strained-Si p-MOSFETsExploiting the demonstrated higher mobility for holes, efforts have beenmade to fabricate strained-Si p-MOSFETs. Various research groupsworking on the problem were able to achieve better performance withstrained-Si compared to control-Si devices. The tensile strain in silicongrown on a relaxed-SiGe buffer raises the light-hole band and lowers theheavy-hole band, leading to a significant increase in the low-field holemobility. Observation of hole mobility enhancement in strained-Si p-MOSFETs was demonstrated by Nayak et al [32]. The initial devices werefabricated on a 1 µm uniform composition partially relaxed-SiGe buffer,which is known to have a very high defect density [56] and this resulted ina limited performance (subthreshold slope 111 mV/decade).

An improved device structure and process to fabricate highperformance strained-Si p-MOSFETs has been reported, with a high-quality (defect density <105 cm−2) step-graded completely-relaxed thick(3 µm) SiGe buffer layer, a low thermal budget (maximum temperature700 C) and a high-quality (100 A) gate oxide [31,50]. The device structureused is shown in figure 6.9(a). It was shown that the high-field channelmobilities of a device, with a germanium concentration of 0.18 in the SiGebuffer, were 40% and 200% higher at 300 K and 77 K respectively, comparedto those of a similarly processed bulk-Si p-MOSFET. Rim et al [30] havealso reported enhanced hole mobility in a surface-channel p-MOSFET (seefigure 6.9(b)) employing strained-Si on pseudomorphic Si1−yGey on a fullyrelaxed-Si1−xGex buffer layer.

Figure 6.10 shows the variation of low VDS (−0.1 and −0.3 V)transconductance of strained-Si and control-Si p-MOSFETs at 300 K, forthe device structure shown in figure 6.9(a). The gate voltage at which peaktransconductance occurs depends on the value of VDS and the device type,namely control-Si or strained-Si. The control-Si device shows one largepeak at −1.7 V. But, for the strained-Si devices, two peaks are perceptibleat −1.5 V and −1.9 V at 300 K. The peak at −1.5 V corresponds tohole confinement at strained-Si/SiGe–buffer interface. At a higher gatevoltage, however, the holes at the SiO2/strained-Si interface dominate thechannel conduction and the device becomes a surface channel device. Thetransition from buried channel to surface channel is clearly seen from thetransconductance plot at 77 K (figure 6.11). The two peaks (−1.55 V and−2.7 V) are clearly seen. The IDS–VGS characteristics at 77 K for both thestrained-Si and control-Si devices are also shown in this figure 6.11. It willbe noticed that there is substantial current at VGS close to zero, particularlyfor the control-Si device. For the strained-Si device the characteristicsindicate an accumulation current threshold of about −1 V. When thetemperature is reduced to 77 K, the mobility improves in both siliconand strained-Si, the factor of improvement depending on the scatteringmechanisms operating at the applied gate voltage.


Figure 6.9. Schematic diagram of a strained-Si p-MOSFET: (a) strained-Sigrown on a fully relaxed-SiGe buffer layer (abrupt) and (b) strained-Si grown ona grade-back Si1−yGey layer (graded).


Figure 6.10. Linear transconductance of a long channel (L×W = 100×300 µm)strained-Si (on an 18% Ge buffer layer) and control-Si p-MOSFETs at 300 K.(After Maiti C K et al 1997 Solid-State Electron. 41 1863–9.)

Figure 6.11. Linear transconductance of a long channel (L×W = 100×300 µm)strained-Si and control-Si p-MOSFETs at 77 K. Drain currents for the devicesare also shown (right scale). (After Maiti C K et al 1997 Solid-State Electron.41 1863–9.)


The transverse field dependence of MOS device parameters hasassumed a greater importance because the thinner gate dielectrics andhigher doping levels used in submicron MOSFETs lead to very hightransverse electric fields well above 0.5 MV cm−1. It is well known that suchhigh fields cause a degradation in device performance. The variation of theeffective mobility with electric field is often used as a basis of comparison ofMOS devices developed for computer-aided design. The transconductancefactor, field-effect mobility and effective mobility computed from IDS–VGS characteristics at room and liquid nitrogen temperature have beencompared for strained-Si and control-Si accumulation p-MOSFET devices[50]. Figure 6.12 shows the variation of computed field-effect mobility andeffective mobility for strained-Si and control-Si at 77 K. The effective fieldvalues assume a flat band voltage of −1 V. The presence of the surfaceand parasitic channels at the strained-Si/SiO2 and SiGe/Si interfaces is

Figure 6.12. Comparison of the field-effect and effective hole mobility of longchannel strained-Si and control-Si p-MOSFETs at 77 K: (a) µfe of strained-Si; (b)µfe of control-Si; (c) µeff of strained-Si; and (d) µeff of control-Si. The effectiveelectric field values applicable at 77 K for a current threshold value of −1.0 V arealso indicated. (After Maiti C K et al 1997 Solid-State Electron. 41 1863–9.)

Simulation of strained-Si HFETs 213

indicated by the transconductance (see figure 6.11). Above VGS = −2.5 V,the strained-Si device shows an improvement in both.

6.4. SIMULATION OF STRAINED-SI HFETS

Abramo et al [57] have presented a study of a novel Si/SiGe n-MOSFETstructure simulated by means of a one-dimensional quantum mechanicalapproach which accounts for the quantum nature of two-dimensionalelectron gas. In simulation, energy splitting between degenerate conductionband valleys of strained-Si layer, optical and elastic acoustic phononscattering among subbands, and surface roughness scattering wereimplemented. The non-parabolicity effect on the scattering rates andvelocities was included by first-order perturbation theory following [58].Room temperature low-field peak electron mobility values greater than2800 cm2 V−1 s−1 were predicted. The authors also showed good turn-on characteristics and linear transconductance behaviour for the structureconsidered.

Although two research groups have demonstrated high-performancestrained-Si channel n- and p-MOSFETs [30, 31, 50, 52], until recently verylittle information on the design issues was available in the literature.Careful design considerations are necessary for gate oxide, strained-Siand graded SiGe layer thicknesses, Ge content and profile, and substratedoping required to control the threshold voltage to optimize the deviceperformance. A simulation study of strained-Si short-channel p-MOSFETshas been presented by Armstrong and Maiti [59, 60] and verified bycomparison with experimental device measurements. Analytical models forboth electron and hole mobilities in strained-Si and SiGe were incorporatedinto the ATLAS device simulator to evaluate the strain dependence oftransconductance on temperature. In the case of a p-MOSFET, the useof a graded SiGe buffer layer reduced the valence band discontinuityat the strained-Si/SiGe interface and decreased the hole concentrationin the buried parasitic SiGe channel to give an overall increase intransconductance.

The basic device structures considered for simulation are similar tothose shown in figure 6.9 and the device data used in simulation are givenin table 6.3. A 0.8 µm strained-Si channel p-MOSFET (figure 6.9(a),abrupt case) on an Si1−xGex buffer cap (0.9 µm) grown on top of a step-graded 2.1 µm relaxed-SiGe buffer layer, having a 100 A gate oxide and a135 A thick strained-Si layer was considered. However, in this structure,a parasitic buried channel is formed at the strained-Si/SiGe interfaceand leads to device performance degradation due to lower hole mobilityin the relaxed-SiGe channel. In the other device structure considered(figure 6.9(b), graded case), a thin (300–400 A) graded strained-Si1−yGeybuffer cap (grade-back layer) was sandwiched between the strained-Si layer


Table 6.3. Strained-Si channel p-MOSFET device data used in simulation.

Device type Abrupt Gradedstructure structure

Strained-Si channel (A) 100 150–220Gate length (µm) 0.8 0.8Oxide thickness (A) 100 135Ge concentration (x) 0.1–0.3 0.04Buffer cap (µm) 0.9 –Grade-back layer (A) – 300–400Relaxed-SiGe layer (µm) 2.1 0.7

(150 A) and relaxed-Si1−xGex layer (0.7 µm) to avoid the problem ofhole confinement at the strained-Si/SiGe interface, as the valence banddiscontinuity is reduced because of Ge grading. For simulation, a channellength of 0.8 µm and a 130 A gate oxide thickness were considered.

To account for the enhanced mobility both in strained-Si and SiGelayers, the low-field hole mobility for Si1−xGex was modelled following[61]. The doping concentration and temperature-dependent mobility dueto Arora [62] was modified by using an analytic expression involving Gecontent, x, as

µ(x, T,N) = µArora(T,N)(1 + 4.31x− 2.28x2

)(6.1)

and µArora is given by

µArora(T,N) = µ1p

(T

300

)αp

+µ2p (T/300)

βp

1 +N/Ncp (T/300)γp (6.2)

where µ1p = 54.3 cm2 V−1 s−1, µ2p = 407.0 cm2 V−1 s−1, αp = −0.57,βp = −2.23, γp = 2.546 and Ncp = 2.67×1017 cm−3. Mobility due to alloyscattering is given by [61]

[µalloy]−1 = x(1 − x) exp(−7.68x)/124.1 (6.3)

for x ≤ 0.2 and[µalloy]

−1 = exp(−2.58x)/2150 (6.4)

for 0.2 < x < 0.6.The modified Arora mobility and the mobility due to alloy scattering

were combined using Mathiessen’s rule and implemented for SiGe regionsin the ATLAS simulator. As the low-field hole mobility in strained-Siincreases with increasing strain (i.e., with Ge mole fraction, x, in the

Simulation of strained-Si HFETs 215

substrate [61]) and due to the absence of alloy scattering in strained-Si [11], the enhancement in hole mobility in strained-Si was considered tobe the same as in SiGe (but without alloy scattering) in accordance withequation (6.1). This model was implemented for the strained-Si regionthrough an external C function, which is accessible to ATLAS through itsC-interpreter interface.

The effect of Ge content x on the transconductance at low drain voltageis shown in figure 6.13 and compared with a control bulk-Si device. Astrained-Si device with an abrupt SiGe cap layer shows a transconductance(mobility) enhancement factor up to 1.6 for x = 0.3, comparable with thetheoretically predicted hole mobility enhancement [31].

Figure 6.13. Simulated linear transconductance at 300 K (VDS = −0.1 V) foran n+-gate strained-Si p-MOSFET (abrupt case) with Ge content (x = 0.10,0.20 and 0.30) and control-Si device. (After Armstrong G A and Maiti C K 1998Solid-State Electron. 42 487–98.)


When a grade-back layer is introduced (see figure 6.9(b)) the problemof confinement of holes at the strained-Si/SiGe interface can be avoided, asvalence band discontinuity is reduced because of Ge grading. It has beenshown that for a graded cap layer thickness of 40 nm, the discontinuityin the valence band is almost zero. Hence, confinement of holes andsubsequent formation of a parasitic buried channel is reduced and the devicebecomes a surface channel device. The simulations showed agreement withthe experimental results of Rim et al [30], who concluded that the optimalconfinement of holes occurs for a graded Si0.7Ge0.3 buffer cap thickness of40 nm, and gives rise to an enhancement in transconductance of 30%.

A separate simulation of a surface-channel long-channel strained-Sin-MOSFET (see figure 6.5(a) for a typical device structure) has beenreported by Armstrong et al [60]. The channel doping was 1016 cm−3.Figure 6.14(a) shows the simulated output characteristics for a transistorhaving a gate length of 2 µm and a width of 7.5 µm at room temperature fordifferent gate bias. The experimental output characteristics are also shown,in figure 6.14(b); the data are reproduced from figure 3(a) in [53]. A goodagreement between the simulated and experimental data is observed.

A hydrodynamic (HD) simulation using TMA–MEDICI [63] has beenused to simulate the deep-submicron (0.1 µm) strained-Si n-MOSFETS[54]. Low lateral field mobility models fitted to the measured mobilities(see figure 6.8) for the strained-Si and epi-Si control devices. In thesimulations, high-field transport was modelled using a Caughey–Thomas-like mobility expression, modified to account for the velocity overshootwhich results from a local solution of the energy balance equation [63,64].

Figure 6.14. Output characteristics of a surface channel strained-Sin-MOSFET: (a) simulated and (b) experimental data. (After Welser J J et al1992 IEEE IEDM Tech. Dig. pp 1000–3.)

MODFETs 217

Figure 6.15. Electron velocity in the channel of a 0.1 µm n-MOSFET calculatedby hydrodynamic simulation. Higher mobility in strained-Si enhances the carriervelocity. Use of higher values of τω and vsat for strained-Si in hydrodynamicmodelling further increases the velocity (see text). (After Rim K et al 1998IEEE IEDM Tech. Dig. pp 707–10.)

An energy relaxation time of 0.1 ps was obtained by fitting the measuredtransconductance for the unstrained Si MOSFETs [65]. A small increasein saturation velocity for strained-Si was observed. Figure 6.15 shows theelectron velocity along the channel. Comparison of the HD simulationsto the measured data indicates that carrier transport is improved instrained-Si MOSFETs by both enhanced low-field mobility, and reducedcarrier scattering at high field and energy. This is consistent with thetrends predicted by MC calculations for steady-state and transient carriertransport in strained-Si.

6.5. MODFETS

In a modulation-doped FET, carriers are separated from their parent donoror acceptor atoms as they fall across a heterojunction to a lower energyundoped layer. A typical MODFET structure consists of a thin (5–30 nm)well with quantized states in which the carriers move collision-free (two-dimensional electron or hole gas (2DEG or 2DHG)); n-wells are strained-Si [66,67], while p-wells are SiGe (typically up to 30% Ge) [68,69]. Doping


Figure 6.16. Typical layer sequence (a) n-MODFETs with Si channel on arelaxed-SiGe buffer, (b) p-MODFET with SiGe channel and (c) p-MODFETwith Ge channel on a relaxed-SiGe buffer. (After Schaffler F 1997 Semicond.Sci. Technol. 12 1515–49.)

is accommodated in a neighbouring SiGe layer or in an Si layer separatedfrom the well by a thin undoped spacer (2–20 nm). The doped layer canbe several nm thin or only a sub-atomic δ-doped layer.

Figure 6.16 shows the layer sequence typically used for n-MODFETswith an Si-channel and graded-SiGe buffer layer. The creation of high-quality quantum wells requires a careful adjustment of the layer thicknesses,composition, strain states and the doping levels. A detailed discussionon design strategy and layer sequence of a MODFET is given in [13].Extensive experimental work on the modulation-doped structures (mostlyn-MODFETs) involving strained-Si on relaxed-Si1−xGex layers has beenperformed by several groups [41,66].

Early work used a uniform composition SiGe buffer, while recent workuses a compositionally graded buffer. Linear or step-grading is essentialto minimize dislocation faults and buffer layers have to be thick (3 µm)for strained-Si channels. Device fabrication steps include low-temperatureprocessing to avoid degradation of the abruptness of the heterointerfaces,mesa etching and a Pt/Ti/Au Schottky gate with a barrier height of about0.9 eV. Table 6.4 summarizes important parameters of some of the n-MODFETs reported in the literature. The dependence of n-MODFETperformance on strain in the Si well and the quality of the SiGe bufferlayer at different temperatures are indicated.

The improvement in transconductance obtained in employing acompositionally graded buffer layer with optimized layer design occursprincipally by minimizing the distance between the 2DEG and the Schottkygate. For 1.2% strain in Si, a room temperature transconductance of

MODFETs 219

Table 6.4. Dependence of n-MODFET performance on strain in Si and qualityof SiGe buffer layer at different temperatures.

Type of Gate Low-field gm (mS mm−1)SiGe buffer length Temp. mobility (∗∗ extrinsic)used (µm) (K) (cm2 V−1 s−1) (∗ intrinsic) Ref

1% strain in Si channel

Uniform comp. 1.6 300 1550 40∗∗ [67]Si0.75Ge0.25 70∗

0.2 µm

1.3% strain in Si channel

Uniform comp. 1.4 300 1090 80∗∗ [70]Si0.68Ge0.32 88∗ [71]0.3 µmSi0.5Ge0.5/Si 155∗∗


Comp. graded 1.4 300 60–72∗∗ [72]Si0.7Ge0.3 77 100–133∗∗

1.5 µm300 340∗∗

300 380∗

77 670∗∗

77 800∗


Step graded 0.25 300 1500 330∗∗ [66]Si0.7Ge0.03 77 9500 600∗∗

(defect density104 cm−2)


Step graded 0.5 300 2600 390∗∗ [73]Si0.7Ge0.3 77 520∗∗

340 mS mm−1 for a 1.4 µm gate length [72], 390 mS mm−1 for a 0.5 µmgate device [66], and 330 mS mm−1 for a 0.25 µm gate device [73] havebeen obtained. At room temperature, the highest reported Hall mobilitywas 2830 cm2 V−1 s−1 [72]. At 77 K and for 1.2% strain, transconductanceof 670 mS mm−1 for a 1.4 µm gate device [72], 520 mS mm−1 for a 0.5 µmgate device [73] and 600 mS mm−1 for a 0.25 µm gate device [66], have beenmeasured. Ismail et al [73] have also shown an improved gate design that


resulted in a lower leakage at high temperature. These encouraging resultsare comparable to those reported for high electron mobility transistors(HEMTs) fabricated in GaAs [74].

The first reported p-channel MODFET in strained-Si grown on arelaxed-SiGe buffer was with a TiSi2 Schottky-barrier gate contact [68].Transconductances of 2.5 and 3.2 mS mm−1 were measured at 300 K forenhancement- and depletion-mode devices, respectively. Arafa et al [75,76]have described a very high-speed p-type SiGe MODFET using Si1−xGexchannel with x ∼ 0.70 and mesa separation with Ti/Pt/Au Schottky gate.The structure is shown in figure 6.17, where an inverted layer sequenceis used. For the channel, the Ge is graded from x = 0.70 to x = 0.55(from bottom to top) to prevent holes from being pulled to the upperheterointerface under negative gate bias. These structures have resultedin a hole mobility of 800–1000 cm2 V−1 s−1 at room temperature and of3300–3500 cm2 V−1 s−1 at 77 K. For a gate length of 0.25 µm, a peaktransconductance of 230 mS mm−1 (almost double that of an equivalentsilicon p-MOSFET), has led to a unity current gain cut-off frequencyof 24 GHz and a maximum oscillation frequency of 37 GHz at roomtemperature. Further improvements may be expected in shorter gate

Figure 6.17. Device structures for a high-mobility p-MODFET with a SiGechannel on a relaxed-SiGe buffer. (After Arafa M et al 1996 IEEE ElectronDevice Lett. 17 124–6.)

MODFETs 221

Table 6.5. Si/SiGe n-MODFET device structure data used in simulation.

Layer sequence Thickness (A) Doping (cm−3)

Si cap 50 1014

SiGe buffer 100 –Top supply layer 40 1.5× 1019Spacer (SiGe) layer 30 –Strained-Si channel 90 –Spacer (SiGe) layer 30 –Bottom supply layer 40 8× 1018SiGe buffer 100 –

Gate length (µm) 0.18 –Ge concentration (x) 0.4 –

length devices by introducing self-aligned gate technology for a reductionin gate/source series resistance.

In the following, we consider the Si/SiGe n-MODFET described byGluck et al [77]. This device was noteworthy (in 1997) as a high-performance MODFET could be realized in SiGe technology, leadingto a maximum oscillation frequency of 81 GHz. In the following, wepresent some results on the high-frequency performance of Si/SiGe n-MODFETs investigated using a computer simulation for Schottky gatedevices. The SiGe MODFET device layer sequence, thickness and dopingused in simulation are shown in table 6.5. The device is depletion modeand operates with the formation of an inversion layer at the heterojunctionin strained-Si.

The spacer layer (30 A) and strained-Si channel (90 A) are assumedto be nominally undoped (∼ 1014 cm−3) but the substrate (relaxed-SiGebuffer) is doped p-type (1000 Ω cm). The top and bottom SiGe supplylayers (with doping levels 1.5×1019 cm−3 and 8×1018 cm−3, respectively)supply carriers to the channel. The supply layers are separated by spacerlayers (30 A) from the heterojunction to prevent ionized impurity scatteringin the channel. The variables for simulation are the substrate doping,spacer layer thickness, supply layer doping and source-to-drain separation.The strained-Si channel is maintained at a thickness of 90 A throughoutand is nominally undoped. A constant gate length of 0.18 µm has beenused. The material parameters and models needed for the simulation aresimilar to those of the SiGe HBTs as discussed in chapter 4.

Most of the relevant transistor parameters, such as transconductance,transit frequency and maximum oscillation frequency, are determined fromsimulation. Figure 6.18 shows the simulated and experimental room


Figure 6.18. Simulated and experimental dc output characteristics of a 0.18 µmgate length SiGe MODFET. Experimental data is from Gluck M et al 1997Electron. Lett. 33 335–7.)

temperature dc output characteristics of a 0.18 µm gate length SiGeMODFET. A comparison of experimental and simulated current gain andmaximum unilateral power gain (MUG) is shown in figure 6.19. Thepredicted unity gain cut-off frequency of 46 GHz and maximum oscillationfrequency of 80 GHz well match the experimental measurement.

In figure 6.20, it is clear from the simulated transconductance thatthe quantum well channel is not completely depleted at zero gate bias.Figure 6.21 shows the gate bias dependence of cut-off frequency of a typicaldevice. The frequency maximum appears at almost the same gate biasas the transconductance maximum. The drain-source voltage dependenceof the device (see figure 6.22) shows that high cut-off frequency is evenobtained at low voltages (VDS ≥ 1–1.5 V). As good performance is achievedat reduced drain bias, these devices are attractive for low-power circuitapplications with reduced supply voltages.

Over the last few years, SiGe heterostructure FET devices withoutstanding RF performance have been demonstrated. Schottky gateMODFETs, with fmax of up to 92 GHz (the highest maximum frequencyof oscillation reported so far for any Si-based FET) and a peaktransconductance of 470 mS mm−1, have been achieved [78]. The n-SiGeMODFET combines the advantages of a heterodevice with well-establishedSi technology. For p-SiGe MODFETs, cut-off frequencies of 70 GHz andfmax of 84 GHz have been measured.

MODFETs 223

Figure 6.19. Simulated and experimental current gain and maximum unilateralgain (MUG) as a function of frequency. Experimental data is from Gluck M etal 1997 Electron. Lett. 33 335–7.)

Figure 6.20. Transconductance of a 0.18 µm n-MODFET.


Figure 6.21. fT as function of gate voltage for a 0.18 µm n-MODFET.

Figure 6.22. fT as function of drain-source voltage for a 0.18 µm n-MODFET.

Figure 6.23 shows computed cut-off frequency for an n-SiGe MODFETas a function of gate length [78]. The factor of improvement ranges fromaround four for a 1 µm gate length down to a limiting value of two forthe shortest gate length. Much of the projected improvement is due tohigher mobility, but a part is attributed to the higher saturation velocityof the SiGe MODFET (107cm s−1 compared to 6 × 106 cm s−1 for theSi-MOSFET) [79, 80]. Figure 6.24 shows transit and maximum oscillation

MODFETs 225

Figure 6.23. Computed performance potential for n-type HFETs with andwithout velocity overshoot. (After Konig U et al 1998 J. Vac. Sci. Technol. B16 2609–14.)

Figure 6.24. RF performance potential for SiGe HFETs. fT and fmax as afunction of gate length for n- and p-SiGe MODFETs are shown. (After Konig Uet al 1998 J. Vac. Sci. Technol. B 16 2609–14.)


Figure 6.25. Calculated gate delays of SiGe hetero-CMOS circuits as a functionof gate length and width. Experimental results from n-type SiGe HFET devicesare also shown. (After Konig U et al 1998 J. Vac. Sci. Technol. B 16 2609–14.)

frequencies as a function of gate length for measured results on wideranging devices of both n- and p-SiGe MODFETs manufactured by IBMand Daimler–Benz [78].

A test chip for digital applications containing inverters, level shiftersand ring oscillators has been realized [81]. For digital logic design usingSiGe HFET inverters, a second stage to shift the output stage to the inputlevels is required. Large signal measurements at a supply voltage of 2 Vhave shown a gate delay of 70 ps for a device with a gate length of 0.3 µmand a delay of 25 ps for a 0.15 µm gate length, after correcting the RCdelays of the test set using appropriate on-wafer calibration structures.Simulations (figure 6.25) predict gate delays below 10 ps even at high loadsand even for gate lengths exceeding 0.1 µm. A demonstration chip set,including ring oscillators, inverters, differential amplifiers and different testdevices, has also been developed [82].

6.6. HETEROJUNCTION SI/SIGE CMOS

The demonstration of the superior performances of strained-Si MODFETsand MOSFETs has led to the proposal of combining n- and p-channeldevices in a CMOS circuit. Owing to a barrier confined carrier transport inquantum wells with higher mobility, higher vsat and higher carrier density,

Heterojunction Si/SiGe CMOS 227

one can expect higher transconductance, higher speed, lower gate delay,lower noise and low power consumption. Due to the enhanced performanceof p-HFETs, equally sized p- and n-FETs can be designed for higherpacking density. While standard CMOS need a gate length below 0.2 µmfor transconductance around 400 mS mm−1 [83, 84], these are even foundat gate lengths of 1.2–1.4 µm with HFETs.

The advantages to be gained by using strained-Si/SiGe in conventionalSi-CMOS technology have been examined by several workers [64,85–88]. Ashigh electron mobility (2200–3000 cm2 V−1 s−1) [28] in strained-Si channelsunder tensile strain and hole mobility (800–1500 cm2 V−1 s−1) [89] incompressively strained SiGe channels have been achieved, both n- and p-type modulation-doped FETs have been fabricated using both strained-Siand SiGe layers.

For the n-MODFET, the n-doped (phosphorus, 25 keV, 5×1014 cm−2)Si0.7Ge0.3 layer was separated from the Si channel by a spacer of 30 A thickSi0.7Ge0.3. The Schottky gate was formed by Pt. At a 0.4 µm gate length,the measured peak transconductance of 420 mS mm−1 was a factor oftwo higher than an equivalent Si n-MOSFET, and comparable to GaAstechnology. The microwave performance was also impressive, with an fTof 40 GHz and an fmax of 56 GHz for a 0.4 µm gate length [85]. This levelof performance is comparable to that of a GaAs/AlGaAs HEMT, and maypotentially be further improved if an insulating SOI substrate is used [90].

For the corresponding p-MODFET, the Si0.7Ge0.3 layer was dopedwith boron, followed by a 25 A thick spacer, and then a strained 40 ASi0.3Ge0.7 channel, which was finally capped with a 200 A thick Si0.7Ge0.3layer. The peak intrinsic transconductance of 280 mS mm−1 at a 0.23 µmgate length was more than double the value of the equivalent Si p-MOSFETat the same gate length, with corresponding high values of fT of 30 GHzand fmax of 45 GHz [85].

It has been predicted that sub-0.2 µm SiGe HFETs will yield morethan 800 mS mm−1 at room temperature and above 1000 mS mm−1

at 77 K [9]. Figure 6.26 shows the predicted transconductance forHCMOS extrapolated from measurements on 1.2–1.4 µm MODFETs incomparison to the best Si-MOSFETs. These results are corroborated byexperimental demonstrations [77,85], which are both based on s-parametermeasurements on mesa-type devices with submicron gates defined by e-beam lithography.

Based on the above experimental demonstration, using computersimulation, O’Neill and Antoniadis [64, 87] have investigated the high-frequency (microwave) performance of submicron p- and n-channelSi/SiGe-based FETs suitable for CMOS technology. Two-dimensionalsimulation of devices, having gate lengths down to 0.1 µm using ahydrodynamic model, demonstrated an enhancement in fT of around 50%for n-channel devices and more than 100% for p-channel devices.


Figure 6.26. Predicted transconductance of high-performance HCMOSextrapolated from measurements on 1.2–1.4 µm MODFETs, in comparison withbest Si-MOSFETs. (After Konig U and Daembkes H 1995 Solid-State Electron.38 1595–602.)

Ismail [85] has modelled the performance of Schottky gatecomplementary MODFET structures, where electrons flow through astrained-Si channel and the holes through a strained-SiGe layer, bothchannels being epitaxially grown on Si substrates (see figure 6.27). Fora 0.1 µm gate length, the calculated peak transconductance of the n-MODFET was 820 mS mm−1, whereas that of the p-MODFET was610 mS mm−1. The predicted delay for an inverter was 11 ps at a powerdissipation/stage of 0.07 mW. The power delay product of Si/SiGe CMOSis evidently lower than Si CMOS or SOI technology while operating at alower supply voltage.

Due to inherent problems, such as nonplanarity, higher leakagecurrent, difficulty in threshold voltage adjustment and reproducibility formanufacturing associated with Schottky gates, the authors also studiedSi/SiGe CMOS structures, as shown in figure 6.28. The structure is planarand uses SiO2 as a gate insulator and polySi as the gate material. In thiscase, an Si cap layer was used, on which either a low-temperature oxide(LTO) was deposited, or a gate oxide was thermally grown. For an effectivegate length of 0.1 µm and with an oxide thickness of 50 A, the predictedtransconductances of n- and p-MOSFETs are 750 and 600 mS mm−1,respectively.

Several authors [86, 88] have proposed the design for an Si/SiGeheterojunction CMOS which is planar and avoids inversion of the parasiticsurface channel within the operating voltage range. The schematic cross

Heterojunction Si/SiGe CMOS 229

Figure 6.27. Complementary Si/SiGe MODFET cross section. (After Ismail K1995 IEEE IEDM Tech. Dig. pp 509–12.)

Figure 6.28. Complementary Si/SiGe MOSFET cross section. (After Ismail K1995 IEEE IEDM Tech. Dig. pp 509–12.)


(a)

(b)

Figure 6.29. (a) Cross section of a proposed Si/SiGe HCMOS technology and(b) schematic diagram of channel layers and conduction and valence band forgate bias just above VT. (After Armstrong M A et al 1995 IEEE IEDM Tech.Dig. pp 761–4.)

section of such a proposed structure is shown in figure 6.29. As discussedabove, the design provides for both a compressively strained-SiGe holechannel and a tensile strained-Si electron channel in a planar structure.The layers are grown on a low defect density (1×105 cm−2) relaxed gradedSiGe buffer. The p-well is in situ doped during growth of the relaxedbuffer, while the n-well is created by ion implantation prior to growth ofthe channel layers. An undoped spacer is grown above the well dopingin order to adjust the threshold voltage. An n-type δ-doped layer is usedto bend the energy bands so as to avoid inversion of the low-mobility Sisurface channel. The strained-Si electron channel is separated from theδ-doped layer by an undoped setback layer to minimize ionized impurity

Summary 231

Figure 6.30. Power delay product versus stage delay for Si/SiGe HCMOS andbulk-Si CMOS. The corresponding drain bias values are indicated on the curves.(After Armstrong M A et al 1995 IEEE IEDM Tech. Dig. pp 761–4.)

scattering. A graded Ge content is used in the strained-SiGe hole channelto minimize the surface roughness scattering by pushing the carriers awayfrom the oxide interface. A thin Si cap layer allows a high-quality gateoxide to be grown. An in situ doped p+-polySi gate is used for the devices.

Device and circuit simulations show the performance advantage ofthe proposed technology over bulk-Si CMOS for an effective gate lengthof 0.2 µm. Figure 6.30 shows the simulated power delay product versusstage delay of an 11-stage inverter ring oscillator, comparing Leff = 0.2 µmSi/SiGe HCMOS to bulk-Si CMOS, for unloaded and loaded (CL = 10 fF)cases. The higher carrier mobility of the HCMOS results in a sixfoldimprovement in the power delay product at a stage delay of 28 ps forthe unloaded case and a fourfold improvement at a delay of 55 ps for theloaded case. A minimum delay of 22 ps is predicted for unloaded Si/SiGeHCMOS running at 1.5 V.

6.7. SUMMARY

In this chapter, recent progress in strained-Si on relaxed-SiGe buffer hasbeen reviewed. Progress in design and fabrication of high mobility n-and p-channel strained-Si/SiGe devices (MOSFETs and MODFETs) were


presented, as well as some of the materials and processing issues relatedto the fabrication of these heterostructures. Due to their compatibilitywith conventional Si-processing technology, mobility enhanced HFETsare expected to provide performance advantage, when down scalingin device dimensions will no longer be possible in bulk-Si. Sincelow-power mixed-mode circuits are becoming increasingly important formobile communications, Si/SiGe heterojunction CMOS technology willbe useful for the improvement of high-frequency performance. However,from a manufacturing point of view, several issues of concern, such asdevice isolation, interconnects and reliability, require further experimentalinvestigation in order to assess the true potential of Si/SiGe HCMOS.

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Chapter 7

SIGE HETEROSTRUCTURE FETS

Over the past 20 years, the channel length of MOS transistors has halved atintervals of approximately three or four years. This continual shrinking ofthe size of MOS transistors has led to increasing performance in electronicsystems and increasing packing density. The question that arises now is‘how long can this trend continue?’ A number of factors are posing a threatto the evolution of CMOS technology. Firstly, the channel length of theMOS transistor is defined using optical lithography, which is limited bythe wavelength of the radiation used. The current thinking is that opticallithography can reach channel lengths of around 0.15 µm, but it is not clearthat it can meet the challenge of smaller geometries. Other lithographytechniques exist, such as electron beam and x-ray lithography, but thesehave associated problems that remain to be solved.

Improvements in MOSFET saturated drain current have been achievedby shrinking the source-to-drain separation or effective gate length (Leff)and through the use of thinner gate oxides to increase the gate capacitanceto improve inversion charge density. Predictions for static random accessmemory (SRAM) technology anticipate gate oxide thicknesses of the orderof 4 nm and gate lengths of 0.15 µm (see table 7.1) [1]. However, therequirement for highly uniform gate oxide films across a large wafer callsinto question the continuous reduction of gate oxide thickness to improveinversion charge density. Also, below 0.35 µm gate lengths, the carriersin the channel of the MOSFET attain a saturated velocity that is nearlyindependent of Leff . As a result of these two limits—oxide scaling andcarrier velocity saturation—it appears that the MOSFET saturated draincurrent is approaching a fundamental physical limit.

In chapter 6, on strained-Si, it has been shown that electron or holeconfinement structures (n-HFET or p-HFET) require more complex growthtechniques for strained-Si on relaxed thick SiGe layers, and are limited interms of processing thermal budget. In contrast, the p-HFET is more easilyrealized, since it involves the growth of strained-Si1−xGex epitaxial films

238

SiGe heterostructure FETs 239

Table 7.1. CMOS scaling guidelines. (After Davari B 1996 IEEE IEDM Tech.Dig. pp 555–8.)

1995 1998 2001 2004

Lithography resolution µmGeneral 0.5 0.35 0.25 0.18Gate level for short L 0.35 0.25 0.18 0.13

Channel length (µm) 0.35/0.25 0.2/0.15 0.1 0.07

Gate insulator thickness (nm) 9/7 6/5 3.5 2.5

Supply Voltage (V)High performance 3.3/2.5 2.5/1.8 1.5 1.2Low power 2.5/1.5 1.5/1.2 1.0 0.8

Relative speedHigh performance 2.7/3.4 4.2/5.1 7.2 9.6Low power 2.0/2.4 3.2/3.5 4.5 5.8

Relative power/functionHigh performance 0.47/0.34 0.29/0.18 0.12 0.077Low power 0.20/0.09 0.08/0.056 0.036 0.027

on an Si substrate. In this device, the Si1−xGex quantum well acts as achannel for holes between the source and drain regions of the device, asshown in figure 7.1. Improved electrical characteristics of this device overthe conventional surface channel Si p-MOSFET are the results of improvedcarrier transport, quantum confinement and buried channel operation.p-HFETs provide quantum confined carrier conduction with high carriermobility, which is critical for high-frequency Si-based integrated circuits.Some of the key parameters of several reported SiGe-channel devices areshown in table 7.2.

High saturated drift velocity of holes, due to strain-induced transportenhancements in SiGe, allows for equivalently sized n- and p-channeldevices and, consequently, increased circuit densities. Coupled to this, theability to produce quantum devices on the same chip gives SiGe substantialpotential for advanced circuits. SiGe channel p-HFETs have the followingpotential advantages:

• large carrier population in the channel at low gate biases due toquantum confinement;

• buried channel operation to suppress hot carrier effects;• low defect density using conventional Si substrates; and• process compatibility with existing CMOS process lines.

240 SiGe heterostructure FETs

Figure 7.1. Device structure for a typical SiGe-channel p-HFET fabricated ina strained-SiGe layer with an Si-cap layer. Layer thicknesses shown are typical.

Table 7.2. Some of the reported results for SiGe p-HFETs.

gm,ext (mS mm−1)Gate

Leffµm

Channel(mode) 300 K 77 K tox (Tech.)

Gatematerial

Ref

0.18buried-SiGe(enhanced) – – 45 A Ther. n+poly [2]

0.25buried-SiGe(enhanced) 167 201 71 A Ther. TiSi2 [3]

0.7buried-SiGe(enhanced) 64 – 50 A Ther. polySi [4]

0.9buried-SiGe(enhanced) – – 70 A PECVD n+poly [5]

1.0surface-SiGe(enhanced) 48 60 100 A ECR n+poly [6]

1.0buried-SiGe(depletion) 80 – 65 A WRTO p+poly [7]

4.0buried-Ge(enhanced) – 50 500 A CVD Al [8]

HFETs: structures and operation 241

In this chapter, a review on the present status of silicon heterostructurefield effect transistors in the SiGe and SiGeC material systems is presented.The physics and modelling of submicron p-HFETs are explored usingnumerical simulation to determine the potential applications in ULSIcircuits. The key design issues such as Ge mole fraction, gate oxidethickness and choice of gate contact material have been considered indetail. The choice of the cap layer thickness for a buried SiGe channelis an important issue, having a bearing on the performance of a p-HFET,and due consideration is given.

Also considered are a number of variants of the basic SiGe HFET, p-HFETs built on SOI substrates and SiC/SiGeC channel devices. VerticalSiGe and SiGeC p-HFETs are also attractive for ultra-short channel devicesbecause the channel length is determined by the thickness of an epitaxiallayer and not by the lithography resolution. Vertical channel and scalingissues are considered. Poly-Si1−xGex has shown great potential as agate material due to its tunable work function, process compatibility andfavourable electrical properties, such as low sheet resistance and highdopant activation rate. It can also be used in place of polySi in thin-film transistors on glass. Finally the noise properties of SiGe p-HFETs areconsidered.

7.1. HFETS: STRUCTURES AND OPERATION

A SiGe p-HFET with a general structure similar to a conventionalMOSFET is shown in figure 7.1. It has an n+ (or p+)-polySi or poly-SiGe gate over a thin gate oxide, with p+ source/drain regions in an n-type body. The main distinctive features are the buried SiGe layer andthe optional p+ doping spike (δ-doping) located below it. The SiGe layeractually constitutes a sub-surface quantum well channel for holes betweenthe source/drain regions. It is required to be buried below an Si-capbecause a high-quality gate oxide directly on SiGe using thermal techniquesis difficult to obtain. If such a direct oxidation of SiGe is attempted, theSi is preferentially oxidized, leading to a pile-up of Ge at the SiGe/SiO2interface [9, 10]. Plasma enhanced chemical vapour deposited (PECVD)oxides do not have significantly lower interface state densities, since theinitial stages of this process consist of oxide growth and not deposition [11].The interface state density of such oxides is greater than 1012 cm−2 eV−1, afigure unsuitable for proper operation of a field-effect device. Stoichiometricoxides formed directly on SiGe using low-temperature plasma techniqueshave been reported [12,13] and microwave/ECR plasma grown oxides havebeen used for device fabrication [6].

The use of an Si-cap layer has been customary as oxidation of the Si-cap assures formation of a high-quality gate oxide. But this requirementreduces the efficiency of the device, to which the high mobility carriers in


the SiGe layer can be modulated, due to the increased physical separationfrom the gate potential and the presence of a surface inversion layerthat forms at high gate overdrive. However, the buried channel providesbenefits, such as the suppression of hot carrier injection into the gateoxide and reduced carrier surface scattering, which tend to enhance deviceperformance and reliability. The next important feature of the device isthe presence of an optional δ-doping spike, which is generally realized usingboron. The doping spike is separated from the SiGe channel by an Si spacerto reduce ionized acceptor scattering which occurs if the spike is placedtoo close to the channel. Furthermore, the doping spike is placed belowthe SiGe channel, so that the application of a negative gate bias drawsholes upward towards the SiGe channel. The doping spike has two majorfunctions:

(i) it creates a retarding electric field for holes at zero gate bias tosuppress source/drain leakage current (threshold adjust); and

(ii) it provides holes for the SiGe quantum well for improved devicetransconductance.

For high-speed operation, the p-HFET should be operated under biasconditions in which the hole density in the SiGe well exceeds that in theSi-cap. Determining this bias range requires the calculation of the holedensity in the two inversion layers as a function of gate bias.

7.1.1. Experimental HFETs

Several research groups have fabricated SiGe-channel p-HFETs, mostlyusing conventional Si-processing technology, and performance enhancementcompared to bulk-Si devices has been reported [2–8]. In some designs, theGe profile was graded to optimize the hole confinement and modulationdoping (δ-doping) was used to adjust the threshold voltage. The crosssection of such a SiGe-channel p-HFET, also known as a modulation-dopedSiGe p-MOSFET (MODMOS), is shown in figure 7.2 [5].

In table 7.2, some of the key parameters are compared for some ofthe reported p-HFETs including those fabricated on Ge substrate [8] andon SIMOX [7]. Deep submicron (gate length 0.18 µm) SiGe-channel p-HFETs using strained-Si1−xGex films in a standard CMOS process havebeen reported by Bouillon et al [2]. The channel architecture of the p+-polySi gate Si0.85Ge0.15 channel p-HFET is shown in figure 7.3. Several0.18 µm transistors with different architectures were fabricated. Retrogradechannel profile, heavy ion implant (HI) using P and As, followed byintrinsic Si epitaxy and conventional processing techniques, were employed.The enhancement of hole mobility in the direction perpendicular to thegrowth plane of strained-Si1−xGex, and grading the SiGe channel, areboth effective in the enhancement of the drive current. Figure 7.4

HFETs: structures and operation 243

Figure 7.2. Schematic cross section of the modulation-doped SiGe p-MOSFET.An n+-gate, together with a boron-doped layer placed underneath the SiGechannel, is used to enhance the carrier confinement while obtaining the correctthreshold voltage. Devices with three different channel gradings are fabricated:(a) the abrupt; (b) the graded; and (c) the retrograded profile. (AfterVerdonckt-Vandebroek S et al 1994 IEEE Trans. Electron Devices 41 90–102.)

Figure 7.3. Cross section of a 0.18 µm p+-polySi gate Si0.85Ge0.15-channelp-HFET. (After Bouillon P et al 1996 IEEE IEDM Tech. Dig. pp 559–62.)


Figure 7.4. Output characteristics of a 0.18 µm p-HFET with an Si0.85Ge0.15channel. Implantation conditions were: AS2, arsenic 200 keV/1E13; AS4, arsenic120 keV/4E12; AS1+40, arsenic 120 keV/1E13 + 40 nm cap layer. (AfterBouillon P et al 1996 IEEE IEDM Tech. Dig. pp 559–62.)

Figure 7.5. Subthreshold characteristics of a 0.18 µm p+-polySi gateSi0.85Ge0.15-channel p-HFET. Implantation conditions were: AS2, arsenic200 keV/1E13; AS4, arsenic 120 keV/4E12; AS1+40, arsenic 120 keV/1E13 +40 nm cap layer. (After Bouillon P et al 1996 IEEE IEDM Tech. Dig. pp 559–62.)

Design of SiGe p-HFETs 245

shows the output characteristics, while figure 7.5 compares short-channelsubthreshold characteristics.

7.2. DESIGN OF SIGE P-HFETS

The SiGe HFET design objective is to maximize the devicetransconductance. This can be accomplished by maximizing the numberof high-mobility holes in the SiGe channel, while minimizing the densityof low-mobility holes which flow at the Si/SiO2 interface. The criticalSiGe HFET design parameters include the choice of gate material, layerthicknesses and SiGe channel profile. The type of gate material usedstrongly influences the degree of hole confinement to the SiGe channelp-HFETs [14].

State-of-the-art CMOS technologies are characterized by dual workfunction polysilicon gates, such that both the n- and p-channel MOSFETsare surface-channel devices [15, 16]. A single work function CMOStechnology leads, however, to significant process simplification. The impactof each of these design parameters on device performance is investigatedwith the use of a simulation tool. For the design of deep submicron p-MOSFETs necessary for ULSI, two-dimensional numerical modelling isnecessary to accurately quantify short-channel effects. Once again theSilvaco–ATLAS device simulation tool has been used.

7.2.1. SiGe: MOS capacitor simulation

A typical Si/strained-SiGe/Si p-HFET structure, as shown in figure 7.1, ischosen and subsequent variations in this structure are studied to maximizethe hole concentration in the SiGe quantum well over the realizable gatebias swing. It is instructive to see the distribution of the hole density inthe Si-cap and SiGe-channel for n+- and p+-poly gate contacts. This canbe accomplished using a 1D Poisson solver. A 1D self-consistent solution ofthe Schrodinger and Poisson equations have been reported [17]. However,the use of the Schrodinger–Poisson solver is very time-consuming, so thesimple 1D Poisson solver is deemed to be adequate to illustrate the mainconcept. Quantum effects are therefore neglected.

In figure 7.6 the integrated density (cm−2) of holes in both the Si-capand SiGe quantum well is plotted as a function of gate bias. From this figureit is seen that, as the negative gate bias is increased, the Si1−xGex channelturns on first, and the hole density in the SiGe quantum well increases,revealing a very interesting effect associated with the buried channel p-HFET—charge screening. For a p+-poly contact, a gate bias in excess of−1.5 V results in a saturation of the hole density in the SiGe quantumwell, while the carrier density in the Si-cap continues to increase. Thissaturation of the SiGe hole population is due to the build-up of holes in


Figure 7.6. One-dimensional Poisson simulations of the Si-cap and SiGe-channelcharges for n+- and p+-poly gate SiGe HFETs. The channel is 300 A wide with aflat 30% Ge profile, oxide thickness is 70 A and substrate doping is 5×1016 cm−3

n-type.

the Si-cap with increasing gate bias. As more holes populate the Si-capinversion layer, the effect of the gate potential is screened out and thequantum well effectively ‘sees’ no increase in the gate potential. The pointat which the number of holes in the SiGe well equals the number in theSi-cap is termed the ‘cross-over point’.

7.2.2. Si-cap/oxide thickness variation

Figure 7.7 is a plot of the integrated hole density in the SiGe well and Si-cap layer as a function of cap thickness, for two oxide (tox = 70 and 140 A)thicknesses. The plot reveals that when VG = −2.0 V, for tox = 140 A, thehole density in the well decreases slightly as the cap thickness is increased,while the hole density in the Si-cap shows a modest increase. The holedensity in the well drops more dramatically (for tox = 70 A) as the capthickness is increased while the hole density in the cap increases. Therefore,it is advantageous to keep the cap thickness as small as possible to keep thehole population in the Si cap low and reduce the effects of charge screeningon the SiGe quantum well.

If the gate oxide is kept thin (∼100 A), then an initial Si-cap thicknessof 50 A is sufficient for a uniform oxide to be grown across a wafer surface.However, it should be noted that a remaining cap thickness of only 10 A isenough to support an inversion layer. Hence, the charge screening problem


Figure 7.7. One-dimensional Poisson simulation of areal hole density in theSiGe well and the Si-cap as a function of cap thickness and oxide thickness.

will still be present with such a structure. Consequently, the device canbe operated at low gate voltages, where the SiGe quantum well dominatesdevice electrical characteristics. A thinner gate oxide results in a highercurrent drive and gm due to the improved capacitive coupling betweengate and channel charges. These improvements in performance will alwaysovercome the disadvantage of the small reduction in VG arising with thethinner oxide.

7.2.3. Germanium mole fraction

A higher Ge mole fraction in the channel is desirable from a transportviewpoint, since the hole mobility in pseudomorphic Si1−xGex filmsincreases with increasing Ge content [18]. Figure 7.8 is a plot of integratedhole density as a function of Ge content. From the figure, it is seenthat hole density in the quantum well increases almost linearly with Gecontent x, once the cross-over point is reached. A capacitance–voltage(C–V ) measurement of a SiGe HFET is an accurate method to confirmthe presence of the 2DHG in the SiGe quantum well and characterize theelectrical quality of the gate oxide [19].

Figure 7.9 displays the simulated low-frequency and high-frequencyC–V characteristics of a p-HFET at room temperature. The kink in thecharacteristics between gate biases of −1 and −2 V is a result of thequantum well. Initially, during inversion, holes reside in the SiGe quantum


Figure 7.8. Simulated Si-cap and SiGe-channel hole density for n+-poly gateSiGe HFETs as a function of mole fraction for a flat Ge profile.

Figure 7.9. Simulated high-frequency (x = 0.2, 0.3 and 0.4) and low-frequency(x = 0.40) capacitance–voltage characteristics showing the hole confinement ina p+-poly gate SiGe HFET with an Si-cap (70 A), oxide thickness (65 A) anda SiGe channel 100 A wide as a function of Ge mole fraction, x, with a flat Geprofile.


well. Hence, the structure exhibits a lower effective capacitance due to theseries combination of the oxide and Si-cap capacitances. As the structureis biased more negatively, the inversion layer in the Si-cap forms and thecapacitance of the structure approaches the oxide capacitance, Cox.

7.2.4. Choice of gate material

The choice of gate material has a significant effect on the turn-on characteristics of a p-MOSFET. Typically for surface channel Sip-MOSFETs, a p+-polySi gate is employed to place the MOSFET thresholdvoltage close to −0.5 V. If a p+-polySi gate is used with a buriedchannel, then the device operates in depletion mode. However, if an n+-polySi gate is used, then the device threshold voltage is shifted towardsnegative by about 1 V. Consequently, the buried channel device operatesin enhancement mode, with the buried channel carrier transport propertiesdetermining the MOSFET electrical characteristics at low gate biases. Thedifference between n+- and p+-polySi gates for the p-HFET structure isillustrated in figure 7.10. For the n+-polySi gate, the SiGe layer dominateschannel conduction for gate biases up to −1.5 V, after which the Si-capinversion layer forms. For the p+-polySi gate, the Si-cap inversion layeris already present at 0 V gate bias, hence the device operates in depletionmode. Hence, an n+ gate design is favourable for the p-HFET, because itpromotes SiGe quantum well operation for low gate biases.

Figure 7.10. Threshold voltage versus substrate doping for p+- and n+-polygate SiGe-channel p-HFETs.


Clearly, based on the foregoing discussions, the cap layer should bemade as thin as possible. However, a minimum value may be obtained byconsidering the two primary limitations: avoidance of high interface statedensities (a minimum thickness of silicon cap layer of the order of 50–60 Amay be required [11]) and the avoidance of remote carrier scattering (by theinsulator–semiconductor interface). Some experimental evidence suggeststhe latter limitation may require a cap layer thickness of the order of100 A [20]. To enable significant benefit to be gained from the use of buriedstrained layer channels in submicron p-HFETs, two options exist: increasethe offset potential between the cap and channel layers or reduce the peakfield in the semiconductor. Growth of the SiGe-channel HFETs on silicon-on-insulator (SIMOX) substrates is one approach to field reduction [7]. Asimpler alternative to increase transconductance is to use a p+ doping spike(δ-doping) below the SiGe quantum well.

7.2.5. Current–voltage characteristics

The use of a buried channel (see figure 7.1) is expected to improve carriermobility and noise performance by reducing the interaction of carriers withthe oxide interface. As previously discussed, a major constraint on HFETperformance is the onset of parasitic inversion at the Si-cap and oxideinterface, where the carriers face mobility degradation. This limits thedegree of inversion in the strained channel layer by electrostatic screeningand hence degrades the small-signal transconductance.

The material parameters and models needed for the simulation ofp-HFETs are similar to those of SiGe HBTs discussed in chapter 4. Areduced effective density of state (DOS) in the valence band, Nv, isinherent in the use of compressively strained SiGe channels on Si [21],being intimately linked to the enhanced hole mobility [22, 23]. The lowerDOS effective hole mass and the reduced carrier scattering due to the liftingof the valence band degeneracy are both thought to contribute to highermobility. As the Ge fraction x in a strained SiGe layer is increased, Nv ispredicted to fall monotonically [23] by a factor of 5.6 at x = 0.3, an effectthat cannot not be ignored in modelling HFETs. The carrier mobility inthe surface channel was assumed to be degraded with increasing transverseand longitudinal fields in a similar manner to a conventional MOSFETusing the special purpose (CVT) MOS mobility model [24]. The mobilityin the buried SiGe channel was assumed to be insensitive to the transversefield and solely a function of doping and longitudinal field.

Fermi–Dirac statistics for the computation of carrier density and adense mesh specification for the thin epitaxial layers are required foraccurate modelling of charge distributions and drift–diffusion-based currentformulations have been found to be sufficient for the range of channellengths investigated (down to 0.1 µm). An epitaxial Si-cap layer (30 A)


and a SiGe layer (300 A) are defined to be doped (1 × 1016 cm−3 and1 × 1017 cm−3, respectively), and the underlying substrate (or n-well),uniformly doped to 1 × 1016 cm−3. The oxide layer thickness is 80 Aand interface states are neglected. An n+-polySi gate is used and thethreshold voltage is allowed to shift freely according to channel dopingand layer thicknesses. The dc output characteristics and small-signaltransconductance have been generated and the respective inversion layercarrier populations in the Si cap and SiGe channel have been extracted byintegrating the carrier profiles across the depths of the respective layer.

The effect of Ge content on the linear transconductance is shown infigure 7.11 as a function of gate voltage. When compared to an Si device,the enhanced mobility in the SiGe-channel p-HFETs gives rise to highertransconductance, which increases further with Ge content x. The effectof Ge content on the output characteristics is shown in figure 7.12. Asexpected, the drain current increases with Ge content x in a similar manner.

A useful measure for characterizing the subthreshold behaviour of aMOSFET is its subthreshold swing, S, which is defined as the slope ofthe log (ID) versus VG characteristic, just prior to the threshold voltage,VT. A low value of subthreshold slope is desirable in submicron gatelength p-HFETs to achieve low threshold voltage and a negligible off-stateleakage. Figure 7.13 illustrates that the incorporation of Ge merely shifts

Figure 7.11. Simulated linear transconductance of a SiGe p-HFET at 300 K(VDS = 0.1 V) as a function of Ge content in the SiGe channel.


Figure 7.12. Simulated I–V characteristics of a SiGe-channel p-HFET at 300 Kfor different Ge content in the SiGe channel.

the threshold voltage and has a negligible effect on the subthreshold slope.If a δ-doping spike is placed below the active Si1−xGex channel separatedby a spacer, then the subthreshold characteristic can be significantlyimproved [17]. The doping spike creates an electric field that repels holesfor gate voltages below the threshold voltage, significantly improving thesubthreshold swing of the p-HFET.

7.2.6. δ-doped p-HFETs

The δ-doped layer is separated from the SiGe quantum well by a thinspacer to reduce the effects of ionized impurity scattering. The purpose ofusing a δ-doping spike is primarily to reduce the number of holes at zerobias by creating a retarding electric field which improves the subthresholdcharacteristic of the device. However, the doping spike does not contributea large number of holes to the SiGe quantum well. The contribution isa function of the spacer thickness, and generally increases with decreasingspacer thickness. It has been shown experimentally that a δ-doped acceptorlayer below (but in close proximity to) the SiGe channel allows the inversionlayer carrier concentration in the SiGe channel to be increased [11, 25]. Inaddition, the δ-doping layer reduces the threshold voltage for inversion ofthe channel and increases VGS. However, locating a narrow highly-dopedboron layer immediately underneath the channel of the n+ gate SiGe HFET


Figure 7.13. Simulated subthreshold characteristics of a SiGe-channel p-HFETat 300 K for different Ge content in the SiGe channel.

Figure 7.14. Simulated dc characteristics of an Si0.7Ge0.3 p-HFET with aδ-doping layer.


places severe limitations on its fabrication since the SiGe channel shouldremain undoped.

Figure 7.14 shows the output characteristics of a device with a 30 Athick Si cap and effective gate length of 0.5 µm is enhanced by the additionof a 50 A thick δ-doping layer (Nδ of 2× 1018 cm−3) with a spacer of 30 Abelow the channel. This very significant increase in the device currentdemonstrates the improvement in performance possible through epitaxialgrowth capabilities, such as in situ modulation doping, apart from gainsachieved through increased mobility. Note that, in this case, an n+-polySigate is required to ensure enhancement mode operation (negative VT) inthe same manner as for a conventional buried channel p-MOSFET. Theincrease in VGS is largely due to the reduction in the transverse fieldachieved by the presence of the fully depleted δ-doped layer.

7.3. SIGE P-HFETS ON SOI

As described in the previous section, a SiGe quantum well p-channel HFEThas been shown to have a higher channel mobility compared to that of abulk-Si MOSFET. In order to further improve the channel mobility, the holeconfinement in the quantum well must be enhanced. This is particularlydifficult to achieve at a higher gate voltage, because the surface channelat the SiO2/Si interface dominates conduction. As discussed more fully inchapter 10, fully-depleted SOI (FDSOI) devices have been considered forULSI applications because of improved device isolation, reduced parasiticcapacitance and higher circuit speed [26,27]. Due to the presence of a thickburied oxide layer in an FDSOI device, the vertical electric field and theband bending at the Si surface are significantly reduced, compared to thatof a bulk-Si device [26]. This property of reduced band bending of an SOIstructure can be used to improve the hole confinement in the buried SiGequantum well, and hence improve device performance.

Schematic diagrams of a device used in simulation for bulk-Si and SiGeSIMOX are shown in figure 7.15. The SiGe SIMOX substrate consists of a

Figure 7.15. Schematic diagrams of a bulk SIMOX substrate and a SiGe SIMOXsubstrate in which a p+-poly gate SiGe-channel HFETs are fabricated. (AfterNayak D K et al 1993 IEEE Electron Device Lett. 14 520–2.)

SiGe p-HFETs on SOI 255

Figure 7.16. Comparison of 1D Poisson simulations of the low-frequencycapacitance–voltage characteristics (showing the hole confinement) in a p+-polygate SiGe HFET on an Si-substrate and on a SIMOX. The simulation was carriedout with an Si-cap (70 A), the oxide thickness (65 A) and a SiGe channel 100 Awide with a flat Ge profile (x = 0.30).

conventional SIMOX substrate, a 100 A Si layer, a 100 A Si0.7Ge0.3 strainedlayer and a 100 A Si-cap layer. As discussed earlier, one way to verifythe hole confinement in the quantum well is to study the low-frequencycapacitance, where a plateau in the inversion capacitance signifies the holeconfinement [28]. Figure 7.16 shows that the plateau in low-frequencycapacitance associated with the buried channel region extends for a widerrange of gate voltage for the SIMOX substrate, when compared to the SiGebulk-Si substrate.

Room temperature hole density profiles for n+-poly gate SiGe-channelHFETs on Si and SIMOX substrates are compared in figure 7.17. It isseen that the hole concentration at the Si surface for the SiGe SIMOXdevice is about two orders of magnitude smaller than that for the SiGebulk device. This means that the channel conduction through the parasiticsurface channel is significantly diminished, due to reduced band bendingat the surface. The reduced band bending results in a more uniform holeconcentration in the quantum well for the SiGe SIMOX device, a conclusionthat has been confirmed by experiment [7].

It has been shown that the linear transconductance remains near itspeak value for a wide range of gate voltages at 300 K due to significanthole confinement in the quantum well near the threshold, which is notobserved for SiGe bulk devices. The centroid of the hole distribution in


Figure 7.17. Comparison of 1D Poisson simulations of hole density profiles atroom temperature for a n+-poly gate SiGe-channel HFETs on Si and SIMOXsubstrates. The simulation was carried out with VG–VT = −0.5 V, an Si-cap(70 A), the oxide thickness (65 A) and a SiGe channel 100 A wide with a flat Geprofile (x = 0.30).

the Si0.7Ge0.3 quantum well of the SiGe SIMOX device is located fartheraway from the Si/SiO2 interface when compared to that in the SiGe bulkdevice, which reduces Si/SiO2 surface scattering for the SiGe SIMOX deviceand results in a further improvement in channel mobility. Experimentallyverified improvement in channel mobility of a SiGe SIMOX device over thatof an identically processed SIMOX device is 90% at 300 K [7], whereas themaximum improvement in channel mobility of a SiGe bulk device over thatof an Si device has been found to be 50% [3, 4]. This large enhancementof channel mobility for the SiGe SIMOX device is believed to be due toimproved hole confinement in the buried quantum well of this device.

Silicon-on-sapphire (SOS) technology, which integrates both themicrowave and the VLSI digital/analogue signal processing functions, isideally suited for microwave circuits since it has a low dielectric losssubstrate, low noise figure, excellent radiation hardness and reducedpunch-through effects. Recent studies of SiGe CMOS on sapphiretechnology [29, 30] have shown improvements in p-MOSFET mobility andtransconductance at 300 and 77 K, compared to Si. Both cut-off frequencyand low-field mobility, µeff improve with the integrated Ge dose in theSiGe channel. Table 7.3 compares the performances of several deviceswhile figure 7.18 shows a comparison of the measured and simulated lineartransconductance of a SiGe p-HFET (flat Ge 20%) fabricated in sapphiretechnology at 300 and 85 K.

SiGeC p-HFETs 257

Table 7.3. Summary of room temperature electrical parameters of SiGe HFETsand Si MOSFETs on SOS. (After Mathew S J et al 1999 IEEE Electron DeviceLett. 20 173–5.)

Device Flat Graded Flat Siparameters Ge 20% Ge 20% Ge 15%

VT (V) −0.77 −0.80 −0.82 −0.97sub-VT slope (mV dec−1) 82.8 80.8 80.6 93.4

µeff (cm2 V−1 s−1) 201 177 192 130

Leff µm 1.30 1.25 1.25 1.04

Peak fTL2eff (GHz) µm2 7.8 7.0 7.4 5.0

Hooge constant (×10−6)at VGS − VT = −1 V 94 81 129 294

Figure 7.18. Comparison of measured linear transconductance versus 2Dsimulation using TMA–MEDICI of the flat Ge 20% p-HFET at 300 and 85 K.(After Mathew S J et al 1999 IEEE Electron Device Lett. 20 173–5.)

7.4. SIGEC P-HFETS

Since the increase in the Ge content leads to a larger strain and reducedthermal stability in the pseudomorphic SiGe films, limitations exist inthe application of the binary SiGe alloys. By incorporating smaller-sized C atoms substitutionally to form Si1−x−yGexCy, the strain canbe compensated, extending the Si-based heterostructures to allow more


Figure 7.19. Room temperature IDS–VGS for epitaxial Si, Si0.8Ge0.2 SiGe andSi0.793Ge0.2C0.007 SiGeC p-HFETs for linear and saturation values of VDS for10× 10 µm devices. Inset shows IDS versus VDS for increasing values of VGS–VT.The curves have been normalized for oxide thickness variations between thesamples. (After John S et al 1999 Appl. Phys. Lett. 74 847–9.)

flexible device design [31, 32]. The ternary alloys are promising for p-channel HFETs, since the addition of C increases the stability of thematerial and reduces the amount of process-induced strain relaxation[33,34].

Figure 7.19 shows the normalized room temperature characteristics of10 µm gate length Si0.8Ge0.2, Si0.793Ge0.2C0.007, and control Si transistorswith the same doping. The respective subthreshold slopes are 101, 90 and75 mV dec−1 for Si0.8Ge0.2, Si0.793Ge0.2C0.007 and control Si devices. Alldevices exhibit good saturation and turn-off characteristics. However, theSi0.793Ge0.2C0.007 transistor exhibits a higher drive current at the sameeffective gate voltage, as shown in the inset.

In figure 7.20, the field-effect mobilities for Si0.8Ge0.2, Si0.793Ge0.2C0.007epitaxial Si and lightly-doped bulk Czochralski–Si (CZ–Si) p-MOS are plot-ted at room and liquid nitrogen temperatures. The peak mobility at 300 Kis enhanced to 190 cm2 V−1 s−1 for Si0.793Ge0.2C0.007 in comparison to140 cm2 V−1 s−1 for the Si0.8Ge0.2 devices. The ternary alloy sample

Devices using poly-SiGe 259

Figure 7.20. Linear field-effect mobility (µFE) for 1.3 × 1015 cm−3 dopedbulk-Si, 2.3 × 1017 cm−3 doped epitaxial Si/Si0.8Ge0.2 and Si0.793Ge0.2C0.007SiGeC p-HFETs as a function of VGS–VT for 10 × 10 µm devices at roomtemperature and 77 K. (After John S et al 1999 Appl. Phys. Lett. 74 847–9.)

shows the highest peak mobility, whereas the mobility for the Si0.8Ge0.2devices is only slightly higher than that of epitaxial Si and lower than thatof a bulk doped CZ–Si device. It is known that the in-plane hole mobilityin compressively strained Si1−xGex is enhanced due to the lifting of valenceband degeneracy and modification of the band structure.

Although performance enhancement has been demonstrated inpartially strain-compensated Si1−x−yGexCy channel p-HFETs overSi1−xGex channels as a result of less process-induced relaxation in theSi1−x−yGexCy layer, complete strain compensation of the SiGe layers,however, degrades the performance of p-HFET devices. The incorporationof a controlled amount of C can provide a wider process window for devicefabrication.

7.5. DEVICES USING POLY-SIGE

In bipolar transistors, SiGe is used to form a narrow bandgap baseregion, while in a field-effect device it has been used as a channelmaterial. Polycrystalline silicon (polySi) finds wide applications in all


types of silicon integrated circuit technology. Poly-Si1−xGex is a promisingalternative to polySi as a gate material due to its process compatibilityand favourable electrical properties, such as lower sheet resistance, higherdopant activation rate and tunable work function [35, 36]. Whileconsiderable research has been carried out on epitaxial SiGe, relativelyless work has been done on polycrystalline SiGe (poly-SiGe) and evenless on other group IV polycrystalline materials. Potential applicationsof polycrystalline SiGe or SiGeC include:

• CMOS—tuning of the work function by 200–300 meV towards midgapand reduced gate depletion due to enhanced dopant activation at lowtemperature;

• TFTs—higher mobility and lower thermal budget processing thanamorphous or polycrystalline silicon;

• BiCMOS—lower thermal budget polysilicon emitters and increasedgain in wide bandgap polycrystalline SiGeC or SiC emitters;

• resistors—tuning of temperature coefficient of resistance inpolycrystalline SiGe or SiGeC resistors.

7.5.1. Poly-SiGe gate MOSFETs

Poly-Si0:75Ge0:25-gated p-MOS transistors with a very thin gate oxidehave been fabricated. In addition to reduced gate-depletion effect (GDE)and reduced boron penetration, an enhancement in performance has beenreported [37]. As a p+-poly-SiGe film has a tunable work function; thecarrier mobility which is affected by the vertical electric field differs fromthat in the device with a conventional polySi gate [38]. Due its superior holemobility and smaller work function, which leads to a lower effective fieldin the inversion layer, an improved current drive is obtained for poly-SiGe.The output characteristics for both p+-polySi and poly-SiGe gate deviceswith various gate biases are shown in figure 7.21. For each gate voltage,the drain current of the poly-SiGe gated device is higher than that of thepolySi gated device. Given its compatibility with current VLSI fabricationprocesses, incorporating SiGe into existing CMOS processing should berelatively easy and should lead to higher performance of MOSFET devices[37]. The gate tunnelling currents (hole and electron) in p+-polySi andpoly-SiGe gated p-MOS transistors with ultrathin gate oxides of 25 and29 A have been measured by employing the charge-separation measurementtechniques [39]. The authors have concluded that the hole direct tunnellingis the dominant gate leakage mechanism under normal operating conditionsfor p+-polySi gated p-MOS devices with very thin gate oxide.

Devices using poly-SiGe 261

Figure 7.21. IDS–VDS characteristics for both p+-polySi and poly-SiGe gateddevices with various gate biases. For the same VDS and VGS, the drain current ofthe poly-SiGe gated device is always higher than that of the polySi gated device.(After Lee W-C et al 1999 IEEE Electron Device Lett. 20 232–4.)

7.5.2. Poly-SiGe thin-film transistors

Thin-film transistors (TFTs) find wide applications in active matrix liquidcrystal displays (AMLCD) and static memory (SRAM) and there has beengreat interest in the possibility of developing a low-cost, glass-compatiblepolycrystalline TFT process, which will enable a high-performance flatpanel displays with integrated drivers. SiGe is of great promise forachieving this goal, due to its lower processing temperature and thermalbudget requirements [40,41].

TFT processes have several characteristics which make them differentfrom the standard Si process. For a glass-compatible technology, allprocessing is done at or below 600 C, and deposited gate dielectrics isused. Active layers are also deposited, usually by LPCVD or PECVD.The deposition conditions of the active layer and the related processparameters greatly affect the device performance, as does the quality of thegate dielectrics, which is generally inferior in quality to thermally oxidizeddielectrics.

To enable the rapid optimization of SiGe TFTs for AMLCDapplications, a response surface characterization of the SiGe depositionsystem has been performed [42]. Controlled nucleation and grain growthhave enabled the fabrication of large-grain high-performance TFTs. Ge hasbeen deposited selectively through an oxide mask onto the source/drain


regions. The film is then crystallized at low temperature. The Ge and Sireact to form SiGe at the interface, which crystallizes first, and then growsout laterally, resulting in spatially specified large-grain polysilicon. Thisprocess is called germanium-seeded lateral crystallization. The fabricatedpoly-SiGe TFTs have shown much higher mobility than comparable polySiTFTs, as indicated in figure 7.21. A comparison of transfer characteristicsof n-MOS and p-MOS TFTS at low and high drain voltages is shown infigure 7.22.

Figure 7.22. Comparison of poly-SiGe TFT transfer characteristics. (AfterSubramanian V and Saraswat K C 1998 IEEE Trans. Electron Devices 451690–5.)

Vertical FETs 263

7.6. VERTICAL FETS

With increasing chip size, the delay introduced by metal linesinterconnecting the various parts of a chip is rapidly becoming a limitingfactor for speed and performance. A solution to this problem is areduction in chip size, which can be accomplished through the use ofvertical integration of active devices. MOSFET channel lengths are beingcontinuously scaled down to improve performance and packing density.Extrapolating the critical device dimensions for silicon ICs to the future,it is anticipated that MOS transistors with gate lengths of about 70 nmwill be required to realize the 64 GB DRAM around the year 2010 [43].However, in the vertical transistor technology, channel length scaling is notlimited by the minimum lithographic resolution. It has been shown thatthe package density of the vertical transistor is doubled [44].

7.6.1. Vertical SiGe HFETs

The advances in the growth of device quality SiGe epitaxial layers on silicon,combined with the higher values of hole mobility, have led to an increasedinterest in heterojunction vertical FETs [45, 46]. In the design of thevertical heterojunction p-MOSFET, the SiGe layer and, more specifically,

Figure 7.23. Schematic diagram of vertical heterostructure field-effecttransistor. (After Collaert N and De Meyer K 1999 IEEE Trans. Electron Devices46 933–9.)


the gate influence on the effective barrier height seen by the carriers playan important role in the device operation. It consists of a source layer,a graded SiGe source layer, a lightly-doped SiGe source layer, an n-typedoped channel region and finally a p-type doped drain layer (as shown infigure 7.23). The gate dielectrics consists of an oxide grown on the verticalsidewalls and the gate electrode is an in situ doped p-type polysilicon layer.

The basic principle of operation of this novel device is: in the on-state, the barrier is decreased by using the gate action on the lightly-dopedsource layer. In the case of a p-channel device, a strained-SiGe layer ontop of an Si substrate is used to create a barrier for the holes [21]. For then-channel devices, the barrier for the electrons will be formed by a strained-Si source layer on top of a SiGe buffer layer, leading to a band alignmentof type II [21]. In that case, SiGe will also be used for the channel anddrain layers. Using the Si/SiGe layer stack for both p- and n-MOSFETs,it is possible to include source engineering in the vertical transistor design.This is an important improvement to vertical Si-only devices, which lack thepossibility of channel engineering that has pushed their planar counterpartstoward the deep submicron regime. Vertical MOSFETs suffer from drain-induced barrier lowering (DIBL), causing reduction threshold voltage roll-off and an increase in subthreshold slope. By using ultrathin pillars (width100 nm), the channel region can be fully depleted by surrounding gates,resulting in an improved subthreshold slope and a suppression of short-channel effects [47, 48]. To reduce the DIBL effect, a material-dependentbarrier between source and channel may also be introduced [45,49].

Enhanced in-plane hole mobility in strained-SiGe alloys, compared tobulk-Si has been employed for the fabrication of planar SiGe-channel p-HFETs [5,14,50]. The enhancement of hole mobility in a direction normalto the growth plane of the strained-Si1−xGex and graded SiGe channel hasalso been found to be effective in the enhancement of the drive currentin implanted-channel MOSFETs. As the vertical structures combine themerits of a very short channel and enhanced hole mobility in strained-SiGelayers, the results are very promising in terms of the possibilities offeredby the SiGe technology. Indeed, a deep submicron vertical SiGe-channelp-HFET using strained-Si1−xGex grown using solid phase epitaxy and thestandard CMOS process has been reported [46].

The scaling of vertical p-MOSFETs with the source and drain dopedwith boron during low-temperature epitaxy is limited by the diffusionof boron during subsequent side wall gate oxidation. By introducingSiGeC diffusion barrier layers, boron diffusion from source and drain intothe channel region has been suppressed during the gate oxidation. Thecharacteristics of scaled vertical p-MOSFETs down to 25 nm in channellength [51] are shown in figure 7.24. These devices suffer from the onset ofpunch-through, but the gate can still control the drain current in the linearregion.

Noise in p-HFETs 265

Figure 7.24. (a) Output I–V and (b) subthreshold drain current versus gatevoltage for devices with L = 25 nm with a gate oxide thickness of 10 nm. (AfterYang M et al 1999 IEEE Electron Device Lett. 20 301–3.)

An analytical model for the threshold voltage of the p-SiGechannel vertical MOSFET has demonstrated its unique characteristicsin suppressing DIBL in sub-100 nm channel length devices [45]. Thedependence of the threshold voltage on Ge concentration, channel length,channel doping and SiGe source doping was evaluated. It was shown thatwith the introduction of a material-dependent barrier between source andchannel, roll-off in threshold voltage can be substantially reduced.

7.7. NOISE IN P-HFETS

Low-frequency noise is important in RF and microwave circuit applications,because it is upconverted to phase noise and thus sets a fundamental limiton the spectral purity of high-speed communication systems. Althoughmuch work has been done on noise in MOSFETs [52], little attention has


Figure 7.25. Spectral density of the input-referred gate voltage noise for theflat Ge 20% and the Si p-MOSFET in saturation. (After Mathew S J et al 1999IEEE Electron Device Lett. 20 173–5.)

been given to the noise properties of SiGe p-HFETs [29, 53]. The noisein MOSFETs is generally related to the fluctuations in the inversion layercarrier density due to traps located at the Si–SiO2 interface. SiGe p-HFETsare bandgap-engineered such that the holes confined to the SiGe channelare physically separated from the Si–oxide interface by an Si-cap layer.Intuitively, one would expect lower noise in SiGe p-HFETs because of sucha physical separation. However, an examination of the trapping-based noisetheory [54] shows that this separation changes only the frequency range overwhich the noise shows a dependence, but not the magnitude of the noise.

Figure 7.25 shows the input referred gate voltage noise for Si/SiGep-HFETs on SOS and bulk-Si. It is observed that all SiGe p-HFETsconsistently show a lower noise than Si p-MOSFETs at all gate biases.The SiGe p-HFETs show a 70% lower noise than the Si p-MOSFETs, dueto the enlarged separation between the hole quasi-Fermi level and valenceband edge, which results in the sampling of a lower density of traps. Thus,the SiGe p-HFETs should have an intrinsic advantage in microwave circuitapplications.

Collaert et al [55] have measured the low-frequency noisecharacteristics for several vertical SiGe-channel HFETs. Figures 7.26(a)–7.26(d) show the noise spectra measured between 3 Hz and 100 KHz fordevices with source top and drain top configurations at constant draincurrent. As can be seen from the figures, the source top configurationexhibits a dominant generation–recombination (g–r) noise behaviour whilethe drain top measurements show 1/fγ-type noise behaviour with γbetween 0.9 and 1.5.

Summary 267

Figure 7.26. Low-frequency noise characteristics for (a) an Si0.90Ge0.10 device;(b) an Si0.80Ge0.20 device, Nsub = 5× 1017 cm−3; (c) an Si0.90Ge0.10 device; and(d) a bulk-Si device, Nsub = 1 × 1018 cm−3. (After Collaert N et al 1999 Proc.ESSDERC pp 308–11.)

7.8. SUMMARY

In this chapter, the electrical operation and modelling of the SiGe p-HFET are presented to provide the device designer with guidelines as toepitaxial layer structure and placement. A range of parameter space hasbeen explored using device simulation to determine the charge distributionwithin the device under various gate bias conditions.

The key design issues for SiGe HFETs have been addressed in detail.The selection of the gate material plays a dominant role, especially fordesigns with threshold voltages in the range of −0.6 V where the use ofn+-polySi is preferable over p+-polySi. With a graded Ge profile, a higher


valence band discontinuity can be obtained at the top of the SiGe channelleading to an increase in transconductance for a given integrated Ge dose.It has been shown that for maximum utilization of the strained-Si1−xGexquantum well, the p-HFET should have the following characteristics:

(i) a thin Si-cap layer,;(ii) a high Ge mole fraction for a large 2DHG population in the quantum

well;(iii) an n+-polySi gate to promote buried channel operation for low-

voltage applications; and(iv) a p+-δ-doping below the SiGe channel to enhance subthreshold

properties of the device.

A number of possibilities have been shown to enhance performanceof SiGe HFETs. From a design point of view, the SiGe p-HFET onan insulating substrate offers better hole confinement in the quantumwell. The incorporation of a controlled amount of carbon in a partiallystrain-compensated SiGeC channel p-HFET can provide a wider processwindow. A vertical SiGe HFET offers higher packing density, lower DIBLand substrate bias effect, more flexible channel engineering and a simplerfabrication process.

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Chapter 8

METALLIZATION ANDHETEROSTRUCTURE SCHOTTKYDIODES

Semiconductor–semiconductor and metal–semiconductor interfaces playa crucial role in modern electronic and optoelectronic devices.SiGe heterostructure materials and devices are expected to play animportant role due to their compatibility with Si-processing technology.Microelectronic circuit fabrication requires metallization and the study ofthe metal/SiGe interface is therefore very important. For applicationsof poly-SiGe as gate material, the interaction of SiGe alloys withnoble/refractory metals should also be investigated, as both refractory andnoble metal-silicides are widely used for ohmic contacts, Schottky barrierdiodes, diffusion barriers, low resistivity gates and interconnects.

As new devices and structures are being contemplated using group IValloy films, a good control of the metal/semiconductor interface, low orhigh barriers, are required to improve the device performance. There aretwo types of metal–semiconductor contacts, one is ohmic and the other isSchottky. Schottky contacts are needed for rectification of electrical signals,mixing of microwave signals and optical detection. Silicide/Si1−xGexSchottky diodes have also been proposed for detection of far-infraredradiation, which will be discussed in chapter 9. In table 8.1, importantmaterial properties of commonly used metals for microelectronic devicefabrication are presented.

During the last few years, several research groups have studied theelectrical properties and chemical phase formation of metal/group IV alloylayers. Two approaches to the formation of ohmic contacts with SiGeand other alloy layers have been proposed [1]. The first approach involvesadding Ge and Si to a thin Al film to avoid known substrate dissolutionand spiking problems. An Al film (3000 A) is deposited over the strainedlayer, followed by the deposition of thin layers of Si (20 A) and Ge (60 A).

272

Metallization and heterostructure Schottky diodes 273

Table 8.1. Material properties of metals commonly used in microelectronicapplications.

Property Al Au Pt Ni Cr

Molecular weight (amu) 26.98 196.96 195.09 58.69 52.02

Density (g cm−3) 2.699 19.288 21.452 8.903 7.19

Melting point (C) 659.4 1062.2 1768 1454 1875

Oxidation potential (V) 1.66 does notoxidize

does notoxidize

0.25 does notoxidize

Work functionat vacuum (eV) 4.25 5.1 5.7 5.1 4.5

Schottky barrierto n-Si (eV) 0.69 0.79 0.9 0.61 0.61

Schottky barrierto p-Si (eV) 0.38 0.25 0.51 0.50

Schottky barrierto n-Ge (eV) 0.48 0.59 0.49

Schottky barrierto p-Ge (eV) 0.3

A 350 C anneal for 1 h was used to alloy the capping Si and Ge layersinto the Al. Contact resistivity measurements between room temperatureand 400 C demonstrated the stability of the contacts. However, the roomtemperature contact resistivity of 0.01 Ω cm−2 was considered too high fordevice applications.

The second approach to contact formation involved deposition of alayer of Pd:Si (3:1, 600 A) on the SiGe, followed by a layer of pure Ge(1000 A). The contacts were annealed for 1 h at 350 C. During annealingthe Pd3Si phase was formed. Concurrently, the surface Ge layer diffusedthrough the silicide and grew epitaxially on the underlying SiGe layer.Contact resistances for these films were typically 5×10−4 Ω cm−2 at roomtemperature.

Liou et al [2] reported the interfacial reactions of Pt and Pd withepitaxial Si1−xGex alloys and the effects of these reactions on Schottkybarrier height. They reported that the barrier heights of Pd and Pton n-Si0.8Ge0.2 were the same, about 0.68 eV, and were not modifiedsignificantly when annealed at a temperature below 550 C. This value isclose to that previously reported by Buxbaum et al [3] for Pd on n-Si1−xGexfilms.

Kanaya et al [4] reported the Schottky barrier height of Pd(Pt)/p-SiGecontacts for infrared detection. It was shown that the barrier height

274 Metallization and heterostructure Schottky diodes

decreased with increasing Ge concentration, and that the barrier heightof a relaxed film was higher than that of a strained-Si1−xGex film. Hongand Mayer [5] studied the Pt/Si1−xGex system and found a similarbehaviour except for the formation of germanide. Thompson et al [6]studied the Ni/Si1−xGex interfacial reaction and found that Ni was thedominant diffusion species below 400 C and that layers of Ni2(Si1−xGex),Ni(Si1−xGex) and NiSi formed in sequence. Above 400 C, homogenizationbetween NiSi and Ni(Si1−xGex) occurs due to interdiffusion of Si and Ge.

Aubry et al [7] studied the Si1−xGex/W metal–semiconductorSchottky junction rather than a silicide junction. The authors reportedthe effects of composition and thickness on the Schottky barrier height ofW/p-Si1−xGex relaxed films and showed that the barrier height decreasedwith the increasing Ge fraction and followed the rate of strain relaxation.Thomas et al [8] investigated the Ti/Si1−xGex contacts with contactresistance measurements and reported that Si and Ge were the dominantmoving species during the reaction. The resistance of contacts was stableand low due to the formation of TiSi2, Ti(Si1−xGex)2 and TiGe2 afterannealing at 650 C for 1 h.

The above studies revealed that during the metal–Si1−xGex reaction,Pd and Pt preferentially react with Si, resulting in Ge segregation [2, 9].These create defects that pin the Fermi level near the midgap leading toa high Schottky barrier height [2]. To avoid Ge segregation, a siliconsacrificial layer was used on top of the SiGe film [10]. The importantapplications of silicide junctions are in IR detectors and will be discussedin chapter 9.

In this chapter, the formation and characterization of silicides (usingPt, Pd and Ti on SiGe, SiGeC, Si and strained-Si) using various analyticaltools, such as x-ray diffraction (XRD), Rutherford backscattering (RBS)and Auger electron spectroscopy, will be discussed. We describe Schottkybarrier diodes (SBDs) using Ti, Pt and Pd on p-type SiGe, SiGeC, strained-Si films and Si. Experimental results on barrier heights, the ideality factorand energy distribution of the interface state density for various diodesand simulation results using SEMICAD [11] on forward current–voltagecharacteristics of Schottky diodes are presented.

8.1. DEPOSITION OF METAL FILMS

One of the various techniques used for metal thin-film deposition isultrahigh vacuum (UHV) electron beam deposition. The schematicdiagram of an electron beam evaporation system used for deposition ofmetals is shown in figure 8.1. The deposition system consists of a singleelectron gun (typically 2 kW) and several crucibles, capable of evaporatingdifferent materials sequentially. A base pressure of about 1× 10−11 Torr isachieved in the chamber with the help of three kinds of vacuum pumps, e.g.,

Deposition of metal films 275

Figure 8.1. Schematic diagram of an e-beam evaporation system.

vac-sorb, ion and titanium sublimation pumps. As there are no oil-basedvacuum pumps (rotary and diffusion) in the system, the UHV e-beam isfree from hydrocarbon contaminations.

The vacuum chamber consists of a rotating substrate holder, a crystalmonitor for monitoring the deposition rate and thickness of the film, aquartz-lamp radiation heater with a heating control unit to maintain thesubstrate temperature up to 300 C and an ion gauge to monitor thepressure. The whole system is separated into upper and lower chambersby an isolation valve. The lower chamber houses a series of ion pumps anda liquid nitrogen cryo panel and is maintained at a vacuum of 10−6 Torror greater by continuous operation of the ion pumps.

In a typical deposition process, the upper chamber was vented bypassing liquid nitrogen, followed by loading of the pre-cleaned substratesin the chamber. A sufficient amount of high-purity source materials inthe form of small pellets was put into the crucibles and the electrongun filament was aligned to it. Initial evacuation of the chamber wascarried out by vac-sorb pumps from atmospheric pressure to a minimum


pressure of 10 mTorr. Finally, pumping to a pressure of 10−9 Torr wasachieved by the combination of sputter ion and titanium sublimationpumps. After attaining the desired base vacuum, deposition was initiatedby evaporating metal by applying power to the electron gun (e-gun) from itscontrol unit. The evaporation rate was controlled by changing the filamentcurrent in the e-gun. Thin films of Ti, Pt and Pd of required thicknesseswere deposited on strained-Si1−xGex, partially strained compensatedSi1−x−yGexCy, strained-Si and Si at the desired pressure level.

8.2. FABRICATION OF SCHOTTKY DIODES

In the fabrication of Schottky diodes, surface preparation for metaldeposition is very important. In most cases, the departure of the idealityfactor of the diodes from unity is due to the presence of an interfacial layerbetween the metal and the semiconductor [12, 13]. Another reason maybe the existence of a laterally varying potential barrier height, caused bya nonuniform interface of the heterostructures [14]. The nonidealities aremostly due to the states associated with the defects near the surface of thesemiconductor. These defects act as recombination centres giving rise toexcess current which causes deviation from the ideal thermionic emissionbehaviour at low voltage and low temperature. The growth temperaturesof strained-Si1−xGex and partially strain-compensated Si1−x−yGexCysamples are typically around 600 C. In order to avoid strain relaxation, thesilicidation temperature should not exceed the film growth temperature.

8.3. SILICIDATION OF GROUP IV ALLOY FILMS

More than half of the elements in the periodic table react with silicon toform one or more intermetallic compounds (silicides). In Si technology,uniform and stable contacts are achieved by reacting metal films with Siuntil the most Si-rich silicides are formed. These silicides not only offer achoice in electrical barrier heights but also serve as protective layers againstoxidation. Al is commonly used as the ohmic contact metal in Si technology.The solid solubility of Si at 525 C is 1.5% and Si molecules from thesubstrate dissolve into Al to satisfy its solubility. Though Al and Al–Sihave been successfully used in Si devices, they do not make good contacts togroup IV alloy films. The choice of metals for ohmic contacts should satisfyseveral requirements. Firstly, the composition of the unreacted alloys mustremain unchanged after contact reactions. Secondly, a single compound,not a mixture of compounds (e.g., silicides and germanides), should be incontact with the alloy films. Thirdly, the consumption of alloy films duringthe reaction must be small since the thicknesses of the strained layers arelimited by the critical thickness.

Silicidation of group IV alloy films 277

The metallization of SiGe and other group IV alloys is complicatedcompared to that of bulk-Si. In a metal–SiGe reaction, metals reactpreferentially with one component of the alloy, leading to a compositionalchange in the unreacted alloy. The compositional change results from theformation of a ternary compound within a narrow range of homogeneity.Ternary metal–SiGe phase diagrams are also required to predict the finalphases of metal/SiGeC ternary reactions.

In a ternary reaction, the identity of moving species is very importantin determining the elemental distribution. For example, in a refractory–noble metal alloy, a reaction (with Si) produces a noble metal silicide innerlayer and a mixture of noble and refractory silicide outer layer. However, nolayered phase separation has been observed in refractory–refractory metalalloy/Si reactions. This has been attributed to the different moving speciesinvolved in the reactions. Noble metals are known to be highly mobilein silicides at low temperature, while Si is the dominant moving speciesduring reactions with refractory metals. Therefore, in a refractory–noblemetal/Si reaction, the noble metal moves first to react with Si leavingbehind a metallic alloy enriched with the refractory component. At hightemperature, Si atoms from the substrate move to react with the metallicalloy to form a mixture of silicides. On the other hand, layered phaseseparation is absent in the refractory–refractory/Si reactions since Si is theonly moving species in the entire temperature range. In the light of theabove arguments, the composition of SiGe alloys would remain unchangedif a mobile species was chosen as the contact material or the transport ofGe and Si is similar during the reaction with the refractory metal.

It has been reported from the kinetic studies of Ti/SiGe systems thatSi and Ge are the dominant moving species during thermal reactions.Resistance of the resulting silicide formed at about 650 C is stable and lowdue to the formation of C54 of TiSi2, along with the Ti(SiGe)2 and TiGe2phases [8]. Strain relaxation has also been observed during the thermalreaction between Ti and Si1−x−yGexCy [15]. Carbon is found to inhibitthe strain relaxation process as well as to delay the formation of the C54phase of TiSi2. Upon complete silicidation, a decrease of Ge concentrationin silicide–germanide/epilayer and an accumulation of C atoms at theinterface have been found. To avoid such complexities associated withthe thermal reactions between metal and group IV alloy films, the use ofa thin Si sacrificial layer on top of the strained SiGe or SiGeC layer iscommon [10].

For Schottky contacts, the general requirement is to adjust the junctionparameters, such as barrier height and ideality factor, and to control theirreproducibility and stability. Thermal annealing influences the interfaceand pinning position of the Fermi level which in turn affects the barrierheight of the Schottky junctions [16]. For the Ti–Si system, the Fermilevel pins at the midgap region. But incorporation of Ge in Si changes


the pinning position of the Fermi level [7]. In Si, reproducible rectifyingand low resistance ohmic contacts can be achieved by choosing appropriatetransition metals with various Schottky barrier heights and by doping thesemiconductor with the desired level. Transition metals react with Siat low temperature so that no liquid phase forms. As a result, uniformsilicide layers with reproducible compositions at the silicide/Si interfaceare formed. The electrical properties of Schottky junctions require theunderstanding of chemical reactions at the metal–semiconductor interface.In the following, we discuss the formation and characterization of silicidesof various group IV alloy films with Ti, Pt and Pd.

8.4. SILICIDATION WITH TITANIUM

Refractory metal silicides, such as TiSi2, WSi2, TaSi2 and MoSi2,have attracted much attention in microelectronic devices due to theirlow resistivity and high-temperature stability, which are required forVLSI/ULSI interconnects. Among various refractory metal silicides, TiSi2possesses the lowest resistivity (∼12.4 µΩ cm−1) [17], high-temperaturestability and excellent compatibility with Si-processing technology, and iswidely used for submicron CMOS contacts.

Titanium disilicide (TiSi2) is a polymorphic material which is formedby thin-film reactions between Ti and 〈100〉 Si, polySi or amorphous silicon.TiSi2 has two different structures: the base-centred orthorhombic C49structure which forms in the temperature range 450–650 C and the face-centred orthorhombic C54 structure which forms above 650 C. The C49TiSi2 is a metastable phase [18] while C54 is the stable phase with lowerresistivity than the C49 phase. But the transformation of C49 TiSi2 to C54TiSi2 is dependent on the doping level and the thicknesses of the film [19].Both the crystal structures exhibit similar arrangements of atoms in theatomic planes with a hexagonal array of Si atoms around the centre, butthe unit cell of each phase shows a different stacking arrangement. TheC54 phase exhibits lower Schottky barrier heights on both p- and n-typesilicon as compared to the C49 phase [20].

The reaction mechanism for the formation of C54 TiSi2 is as follows.First, the Ti layer reacts with crystalline silicon producing an amorphousTiSix phase at a temperature ranging from 400–500 C. With furtherheating, the amorphous phase, together with the silicon and Ti, formsC49 TiSi2 between 500–700 C which eventually transforms into C54 at atemperature above 700 C [21]. The determination of the chemical phaseformation during annealing requires in situ characterization tools, whilethe final phase formation is generally studied ex situ using XPS.

Silicidation with titanium 279

8.4.1. Rutherford backscattering characterization

Rutherford backscattering (RBS) analysis is carried out to estimate thecomposition and thickness of the deposited films. The advantages of RBSare the following:

(i) speed;(ii) ability to perceive depth distribution of atomic species below the

surface;(iii) the quantitative nature of the results and the technique is

nondestructive.

The 1–2 MeV He+2 beam is normally used for RBS and channellingmeasurements.

The random incident backscattering spectra of Ti on Si samplesannealed at 600 C for 20 min is shown in figure 8.2 with a 2.551 MeV

Figure 8.2. The 2.551 MeV 4He++ backscattering spectra of the TiSi/Si sampleannealed at 600 C for 20 min: (· · · · · ·) experimental and (——) simulation.


Figure 8.3. The 2.551 MeV 4He++ backscattering spectra of theTiSi/Si0.81Ge0.19 sample annealed at 600 C for 20 min: (· · · · · ·) experimentaland (——) simulation.

4He+2 ion beam. The scattered He+2 from the TiSi2 layer appears athigher energies (channel nos 576–541) while those from the Si substrateappear at lower energies (channel nos 445–100). Computer simulation ofthe backscattered spectra (using the GISA-3.95 program) is usually doneto obtain the thickness and composition of different layers.

Figure 8.3 shows the RBS spectrum for a Ti/SiGe sample annealedat 600 C. It is evident from figure 8.3 that the scattered He+2 from Geappears at a higher energy (channel nos 643–591) and the scattered atomsfrom Ti and Si appear at relatively lower energies (channel nos 576–543and 445–200, respectively). From the simulation, it is found that the totalTi signal is contributed partly from the TiSi layer and a part from theunreacted Ti. Similarly, the Si fraction is contributed partly from theTiSi layer and partly from the SiGe epitaxial layer as well as from the Sisubstrate.


Figure 8.4. The 2.551 MeV 4He++ backscattering spectra of theTiSi/Si0.79Ge0.20C0.01 sample (with Si-cap) annealed at 600 C for 20 min:(· · · · · ·) experimental and (——) simulation.

RBS spectra of Ti–Si–Si0.79Ge0.20C0.01 and Ti–Si0.79Ge0.20C0.01samples (annealed at 600 C for 30 min) are shown in figures 8.4 and8.5, respectively. From the simulation, it is found that the Ti peak iscontributed by the unreacted Ti and the TiSi layer. Similarly, the Si edgecomes from both the TiSi layer and Si1−x−yGexCy (x = 0.2, y = 0.01)epitaxial layer and also from the Si substrate. For all silicide samples,the Ge peak occurs at a higher energy compared to those of Ti and Si.Generally, the Ge peak occurs in the channel region of 645–600 and the Tipeak occurs in the channel range of 576–550 while Si shows a peak aroundthe channel no 445 and below.


Figure 8.5. The 2.551 MeV 4He++ backscattering spectra of theTiSi/Si0.79Ge0.20C0.01 sample (without Si-cap) annealed at 600 C for 20 min:(· · · · · ·) experimental and (——) simulation.

8.4.2. Auger electron spectroscopy characterization

In Auger electron spectroscopy (AES), a focused beam of electrons in theenergy range 2–20 keV irradiates the sample. Atoms up to a depth of1 µm are ionized in an inner core level, e.g., the K level, and subsequentlyde-excited by an electron falling from a higher level L1, with the balanceenergy removing a third electron from level L3. The electron emitted withan energy EA is given by

EA = EK(Z) − EL1(Z) − EL2(Z +∆) − ξ (8.1)

where Z is the atomic number of the atom and ξ is the work functionof the surface. The third term on the right-hand side of equation (8.1)has an extra component ∆ which is included to take account of the fact


that the atom is in a charged state when the final electron is ejected.Experimentally, ∆ is found to have a value between 1

2 and 32 .

In sputter depth profiling analysis of thin films, an ion beam is usedto etch the surface at rates up to 2 µm h−1. For AES depth profiles, theelectron beam is placed in the middle of the ion beam crater and, if thesystem alignment is suitable, the crater size may be limited to 100 µm orless. If a monoenergetic argon ion of current density Ji is used to sputtera target with a sputtering yield of S atoms per ion, the rate of removal isgiven by

dzdt

=JiSM

qρNAna(8.2)

where M is molecular weight of the material with na atoms per molecule,q is electronic charge, ρ is density and NA is Avogadro’s number. In theabove equation, dz/dt is the sputter rate. Thus, for a given material, theremoval rate may be determined if Ji and S are known.

Figure 8.6 shows typical AES depth profiles for Ti, Si and Ge of theTi/Si/Si1−xGex sample having a Ti thickness of 700 A annealed at 600 Cfor 20 min. The spot size of the beam was 0.5 µm and the etch rate forprofiling was 5 A min−1. As seen from the depth profile, about 600 A of Tiremains unreacted and only 100 A of Ti takes part in silicide formation. It isclear from the profile that TiSi formation is observed up to a depth of about100 A below the interface. An accumulation of Ge atoms is also observedbelow the interfacial region. It is desirable to consume the sacrificial Si-caplayer completely by Ti to obtain a pure TiSi/Si1−xGex interface.

Figure 8.6. AES depth profiles of Ti, Si and Ge for the TiSi/Si0.81Ge0.19 sampleannealed at 600 C for 20 min.


8.4.3. Sheet resistivity

The effects of the alloy composition on the annealing temperature andthe electrical resistivities of C54 titanium germano–silicide formed duringthe Ti/Si1−xGex (x = 0.0, 0.3, 0.4, 0.7, 1) solid-state reaction have beeninvestigated [22]. The resistivities of C54 Ti(Si1−xGex)2 were measured tobe in the range of 15–20 µΩ cm−1. The electrical resistivities of alloysare influenced by the difference of atomic size, atomic disorder, strainand band structure effects. From electrical measurement, the instabilityof titanium germano–silicide is manifested by the increase in the resistancewith the annealing temperature. The increase has been attributed to boththe segregation of Si1−xGex and the agglomeration and spheroidizationof the germanide and germano–silicide and are correlated with the phasetransformation. The sheet resistances fell drastically (see figure 8.7) at 600,650, 650 and 700 C in the annealed Ti/Ge, Ti/Si0.3Ge0.7, Ti/Si0.6Ge0.4and Ti/Si0.7Ge0.3 samples, respectively. The lowest electrical resistivitieswhich appeared for smooth thin films of C54 Ti(Si1−xGex)2 were foundto be 20, 20, 17 and 15 µΩ cm−1 for the 800 C annealed Ti/Si0.7Ge0.3,Ti/Si0.6Ge0.4, Ti/Si0.3Ge0.7 and Ti/Ge samples, respectively. The valuesof x were estimated to be 0.19, 0.28, 0.55 and 0.98, respectively, by EDSanalysis, as shown in figure 8.8.

Figure 8.7. Sheet resistance versus annealing temperature curves for theTi/Si1−xGex and Ti/Ge samples. (After Lai J B and Chen L J 1999 J. Appl.Phys. 86 1340–5.)

Silicidation using Pt and Pd 285

Figure 8.8. The lowest electrical resistivity versus concentration of Ge data inTi(Si1−xGex)2. (After Lai J B and Chen L J 1999 J. Appl. Phys. 86 1340–5.)

8.5. SILICIDATION USING PT AND PD

During the metal–Si1−xGex reaction, Pd and Pt react preferentially with Siresulting in Ge segregation. This creates defects which pin the Fermi levelnear the midgap leading to a high Schottky barrier height [2]. Generally,silicidation studies of Pt and Pd with SiGe alloys are carried out in thetemperature range of 300–500 C. It has been reported that Pt or Pd reactswith SiGe alloys to form ternary compounds such as Pt2(Si0.8Ge0.2)1 orPt1(Si0.8Ge0.2)1 at 300 and 400 C for different durations of annealing [23].Thermodynamically, Si is more reactive than Ge with Pt. At 350 C, thereaction between Pt and Si1−xGex consists of interdiffusion of Pt, Si and Gewith Pt as the dominant diffusion species, and while Pt diffuses in some Gediffuse out [2,24]. As Pt atoms reach the silicide/Si1−xGex interface, theyreact preferentially with Si to form silicide, and the Ge atoms which areleft behind diffuse out and pile up at the surface. Experimental evidencesuggests that Pt selectively bonds with Si, the bonding between Pt–Siis stronger than that of Pt–Ge, and the formation of PtSi is favoured.Microscopically it creates a nonuniform interface at the PtSi/Si interfaciallayer [23]. Annealing at a lower temperature shows some fraction of Gesegregation at the silicide–SiGe interface. However, during annealing ata higher temperature, Ge is repelled from the surface layer and forms aGe-rich layer underneath the interface.

Transmission electron microscope (TEM) analyses of low-temperatureannealed Pd-strained Si1−xGex alloys show the formation of hexagonal


Pd2Si or Pd2Ge with a measured plane symmetry of 5.5 A. There is alsoa report of strain relaxation in the underlying Si1−xGex layer due to high-temperature annealing of Pd at about 550 C [25,26]. In these compounds,a decrease in the vertical lattice parameter has been observed. Annealingof Pd–Si1−xGex at about 550 C results in the formation of a double layerstructure: the top layer contains a relatively small amount of Ge and theadjacent Si1−xGex layer is enriched with Ge. Hong et al [5] have studiedPt/SiGe systems and have observed the formation of PtGe2 at annealingtemperatures beyond 450 C.

XRD spectra for the SiGe sample annealed at 400 C for 30 mincontaining 19% Ge and a 50 A Si sacrificial layer are shown in figure 8.9.The resulting silicide peaks are oriented along the (200), (021), (115) and(222) directions. Figure 8.10 shows the XRD pattern of the SiGe samplewith 29% Ge and a 50 A thick cap layer. As seen in figure 8.10, the PtSipeak is oriented in the (200), (222) and (115) directions along with the

Figure 8.9. XRD spectrum for PtSi/Si0.81Ge0.19 film annealed at 400 C for20 min.

Heterostructure Schottky diodes 287

Figure 8.10. XRD spectrum for PtSi/Si0.71Ge0.29 film annealed at 400 C for20 min.

peak arising from the Si(400) plane. It is observed from x-ray analysis thatthere is no evidence of germanide formation.

8.6. HETEROSTRUCTURE SCHOTTKY DIODES

Schottky contacts play an important role in determining the performanceof semiconductor devices required for various electronic and optoelectronicapplications. Barrier heights of Schottky junctions depend strongly onthe chemical phases formed by thermal reactions between the metal andsemiconductor. Details of the chemical phase formation of Ti, Pt and Pdwith group IV alloys have been described earlier. The barrier heights ofmetal/(SiGe, SiGeC or strained-Si) Schottky junctions are predicted to belower than the corresponding metal/Si junctions.


According to the Schottky–Mott model [27], the barrier heightof a p-type Schottky junction depends on the metal work function,semiconductor bandgap and electron affinity of the semiconductor. Inthe drift–diffusion emission model, hole current density across the metal–semiconductor interface is usually given by [27,28]

Jp = qvrp (po − ps) (8.3)

where vrp is the effective hole surface recombination velocity, ps is thedensity of holes near the interface in the semiconductor and po is holedensity that would be there if the potential distribution could remain thesame while the hole quasi-Fermi level came into equilibrium with the metalFermi level. Moreover, due to image force lowering and thermionic fieldemission, which usually occur in a practical Schottky diode, the barrierheight can be modelled using the term [14]

∆φb =√qEmax4πεs

+(34h

2πEmax

)2/3(2qm∗)−1/3 (8.4)

where Emax is the electric field at the metal–semiconductor interface, εs isthe dielectric constant of the semiconductor and m∗ is the effective holemass. In the above expression, the first term corresponds to the imageforce lowering while the second term is responsible for the thermionic fieldemission. Considering these effects, the current in a Schottky barrier diodecan be expressed as

Jp = qvrp (po − ps) exp(q∆φbkT

)(8.5)

and

po = Nv exp(−qφbkT

)(8.6)

where k is the Boltzmann constant and Nv is the effective density of statein the valence band.

Assuming thermionic emission as the main mechanism of current flowacross a Schottky junction, the barrier height can be calculated using therelation

φb =kT

qln(AA∗T 2

I0

)(8.7)

where A∗ is the effective Richardson constant, A is the area of the diodeand I0 is the saturation current. The ideality factor, m, is obtained fromthe relation [28]

m =q

kT

∂v

∂ (ln I)(8.8)

Heterostructure Schottky diodes 289

Figure 8.11. Forward and reverse current–voltage characteristics of aPtSi/Si0.81Ge0.19 Schottky diode at different temperatures.

where ∂v∂(ln I) is the slope of the linear extrapolated part of the current–

voltage characteristics.The barrier height of a Schottky junction can also be determined from

the measured reverse capacitance value. The determination of the Schottkybarrier height by the capacitance–voltage method is based upon the voltagedependence of the charge in depletion region of the diode. Capacitance perunit area of a reverse biased Schottky junction is expressed as [27]

CD =

√qεsNa

2(Vbi − V − kT/q) =εsW

(8.9)

where εs is the dielectric constant of the semiconductor, Na is the acceptorconcentration of the diode, V is the applied reverse bias, Vbi is the built-inpotential and W is the depletion width. It is evident from equation (8.9)that the plot of 1/CD2 versus applied reverse voltage for an ideal Schottky


Figure 8.12. Forward and reverse current–voltage characteristics of aPtSi/Si0.71Ge0.29 Schottky diode at different temperatures.

diode will be a straight line. From the intercept on the voltage axis, thebarrier height is determined from the relation

φb = Vi + ψp +kT

q(8.10)

where Vi is the voltage intercept and ψp is the potential difference betweenthe hole quasi-Fermi level and the top of the valence band, which can becomputed from the doping concentration and is given by

ψp =kT

qln(Nv

Na

). (8.11)

The C–V method measures the electrostatic properties of the Schottkybarrier and is insensitive to transport effects such as tunnelling andimage force lowering. For an inhomogeneous interface, the C–V method

Schottky diodes on strained-Si1−xGex 291

averages over the whole sample area and measures the mean barrierheight. Using the C–V technique, the energy distribution of the interfacestate density at a metal–semiconductor interface has been measured byChattopadhyay et al [29].

8.7. SCHOTTKY DIODES ON STRAINED-SI1−XGEX

The forward and reverse logarithmic current–voltage characteristics atdifferent temperatures of PtSi/Si0.81Ge0.19 and PtSi/Si0.71Ge0.29 Schottkydiodes are shown in figures 8.11 and 8.12, respectively. It is seen fromthe figures that the diode with a higher Ge concentration shows a highercurrent. It is also seen from figures 8.11 and 8.12 that reverse currentsdo not saturate for PtSi/Si1−xGex Schottky diodes. The simulated banddiagram of a PtSi/Si1−xGex Schottky diode is shown in figure 8.13,considering the effect of interface states and the associated series resistance.For simulation, a thin interfacial oxide layer of 10 A was taken intoaccount. It is seen from the simulated band diagram that the valenceband discontinuity is in close proximity to the interface. This happens

Figure 8.13. Simulated energy band diagram of a metal-silicide/strainedSi1−xGex Schottky barrier diode with an interfacial layer and a series resistance.


as the thickness of the SiGe layer is small (limited by the critical layerthickness) to retain the strain in the epitaxial layer. Moreover, the layersget unintentionally doped during film growth in an MBE system. As thevalence band discontinuity is in close proximity to the Schottky junction,the total effective barrier can be changed by changing the applied reversebias. The sensitivity of the barrier height change can be controlled bychanging the SiGe layer thickness. As a result, the barrier height decreaseswith the applied reverse bias [30].

Room temperature experimental and simulated forward current–voltage characteristics of PtSi/Si1−xGex (x = 0.19 and x = 0.29) Schottkydiodes are shown in figure 8.14 [31]. For simulation of forward current–voltage characteristics, thermionic emission, image force lowering andthermionic field emission models were considered. Since the existence of a

Figure 8.14. Experimental and simulated current–voltage characteristics ofPtSi/Si1−xGex (x = 0.19 and 0.29) Schottky diodes.


thin interfacial layer (typically a few atomic layers) between the Schottkycontact and the semiconductor affects the current–voltage characteristicssignificantly, interfacial layers of a thickness of 8 A and 10 A were includedin the simulation of the current–voltage characteristics of PtSi/Si0.81Ge0.19and PtSi/Si0.71Ge0.29 Schottky diodes, respectively. The interfacial layerwas assumed to be transparent to the carriers, so that they tunnel throughit without any reflection, but able to withstand a potential drop acrossit. Associated series resistances were computed to be 12.2 Ω cm−2 and0.70 Ω cm−2, respectively. Fermi level pinning was also incorporated inthe model. To fit the experimental current–voltage characteristics, theinterface state density for both the diodes was taken to be the same,1 × 1012 cm−2 eV−1. The simulated current–voltage characteristics agreewell with the experimental data for both the heterostructure Schottkydiodes, as shown in figure 8.14.

8.7.1. Barrier height and ideality factor

The saturation current density of a Schottky diode (J0) at zero bias isusually obtained by extrapolating the linear portion of the forward current–voltage characteristics to zero applied bias. Using the saturation current,important parameters such as the barrier height and ideality factor for a

Figure 8.15. Schematic structures of Schottky diodes fabricated on solid sourceMBE grown Si0.81Ge0.19 and Si0.71Ge0.29 films. (After Dentel D et al 1998Semicond. Sci. Technol. 13 214–9.)


Schottky diode can be determined. However, it is difficult to apply atlarge biases where the voltage drop across the series resistance of the diodemay become a significant proportion of the applied voltage. To avoid thisdifficulty, the saturation current and ideality factor are calculated by usinga least-squares fitting method [32].

Dentel et al [24] have measured the barrier heights of platinum–silicideSchottky diodes on p-type Si1−xGex (x = 0.19 and x = 0.29) films.The device structures are shown in figure 8.15. The barrier height andideality factor were extracted using equations (8.7) and (8.8), respectively.The variation of the barrier height as a function of temperature is shownin figures 8.16 and 8.17. It is seen from the figures that the Schottkybarrier height (SBH) increases with the increase in temperature. Theroom temperature SBH values of PtSi/strained Si1−xGex Schottky diodesextracted were 0.57 eV (x = 0.19) and 0.52 eV (x = 0.29). When thetemperature was lowered to 95 K, barrier heights decreased to 0.20 eV and

Figure 8.16. Variation of Schottky barrier heights with temperature ofPtSi/Si0.81Ge0.19, PdSi/Si0.81Ge0.19 and TiSi/Si0.81Ge0.19Si diodes.


Figure 8.17. Variation of Schottky barrier heights with temperature ofPtSi/Si0.71Ge0.29, PdSi/Si0.71Ge0.29 and TiSi/Si0.71Ge0.29Si diodes.

0.19 eV, respectively. For comparison, the temperature dependences of thebarrier height of the PtSi/Si Schottky diode are shown in figure 8.18. Thesame trend of barrier height variation with temperature is also observedfor Si. Such a strong dependence of the barrier height on temperature isdue to the fact that the measured current through a Schottky junctionis a combination of thermionic and recombination currents. As a result,barrier height values calculated using the thermionic emission model showtemperature dependence, since deviation from ideal behaviour due torecombination becomes more pronounced as the temperature is lowered[16,33,34]. Also the presence of a thin native oxide layer on the Si surfacestrongly influences the temperature dependence of the barrier height [35].

At a particular temperature, the barrier heights of the PtSi/Si1−xGex(x = 0.19 and 0.29) Schottky diodes are smaller than those of the PtSi/p-SiSchottky diode. The biaxial strain in Si1−xGex causes a change in thebandgap which is empirically expressed as Eg(x) = 1.11–0.74x eV, where


Figure 8.18. Variation of barrier heights with temperature of PtSi/Si, PdSi/Siand TiSi/Si Schottky diodes.

x is the Ge concentration [36]. The bandgap reduction for 19% Geconcentration is 0.13 eV, while it is 0.20 eV for a 29% Ge concentrationwith respect to Si. This bandgap reduction is the reason for the smallerbarrier height obtained for Schottky diodes on p-SiGe films with a higherGe concentration.

The room temperature ideality factor, extracted from the experimentalI–V characteristics were found to be 1.10 and 1.15 for PtSi/Si1−xGexdiodes for x=0.19 and 0.29, respectively. The current–voltagecharacteristics depend on the interface quality. In a Schottky diode, evenwith a good surface treatment, an interfacial oxide layer, of a thicknessof about 5–10 A with a considerable amount of surface states, is present.According to the Bardeen limit [27], surface states pin the Fermi levelat the mid energy gap of the energy band and make the barrier heightless sensitive to the metal work function. The greater than unity idealityfactor shows the deviation of Schottky diode characteristics from their idealbehaviour.


Figure 8.19. Plots of 1/C2D versus applied reverse bias at room temperature for(a) TiSi/Si0.81Ge0.19 and (b) TiSi/Si0.71Ge0.29 Schottky diodes.

In thermionic emission theory, which models the ideal Schottkycurrent–voltage characteristics, there is no satisfactory explanation for thegreater than unity ideality factor [37, 38]. The departure of the idealityfactor from unity may be due to the presence of an interfacial layer betweenthe metal and semiconductor [14] and also due to the existence of a laterallyvarying potential barrier height, caused by a nonuniform interface [39].Image force lowering has also been shown to be responsible for a greaterthan unity ideality factor [27]. The dependence of the ideality factor ontemperature is due to thermionic field emission and also recombination inthe depletion region. As the bias voltage increases, the electric field atthe Schottky boundary decreases the potential drop across the interface.The bias voltage at which current–voltage characteristics become stronglynonideal depend more on the potential drop across the interfacial layerthan on series resistances present in the diodes [35].


Table 8.2. Schottky barrier height and ideality factor of group IV alloy layerswith Pt, Pd and Ti.

Parameter Film Si0.71Ge0.29 Si0.79Ge0.20C0.01with Si-cap with Si-cap

Metal Pt Pd Ti Pt Pd Ti

Ideality 300 K 1.15 1.12 1.03 1.11 1.20 1.20factor (n) 100 K 1.32 1.52 1.53 1.48 1.47 1.30

Barrier 300 K 0.52 0.54 0.56 0.56 0.57 0.58height (eV) 100 K 0.19 0.23 0.27 0.21 0.22 0.23

Figure 8.20. Plot of forward capacitance–voltage characteristics of aPtSi/Si0.81Ge0.19 Schottky diode at different frequencies.


Figure 8.21. Forward capacitance–voltage characteristics of a PtSi/Si Schottkydiode at different frequencies.

From the forward and reverse currents of PdSi/strained Si1−xGexand TiSi/strained Si1−xGex Schottky diodes barrier heights have beenextracted by Maiti and Chattopadhyay [40]. The variation of the barrierheights of the diodes with temperature is shown in figures 8.16 and 8.17. Inthe case of PdSi/strained Si1−xGex and TiSi/strained Si1−xGex Schottkydiodes, the barrier height increases with the increase in temperature. Theroom temperature values of the barrier heights for PdSi/strained Si1−xGexSchottky diodes with x = 0.19 and 0.29 Ge are 0.58 eV and 0.54 eV,respectively. At 100 K, these values reduce to 0.28 eV and 0.23 eV,respectively. The values of the ideality factor of the diodes were within1.03–1.50. Table 8.2 shows the extracted values of SBH and ideality factorsof various metal–film combinations at room temperature and 100 K.

Barrier heights may also be determined from reverse capacitance–voltage measurements. When a small ac voltage is superimposed upon thedc bias, charges of one sign are induced on the metal surface and charges of


Figure 8.22. Forward capacitance–voltage characteristics of PtSi/Si1−xGex(x = 0.19 and 0.29) Schottky diodes at 10 kHz (LF) and at 1 MHz (HF).

opposite sign in the semiconductor. The relationship between capacitanceand reverse applied voltage is given by equation (8.9). Figure 8.19 showstypical plots of 1/C2

D versus applied reverse voltage of TiSi/Si1−xGex(x = 0.19 and 0.29) Schottky diodes measured at a frequency of 1 MHz.Using the voltage intercepts (on the x-axis) of 0.35 V and 0.28 V for thesamples containing 19% and 29% Ge, the barrier heights extracted were0.61 eV and 0.56 eV. The difference in the Schottky barrier height valuesdeduced from current–voltage and C–V measurements is attributed to theeffect of inhomogeneities at the interface of the diodes.

8.7.2. Interface state density distribution

The Schottky barrier diode characteristics deviate from their idealbehaviour due to the presence of an interfacial layer at the junctionand the associated interface states. The distribution of the interfacestate density in metal/SiGe Schottky diodes has been reported byChattopadhyay et al [29].


Figure 8.23. Energy distribution of interface state density of TiSi/Si0.81Ge0.19,PdSi/Si0.81Ge0.19 and PtSi/Si0.81Ge0.19 Schottky diodes.

The distribution of the interface state density in a Schottky diode isdetermined from capacitance–voltage measurements. Figure 8.20 showsthe plots of forward C–V characteristics of the PtSi/Si0.81Ge0.19 Schottkydiode in the frequency range of 10 kHz to 1 MHz. At high frequency, thecapacitance value becomes almost constant but in the low-frequency rangethe capacitance value shows a peak. The peak arises from the contributionof interface states present in the Schottky junction and partly due to theinjection of minority carriers from the non-ohmic back side [41]. Thecorresponding plot for a PtSi/Si Schottky diode is shown in figure 8.21.It is seen that the variation of capacitance is of same nature as that ofPtSi/Si1−xGex diodes. Figure 8.22 shows only the plots of measured C–V data at 10 kHz and 1 MHz for PtSi/Si0.81Ge0.19 and PtSi/Si0.71Ge0.29diodes. Taking CLF (10 kHz) and CHF (1 MHz) values, the interface statedensity Dit is extracted.


Figure 8.24. Energy distribution of interface state density of TiSi/Si0.71Ge0.29and PtSi/Si0.71Ge0.29 Schottky diodes.

The energy distribution of the interface states of Si1−xGex (x = 0.19and 0.29) Schottky diodes using Pt, Pd and Ti are shown in figures 8.23and 8.24, respectively. In figures 8.23 and 8.24, the energy has been plottedfrom the valence band edge. It is seen that the distribution of the interfacestate densities for all cases is maximum near the valence band edge anddecreases (and remains almost constant) with energy from the valence bandedge to the midgap. The minimum value of the interface state density forall the diodes lies in the energy range from 0.5–0.6 eV and has a value inthe range of 6 × 1011 cm−2 eV−1 to 4.5 × 1012 cm−2 eV−1 [29]. It is seenfrom figures 8.23 and 8.24 that the PtSi/Si1−xGex Schottky interface hasthe lowest interface state density as compared to PdSi and TiSi Schottkydiodes on Si1−xGex.

The energy distributions of the interface state densities of TiSi/Si andPdSi/Si Schottky diodes are shown in figure 8.25. It is seen that the

Schottky diodes on strained-Si 303

Figure 8.25. Energy distribution of interface state density of TiSi/Si, PtSi/Siand PdSi/Si Schottky diodes.

distribution of the interface state density with energy is maximum nearthe valence band edge and it decreases with energy from the band edge tomidgap energy for all Schottky diodes. The minimum value of the interfacestate density for all diodes is in the energy range from 0.50–0.60 eV andits value lies in the range of 1 × 1011 cm−2 eV−1 to 8 × 1011 cm−2 eV−1.It is also evident from figure 8.25 that the energy distribution of interfacestates near the midgap is almost constant for all the diodes.

8.8. SCHOTTKY DIODES ON STRAINED-SI

Schottky diodes on p-type strained-Si on graded relaxed Si1−xGex havebeen characterized by Chattopadhyay et al [13]. The forward logarithmiccurrent–voltage characteristics of as-deposited Pt/strained-Si Schottkydiodes at different temperatures are shown in figure 8.26. The current–voltage characteristics of the heterostructure Schottky diodes have also


Figure 8.26. Forward current–voltage characteristics of a Pt/strained-SiSchottky diode (as-deposited) at different temperatures.

been simulated [35]. The simulated current–voltage characteristics for 95,150 and 300 K are shown in figure 8.27.

Among Pt, Pd and Ti, Pt shows the lowest barrier height and is not sosensitive to the metal work function. As discussed earlier, this is attributedto Fermi level pinning by the interface states or by metal-induced gapstates. Figure 8.28 shows a typical plot of 1/C2

D versus applied reversevoltage which is a straight line for Ti/strained-Si Schottky diodes. It isseen from the figure that the intercept on the voltage axis is 0.38 eV and,for a substrate doping concentration of 5 × 1015 cm−3, the barrier heightis found to be 0.60 eV.

Summary 305

Figure 8.27. Experimental and simulated current–voltage characteristics ofPt/strained-Si Schottky diode at 95, 150 and 300 K.

8.9. SUMMARY

Formation and characterization of noble/refractory metal silicides (Pt,Pd and Ti on SiGe, SiGeC, Si and strained-Si) using x-ray diffraction,Rutherford backscattering and Auger electron spectroscopy have beendiscussed. Different phase transformations are observed during silicideformation on SiGe and other alloys. Among all (Pt, Pd and Ti onSiGe, SiGeC and strained-Si), the PtSi/Si1−xGex Schottky diodes exhibita minimum barrier height with excellent interfacial quality and aretherefore, preferable for far-infrared detector applications, as has alsobeen demonstrated experimentally. Electrical characterization, over a


Figure 8.28. Plot of 1/C2D versus applied reverse bias of Ti/strained-Si Schottkydiode at room temperature.

wide range of temperatures to determine Schottky diode parameters, hasshown that the barrier heights decrease with the decrease in temperatureand increase in Ge mole fraction in the epilayer. Extracted idealityfactors have values slightly greater than unity and are found to increasewith decrease in temperature for all metal-material systems discussed.The interface state density decreases with increase in energy from thevalence band edge for all diodes. The barrier height values determinedfrom the reverse C–V characteristics at room temperature are found tobe slightly higher than that extracted from the forward current–voltagecharacteristics. PtSi/Si1−xGex and PtSi/Si Schottky photodetectors havebeen simulated in the wavelength range of 2–8 µm for detector applicationsand the simulation results compare favourably with reported experimentalresults as will be presented in chapter 9.

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[37] Tung R T 1992 Electron transport at metal–semiconductor interfaces:general theory Phys. Rev. B 45 13 509–23

[38] Tung R T 1993 Schottky barrier height—do we really understand what wemeasure? J. Vac. Sci. Technol. B 11 1546–52

[39] Schneider M V, Cho A Y, Kollberg E and Zirath H 1983 Characteristics ofSchottky diodes with microcluster interface Appl. Phys. Lett. 43 558–60

[40] Maiti C K and Chattopadhyay S unpublished data[41] Green M A and Shewchun J 1973 Minority carrier effects upon the small-

signal and steady-state properties of the Schottky diodes Solid-StateElectron. 16 1141–50

Chapter 9

SIGE OPTOELECTRONICDEVICES

Elemental silicon and germanium have long been used as photodetectors.The tunability provided by SiGe and SiGeC alloys has recently beenexploited for extending the range of application. The fabrication andperformance of several classes of photodetector based on a heterostructureare examined in this chapter. Methods of meeting the limitations ofindirect band-gap and small allowable thickness of stable strained alloylayers are described. Silicon based optical waveguides and prospects ofdevice integration receive special emphasis.

The demand for optoelectronic technology is increasing rapidlyand is being driven by the exponential growth in personal computers,high-speed computer interconnections, high-speed telecommunicationsand other commercial optoelectronic products. Optical communicationsystems are the most promising candidate for achieving large capacitytransmission over high-speed local area networks (LANs) using fibrechannel and optical interconnection systems. The wide spread useof multimedia communications will require over 1 Gbit s−1 capacitytransmission, even in LANs. Optical communications offer a wide varietyof applications toward building the information superhighway, rangingfrom short distance chip-to-chip communication, LAN, fibre-to-home, tooverseas telecommunications. Furthermore, with optical communicationsystems, optoelectronic integrated circuits (OEICs) have the potential toovercome the limitations in electronic integrated circuits for high speed,wide bandwidth, and high density interconnects as device dimensionsshrink to the deep submicron regime.

Although silicon is the dominant material in electronics, its indirectbandgap physically restricts its application in electro-optical devices. Mostof the high-performance devices in optoelectronics are made from III–Vcompound semiconductor heterostructures, such as AlGaAs/GaAs and

310

SiGe optoelectronic devices 311

Table 9.1. Optical properties for Si and Ge.

Property Si Ge

Transparent regions (µm) 1.1–6.5 1.8–15(absorption coefficient <1 cm−1)Dielectric constant 11.9 16Refractive index (optical) 3.455 4.001Optical–phonon energy (eV) 0.063 0.037Phonon mean free path (A) 76 (electron) 105

55 (hole)

InGaAsP/InP, because of their direct bandgap and high quantum efficiency.There are also several III–V compound semiconductor pairs with excellentlattice matching capability (≤1%), which is favourable for advancedheterostructures and bandgap-engineered devices. However, there are someinherent disadvantages of III–V semiconductors, such as poor mechanicaland thermal properties, difficulty in processing, incompatibility with siliconand, more importantly, high cost.

Cost-effective silicon-based optoelectronics has attracted a great dealof research effort and significant progress has been made [1–5]. If theoptical properties of silicon-based materials could be enhanced, in both thevisible and infrared regions, especially at wavelengths of 1.3 and 1.55 µm,which are beyond the limitation of the Si bandgap but correspond tominimum values of absorption and dispersion in glass optical fibres used forlong distance telecommunications, very powerful optoelectronic integratedcircuits could be realized entirely in silicon. Incorporation of Ge in Sireduces the bandgap of the resulting SiGe alloys, shifting their absorptionwavelengths towards red compared to Si. SiGe strained layer superlattices(SLS) offer the possibility of a fundamental change in optical properties ofSi. The important optical properties of Si and Ge are presented in table 9.1.

Optical communication systems with a Gbit s−1 capacity require thedevelopment of high-speed, highly reliable, low-cost and compact opticalterminal ICs, such as Si-based optoelectronics integrated circuits. Byincorporating future Si-based optical devices (emitters and detectors) withexisting Si-based electronic circuitry all on a single silicon ‘superchip’ (seefigure 1.10), these Si-based OEICs would represent a great cost reductioncompared to their III–V counterparts and with added computational power.

Efforts to realize silicon-based optoelectronic devices include III–Von-chip light sources grown on silicon [6] or bonded to silicon [7], poroussilicon [8–10], erbium-doped silicon [11, 12] and group IV semiconductorheterostructures [4]. In hybrid optoelectronic integration on Si, III–Vphotonic devices and Si or SiGe electronic devices are bonded on an Si

312 SiGe optoelectronic devices

Table 9.2. ICs for optical fibre communication systems fabricated by usingSiGe HBTs.

Circuit Maximum speed/bandwidth

Multiplexer 40 Gb s−1

Pre-amplifier 35.1 GHzAGC amplifier 31.6–32.7 GHzDecision circuit 40 Gb s−1

Demultiplexer 40 Gb s−1

Static frequency divider 50 GHz

chip. This approach combines the high-speed and light emission advantagesof III–V semiconductors and the mature and reliable Si technology. It ispractical and has achieved some success for optoelectronic signal processingin the last few years [7, 13]. However, the fabrication of hybrid OEICs ismore complicated, expensive and less reliable than monolithic OEICs. Also,interconnection density and speed in hybrid OEICs are limited.

As applications of SiGe HBTs, various ICs for optical-fibre-linksystems, have been developed (see table 9.2) [14, 15]. These include bothdigital ICs of a static frequency divider and a time-division multiplexer(MUX), demultiplexer (DEMUX) and analogue ICs of a pre-amplifier, anAGC amplifier core and a decision circuit. A maximum operating frequencyof up to 50 GHz for a 1/8 static frequency divider has been achieved. A2:1 time-division MUX and a 1:2 DEMUX built from basic circuit coremodules operated at 40 Gb s−1. In a pre-amplifier with an input stageconsisting of a common base transistor, a bandwidth of 35 GHz was alsoachieved. In an AGC amplifier core, a bandwidth of about 32 GHz with adynamic range of 19 dB was obtained by using a transimpedance amplifieras an active load circuit and a peaking capacitor.

Highly porous silicon (PS) has attracted much attention because itexhibits strong photoluminescence (PL) from the near-infrared to visiblegreen–blue range by varying the porosity at room temperature [9,16]. Theexternal quantum efficiencies of light emission of highly porous silicon canbe as high as 1–10%. There is still a debate in the scientific communityregarding the physics of this phenomenon. The common views of the originof light emission are:

(i) the two-dimensional quantum-size effects;(ii) surface molecular species coating the porous skeleton;(iii) radiative decay at surface/interface states; and(iv) hydrogenated amorphous silicon as a product of the invasive

electrochemistry [10].

SiGe optoelectronic devices 313

Similar observations of strong visible PL from MBE grown B-doped porousSi0.7Ge0.3 grown on p-type Si wafers have been reported [17]. The porouslayers were formed by an electrochemical etching process. A significantshift in the emission energy of porous Si0.7Ge0.3 grown on Si has beenobserved for various anodization conditions and the temperature range78–295 K. The PL emission energy has been found to remain almostunchanged on varying excitation energy, and to increase linearly withreciprocal temperature. The position of the PL emission, however, wasobserved to be strongly dependent upon the anodization current densityand the duration of the etching process. The origin of visible PL of theporous MBE grown SiGe films is interpreted by considering the quantumconfinement effect, as in the interpretation of PL from porous Si. Despiteits high efficiency, highly porous silicon has a problem with integration dueto mechanical fragility and poor thermal conductivity and ohmic contacts.

When doped with rare earth ions, silicon produces intense PL [11,18].Erbium is of great interest among these rare earth ions, because itsluminescence spectrum, due to the transitions from the first excited spin-orbit state to the first ground state, is centred around 1.54 µm which isthe absorption window in silica-based optical fibres. However, couplingbetween Er and the host Si remains a problem.

Absorption of infrared radiation of 8–12 µm in atmosphere is smalland this wavelength range is important for night vision applications. Thegroup II–VI compound semiconductor (HgCdTe) IR sensor is most sensitivein this wavelength range. But monolithic integration on Si substrates forlarge scale use with charge coupled devices is difficult. PtSi/p-Si Schottkydiodes are presently being used but operate only in the 3–5 µm wavelengthrange. IrSi/p-Si Schottky diodes have a low barrier height with a cut-offwavelength of about 7.3 µm [19]. PtSi/Si1−xGex Schottky diodes are alsopromising for sensing far-infrared radiation due to its smaller barrier heightcompared to PtSi/Si or IrSi/Si Schottky diodes.

SiGe alloys have led to the realization of many novel bandgap-engineered high-speed optoelectronic devices with significantly improvedperformance and are easily integrated with conventional Si technology[1, 2, 5]. For compatibility with Si technology, strained layer superlatticesare generally grown on an Si substrate. Using Si/SiGe/Si SLS, it ispossible to convert the indirect bandgap of Si to a quasi-direct bandgap viaBrillouin zone folding and to exploit the new optical properties in termsof Si-based optical devices. The aim is the fabrication of Si-based activeand passive optical devices (light emitters and receivers such as LEDsand photodetectors) which could be integrated in silicon together withthe electronic driver circuits [20]. Experimental studies have shown thatinfrared (>1.2 µm) light can be waveguided, detected, emitted, modulatedand switched in Si and in binary group IV alloy films [21].

However, a 4.2% lattice mismatch between silicon and germanium is


a serious constraint in the design of SiGe heterostructures necessary foroptical applications [22–25]. Most of the earlier investigations have involvedSiGe heterostructures with a limited Ge content (<30%). In order toobtain a reasonable photoresponse in the 1.3 µm wavelength region, theGe concentration should be more than 50%, whereas the critical thicknessfor a strained pseudomorphic SiGe epilayer with x = 0.5 is limited to only100 A or less [4]. As described in chapter 2, for epilayers with a thicknessgreater than the critical thickness, misfit dislocations are introduced atthe interface and the quality of the epilayer is degraded, affecting theperformance of the devices.

In general, the group IV alloy system includes three binary alloys:SiGe, SiC and GeC. By adding a small substitutional C to the SiGesystem, it is possible to adjust the lattice constant and strain (fromcompressive to tensile) and obtain an adjustable bandgap (from 0.67 eVto 5.48 eV by varying the composition) [26]. Ternary SiGeC andquarternary SiGeSnC systems offer an additional degree of freedom forstrain and bandgap engineering in Si-based alloys. Guarin et al [27] havereported the growth of ternary Si0.955Sn0.03C0.015 alloys up to 4500 Ain thickness and quarternaries of composition in the neighbourhood ofSi0.835Ge0.125Sn0.03C0.01. Infrared absorption spectroscopy and PL datahave provided evidence of the potential for significant bandgap modificationin these alloys. For this reason, renewed attention has shifted to the novelternary Si1−x−yGexCy and SiGeSnC material systems [28,29].

The other group IV alloy material with a potential for applicationsin the fabrication of Si-based infrared devices is metastable SnxGe1−xfilms [30]. Band structure calculations have suggested that the SnxGe1−xalloys have direct energy gaps continuously tunable from 0.55 eV to 0 eVfor compositions x from 0.2 to 0.6 with very small electron effective masses.The relatively low growth temperature of SnxGe1−x (∼200 C) opensthe possibility of direct monolithic integration of detector arrays on Siintegrated circuits.

The bandgap of a–SiGe:H can be varied from 1.75 to 1.0 eV bychanging the Ge content, and makes the material suitable for detection oflight emitted from commercial laser diodes or LED. Films can be depositedat a low temperature of about 250 C on glass as well. Hydrogenateda–SiGe:H has been used for implementing phototransistors in the infraredrange, solar cells, for optical detection and image sensing. Dilutionwith hydrogen causes a small decrease of the bandgap and improves thestructural and electronic properties [31]. However, a simulation study ofcarrier multiplication in the Si1−xGex material system shows that only asmall increase of solar cell efficiency is expected from the impact ionizationof hot carriers [32].

The objective of this chapter is to review the recent developmentsand the possible applications of group IV (SiGe, GeC, SiGeC, SiGeSnC

Optoelectronic devices in silicon 315

and strained-Si) alloys in optoelectronics for integrated circuits entirelyon silicon. Photoresponsivity and refractive index data obtained fromexperimental SiGe, SiGeC and GeC photodiodes are presented. Simulationof PtSi/Si1−xGex and PtSi/Si Schottky photodetectors in the wavelengthrange of 2–8 µm, p-doped/intrinsic/n-doped (p–i–n) photodetectors,photoresponse characteristics of Si1−xGex metal–semiconductor–metal(MSM) photodetectors and Si1−xGex/Si waveguide photodetectors will beconsidered.

9.1. OPTOELECTRONIC DEVICES IN SILICON

A photodetector converts an incident optical signal to an electrical signalthat can be processed electronically to extract the required informationcarried by the incident optical signal. Semiconductor photodetectors aremade by forming a p–n junction within the semiconductor or by forming ametal–semiconductor junction. On application of a suitable reverse bias tothe device, an electric field is created which separates the photogeneratedelectron–hole pairs. The device can operate either in photovoltaic orphotoconductive mode. Photodetectors play an important role in opticalfibre communication systems and are generally used in optical receivers.The requirements for a good photodetector include high quantum efficiencyat the operating wavelength, high speed, wide bandwidth, high reliability,low noise and low cost.

An optical transmission and processing system consists of lightsources (LED), photodetectors, modulators, electronic devices, and otherpassive or quasi-passive optical components. In a photoreceiver, aphotodetector is monolithically integrated with a pre-amplifier whichuses an FET or an HBT. Different types of photodetectors proposedfor optical fibre communication are: p–n junction photodiodes (PN-PDs), p–i–n photodiodes (PIN-PDs), avalanche photodetectors (APDs),optical field effect transistors (OPFETs), MSM photodetectors (MSM-PDs), p-heterojunction bipolar transistors (PHBTs) and photoconductors.

Electron–hole pairs can be produced in a semiconductor by incidentlight through two different processes. For incident radiation with an energyhν > Eg, where ν is the frequency of light and Eg is the semiconductorbandgap. The intrinsic photoexcitation process occurs where electron–holepairs are generated by band-to-band transitions. In the other process, theextrinsic excitation process, the incident photon excites an electron froma donor level into the conduction band, or an electron is excited from thevalence band to an acceptor level creating a hole in the semiconductor.Most photodiodes are of the intrinsic type.

For intrinsic excitation processes, the long wavelength cut-off λc is


given by

λc =hc

Eg=

1.24Eg

(9.1)

where c is the velocity of light. The external quantum efficiency of thephotodiode is defined as the number of electron–hole pairs generated perincident photon and is given by

η =Ip/q

Popt/hν(9.2)

where Ip is the photogenerated current, Popt is the incident optical power,and hν is the photon energy with a wavelength of λ. A related figure-of-merit is photoresponsivity, which is given by

Rphoto =IpPopt

=ηq

hν=ηλ

1.24. (9.3)

The most common type of photodetection device is the depletion layerphotodiode, which includes a p–n junction diode or a p–i–n diode. Anothercommon type which exhibits gain is the avalanche photodiode. The othermembers of the photodiode family are Schottky barrier and MSM diodes.

9.1.1. p–n junction photodiode

A p–n junction photodiode is the simplest type of junction diode. Itworks under relatively large reverse bias, which is substantially belowthe avalanche breakdown voltage. The incident optical signal produceselectron–hole pairs in the photodiode, but only the carriers createdwithin the depletion region or within a diffusion length of the depletionedge contribute. The reverse bias field in the depletion region sweepsthe photogenerated carriers towards the contacts and gives rise to aphotocurrent in the external circuit. The holes and electrons, separated bythe electrical field, travel at different velocities towards the contacts due totheir different effective masses. A large reverse bias reduces the transit timethrough the depletion region as well as the depletion region capacitance,thus improving the diode capability for high-frequency operation.

Free carriers generated by incident photons move by drift and diffusionand the total current density through the reverse biased depletion layer is

Jtot = Jdrift + Jdiff (9.4)

where Jdrift and Jdiff are the drift and diffusion components, respectively.For a p+–n junction diode, the total current is given by

Jtot = qφopt

(1 − e−αW

(1 + αLp)

)+ qpn0

Dp

Lp(9.5)


where φopt is the total photon flux, W is the width of the depletionlayer, q is the free electron charge, α is the optical inter-band absorptioncoefficient, pn0 is the equilibrium hole density, and Lp and Dp are thediffusion length and the diffusion constant, respectively, for holes. The lastterm in equation (9.5) represents the reverse leakage current (dark current).When the reverse leakage current is very small, then the quantum efficiency,η is given by

η =Ip/q

Popt/hν= 1 − e−αW

1 + αLp. (9.6)

It is clear that the quantum efficiency is determined mainly by theabsorption coefficient, α, of the semiconductor. In order to maximize η, itis desirable to make the products αW and αLp as large as possible, i.e.,the depletion layer must be sufficiently wide to allow a large fraction ofthe incident light to be absorbed. On the other hand, the depletion regionmust be kept narrow to reduce the transit time for high-speed devices.

The avalanche photodiode is essentially a p–n junction operated ina reverse bias condition at or above the avalanche breakdown voltage.Photogenerated carriers in the depletion region travel at their saturationvelocities. When these photogenerated carriers acquire enough energyfrom the electric field, impact ionization occurs and results in avalanchemultiplication of the carriers. Therefore, the gain of the APD can besubstantially increased over conventional p–i–n photodiodes, but withelevated noise inherent to the avalanche process.

9.1.2. Schottky barrier photodiode

Metal–semiconductor contacts (Schottky diodes) are used as very efficientphotodetectors as these are majority carrier devices. The barrier height,φb depends on the particular metal–semiconductor combination. As thesedevices do not suffer from minority carrier storage and removal problems,one can expect high speed and operation bandwidth. The temporalresponse, speed and frequency bandwidth of detectors are controlled bythe transit time of the carriers through the absorption region and externalcircuit parameters. In high-speed diodes, the absorption region is between0.2–0.5 µm which ensures full depletion of the region even at low valuesof reverse bias, and both electrons and holes can travel at their respectivesaturation velocities. Schottky barrier photodetectors can operate in twomodes.

(i) When qφb < hν < Eg, i.e., the energy of incident photon flux is higherthan the corresponding Schottky barrier height but smaller than thebandgap energy of the semiconductor, electrons will be photoexcitedin metal and surmount the barrier by thermionic emission. Emittedelectrons transit through the semiconductor and are collected at the


contact electrodes. The process extends the spectral range towardsred (as it absorbs an energy lower than the bandgap energy) butdecreases device speed as thermionic process is a slow one.

(ii) When hν > Eg, the photon flux penetrates through the semi-transparent metal layer and gets absorbed in the semiconductor. Thephotogenerated electron–hole (e–h) pairs move in opposite directionsdue to the existing electric field with their respective saturationvelocities and are collected at the electrodes. This is a very efficientmode of operation of Schottky diodes and is similar to that of a high-speed p–i–n diode. The fabrication of a Schottky barrier photodiodeis also easy and lends itself for integrated applications.

9.1.3. p–i–n photodetectors

p–i–n photodetectors are finding extensive applications in long haul andhigh bit rate optical communication systems and in local area networksfor operation in the infrared region (0.8–1.6 µm). In addition to opticalcommunication, these devices are also useful for sensing applications as theyhave superior electro-optical characteristics, namely low dark current, highquantum efficiency, greater sensitivity and high speed of response [33–35].

An important mode of operation of a p–i–n photodiode under theexposure of photon flux is the reverse biased configuration. In order tomaximize the quantum efficiency of the diode, an intrinsic layer (i-layer) isinserted between two heavily-doped p+- and n+-layers and the resultingstructure is a p–i–n diode. When a reverse bias is applied across thedevice, entire i-region becomes depleted. Due to high resistivity andtotal depletion of the i-layer, almost all the electric field appears acrossit. The applied reverse bias should not be so high that breakdown cantake place. The dark current is independent of applied reverse bias.As light impinges from the top surface, most of the photon flux passesthrough the relatively thin top layer. The absorbed photons generateelectron–hole pairs which drift towards the electrodes due to the existingelectric field to give rise to a photocurrent in the external circuit. Oneof the advantages of heterojunction p–i–n photodiodes is that the devicecharacteristics are tunable by changing the composition of the i-layer.Another is the resonant–cavity effect, due to the refractive index changeat the heterojunction, which increases the photoresponsivity of the diodewithout affecting the transit-time-limited bandwidth [36].

9.1.4. Metal–semiconductor–metal photodetectors

Metal–semiconductor–metal photodetectors (MSM-PDs) are made up ofinterdigitated metal fingers forming back-to-back Schottky diodes onan undoped semiconductor surface (see figure 9.1). These detectors


Figure 9.1. (a) Schematic structure of an MSM photodiode and (b) analysingarea. (After Chattopadhyay S and Maiti C K, unpublished data.)

are very attractive for many optoelectronic applications, particularly forhigh-frequency wideband operation and are used in multi-gigabit opticalcommunication with high sensitivity. MSM devices can be integrated inconventional IC-processing technology. On application of the bias, onejunction becomes forward-biased while the other becomes reverse-biased.It can be designed so that the region between the two electrodes is almostdepleted. When the incident photon flux impinges on the photo-activearea (interdigitated area), the diode responds as a Schottky photodetectordiscussed above. Some of the important design parameters for MSM-PDs


are responsivity, dark current and capacitance, which are discussed below.The dark current (which decides the minimum detectable power) of

a photodetector significantly contributes to the noise at the input of anoptical receiver, which in turn plays a crucial role in deciding the sensitivityof a receiver. Excess carriers responsible for dark current increase thecapacitance and decrease the response speed of a detector. The detectornoise associated with its dark current is a shot noise and its mean squarevalue is given by

〈i2d〉 = 2qId∆f. (9.7)

Furthermore, the minimum optical power required to achieve aphotocurrent equal to the noise current id is usually regarded as theminimum detectable power of a detector. In an MSM structure, the darkcurrent is a metal/semiconductor interface phenomenon and is attributedto thermionic emission of the carriers across the Schottky barriers [37].Usually, thermionic emission of the carriers across a reverse-biased Schottkyjunction accounts for the dark current in MSM photodiodes [38] and thedark current density is given by

J = A∗nT

2e−q(φb−∆φb)/kT . (9.8)

It is noted that a low Schottky barrier height would result in excess carrierinjection in the semiconductor from the cathode and would lead to a largedark current. It has been proposed that equation (9.8) is valid until theconduction band profile of an MSM photodiode does not reach the flat bandcondition at the forward-biased contact [39]. When the conduction bandat the anode reaches the flat band condition, thermionic emission of holesacross the barrier at anode starts and is accounted for the dark currentwhich is given by

J = A∗nT

2e−q(φb−∆φb)/kT +A∗pT

2e−q(φb−∆φb)/kT (9.9)

where A∗ are the respective Richardson constants and ∆φ are the respectivebarrier height lowering due to image force. The flatband voltage VFB canbe expressed as [37]

VFB =qNdS

2

2εsε0(9.10)

where S is the electrode spacing and Nd is the donor concentration in thelayer.

The dark capacitance of an MSM photodetector is contributed by theelectrostatic field around the alternatively charged parallel metal fingers.The speed of an MSM detector is limited by RLC time constant if it islonger than the transit time or recombination time. Here, RL consistsof the load resistance and series resistance of the metal fingers. Thedetector capacitance can be estimated by using a model based on conformal

Optical properties of SiGe and SiGeC films 321

mapping [40]. If W is the finger width and P is the finger pitch (sum ofwidth and spacing, i.e., P =W+S), the total detector capacitance is givenby

Ctotal =C0A

P(9.11)

where A is active area of the detector.

9.2. OPTICAL PROPERTIES OF SIGE AND SIGEC FILMS

It has been shown that quantum efficiency is determined mainly bythe absorption coefficient of the semiconductor. The measured opticalabsorption coefficient, α, and refractive indices of Si and Si1−xGex fordifferent values of the Ge fraction, x, are shown in figures 9.2 and 9.3. The

Figure 9.2. Optical absorption coefficients of Si, Ge and undoped SiGe alloys.


Figure 9.3. Refractive indices of Si, Ge and undoped SiGe alloys.

data are taken from [41]. It is seen from figure 9.2 that Si is transparentin the wavelength region 1.20–1.60 µm, while the SiGe absorption edgeshifts towards the red with increasing Ge concentration in the alloy. Theshift offers a means for absorbing 1.3–1.6 µm light, by choosing x > 0.3 for1.3 µm and x > 0.85 for 1.55 µm. From figure 9.3, it may be noted thatthe refractive index increases with the increase in Ge concentration. Whileintrinsic Si and Ge are transparent from near-infrared up to 20 µm andbeyond, the optical transmission of group IV alloys is found to reduce byheavy doping [2]. For unstrained (bulk) SiGe alloys, the absorption datahave been provided by Braunstein et al [42].

Orner et al [43] have measured the optical absorption at phononenergies near the bandgap of a Ge-rich SiGeC (x ≈ 0.90, y ≤ 0.02) filmby employing Fourier transform infrared (FTIR) spectroscopy. As the film

Optical properties of SiGe and SiGeC films 323

Figure 9.4. Optical absorption coefficient (α) of a Ge-rich Si0.11Ge0.88C0.01film: (a) C is primarily substitutional and (b) C is primarily interstitial. (AfterOrner B A et al 1996 Appl. Phys. Lett. 69 2557–9.)

was Ge-rich, their bandgap energies are less than that of Si. Absorptiondata and the best fit curves are as shown in figure 9.4. Figure 9.4(b)shows a comparison between two films with carbon at the interstitial andsubstitutional sites. In both cases the infrared absorption edge of the alloyshifts towards the red.

Figure 9.5 shows the refractive index of the epitaxial Ge1−xCx as afunction of donor concentration and compares it to Ge epitaxial layersgrown under identical conditions. Introducing carbon into epitaxial Gefilms doped with P decreases the refractive index near the absorptionedge. Figure 9.6 illustrates the absorption coefficient, α, of phosphorus-


Figure 9.5. Refractive index versus donor concentration for Ge1−yCy and Geepitaxial films on Si(100). (After Dashiell M W et al 1998 Thin Solid Films 32147–50.)

Figure 9.6. Absorption coefficient versus photon energy of Ge1−yCy layers onSi(100) for ND = 7×1019 cm−3, ND = 2×1018 cm−3 and undoped. Included arevalues for intrinsic bulk-Ge. (After Dashiell M W et al 1998 Thin Solid Films321 47–50.)

Optical devices using SiGe alloys 325

doped Ge1−yCy films grown epitaxially on Si(100) for α > 100 cm−1.The absorption edge experiences a redshift with increasing phosphorusconcentrations for both Ge1−yCy and Ge films. High-purity Ge data arealso included in the figure. Note that undoped Ge1−yCy epitaxial layersexhibit the same absorption coefficient as does intrinsic bulk germaniumfor α > 100 cm−1. Thus, a significant band structure modification was notobserved by optical absorption for these C concentrations.

9.3. OPTICAL DEVICES USING SIGE ALLOYS

The main aims of SiGe optoelectronics are: high responsivity, lownoise, fast response and integration with the conventional Si-processingtechnology. Most of the reported studies include:

(i) p–i–n diode for 1.3 µm wavelength with 50% internal quantumefficiency, 200 ps impulse response and 10 pA µm−2 dark currentat 15 V bias [2, 44–46];

(ii) waveguided p–i–n photodetectors with 50% internal quantumefficiency at 1.3 µm and 200 nA dark current at −15 V in a 10×750 µmdevice [25,47]; and

(iii) a waveguided metal–semiconductor–metal photodiode [48].

A responsivity of 0.2 A W−1 was measured at 1.3 µm over a 1 nmdetector length with a 500 pA µm−2 dark current at 5 V bias. Si1−xGexrib waveguide avalanche photodetectors for operation at 1.3 µm andstrained layer superlattice waveguide photodetectors have also beenreported [49–52].

Silicide/Si1−xGex Schottky diodes have been proposed for detectingfar-infrared radiation, taking advantage of the controllable bandgap ofSiGe. For such diodes, the general requirement is to adjust the parameterssuch as the barrier height and ideality factor. PtSi/Si1−xGex Schottkyphotodetectors have been proposed for detection of infrared radiationof wavelengths up to 10 µm [19]. Xiao et al [53] have demonstratedPd2Si/Si1−xGex and PtSi/Si1−xGex Schottky-barrier long-wavelengthinfrared detectors The cut-off wavelength is found to be dependent onthe amount of Ge present in the strained layer. Figure 9.7(a) shows themeasured Fowler plots for three Pd2Si/Si1−xGex (x = 0, 0.20 and 0.35)detectors using an FTIR spectrometer at 77 K. As expected, the cut-offwavelength clearly increases with the increasing Ge fraction, x, for thePd2Si/Si1−xGex detectors.

The spectral response of a PtSi/Si0.85Ge0.15 detector is shown infigure 9.7(b) along with that of a PtSi/Si control device. The cut-offwavelength is extended from 5.2 to 8.8 µm with only 15% Ge in the alloy,corresponding to a barrier height reduction of 100 meV. By extrapolation, acut-off wavelength beyond 10 µm is expected for a PtSi/Si1−xGex detector


Figure 9.7. Infrared photoresponse at 77 K of (a) Pd2Si/Si1−xGex and (b)PtSi/Si1−xGex Schottky barrier detectors. (After Xiao X et al 1993 IEEEElectron Device Lett. 14 199–201.)


Figure 9.8. Comparison of measured external responsivities of PtSi/Si0.80Ge0.15and PtSi/Si infrared detectors. The points represent data obtained with acalibrated infrared monochromator (40 K), while the lines are scaled results fromFTIR measurements. (After Xiao X et al 1993 IEEE Electron Device Lett. 14199–201.)

with as little as 18% Ge in the alloy. The measured external responsivities(40 K) of the PtSi/Si0.85Ge0.15 detector and the PtSi/Si control deviceare shown in figure 9.8. Although the actual measurement was limitedto 4 µm, extrapolated full responsivity curves for the PtSi/Si0.85Ge0.15detector showed superior responsivity to the conventional PtSi/Si detectorover the whole wavelength range.

Low-loss waveguides have been proposed using group IV alloy films.Light can propagate in four types of group IV waveguides: lightly-doped silicon on heavily-doped silicon [54–57], epitaxial Si1−xGex onSi [58–62], silicon-on-sapphire [63] and silicon-on-insulator [64–68]. Inaddition to epitaxial SiGe, SiC or SiGeC can be used as waveguide cores.Crystallographic defects such as threading dislocations need to be keptbelow 104 defects/cm2 in order to keep losses below 1 dB cm−1 in silicon-on-insulator and SiGe/Si waveguides [68]. A loss of 0.5 dB cm−1 for transverseelectric (TE) and 0.6 dB cm−1 for transverse magnetic (TM) modes at1.32 µm have been reported in chemical vapour deposited Si0.99Ge0.01 ribson Si [60]. The propagation loss in a polarization independent single-moderib made from Ge-diffused Si has been found to be 0.3 dB/cm at 1.3 and


Figure 9.9. Schematic view of integrated SiGe/Si planar photodetector withtrench for optical fibre guide. The optical fibre is attached to the trench and thecore of optical fibre is coupled to the photodetector with alignment-free. (AfterTashiro T et al 1997 IEEE Trans. Electron Devices 44 545–50.)

1.55 µm. In a single-mode SOI/SIMOX rib, the reported propagation lossis about 0.4 dB cm−1 for polarization independent 1.3 and 1.55 µm infraredradiations [65].

An integrated p–i–n SiGe/Si-superlattice photodetector (as shown infigure 9.9) with a planar structure has been developed on a bonded silicon-on-insulator for Si-based optoelectronic integrated circuits [69, 70]. An Si,30 periods, superlattice absorption layer, a 0.1 µm p-Si buffer layer and a0.2 p+–Si contact layer were deposited on a bonded SOI. The bonded SOI isused to increase the external quantum efficiency, ηext of the photodetector.Moreover, to achieve simple and stable coupling of an optical fibre to thephotodetector, a 63 µm deep and 128 µmwide trench is formed in the siliconchip. The p–i–n planar photodetector exhibits a high ηext of 25–29% witha low dark current of 0.5 pA m−2 and a high-frequency photoresponse of10.5 GHz (3 dB bandwidth) at a wavelength of 0.98 µm. A vertical-cavityp–i–n SiGe/Si photodetector in bonded SOI substrate has been reported toexhibit a high external quantum efficiency of 60% with a low dark currentof 0.5 pA µm−2 and a high photoresponse of 7.8 Gbit s−1 at λ = 980 nmas shown in figure 9.10.

Light emission has been observed in various structures, such as rareearth metal-doped Si, strained-SiGe quantum wells, porous-Si, quasi-directgap short period SiGe superlattices and Si quantum wires [71,72]. Si1−xGexquantum well structures exhibit type I band alignment, where most of theband offset occurs in the valence band when the Ge concentration is low.This type of structure allows for only holes to be effectively confined in


Figure 9.10. Frequency response of a photodetector at an area of 5000 µm2.A 3 dB bandwidth of 7.8 GHz is confirmed at 5 V reverse bias at λ = 980 nm.(After Morikawa T et al 1996 IEEE IEDM Tech. Dig. pp 661–4.)

the quantum wells, whereas to form a light emitter, it is necessary to havean asymmetric type II structure which confines electrons in the conductionband. Neighbouring confinement structures (NCS) using Si1−xGex havebeen developed [73]. NCS structures consist of a thick (>3 µm) Si0.82Ge0.18buffer in which a step-graded Si1−xGex layer with x ranging from 0 to 0.18is grown, and then capped with a uniform 2.5 µm Si0.82Ge0.18 layer. TheNCS structure is then grown on Si0.82Ge0.18 in which a tensile strained 10 ASi-only QW is grown for electron confinement, and a 10 A Si0.64Ge0.36 QWis grown for hole confinement. This structure allows for a nearly ‘direct’transition as evidenced by orders of magnitude enhancement of no-phononlow-temperature PL, as compared to SiGe QWs using type I and symmetrictype II QWs. The NCS technique, when coupled with growth on relaxed-SiGe buffers, is a promising approach in the production of Si-based lightemitters [71].

Some reports on Si1−xGex/Si quantum well infrared photodetectors(QWIP) have appeared [1,74]. An integrated waveguide photodetector, asshown in figure 9.11, deposited on a SIMOX substrate, has been fabricatedand an external quantum efficiency of 11% with an impulse response timeof 400 ps has been observed. For the mid-IR range (3–5 µm) highly p-doped


Figure 9.11. Schematic layout of a waveguide/detector device on a SIMOXsubstrate. (After Presting H 1998 Thin Solid Films 321 186–95.)

Si/SiGe QW detectors have been deposited on an undoped, double-sidedpolished Si substrate based on hetero-internal photoemission (HIP) overthe Si/SiGe barrier. The absorption and photocurrent spectra have beenmeasured from fabricated mesa detectors at 77 K. The photoresponsespectrum of the HIP detectors is found to be widely tunable in thetechnological important wavelength band of 3–5 µm by choice of Gecontent, well thickness and doping level. Quantum efficiencies of 1% at4 µm and 77 K have been achieved from SiGe HIP structures, dark currentsas low as 10 × 10−8 A cm−2 can be obtained by modulation doping.

The key features of a p-Si1−xGex/Si QWIP are shown in figure 9.12.The alloy layers are grown pseudomorphically on an Si substrate, and arecompressively strained. The alloy bandgap is smaller than that of Si for afully strained layer [75]. The higher density of states in SiGe subbandssuggests that SiGe QWIPs are inherently superior to AlGaAs QWIPs.Valence band technology is preferred for 8–14 µm SiGe/Si QWIPs becauseit allows normal incidence of light on the detectors. The polarization ofnormal light is always perpendicular to the growth direction of the QWlayers. Although low noise and good responsivity have been realized, a


Figure 9.12. Energy band diagram showing the shift of the absorption edges in asymmetrically strained-Si1−xGex/Si multiple quantum wells (MQWs). Electronsare confined in the wider bandgap of Si layers and holes are confined in thenarrower bandgap of Si1−xGex layers. E1 and HH1 are the minimum electronand hole energy levels in the quantum wells. L is the width of the quantum well.

long length in the waveguided diode is needed due to a low absorptioncoefficient. This long length tends to raise the parasitic capacitance of thedistributed diodes. It becomes difficult to obtain better responsivity athigher wavelengths as the stability of strained-SiGe QWs decreases rapidlyas the Ge fraction increases.

Photocurrent and absorption characteristics of SiGe QWs and SimGenSLS have been measured at room temperature by Presting [1]. Thewavelength-dependent photocurrent spectrum has been measured using agrating monochromator illuminated by a tungsten lamp, and the electricalsignal has been detected by a lock-in amplifier technique. When comparingthe absorption characteristics of the SLS and QW structures, it is evidentthat substantial absorption at 1.3 µm occurs for both structures. Thedifferent long wavelength absorption limits between the two were explained


Figure 9.13. Circuit diagram of a SiGe–Si p–i–n HBT photoreceiver. (AfterRieh J-S et al 1997 IEEE Photonics Technol. Lett. 10 415–7.)

by taking into account the different buffer layer thicknesses and Ge contentin the structures.

A monolithic SiGe/Si p–i–n HBT front-end transimpedancephotoreceiver circuit, as shown in figure 9.13, has been fabricated by Rieh etal [76]. Figure 9.13 shows the circuit diagram with a transimpedanceamplifier which consists of a photodiode, common-emitter gain stages, twoemitter follower buffers and a resistive feedback loop. For fabrication, amesa-type SiGe/Si p–i–n HBT technology was used. Fabricated HBTsshowed an fmax of 34 GHz with dc gain of 25. SiGe/Si p–i–n photodiodes,which share base and collector layers of HBTs, demonstrated a responsivityof 0.3 A W−1 at λ = 850 nm (incident optical power of 22 mW) ata reverse bias of 5 V, and steadily increased as the reverse bias wasincreased. The corresponding external quantum efficiency was 43%. Thebandwidth of the photodiode was about 450 MHz (see figure 9.14(a)).The frequency response of the monolithically integrated single-feedbackp–i–n HBT photoreceiver, excited with λ = 850 nm light, is shown infigure 9.14(b) and exhibited a bandwidth of about 460 MHz, which islimited by the bandwidth of p–i–n photodiode.

The integration of Ge photodetectors on silicon substrates isalso advantageous for various Si-based optoelectronics applications [77].Figure 9.15 shows the schematic diagram of an integrated p–n mesa


Figure 9.14. (a) Measured frequency response of the SiGe p–i–n photodiodeand (b) measured frequency response of the SiGe photoreceiver. The solid curvesshow the fit to the measured response. (After Rieh J-S et al 1997 IEEE PhotonicsTechnol. Lett. 10 415–7.)


Figure 9.15. A schematic diagram showing the optimized relaxed graded buffergrowth sequence with the Ge mesa photodiode on top. (After Samavedam S B etal 1998 Appl. Phys. Lett. 73 2125–7.)

photodiode. Integrated mesa Ge photodiodes on an optimized gradedrelaxed-SiGe buffer on Si showed a very low dark current of 0.15 mA cm−2.Capacitance measurements indicate that the detectors are capable ofoperating at high frequencies (2.35 GHz). The photodiodes showed anexternal quantum efficiency of 12.6% at 1.3 µm wavelength laser excitationin the photodiodes.

9.4. OPTICAL DEVICES WITH SIGEC AND GEC ALLOYS

Conventional Si Schottky photodiodes and MSM photodetectors operateat wavelengths in the UV and visible region (<700 nm) of the spectrum[78, 79]. Si photodetectors operating at an 830 nm wavelength have beenreported [80]. Normal incidence strained or relaxed SiGe and SiGeCp–i–n photodiodes have been studied by several researchers [46, 81, 82].Although these devices used a thin intrinsic layer of 800–4000 A, the

Optical devices with SiGeC and GeC alloys 335

external quantum efficiencies were less than 1%. These results show thatGe-rich SiGeC diodes have a higher photoresponse to 1.3 µm excitationthan Si-rich SiGeC diodes, because of the narrower bandgap of Ge-richSiGeC, and hence the larger absorption coefficient at a 1.3 µm wavelength.It was observed that the C blueshifted the photoresponse edge from thespectral response, suggesting that carbon increased the bandgap of the Ge-rich SiGeC alloys. This is consistent with the decrease of quantum efficiencywith the increase of carbon composition in p-GeC/n-Si photodiodes, whichagrees with the absorption studies [43]. However, SiGe and/or SiGeC MSMphotodiodes operating in the near-infrared or infrared wavelength regionhave not yet been explored.

p–n heterojunction photodiodes on epitaxial p-type Ge1−xCx filmswith carbon percentages of 0.2, 0.8, 1.4 and 2% on n-Si substrateshave also been studied. Photoresponse characteristics of the diodes areshown in figure 9.16. The photocurrents of the p-Ge0.992C0.008/n-Si, p-Ge0.986C0.014/n-Si, and p-Ge0.98C0.02/n-Si photodiodes under an appliedreverse bias of −20 V are 4.4, 4.0 and 2.6 µA, respectively, correspondingto external quantum efficiencies of 2.2%, 2% and 1.3%, respectively, for anincident power of 192 µW. The measured external quantum efficiencies atλ = 1.3 µm for different diodes are shown in figure 9.17. For the purposesof ηext comparison, data of a p–i–n diode using SiGeC films are shown.

Figure 9.16. The photoresponsivity of p-type Ge0.992C0.008, p-typeGe0.986C0.014 and p-type Ge0.98C0.02 on n-Si photodiodes. (After Shao X 1997Structural and electrical characterization of SiGeC and GeC alloys and theirapplication to optical detectors PhD Dissertation University of Delaware.)


Figure 9.17. The measured external quantum efficiency at λ = 1.3 µmfor the p-Ge1−xCx/n-Si photodiodes and compared to a SiGeC p–i–n diode.(After Shao X 1997 Structural and electrical characterization of SiGeC and GeCalloys and their application to optical detectors PhD Dissertation University ofDelaware.)

9.5. SIMULATION OF OPTOELECTRONIC DEVICES

For the design and simulation of photodetectors, an understanding ofthe behaviour of photogenerated carriers under the influence of drift anddiffusion is essential. The basic semiconductor equations, namely Poisson’sand current continuity equations for electrons and holes, are solved, alongwith a rate equation for the charged traps. Additionally, the opticalgeneration term Gopt and recombination term Ropt are incorporated inthe current continuity equations.

A general purpose two-dimensional drift–diffusion simulator, SEMICAD,capable of simulating a wide range of semiconductor devices, has been usedfor simulation purposes. Important optical parameters, namely the absorp-tion coefficient and refractive indices, were supplied. Several additionalmechanisms particularly applicable to optoelectronic devices are incorpo-rated. These comprise:

(i) dynamic capture and emission of carriers by multiple trap levels ofbulk and surface traps;

(ii) carrier generation due to light or other ionizing radiation; and(iii) quantum-mechanical tunnelling between traps.

Simulation of optoelectronic devices 337

The performance of a photodetector depends on the materialparameters, device structure and configuration, thickness of different layers,doping levels, ohmic contact at electrode boundaries and anti-reflectioncoating. The selected material should have a high absorption coefficientat wavelengths of interest, high carrier mobility, direct bandgap and thepossibility to tailor the bandgap for high quantum efficiency and widebandwidth.

Besides the material selection, other important issues include:

(i) reduction of surface reflection loss by using a transparent anti-reflective coating on the incident surface;

(ii) for high detection efficiency, absorption at the depletion layer shouldbe large by increasing the depletion width;

(iii) to improve the efficiency and noise performance, generationrecombination of the carriers in the depletion region should be small;

(iv) to minimize the transit time, depletion width should be narrow; and(v) to reduce the capacitance, detector area should be small.

Clearly an element of design trade-off is necessary to balancethese somewhat conflicting requirements. In addition to the aboveconsiderations, the device time response is controlled by the external circuitcomponents. For a good frequency response, both the capacitance andresistance need to be minimized, by reduction in area. However, if thedepletion width is increased too much, the device is limited by the transittime effects. The transit time, ttr is controlled by the width of depletionregion and the saturation velocity, vs of the carriers, and is given by

ttr =W

vs. (9.12)

For a high-frequency response, optimization of the depletion width isnecessary. In simulation, the basic semiconductor equations—Poisson’s,the current continuity equations for electrons and holes and a rateequation for the charged traps—need to be solved for the determinationof electrostatic potential and total carrier concentration in the structure.These have been discussed in detail in chapter 4. Additionally, anoptical generation term Gopt and the recombination term Ropt mustbe incorporated in the continuity equations for the analysis of p–i–nphotodetectors. Two of the three recombination mechanisms, Shockley–Read–Hall (SRH) and Auger recombination, have been considered inchapter 4. The additional optical recombination rate term in the currentcontinuity equations due to the creation of photons is given by

Ropt = Coptc(np− n2io

)(9.13)

where Coptc is the optical capture rate.


The rate of carrier generation due to photon absorption is calculatedfrom the rate of decay of the photon flux. For a spatially uniform absorptioncoefficient, the photon flux, φopt decreases exponentially with distance as

φ = φopt exp (−αy) . (9.14)

The initial photon flux can be calculated from the incident optical powerdensity and from the wavelength as

φopt =Popthν

(9.15)

where h is Planck’s constant and ν is the optical frequency.The generation rate of photo carriers can be expressed as

Gopt = −dφdy

= αφ (9.16)

where dy is the differential distance along the direction of propagation of theincident beam and α is the absorption coefficient. The quantum efficiency, ηis calculated from the equivalent beam current at unity quantum efficiency[83] and is given by

η =IaIeq

(9.17)

where Ia is the p–i–n diode terminal current and Ieq is the equivalentbeam current at unity quantum efficiency. The responsivity is the ratio ofphotocurrent and incident optical power and is obtained from the externalquantum efficiency. The diode capacitance can be computed from small-signal ac analysis using y-parameters in a similar manner to that describedin chapter 4.

9.5.1. PtSi/SiGe Schottky photodetectors

In this section, we compare the performance of a PtSi/Si1−xGex Schottkydiode with that of a PtSi/Si Schottky diode. The structure consideredfor simulation is a cylindrical Schottky diode of 1 µm radius. The topSi1−xGex epitaxial layer is grown on a graded Si1−yGey (y : 0 → x) layer.The graded layer prevents the formation of a parasitic hole barrier at thesubstrate/Si1−xGex interface. The thicknesses of both graded and epitaxiallayers are 500 A. An ohmic contact has been taken from the back side ofthe photodetector. The power of the incident beam normal to the frontside of the diode has been taken to be 10 µW.

Figure 9.18 shows the simulated photoresponse characteristics of aPtSi–Si1−xGex Schottky diode with that of a PtSi/Si Schottky diode ofidentical geometry, in the wavelength range of 2–8 µm. It is seen fromfigure 9.18 that the maximum value of responsivity in the wavelength range


Figure 9.18. Simulated photoresponse of PtSi/Si1−xGex and PtSi/Si infraredSchottky photodetectors. (After Chattopadhyay S and Maiti C K, unpublisheddata.)

considered here is 0.106 A W−1, and in the 8 µm wavelength region thediode has a responsivity of approximately 0.032 A W−1. For comparison,the spectral response of a PtSi/Si Schottky diode has also been simulated.It is seen from figure 9.18 that a PtSi/Si1−xGex Schottky diode has a higherresponsivity than a PtSi/Si Schottky diode. Above a wavelength of 5 µm,the responsivity of the PtSi/Si Schottky diode is negligible. The cut-offwavelength of PtSi/Si1−xGex is also higher than that of a PtSi/Si Schottkydiode. This is expected as the PtSi/Si1−xGex diode has a lower barrierheight. The reduction of barrier height of the PtSi/Si1−xGex Schottkydiode is responsible for the detection of a longer wavelength.

It is also evident in figure 9.18 that the computed results agree wellwith the reported experimental results for a similar structure [53]. Also, thesimulated responsivity is comparable to the highest reported responsivitiesfound in Si/Si1−xGex hetero-internal photodetectors [84,85].


Figure 9.19. (a) Schematic structure of Si0.7Ge0.3 p–i–n diode; (b) computedband diagram; (c) doping profile; (d) electric field; and (e) optical generation.(After Chattopadhyay S et al 1999 Solid-State Electron. 43 1741–5.)

Figure 9.20. p+–Si–n−(SiGe)–n−(SiGe) photodiode structure. (After Lee J etal 1995 Appl. Phys. Lett. 66 204–5.)


Figure 9.21. Dark current versus reverse voltage characteristics of Si1−xGexp–i–n photodiodes: (a) x = 0; (b) x = 0.2; (c) x = 0.3. (After Chattopadhyay S etal 1999 Solid-State Electron. 43 1741–5.)

9.5.2. SiGe p–i–n photodetectors

A schematic structure of a SiGe p–i–n photodiode considered for simulationis shown in figure 9.19(a). The diode has a Si1−xGex cylindrical-shapedintrinsic layer typically 1–3 µm thick on an n+–Si substrate. The top andbottom surfaces have radii of 70 µm and 90 µm, respectively, with anaverage area of 2 µm× 104 µm. Electrical contacts are taken from the topand bottom surfaces [86]. The structure shown in figure 9.20 was consideredfor simulation as there are reliable experimental data for a similar structure[87,88]. At a reverse bias of 5 V, the computed energy band diagram for anSi1−xGex (x = 0.30) photodiode is shown in figure 9.19(b). Figures 9.19(c)and (d) show the doping concentration and electrical field across the diode,respectively. The optical carrier generation in the photodiode is shown infigure 9.19(e).


Figure 9.22. Computed spectral response of Si1−xGex p–i–n photodiodes for:(a) x = 0; (b) x = 0.1; (c) x = 0.2; (d) x = 0.3; (e) x = 0.5; (f) x = 0.75. (AfterChattopadhyay S et al 1999 Solid-State Electron. 43 1741–5.)

Figure 9.21 shows the dark currents in three photodiodes (Si, Si0.8Ge0.2and Si0.7Ge0.3) of identical geometry with a 1 µm thick intrinsic layer. Itis seen from figure 9.21 that the dark current increases as the Ge molefraction is increased. This is attributed to the decrease of bandgap due tothe increase in Ge content in the intrinsic layer. For a 30% Ge content inthe i-layer, the value of the dark current is in the nA range and saturatesat a reverse bias of about 3 V or above.

Figure 9.22 shows the computed responsivities of Si1−xGexphotodiodes of different Ge concentrations (x = 0.0, 0.1, 0.2, 0.3, 0.5 and0.75) as a function of wavelength (0.6–1.5 µm). It is seen from figure 9.22that the cut-off wavelength of the photoresponse curves increases as Gecontent in the absorbing i-layer increases. It is observed that the cut-offwavelengths for x = 0.0 (i.e., for Si) and for x = 0.75 are about 1.10 µmand 1.50 µm, respectively. This is due to the fact that, as the Ge content


Figure 9.23. Simulated photoresponse of an Si1−xGex p–i–n photodiode for:(a) x = 0.1 and (b) x = 0.3. (- - - -) computed and (——) experimental. (AfterChattopadhyay S et al 1999 Solid-State Electron. 43 1741–5.)

is increased in the i-layer, the bandgap decreases which in turn extends theabsorption tail towards the higher wavelength region.

The reported experimental value of the photoresponse for Si1−xGexp–i–n photodiodes (x = 0.08–0.69) in this wavelength range is about0.4–0.5 A W−1 [87, 88] and is compared with simulation results infigure 9.23 for x = 0.1 and 0.3. The agreement is found to be verygood. Photoresponse characteristics of a constant Ge content (x = 0.30)photodiode as a function of i-layer thickness (1.0, 1.5, 2.0 and 2.5 µm) areshown in figure 9.24 in the wavelength range of 0.6–1.4 µm. It is seen that,for a particular wavelength of the incident photon, responsivity increaseswith the thickness of i-layer. This is obvious because as the i-layer thicknessincreases, more incident photons get absorbed in the thicker i-layer regionwhich in turn generates more photo-carriers.


Figure 9.24. Plot of photoresponse versus wavelength of an Si0.7Ge0.3 p–i–ndiode for different i-layer thicknesses. (After Chattopadhyay S et al 1999Solid-State Electron. 43 1741–5.)

Figure 9.25 shows the variation of the reverse capacitance of a 30% Gecontent photodiode as a function of i-layer thickness. The capacitancedecreases with the increase in i-layer thickness at a particular reversebias. Figure 9.26 shows the variation of computed dark capacitance ofan Si1−xGex p–i–n photodiode having a 1 µm i-layer thickness for differentGe mole fractions (x = 0.10, 0.20 and 0.30). It is seen that for a particulari-layer thickness, the dark capacitance increases as the Ge content in thei-layer increases, as expected. The capacitance of a p–i–n diode is basicallythe depletion capacitance and it is clear from figure 9.26 that above 1 Vreverse bias, the diode has a capacitance in the range 2.3–2.5 pF. Such a lowvalue of depletion capacitance is essential for ultra high-speed applications.


Figure 9.25. Variation of capacitance with applied reverse bias of an Si0.7Ge0.3p–i–n diode for: (a) W = 1.0 µm; (b) W = 1.2 µm; (c) W = 1.5 µm and(d) W = 2.0 µm. (After Chattopadhyay S et al 1999 Solid-State Electron. 431741–5.)

9.5.3. MSM photodetectors

The schematic view of an interdigitated MSM photodiode consideredfor simulation is shown in figure 9.1(a). Due to the symmetry of thestructure of the MSM photodiode, the region chosen for analysis is shownin figure 9.1(b). Spacing between the positive electrode (anode) and thegrounded electrode (cathode) is 2 µm and the finger widths are takento be 1.5 µm. The responsivity and other important parameters of arepresentative unit cell of the device, in which the illumination is uniform,have been simulated. The responsivity has been calculated assumingthe beam to be centred within the unit cell and the metallic fingers arecompletely transparent.


Figure 9.26. Variation of capacitance with applied reverse bias of an Si1−xGexp–i–n diode for: (a) x = 0.1; (b) x = 0.2 and (c) x = 0.3. (AfterChattopadhyay S et al Solid-State Electron. 43 1741–5.)

Metal fingers on the surface of MSM photodetectors form a Schottkybarrier between the metal and semiconductor and therefore there will be avoltage-dependent depletion region beneath the metal fingers. Figure 9.27shows the computed depletion layer capacitance as a function of biasvoltage for Si and Si0.80Ge0.20 MSM photodetectors. An active area of500×500 µm of the photodetector was considered. The capacitance valuescomputed at 1 MHz for both detectors show an increase in depletioncapacitance with increasing bias voltage, due to the fact that the absorptionlength exceeds the depletion layer width. At high bias voltage, thedependence of capacitance on voltage is weak. As seen from figure 9.27, thevariation of capacitance with voltage of Si0.80Ge0.20 MSM photodetectoris similar to that of Si MSM-PDs. Si0.80Ge0.20 MSM photodetectors showa slightly higher capacitance because of the higher dielectric constant ofSi0.80Ge0.20.


Figure 9.27. Computed capacitance versus applied voltage for (a) Si and (b)Si0.80Ge0.20 MSM photodetectors. Detectors have an active area of 500×500 µmwith 1.5 µm finger width and 2 µm finger spacing. (After Chattopadhyay S andMaiti C K, unpublished data.)

Computed dark and photo currents for Si, Si0.80Ge0.20 and Si0.70Ge0.30MSM-PDs are shown in figure 9.28. The dark current I–V characteristicsare typical for a back-to-back Schottky contact. The Si0.80Ge0.20 MSM-PDshave higher dark current compared to Si, increasing with the increase inGe concentration in the Si1−xGex epitaxial layer. Si has a dark current of15 µA at 8 V and Si1−xGex has a dark current of 60 µA (x = 0.2) and95 µA (x = 0.3) at 6 V.

Figure 9.29 shows the plot of computed responsivities of an SiMSM-PD in the wavelength range 0.4–1.20 µm for different voltages (1, 3and 5 V). An active area of 500 Kc ×500 µm, a finger spacing of 2 µm anda finger width of 1.5 µm were simulated. It is seen that the photoresponsesare strongly dependent on applied reverse bias. It is expected that thecut-off wavelength of an Si MSM-PD will correspond to its bandgap energy.Figure 9.30 shows the plot of computed responsivities of an Si1−xGex MSM-PD in the wavelength range 0.4–1.40 µm, for different values of x (0.10, 0.20and 0.30) at 3 V. As shown in figure 9.30, the responsivity drops rapidly


Figure 9.28. Dark and photo currents versus applied voltage of Si and Si1−xGexMSM photodetectors. The detectors have an active area of 500 × 500 µm with1.5 µm finger width and 2 µm finger spacing. (After Chattopadhyay S andMaiti C K, unpublished data.)

as photon energy decreases close to bandgap energy, while at a particularwavelength responsivity increases with increasing Ge content.

Figure 9.31 shows the variation of computed responsivity withwavelength for different finger widths and spacings. Curve a shows theresponsivity of an Si0.8Ge0.2 MSM photodiode for a finger width of 1.5 µmand spacing 2 µm while curve b shows the responsivity a for finger widthand spacing of 2 µm and 1 µm, respectively. From curves a and b, onenotices that the responsivity does not change much. Curve c shows theresponsivity of an MSM-PD with the same Ge content but the fingerwidth and spacing were 2 µm and 1 µm, respectively. We see that theresponsivity has increased significantly. This is due to the increase of theactive area, which in turn increases the depletion area underneath the metal


Figure 9.29. Plots of responsivity versus wavelength of an Si MSMphotodetector at different voltages. The area of the detector is 500 × 500 µmwith a finger width of 1.5 µm and a spacing of 2 µm. (After Chattopadhyay Sand Maiti C K, unpublished data.)

fingers. Figure 9.32 shows the responsivity variation of an Si0.8Ge0.2 MSM-PD with different thicknesses of top absorbing layer. It is seen that theresponsivity increases as the top absorbing layer thickness under the metalfingers increases. This is expected because a thicker layer will absorb morephotons, which in turn increases the photocurrents.

The Si1−xGex MSM-PDs have a dark current which increases with theincrease in Ge concentration. Si has a dark current of 10 µA at 6 V andSi1−xGex has dark currents of 60 µA (x = 0.2) and 90 µA (x = 0.3, notshown in figure 9.32) at 6 V. Si MSM-PDs have a peak photoresponsivityof 0.60 A W−1 at 0.72 µm at an applied voltage 5 V. Si0.80Ge0.20 PDshave peak responsivities of 0.76 A W−1 at 0.80 µm at an applied voltageof 3 V while Si0.70Ge0.30 MSM-PDs have the responsivity of 0.88 A W−1


Figure 9.30. Plot of responsivity versus wavelength of an Si1−xGex MSMphotodiode at 1 V for different Ge mole fractions: (a) x = 0.1; (b) x = 0.2;(c) x = 0.3. The area of the diode is 500× 500 µm with finger width and spacingof 1.5 µm and 2 µm, respectively. (After Chattopadhyay S and Maiti C K,unpublished data.)

at the same conditions. Si PDs have a cut-off wavelength of 1.10 µm whichcorresponds to its bandgap energy. The cut-off wavelength of SiGe PDsvaries with Ge mole fraction. For a 30% Ge content, the cut-off wavelengthis about 1.3 µm.

9.5.4. SiGe/Si waveguide photodetectors

The influence of various design parameters in determining the externalquantum efficiency of waveguide detectors based on Si/Si1−xGex/Sistrained layer superlattices, for use in optical communications at λ =1.3 µm has been studied in detail by Naval et al [89]. The authors havepresented an algorithm that automatically generates structurally stable


Figure 9.31. Photoresponse characteristics of an Si0.80Ge0.20 MSM-PD fordifferent geometry: (a) W = 1.5 µm, S = 2.0 µm; (b) W = 2.0 µm, S = 1.0 µm;(c) W = 2.0 µm, S = 2.0 µm, with an active area of 500 × 500 µm. (AfterChattopadhyay S and Maiti C K, unpublished data.)

SLS. The simulation includes various design parameters such as opticalwaveguiding, absorption, quantum size effect as well as thermodynamicsof the strained layers. A conservative model for the critical thickness, hc,corresponding to the equilibrium regime has been shown to be importantfor relatively high Ge content, necessary to achieve moderate efficiency.Limiting the superlattice thickness and detector length to 1 µm and 1 mm,respectively, yielded discrete maximum values for ηext (around 12%) andηint (around 30%) that were mainly dependent on the alloy absorption.A more optimistic model for hc, corresponding to the metastable regime,produced considerably higher ηext (around 60%), which shows the greatimportance of fibre-to-waveguide coupling efficiency. The importance ofthe passive waveguide coupler geometry was investigated using the beampropagation method.


Figure 9.32. Photoresponse characteristics of an Si0.80Ge0.20 MSM photodiodefor different absorbing layer thicknesses at 1 V applied bias. (AfterChattopadhyay S and Maiti C K, unpublished data.)

9.6. SUMMARY

The highly-developed Si technology makes SiGe and other group IV alloys,ideal materials for realizing optical devices in the near-IR as well asin the mid- to far-IR regime, monolithically integrated with electronicdriver circuits for optical communication systems. In this chapter, recentdevelopments and the possible applications of group IV (SiGe, GeC, SiGeC,SiGeSnC and strained-Si) alloys in optoelectronics for integrated circuitsentirely on silicon have been discussed. Photoresponsivity and refractiveindex data obtained from experimental SiGe, SiGeC and GeC photodiodeswere presented. Simulation results, obtained using a 2D heterostructuredevice simulator, for PtSi/Si1−xGex and PtSi/Si Schottky photodetectorsin the wavelength range of 2–8 µm, have been presented. It was found

Bibliography 353

that the PtSi/Si1−xGex photodetectors offer superior responsivity andhigher cut-off wavelength compared to conventional PtSi/Si Schottkyphotodetectors. Simulation results compare favourably with reportedexperimental results.

Responsivity, dark current and cut-off wavelength of an Si1−xGexp–i–n photodetector increase with increasing Ge mole fraction in theabsorbing i-layer and cover a wavelength range of 1.10–1.50 µm as the Gemole fraction increases from 0.0 to 0.75. Simulated high responsivity, lowdark current (in the range of nA) and low capacitance suggest that thesedetectors are good candidates for infrared light detection in the wavelengthrange of 1.30–1.50 µm. The photoresponse of Si1−xGex MSM-PDs hasbeen found to increase with increasing Ge mole fraction. However, thedark current of a SiGe detector is higher than that of an Si photodetector.Due to lack of experimental data, no comparison could be made for SiGeMSM-PDs. It was also observed that the responsivity increases with theincrease of the absorption layer thickness underneath the metal fingers.However, the main hindrance for a total Si-based integrated optic solutionis the lack of a sufficiently intense Si-based transmitter at 1.3 µm.

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Chapter 10

RF APPLICATIONS OF SIGEHBTS

The revolution in wireless communications has been brought about bythe recent advances made in the areas of digital integrated circuits, radiofrequency components and circuits, digital communications and networkingtechniques. Mobile communication is now the fastest growing consumerelectronics segment in all parts of the world. Digital services, internetand multimedia are all becoming mobile. The last few years have seena remarkable expansion in the use of cellular and cordless phones andother personal communication systems and, as a result, the demand fortransceivers with small size, fewer off-chip components, better integrationand low operating voltage has increased dramatically. According to themarket research firm Dataquest, the production of wireless devices isexpected to grow to over 450 million units annually by the year 2002. Theopportunity for chips that process radio frequency signals alone is expectedto reach $7 billion by 2002. A recent US Department of Commerce reportindicates that global positioning satellite (GPS) equipment sales will reach$16 billion in 2003.

RF communication systems can be broadly classified into two sectors,namely ‘low-end’, such as pagers, cordless phones etc, and ‘high-end’,such as PCS, GSM, IS-136 etc. DECT (digital enhanced cordlesstelecommunications) is also an acknowledged standard in many countriesall over the world, replacing conventional analogue systems for wiredand cordless telephones. DECT holds substantial promise for residentialcordless, wireless PBX and wireless local loop (WLL) applications. Thishigh-performance micro-cellular technology is a particularly attractiveWLL alternative in areas where laying a wired infrastructure posesproblems, or in urban areas where traditional cordless telephones areoverburdened. The DECT standard specifies that communications willbe done in a frequency band with a bandwidth of 17 MHz centred at

359

360 RF applications of SiGe HBTs

Table 10.1. Comparison of wireless communications standards.

Frequency Channel Maximum user PowerStandard System band BW/SP average peak

GSM Cellular 900 MHz 200 kHz 250 mW 2 WAMPS Cellular 800 MHz 30 kHz 600 mW 600 mWPACS PCS-TAG-3 1.9 GHz 300 kHz 25 mW 200 mWPCS-1900 PCS-TAG-5 1.9 GHz 200 kHz 125 mW 1 WIS-136 PCS-TAG-4 1.9 GHz 30 kHz 200 mW 600 mW

approximately 1.89 GHz, making it a narrowband communications systemwhich requires a peak output power of 250 mW.

In the United States and Canada, the 902–928 MHz ISM (industrial–scientific–medical) frequency band has been established as a licence-freespectrum, for use by low-power communication devices such as cordlesstelephones. The ISM standard specifies operation from 902–928 MHzand 1 mW transmitted power. Table 10.1 summarizes the specificationsfor some of the wireless communications systems presently in use. It isclear that a variety of frequencies, modulation schemes and output powerrequirements have proliferated on a worldwide basis, and that no one singlestandard or frequency can be expected to dominate wireless data systemsfor the foreseeable future. Instead, in order to address a broad market,radio transceivers must increasingly satisfy the competing constraints offlexibility and low cost [1].

Present wireless communication systems, in the frequency range0.8–2.5 GHz, will require integrated low-noise front-end circuits, activefilters, wideband AGC amplifiers, AD/DA converters, mixers, synthesizerswith voltage controlled oscillators and power amplifiers. The circuits arebattery operated and must function at relatively high currents and lowvoltages. While integration in the baseband has been pursued relentlesslyresulting in very high density circuits, attention has only recently beenfocused on radio frequency integrated circuits (RFICs) for communication.

The standard transceiver architecture for most wireless systems hasso far been based on the superheterodyne principle since its initialdevelopment by E Armstrong in the early 1900s. In this configuration, theradio signal received at the receiving antenna is sent to a low-noise amplifier(LNA), whose purpose is to boost the signal level without reducingthe signal-to-noise ratio significantly. Following the LNA, the signal ispassed through a mixer, which essentially multiplies the input signal by alocal oscillator signal of constant frequency, producing an output signal,whose frequency is the difference between the two inputs, the so-called

RF applications of SiGe HBTs 361

‘intermediate frequency’ (IF), the amplitude of which is proportional to theoriginal input signal. Preceding the mixer, an analogue filter eliminatesthe response to an undesired input signal at (2flo–frf) that would alsodownconvert to the intermediate frequency. This ‘image reject’ filter istypically implemented with a physically large surface acoustic wave (SAW)filter.

The basic limitation of the traditional frequency translating mixersand the heterodyne architecture is their sensitivity to ‘spurious responses’resulting from nonlinearities in the preceding amplifier and mixer. Inhighly integrated transceivers, one may allow these filters to be dispensedwith, significantly reducing the power dissipation and the physical size.The spurious responses must be carefully controlled through bulky andexpensive off-chip filters which are not suitable for monolithic integration,the key to lower power operation.

Significant improvements in the area of receiver architecture havebeen made recently by the use of quadrature signal processing techniques,also known as the Hartley phasing method and ‘direct downconversion’or homodyne approaches for wireless receivers, which eliminate theneed for image rejection filters and are better suited to monolithicintegration. However, the direct conversion receiver has not gainedwidespread acceptance due to its intrinsic sensitivity to dc offset problems,even order harmonics of the input signal that interfere with the desiredsignal, and local oscillator leakage problems back to the antenna whichare being actively pursued by several research groups. Several excellentreviews of research in this field are presented in [2, 3]. Rudell et al [4]have reported an interesting variation in the superheterodyne/homodynereceiver architecture using the wide band IF double conversion technique.

Field-effect transistors in III–V semiconductors have so far been theworkhorse of the microwave industry because of their excellent high-frequency performance and, with the introduction of heterojunction FETs,low noise figures. The integration of highly complex digital circuits onGaAs is often prohibitive because of cost, limited wafer sizes, processingcomplexities and poor yield. A current solution to this problem is to mixGaAs and Si technologies using a multichip module (MCM) platform. ButGaAs monolithic microwave integrated circuits (MMICs) are expensive andthere are difficulties associated with high pin count flip-chip solder bonding.

Silicon, although not traditionally the material of choice for RFand microwave applications, has become a serious challenger to othersemiconductor technologies for high-frequency applications. Passivemicrowave components have been demonstrated on high resistivity siliconsubstrates. Arnold and Pedder [5] reported transmission lines and spiralinductors working at microwave frequencies on high resistivity substrates.Fine-line electron beam and photolithographic techniques are now capableof fabricating geometries as small as 0.1 µm while high resistivity silicon


wafers support low loss microwave transmission lines.An integrated Si-based MMIC technology circumvents some of the

difficulties encountered in III–V material systems, offers improved thermalmanagement by virtue of a higher thermal conductivity, and the designcapabilities of CMOS for complex logic circuits and more compact modules.All-Si MMIC technologies have been investigated previously. Hanes et al [6]have reported such a technology, based on the SIMOX process with highresistivity substrates, and obtained a maximum frequency of oscillation of32 GHz.

Evidence from the literature suggests that the impedance of a highresistivity (104 Ω cm−1) Si substrate will allow microwave/millimetrewave operation, although it is anticipated to be a more difficult designconsideration than the GaAs MMICs. Surface pinning, which is a featureof GaAs, does not occur in Si which may offer some advantage in terms ofreducing parasitic capacitances.

These advances, coupled with SiGe, open the possibility of siliconintegrated circuits (ICs) with the speed required for increasingly higher-frequency applications. Manufacturing costs are the key to SiGe success,which are about one fifth of the costs of GaAs for equivalent performance[7]. Applying SiGe does not mean using a completely new process as thetechnology and manufacturing are very similar to well-proven methods, buthave considerably extended features.

A complete RF transceiver (see figure 10.1), including VCO andsynthesizer, has been integrated on one chip. A second IC, implemented

Figure 10.1. A schematic diagram of an RF transceiver including SiGefront-end. (After Bopp M et al 1999 IEEE ISSCC Tech. Dig. pp 68–9.)

SiGe: perspective for wireless communication 363

in SiGe technology, includes an LNA in the receive path as well as a poweramplifier for the transmit path and a driver for an external PIN diodeswitch [8].

The circuit configurations for the LNA, oscillator, mixer and thedevices selected must be such as to ensure low power and low noise. Since ina portable wireless environment all circuits are drawing power from a smallbattery, it is clear that one of the most important aspects of the circuitsthat needs to be optimized is power consumption. Additionally, since thesedevices must be used in a low-cost product, the cost of the circuits mustbe lowered as well.

High-quality microwave switches are a key building block ofcommunication systems as they perform the crucial task of switchingbetween the transmit and receive modes. Microwave switches arecommonly realized with high-quality p–i–n diodes. However, the largecontrol currents required by these devices have traditionally necessitatedthe use of GaAs FET-based switches for most hand-held applications, dueto their low dc power consumption [9]. In contrast, a SiGe switch designedto be part of a transceiver front-end for DECT and DCS-1800 applications,requires no external dc bias and gives 25 dB receiver insertion loss at theoperating frequency, with 25 dB isolation [10].

Discrete passive components dominate in the RF part. Morethan 90% of all components are passive, and roughly 70% of the costcomes from these. The level of integration is increasing, but themost space consuming components—filters, resonators, matching circuitry,oscillators—are difficult to integrate. Capacitors, resistors and inductorsare needed for biasing, bypassing, and interference filtering. The use ofintegrated spiral inductors in many RF applications can reduce the numberof external elements and, by using the appropriate design technique, theoverall noise behaviour of the circuit is minimized.

10.1. SIGE: PERSPECTIVE FOR WIRELESS COMMUNICATION

In the beginning, SiGe HBT technology was investigated with a viewto high-speed digital applications, which is the area that best fits SiGeHBTs with low base resistance, low noise, excellent high-frequency responseand large gain-bandwidth product. A 12-bit digital-to-analogue converter,designed and produced jointly by IBM and Analog Devices [11,12] was thefirst commercially available SiGe IC until 1997. At that time, it matchedthe speed of the best such circuits built using GaAs technology, whileoperating at a lower voltage. This 1 Giga samples/s chip utilized 2854 SiGeHBTs and 1465 polysilicon resistors with three levels of metallization.

In the intervening years, other companies such as TEMICSemiconductors, Daimler–Chrysler and Hitachi have clearly demonstrateda high-performance SiGe HBT technology, now capable of mass production.


As of 2000, SiGe-based HBTs exhibiting fT and fmax values above 100 GHz(values which are 50% higher than the best Si BJTs, but some two to sixtimes lower than the best GaAs devices). Only five years previously, manyapplications such as optical networks and wireless RF technology in the1–20 GHz range, which had been difficult to achieve with conventionalCMOS and bipolar technologies, were demonstrated with SiGe HBTtechnology, as evidenced by reports of circuits for 20 Gb s−1 opticalnetworks [13] and RF wireless circuits up to 24 GHz [14–17]. At thattime, the availability of SiGe BiCMOS technology [18], with both veryhigh-performance HBTs with fmax of 60 GHz and 0.25 µm Leff CMOS forlogic and memory, offered the possibility of combining analogue and digitalcomponents on the same chip in a new ‘single chip’ architecture.

The first evidence that SiGe HBT technology can successfully competewith GaAs technology in the rapidly emerging wireless communicationmarket, with comparable performance in high volume production, was firstdemonstrated by Harame et al [19] using a commercial UHVCVD systemfor SiGe film growth. Within five years, this technology has matured toa volume production, very high-performance SiGe BiCMOS process [20]which can be tailored for low-voltage, low-power RF and mixed-signalapplications. The utilization of SiGe has modified the original marketsplit between silicon and GaAs technology and allows for a silicon-basedtechnology to address existing wireless communication market applications,as well as future requirements in the 5700–5800 MHz ISM band.

The figures-of-merit that apply to SiGe HBTs for use in wirelesscommunication ICs are:

• cut-off frequencies beyond 100 GHz are possible;• maximum frequency of oscillation beyond 100 GHz demonstrated;• high transconductance and output resistance provide high voltage

gain;• high current density and high breakdown voltage combine for high

output powers, particularly under pulsed condition;• low 1/f corner frequency, low noise, and high nonlinearity provide

excellent oscillator and mixer performance;• high power added efficiency.

The SiGe process provides the designer with additional benefits:

• vertical npn HBTs having a small emitter size;• lateral homojunction pnp;• three types of resistors;• nitride capacitors with high specific capacitance;• on-chip spiral inductors with high-quality factors for the 1–10 GHz

range;• ESD structures to avoid damage to the IC;

SiGe: perspective for wireless communication 365

• cost-effective solutions as SiGe does not sacrifice the economies ofsilicon manufacturing; and

• high power output makes designs feasible which are now possible inGaAs only.

SiGe HBT bipolar/BiCMOS technology has a unique opportunityin the wireless marketplace because of its high-performance andintegration/cost benefits of silicon bipolar/BiCMOS [21]. It has been shownthat low-noise operation, unparallelled in other bipolar devices, can beobtained in Si/SiGe double HBTs. A microwave noise figure below 1 dB at10 GHz has been reported [22,23]. Typical applications include integratedRF front-ends where low-noise amplification is desired in addition to lowphase-noise oscillation and mixing which typically benefit from bipolardevices.

SiGe HBT technology is also ideally suited to other analogueapplications. These include high bandwidth amplifiers, mixers and voltagecontrolled oscillators, all key functions for radio frequency and low-endmicrowave communication systems. Power added efficiency (PAE), a keyfigure-of-merit for high bandwidth amplifier design, has been measured tobe as high as 70% in SiGe HBTs, nearly double that of silicon junctiontransistors and comparable to the figure-of-merit for GaAs MESFETs.Transistor noise often constrains the design of communication systems.Measurements of SiGe HBTs indicate that for low-frequency (less than10 kHz) and high-frequency (2–10 GHz) noise, they are comparable tothe best available GaAs devices. The microwave noise performance ofSiGe HBTs has been evaluated on-wafer, for frequencies ranging from 2to 26 GHz with corner frequencies as low as 300–400 Hz. Noise figures of0.6 dB at 2 GHz and 1.2 dB at 10 GHz were found to be among the lowestreported for bipolar transistors in general.

SiGe technology provides easy access to different integrated active andpassive devices. For high-frequency applications, most important are theSiGe HBT itself and the passive inductor, capacitor, and transmission lineelements that are the key to RF design. Current gain, Early voltageand noise properties of SiGe HBTs are better compared to FETs andother bipolar technologies, resulting in a better phase noise performance inmixers and VCOs. The 1/f noise has an extremely low corner frequencyfor SiGe HBTs. For high-power applications, high gain, good efficiencyand linearity are also obtained in SiGe. Table 10.2 shows a wide varietyof circuits that have been demonstrated in the SiGe technology, showingthe versatility of the technology and demonstrating performance and/orpower improvement compared to other fabrications. BiCMOS also reducescomponent count and improves overall system performance by combiningoptimized functional blocks using either bipolar or CMOS [9].


Table 10.2. Demonstrated circuits using SiGe technology. (After Subbanna S etal 1999 IEEE ISSCC Tech. Dig. pp 66–7.)

Circuit type

Performance Year Process

D/A converter

12-bit, 1.2 Gbits s−1, 750 mW 1994 ADI/IBM

Frequency divider

Divide-by-128, 6.4–23 GHz, 1.5W 1995 NORTEL/IBMDivide-by-8, up to 50 GHz, 226 mW FF−1, 5.5 V 1998 Hitachi

Return-to-zero comparator

5 GHz, 1.5 V, 89 mW 1995 NORTEL/IBM

Monolithic VCO

12 GHz, l9 dBm, 5% tuning, −80 dBc phase noise 1996 Hughes/IBM17 GHz, −110 dBc, on-chip LC resonator 1997 IBM

Active mixer

12 GHz, >0 dB gain @ +3 dBm LO 1996 Hughes/IBM

ECL ring oscillator

6.7 ps, 0.25 V swing at 1.3 mA, 400 mV swing 1999 Hitachi

ECL ring oscillator

13.7 ps, 8 mA/stage, 200 mV swing 1995 Philips

LNA

2.4 GHz, 10.5 dB gain, 0.95 dB NF 1996 NORTEL/IBMPCS CDMA, 12 dB gain, 13 dB NF, 3 V/5 mA, 1999 IBMIIP3 > +10 dBmDECT, 1.8 GHz, 20 dB gain, 1.8 dB NF 1998 TEMIC

Broadband amplifier

8 dB gain, 17 GHz BW, 16.8 mA @ 2.5 V 1996 NORTEL/IBM35 GHz BW, 270 mW 1998 Hitachi

Timing circuit

10 Gb s−1, 150 mA @ 5 V 1996 NORTEL/IBM

Power transmitter

2.4 GHz, 1W Pout, 48% PAE, 1998 IBM3.5 V, @ 1.5 V 150 mW Pout W, 47% PAE

Technology comparison 367

Table 10.2. (continued)

Circuit type

Performance Year Process

Power amplifier

Tx, 900 MHz, 70%PAE, 16 dB gain 1997 IBM30 dBm, 16 dB gain, 75% PAE, 3.5 V 1999 IBM27 dBm, 26 dB gain, 1998 TEMIC45% PAE, 3.6 V, 1.9 GHz

CMOS ASIC

chip 1998 IBM

Multiplexer

2:1, 40 Gb s−1 output 1998 Hitachi

Demultiplexer

1:2, 60 Gb s−1 output 1997 Siemens

5.5 GHz LNA

14.1 dB gain, 2 dB NF 1998 IBM

Mixer, VCO

Mixer: 16.4 dB Power conversion gain,IIP3 11.1 dBm, NF 6.6 dB, <10 mA/3 VVCO:differential, 15% tuning range,−90 dBc Hz−1 @ 100 kHz offset, 22 mW/3 V

I/Q modulator/demodulator synthesizer chip

11 MBits s−1 radio bit rate 1999 IBM

10.2. TECHNOLOGY COMPARISON

Silicon bipolar IC processes tailored for low-voltage, low-power RF andmixed-signal applications have reached the performance and cost requiredfor mass production of RF transceivers operating in the 1–2 GHz range.GaAs, which initially was the only contender above 2 GHz, is beingchallenged by small geometry SiGe HBTs.

Table 10.3 summarizes the performance of competing technologies forRFIC applications. It is seen that Si technology compares extremelywell with GaAs in terms of performance, with the advantage ofproviding an existing low-cost, high-volume production base. Also,miniaturization of CMOS devices has significantly improved the CMOS


Table 10.3. Comparison of key figures-of-merit for different technologies.(After Kermarrec C et al 1997 IEEE RFIC Symp. Dig. pp 65–8.)

SiGe Si AlGaAs/ GaAs Si BJTHBT BJT GaAs HBT MESFET BiCMOS

Emitter size (µm) 0.5× 1 0.5× 1 2× 5 0.5× 5 1.2× 1.5BVceo/BVDS (V) 4 4 15 8 6fT (GHz) 50 32 50 30 13fmax (GHz) 55 35 70 60 11Gmax (dB) @2 GHz 28 24 19 20 17

@10 GHz 16 11 13 13 1Fmin (dB) @2 GHz 0.5 1.5 0.3

@10 GHz 0.9 0.9IIP3/P1dB 9 9 16 12 9PAE(%) @3 V 70 60 @ 5 V 70 401/f corner 0.1–1 0.1–1 1–10 10 000 0.1–1frequency (kHz)

IIP3: third-order input intercept point.PAE: power added efficiency.

RF characteristics [24]. Submicron low-voltage CMOS technologies haveattained fT and fmax in excess of 40 GHz, less than 2 dB noise figure at2 GHz, and excellent linearity up to 2 GHz. These will be discussed insection 10.3.

SiGe HBTs offer the high performance of GaAs devices with lowerpower consumption. In addition, these provide higher gain and less noisethan silicon BJTs. These powerful features, combined with a cost andcomplexity level comparable to a silicon process, make SiGe BiCMOStechnology an ideal solution for high-frequency applications, includingcellular telephones and radio transceivers. The key to the replacementof GaAs with SiGe HBTs lies in the fact that SiGe not only offers highspeed, it also enables high levels of integration. For example, chipscontaining voltage controlled oscillator circuits are fully monolithic andcontain no external components, such as inductors and varactor diodes.Fully differential architecture, which minimizes noise coupling from digitalparts of a highly-integrated chip into a sensitive analogue VCO, has beenpossible in SiGe technology with minimum increase in power consumption.

Noise is a very important parameter for telecommunication circuitsand a minimum noise figure is commonly used to compare the noiseperformance of a technology [25]. For the realization of mobilecommunication products in the low GHz range, several technologies

MOS versus bipolar 369

Figure 10.2. Comparison of minimum noise figures of different technologies.(After Plouchart J-O et al 1999 IEEE CICC Proc. pp 217–20.)

are available. The well-known GaAs technologies with MESFETs andheterostructures are in keen competition with Si and SiGe bipolar andCMOS technologies. Thus, an evaluation of the different technologies withrespect to noise performance is important. A comparison of minimumnoise figures reported in various technologies is shown in figure 10.2. Theminimum noise figure is close to that of a 0.5 µm MESFET technology and,due to lower parasitic, is better than that of GaAs HBT technology [26,27].

10.3. MOS VERSUS BIPOLAR

The availability of inexpensive, high-quality silicon wafers and an extensivemanufacturing experience favours standard CMOS for most applications.At present, complex integrated circuits are fabricated almost exclusively inCMOS on standard silicon substrates. Low power consumption, high inputimpedance, excellent noise immunity, high integration levels and provenreliability are amongst the MOS attributes. With each new generation,there are improvements in speed, current drive and noise performance alongwith reductions in supply voltage.

Recently, much attention has been paid to the development ofdedicated RF CMOS technologies [28]. Building blocks implementing theRF and baseband circuits in a 900 MHz wireless transceiver have beendeveloped. Many of the problem areas in the quest for a one-chip solutionto cellular phones using CMOS technology are being researched with somesuccess, but the design bottleneck, preventing further integration, is the


RF section, where the key issue is high-frequency performance.In 1996, a 1 µm CMOS circuit for a 900 MHz spread-spectrum

wireless transceiver was demonstrated, showing the operation of an entiretransceiver on a single-chip, to give a level of performance previously onlypossible by combining advanced silicon bipolar technology with specializedpassive components [29]. However, recent miniaturization of CMOS deviceshas significantly improved the CMOS RF characteristics. For example,typical values of fT and fmax for 0.25 µm n-MOSFETs already exceed40 GHz, and those for 0.1 µm n-MOSFETs are more than 100 GHz [30].The RF noise figure of the MOSFETs is less than 1 dB at 2 GHz operation.

Modern wireless systems increasingly blend digital blocks intoconventional analogue front-ends for frequency synthesis, adaptivity, multi-mode operation and detection. This raises questions such as how welldigital CMOS circuits can coexist on the same chip as the RF front-end,or whether there is sufficient on-chip isolation. In conventional CMOSprocesses, circuits are built on silicon wafers about 500 microns thick,but all the circuitry is actually formed in the top 1 µm thick layer of thesubstrate. These standard silicon devices are far from ideal as the circuitsinteract with the conductive silicon substrate, causing many parasiticeffects. In particular, capacitance between the circuitry and the substratecauses power consumption to increase with switching speed and createsundesirable coupling between circuits. The bulk substrate’s dispersion ofhigh-frequency signals precludes the construction of microwave devices.These effects become more pronounced as advances in manufacturingtechnology lead to smaller transistor dimensions and lower operatingvoltages. Nevertheless, in the long run, CMOS technology is expectedto overcome many of these problems by using alternative technologies andSi bipolar and GaAs technologies will find themselves increasingly pressedby competition with CMOS in the 1–2.5 GHz frequency range.

When transistors are fabricated in a very thin layer of silicon near-ideal devices can be realized. This is the reason for the surge in interestin silicon-on-insulator technology. SOI circuits are attractive because oftheir enhanced performance for deep submicron CMOS. Over the pasttwenty years, a variety of possible structures based on the concept of aburied oxide have been researched, with the aim of separating the activedevice area from the silicon substrate. An early SOI process was silicon-on-sapphire (SOS), in which a thin film of silicon is grown on a sapphirewafer. SOS is an established technology used primarily in military andspace applications, where its inherent resistance to the effects of radiationis essential. While SOS has been proven manufacturable and has significantperformance advantages, it has seen little commercial use because it isunsuitable to the fabrication of the deep submicron transistors needed formodern, high-density circuits, principally because of the high density ofdefects at the silicon–sapphire interface.


Alternative technologies, such as wafer bonding or separation byimplanted oxygen (SIMOX) [31], have been proposed to produce a thinsilicon layer on top of a silicon–dioxide layer, on a bulk-Si substrate.However, crystalline silicon cannot be grown on amorphous silicon dioxideand both methods need an insulating oxide layer between the existing layersof silicon. In the wafer bonding process, two oxidized bulk wafers arebonded together. Polishing or etching the top wafer leaves a thin layer ofsilicon supported by the bottom wafer, but insulated from it by an oxidelayer. This is a mechanical process, requiring an extremely clean wafersurface to prevent voids. Doping procedures used to control the etching ofthe thick upper wafer increase the defect density in the final silicon layer.In the SIMOX process, oxygen atoms implanted just beneath the wafersurface create a thin, buried layer of silicon dioxide. High implant energiesand multiple implant-and-anneal cycles are required, since the implantationprocess severely damages the silicon surface.

The recent novel UNIBOND process uses deep implantation ofhydrogen. After bonding and annealing, the wafers separate naturallyat a depth defined by the location of hydrogen microcavities. Thismechanism has been given the acronym SMART-CUT [32]. SMART-CUT has a number of advantages as a production process. Perhaps themost significant, from a CMOS scaling viewpoint, is the relative simplicityin realizing a specific combination of buried oxide thickness and Si layerthickness.

All SOI technologies have been used for the fabrication of smallertransistors, particular deep submicron CMOS. It is in the highlycompetitive field of low-power circuits that SOI is most attractive. SOIoffers the possibility to achieve the almost ideal subthreshold slope of60 mV per decade at room temperature and consequent lower thresholdvoltage. Low leakage currents limit static power dissipation while thecombined effects of lower parasitic capacitance and reduced supply voltageminimize dynamic power dissipation. Some compromises in performanceare however, inevitable. As silicon dioxide is a poor thermal conductor, self-heating effects degrade transistor performance, as discussed in chapter 5.Although circuits in SOI material are better electrically isolated fromthe conductive silicon below, than those produced in bulk-Si wafers, theyremain subject to many of the parasitic effects seen in conventional bulk-silicon circuits, although the reduced capacitance from the active devicearea to the substrate is a particular benefit. However, high-frequencydispersion losses still persist.

It is still a matter of considerable controversy whether or not SOI willhold the key to the future successful implementation of CMOS circuitswhen the gate length is shrunk even further. An excellent review of thestate of the art and future of SOI technology, material and devices is givenin [33]. Particularly novel applications of SOI in the future are likely to


include buried ground planes for reduction in cross talk [34], ultrathin layerMOSFETs [35] and eventually double gate transistors [36] for realizationof volume inversion, leading to enhanced mobility, subthreshold swing andreduced 1/f noise.

SiGe HBTs have also recently been successfully produced on SOIsubstrates fabricated using wafer bonding. Associated with this approach isthe creation of thermal vias to remove heat from the SOI islands. Thermalvias have been produced with high breakdown voltage, and a factor of fourimprovement in thermal conductivity over a conventional buried oxide. Thewafer bonding approach [37] can also permit the incorporation of a buriedsilicide layer above the insulator layer, to minimize collector resistance.Such is the flexibility of this approach that the buried silicide can becreated below the insulator layer (GPSOI). This substrate is intended foruse as a buried ground plane in electronic systems that combine digitaland analogue circuitry on the same chip. Measurements of cross talk onpatterned GPSOI ground planes show world record suppression of crosstalk at frequencies in the range 1–50 GHz [34].

The trade-off between the use of GaAs, Si bipolar and/or MOS devicesfor RF applications is a very complicated task due a number of factors. RFtransceiver circuits have a very broad range of requirements, including noisefigure, linearity, gain, phase noise and power dissipation. The advantagesand disadvantages of each of the competing technologies Si-CMOS, BJTs,Si/SiGe HBTs, and GaAs MESFETs, p-HEMTs and HBTs has beenexamined recently by Larson in the light of these requirements [9].

CMOS technology development proceeds at a rapid pace, so anycomparisons can only relate to the state of the art at a particular time.However, as an example, in a 1995 CMOS process, a 0.5 µm n-MOSdevice exhibited peak fT and fmax of approximately 20 and 40 GHz,respectively. By comparison, the peak fT and fmax of the correspondingnpn bipolar transistor fabricated in a comparable process are 20 and28 GHz, respectively. The improvement in microwave gain of MOS devicesis primarily due to the lower gate resistance compared to the base resistanceof a bipolar device. MOS devices exhibit a substantial speed advantage atlow currents compared to bipolar devices, but bipolar devices exhibit betterperformance at low voltages as shown in figure 10.3.

When properly scaled for width and normalized for power dissipation,MOS devices exhibit a slightly lower minimum noise figure than bipolardevices, but their associated optimum source resistance is not well matchedto 50 Ω (close to an open circuit because of the low equivalent input noisecurrent), making optimum low-noise impedance matching difficult. Theoptimum source impedance can be moved closer to 50 Ω in a MOS device,but only at the expense of increased power dissipation or noise figure [38].

With SiGe, there are excellent prospects of rejuvenating CMOStechnology. The major potential market for heterostructure FETs


Figure 10.3. Measured high-frequency performance of Si BJT and n-MOSdevices: (a) fT and fmax versus collector/drain current; (b) fT = fmax versuscollector/drain voltage. (After Larson L E 1998 IEEE J. Solid-State Circuits 33387–99.)


(discussed in chapters 6 and 7) is for low-power applications. The enhancedcarrier mobility in strained group IV alloy layers, particularly at low verticalfields, is useful for high-speed low-voltage and low-power circuits involvingMOSFETs [39]. The ability to integrate SiGe-channel p-MOSFETs withCMOS is a great advantage over III–V technologies and opens up thepossibility of SiGe ultimately receiving a larger market share than III–Vs.Higher mobility improves the p-MOSFET performance, and gives riseto better linearity, higher current drive, better noise performance andreductions in the supply voltage. Figures 10.4, 10.5 and 10.6 comparethe enhanced effective hole and electron mobilities measured in variousMOSFET/MODFET structures demonstrated in SiGe technology.

It is possible to design layer structures with both electron and holechannels with balanced conductance, therefore allowing high-performanceheterostructure CMOS designs. The possibility of matched n- and p-channel performance in CMOS considerably facilitates the design ofamplifiers, mixers and filters. Major problems of integration of strained

Figure 10.4. Reported experimental hole effective mobilities at roomtemperature obtained in pseudomorphic Si/Si1−xGex/Si structures plottedagainst effective field (Eeff). The bars indicate the range of Eeff values presentin micropower, 1 and 0.1 µm CMOS technologies. (After Parker E H C andWhall T E 1999 Solid-State Electron. 43 1497–506.)

SiGe BiCMOS technology 375

Figure 10.5. Reported experimental hole effective mobilities at roomtemperature in compressively strained Si1−xGex and tensile strained-Si grownon virtual substrates with terminating composition Si1−yGey. The upper sectionshows mobilities for remote-doped hetero-interface and the lower section foroxide-gated/strained-Si (tensile) interfaces. (After Parker E H C and Whall T E1999 Solid-State Electron. 43 1497–506.)

layers into a CMOS production line are:

(i) the structures should be as far as possible compatible withconventional processing;

(ii) the high thermal budgets used in present CMOS production are notideal for strained layers and may cause strain relaxation or diffusion;

(iii) any strained layer incorporated must be below the equilibrium criticalthickness, otherwise dislocations and defects will result reducingperformance and yield.

10.4. SIGE BICMOS TECHNOLOGY

To retain the yield in the basic CMOS process, it is important tokeep the actual physical process steps the same, as far as possible (seefigure 10.7). Several SiGe bipolar-only processes have been proposed orare in development. Robust and manufacturable SiGe HBT technologies,potentially suitable for commercial applications, now exist in the US,Europe and Japan [13, 19, 26, 40–44]. SiGe HBTs can be integrated with


Figure 10.6. Reported experimental electron effective mobilities at roomtemperature in strained-Si grown on virtual substrates with terminatingcomposition Si1−yGey. The upper section shows mobilities at remote-dopedhetero-interface and the lower section refers to oxide-gated/strained-Si (tensile)interfaces. (After Parker E H C and Whall T E 1999 Solid-State Electron. 431497–506.)

Figure 10.7. SiGe BiCMOS process modules in comparison to CMOS. (AfterSubbanna S et al 1999 IEEE ISSCC Tech. Dig. pp 66–7.)

SiGe BiCMOS technology 377

conventional CMOS silicon circuits to form a BiCMOS technology in whichthe bipolar transistors. SiGe HBTs can be exploited for critical high-speed analogue or digital functions and the silicon CMOS can serve forvery high-density memory or compact on-chip signal processing functionsin system-on-a-chip (SOC) applications. This ability sets SiGe HBTtechnology apart from the competing III–V technologies, which cannotsupply the high-quality native oxide essential to implementations inCMOS. At the time of completing this book, IBM [45] have developedand reported a production technology, based on 15 years research anddevelopment and four generations of scaling CMOS compatible SiGetechnology. Performance of the SiGe HBT can be optimized to a particularapplication, and both fT and fmax of 90 GHz have been simultaneouslyachieved in a single transistor, with 0.18 µm lithography [46].

IBM’s SiGe BiCMOS technology with 3.3 V, 0.5 µm CMOS is a uniqueand versatile process integrating high-performance SiGe HBTs [20]. Thestandard device (3.3 V/50 GHz) is targeted at high-speed, small-signalapplications, while a high breakdown device (5.8 V/30 GHz) is targetedat power amplifier applications. Table 10.4 summarizes the key figures-of-merit. The SiGe HBT can operate at current densities in excess of1.5 mA µm−2 and with near perfect ideality and flat β over a currentrange of seven orders of magnitude. Unique to the SiGe HBT is the fact

Table 10.4. Summary of the key figures-of-merit of the devices realized in SiGeBiCMOS technology.

SiGeHBTs Small-signal/low voltage High power/high voltage(npn) high-speed device low-noise device

BVceo 3.3 V 5.5 VGain 100 80fT 47 GHz 30 GHz

fmax65 GHz @ Vbc = 1 VVbe = 0.72 V

55 GHz @ Vbc = 1 VVbe = 0.72 V

VA 65 V 124 V

FETs n-FET (W/L = 10 µm/0.5 µm) p-FET (W/L = 10 µm/0.5 µm)

Tox 7.8 nm 7.8 nmLeff 0.39 0.39Gm,sat 103 mS mm−1 180 mS mm−1

VT,lin 0.55 V 0.6 VRext 500 Ω mm−1 500 Ω mm−1

ID,sat 400 µA mm−1 400 µA mm−1


that β also remains virtually flat over a broad temperature range. Becauseof its large peak fT, the SiGe HBT retains significant high-frequencyperformance even at low currents, allowing the designer the choice to trade-off speed for low-power operation.

This HBT and CMOS integration, without any loss of HBTperformance, makes it possible to implement a complete system on achip with, for example, high-performance analogue functionality and A/Dconversion implemented using the SiGe HBT device, combined with CMOSfor digital signal processing.

10.5. RF CIRCUITS

In this section, we discuss some of the technology considerations involvedin the implementation of key wireless system building blocks.

10.5.1. Low-noise amplifiers

Low-noise amplifiers are one of the key building blocks in an RF system.They are required to contend with a variety of signals coming from theantenna, often of larger amplitude than the desired signal and henceboth low noise and high linearity are required simultaneously. Theserequirements are often contradictory with an additional requirement forlow-power dissipation. The radio signal received at the receiving antennais sent to the LNA, whose purpose is to boost the signal level withoutreducing the signal-to-noise ratio significantly. The signal level at theantenna can range between 1–100 mV rms. At the low end of the signalrange, the LNA performance is fundamentally limited by thermodynamicissues, while at the high end of the signal range, the challenge is to minimizethe effects of nonlinearities on receiver performance. The measures forthese requirements are the amplifier noise figure, which determines theminimum detectable signal (MDS), and the third-order input interceptpoint (IIP3). In addition, high gain and low dc power consumption areother requirements of an LNA. A very simplified expression for transistorminimum noise figure, which is applicable to both BJTs and FETs, is givenby [47]

NF ≈ 1 + kgmrb/g

(f

fT

)(10.1)

where gm is the device transconductance, rb/g is the base or gate resistance,depending on whether the device is a bipolar transistor or FET, and k isa material-dependent constant. Clearly, the noise figure of the amplifierwill be improved by employing a technology that operates with as lowa resistance as possible at a given current [1]. Low-noise amplificationat microwave frequencies has been the exclusive domain of MESFETsand HEMTs. Bipolar transistors are traditionally excluded from these

RF circuits 379

applications despite their popularity in other analogue circuits in the lowermicrowave range.

The outstanding high-frequency performance of Si/SiGe HBTtechnology has been well established [11, 21]. In addition, for a givenrequired fT or fmax, SiGe HBTs require roughly one third the collectorcurrent of an ‘equivalent’ Si BJT for equivalently sized devices. In manyapplications, this speed performance advantage can be ‘traded off’ in a verysatisfactory way for reducing the power dissipation. It is at these low-powerlevels that Si/SiGe HBT technology has a distinct advantage compared toSi BJT or CMOS technology. As a result, technology scaling will have asignificant impact on LNA performance, as has been shown in a review byLarson [9].

Figure 10.8 plots amplifier gain/dc power dissipation (in dB mW−1)as a function of noise figure (in dB) for a variety of reported LNAsin silicon and GaAs technology at 2 GHz. However, one must becareful in comparing reported circuit performance, since it representsan intermingling of intrinsic device performance, process features andcircuit design. Nevertheless, by comparing the best reported resultsin each technology, the fundamental device performance limits can beassessed. These results demonstrate the potential performance advantageof SiGe technology at this frequency, if dc power dissipation is a majorconsideration.

Figure 10.8. Gain-to-dc power ratio plotted versus noise figure forstate-of-the-art 2 GHz LNAs. Note that the SiGe HBT circuit provides thebest result when power dissipation is a critical factor. (After Larson L E 1998IEEE J. Solid-State Circuits 33 387–99.)


Because of the extreme dynamic range considerations of the low-noise front-end, linearity is an equally important figure-of-merit forLNAs. In this case, a linearity figure-of-merit is the ratio of the inputthird-order intercept point (IIP3) to the dc power dissipation. Field-effect transistors generally exhibit improved third-order intermodulationdistortion compared with bipolar devices, due to their near square-lawcurrent versus voltage behaviour. On the other hand, bipolar transistoramplifiers have demonstrated outstanding linearity performance as well,apparently due to the partial cancellation of the resistive and capacitivenonlinearities in the emitter–base junction at certain frequencies [48].

Figure 10.9 compares this linearity figure-of-merit for a variety ofrecently reported monolithic LNA circuits, all operating at approximately2 GHz. As with the case of noise figure, the performance advantages ofSiGe and GaAs technologies are significant if dc power dissipation is acritical parameter, although the improvement is less dramatic. The bestLNA results have a ratio of IIP3/dc power of approximately 0.15, as shownin figure 10.9.

The gain characteristic of a SiGe LNA, with a 19 dB gain and1.7 dB noise figure, is shown in figure 10.10. SiGe LNAs have even beenimplemented at even higher frequencies. A 5.8 GHz LNA [49] with a

Figure 10.9. Amplifier linearity figure-of-merit plotted for the samemonolithic 2 GHz amplifiers. The best results fall on a line of approximately0.15 mW mW−1. The advantages of SiGe HBT technology are not as dramatic.(After Larson L E 1998 J. Vac. Sci. Technol. B 16 1541–8.)

RF circuits 381

Figure 10.10. Performance characteristics of a low-noise amplifier in a SiGefront-end. (After Bopp M et al 1999 IEEE ISSCC Tech. Dig. pp 68–9.)

minimum noise figure of 1.65 dB and an associated gain of 15 dB dissipatesonly 13 mW from a 1 V supply (with only 9 mW in the gain stages), whilea 6.25 GHz monolithic LNA [50] operating from a 2.5 V supply shows aminimum noise figure of 2.2 dB and an associated gain of 20.4 dB.

10.5.2. Power amplifiers

The power amplifier (PA) is a component of the total RF system thattakes the signal to be transmitted and amplifies it to the necessary levelneeded to drive the antenna. For applications requiring moderate-to-highoutput power, the PA contributes significantly to the total transceiverpower consumption, making the PA efficiency crucial to the overall systemperformance. The total power consumed by the PA is greater than thepower output, as there will always be some power consumed in the activedevices and peripheral circuitry. Because the power output specificationitself is often larger than the power consumption of the rest of the blocksin the RF system, and the power consumption of the PA will be greaterthan the specified power output, the PA is decidedly the major powerconsumer of the system [51]. The integration of the PA also remains adifficult challenge. Power amplifiers need to deliver a wide range of outputpowers to the antenna, as the user moves throughout the cell site.

The efficiency defined in traditional approaches (e.g., classes A, B, ABand C), is often optimized merely at the maximum output power. Threedifferent types of efficiency are generally quoted. Firstly, the collector/drain


efficiency, ηc/d which is defined as [52]

ηc/d =Prf,outPdc

(10.2)

where Prf,out is the power delivered to the load at the desired RF frequencyand Pdc is the total power taken from the dc supply. Secondly, the poweradded efficiency (PAE) of a power amplifier is given by the well-knownexpression

PAE =Prf,out − Prf,in

Pdc(10.3)

where Prf,in is the power needed to drive the input. Thirdly, the overallefficiency is defined as

η =Prf,out

Pdc + Prf,in. (10.4)

Both the PAE and the overall efficiency are better gauges of the trueperformance of a PA, since they include the power needed to drive thePA in the determination of the efficiency.

The complications associated with power amplifiers for RFapplications are challenging, as in the case of LNAs. The PA mustsatisfy the requirements of linearity, gain, output power and power addedefficiency. In addition, mobile applications which require a lower powersupply (3 V and even lower), have made it difficult to maintain the requiredoutput power and efficiency due to impedance matching limitations.Ideally, the PAE of the amplifier should not degrade significantly, as theoutput power varies from near zero to its maximum value.

In the past, a host of different architectures in which a PA could beimplemented have been proposed [53]. The number of different types ofclasses of power amplifiers is too numerous, and they range from entirelylinear to entirely nonlinear, as well as from quite simple to a very complexone. A class A PA is the simplest and most basic form of power amplifier.In a class A operation, the transistor is in its active region for the entireinput cycle, and thus is always conducting current. As such, the devicemaintains approximately the same gain throughout the entire region and,in the case of a MOS device, is linear in that region. The problem with classA structures, however, is their inherently poor efficiency since it is on at alltimes, and the current represents a continuous loss of power in the device.The efficiency of an RF class A PA is limited to 50%. As a result, class Aamplifiers are used only in those situations where the linearity requirementsare stringent.

In a class B structure, there are two devices: one which providescurrent to the load during the positive half cycle and one which removescurrent from the load during the negative half cycle. The structure isusually called a push–pull structure. When no signal is applied, however,

RF circuits 383

there is no current flowing, as both the devices are biased at their turn-onvoltages. As a result, in an ideal case, any current through either devicegoes directly to the load, and thus attempts to maximize the efficiency.Although this is generally a linear amplifier, there is an instant duringeach cycle when both devices are off, which produces distortion in theoutput known as crossover distortion. This architecture allows for very highefficiencies, as theoretically the efficiency can approach 78%. Hence, thisarchitecture can be useful in applications where the linearity requirementsare a little less stringent. In situations where the linearity is still animportant issue, the class AB structure, a cross between a class A anda class B structure, is used. The above classes are examples of linearstructures, where the output amplitude and phase are linearly related tothe input amplitude and phase.

In a communication system, power amplifiers are used to amplify thesignal to the proper power level to reliably transmit the signal which is oftenquite high. In many applications, the amount of power consumed by theamplifier is not critical, as long as the signal being transmitted has adequatepower. However, in a situation where there is a limited amount of energyavailable, e.g., in mobile communication systems, the power consumed byall devices must be minimized in order to maximize the length of time forwhich that energy is available.

Power amplifiers are typically operated in class AB mode for mostRFIC applications, in an attempt to achieve a compromise betweenlinearity and power added efficiency. In this case, the factors of keyimportance for amplifier performance are the transistor specification(for high power gain), linearity (for lowest possible adjacent channelinterference) and breakdown voltage (BVceo for bipolar devices). However,the breakdown voltage has become less critical for handsets in recent years,due to the reduction of operating voltages in most handheld units.

In cases where linearity is not critical, and efficiency is highly critical,class C power amplifiers are used. A class C power amplifier is the mostbasic of the nonlinear power amplifiers used at RF frequencies. Thisarchitecture is based on the idea of a class B structure, where the deviceis biased at the edge of conduction and the device conduction angle is lessthan 180. As a result of the pulsed nature of the output current, the inputand output voltages are not linearly related, and the output of the PA willbe highly distorted if the input voltage amplitude changes.

Since gain is very critical for achieving the best performance, mosthigh-performance power amplifiers in the 2 GHz frequency range have beenimplemented in GaAs or SiGe technology, to achieve the highest possiblepower added efficiency. At lower frequencies, silicon MOS devices areoften employed for power amplifiers because of their low cost and robustoperation, despite their poor performance compared to GaAs technology.A comparison of monolithic power amplifier performances for mobile


Table 10.5. Summary of maximum PAE, Pout at maximum PAE, gain, PAE at3 dB compression and Pout at 3 dB compression under four biasing conditions,tuned for maximum PAE. (After Greenberg D et al 1997 IEEE IEDM Tech. Dig.pp 799–803.)

Bias Maximum Pout @ Gain PAE @ Pout(mA) PAE maximum PAE (dB) 3 dB 3 dB

(%) (dBm) (%) (dBm)

2 (B) 69 15.2 24.9 67 14.26.5 (AB) 60 15.2 28.9 48 12.312.5 (AB) 52 15.2 29 42.3 12.925 (A) 42 15.2 30.1 26.2 12.7

telephone PHS applications at 1900 MHz, where the adjacent channelleakage specification of 55 dBc is specified at 600 kHz from the carriercentre, is available in [54].

Power amplifiers with high breakdown voltage (6 V) HBTs for 3 Vwireless applications have been demonstrated in IBM’s 200 mm SiGetechnology [55]. At 0.9 GHz and 1.8 GHz, excellent power densities of upto 1.36 mW µm−2, an outstanding PAE reaching 70% and no performancedegradation in integrating the HBT with CMOS have been observed. Theseresults suggest that SiGe can meet the demands of many large-signalwireless applications. Table 10.5 summarizes the peak PAE and 3 dBcompression point load–pull data for the four biases tuned for maximumPAE. Despite the extra processing steps associated with integrating aSiGe HBT process with CMOS, it was observed that the BiCMOS versionachieves virtually identical performance to the device from the HBT+p-FET process. The detail of the HBT+p-FET and BiCMOS processes usedto fabricate the devices may be found in [56].

A fully integrated RF transceiver for a DECT application [8] comprisestwo bipolar ICs including a power amplifier, a low-noise amplifier and aVCO. The SiGe HBT power amplifier has a 33 dB small-signal gain, 38%max PAE and 26.6 dBm saturated output power at a 3 V supply. Theperformance of the transceiver is shown in figure 10.11.

10.5.3. VCOs and frequency synthesizers

The voltage controlled oscillator (VCO) represents one of the most difficultchallenges for a design engineer. The ideal VCO output should exhibitno phase noise, tune over a fixed frequency range and be insensitive totemperature, process drift, output loading or power supply variations.While hybrid VCOs, which typically employ discrete silicon bipolar

RF circuits 385

Figure 10.11. Performance characteristics of a power amplifier in SiGefront-end. (After Bopp M et al 1999 IEEE ISSCC Tech. Dig. pp 68–9.)

transistors, high-quality surface mount inductors and varactor diodes, andare temperature compensated and laser trimmed to the proper centrefrequency, closely match these ideal conditions, monolithic integratedVCOs suffer from low-quality monolithic inductors and varactor diodes anda difficulty in trimming the centre frequency to accommodate its inevitabledrift due to process variations [57, 58]. The quality factor of the VCOresonator, which is mostly determined by the inductor in the resonator, isespecially important due to its effect on the phase noise of the resultingoscillator.

A simplified expression for oscillator phase noise, in good agreementwith experimental data over a broad range of oscillator circuits, derived byLeeson [59] to account for flicker noise is given by

Sφ(ωm) = S∆θ

[1 +(ωo

2Qωm

)2](1 +

ωcωm

)(10.5)

where Sφ(ωm) is the output power spectral density at frequency ωm offsetfrom the oscillator centre frequency, S∆θ is the power spectral density ofthe oscillator input phase error, Q is the resonator loaded quality factor,ωo is the centre frequency of the oscillator output and ωc is the flicker noisecorner frequency.

Several VCO configurations have been implemented in SiGetechnology. Monolithically integrated 26 GHz and 40 GHz VCOs werefabricated on high resistivity substrates using SiGe HBTs and on-chipvaractors. A hybrid 8–12 GHz VCO has also been built using a SiGeHBT in common-emitter configuration [60]. With a tuning range of morethan 3 GHz, the output power behind an on-chip 10 dB attenuator reached−13 dBm. The transistors had an fmax of approximately 60 GHz, and wereoperated in common-emitter series feedback configuration.


A 2.4 GHz VCO for wireless local loop (WLL) applications, with apower dissipation of 28 mW and phase noise of −110 dBc Hz−1 (at 1 MHzoff carrier), has been fabricated using RPCVD-grown SiGe HBTs and aresonator consisting of a chip varactor and a microstrip line inductor [61].An 11 GHz 3 V SiGe VCO with integrated resonator has been reported bySoyuer et al [62] with a fully differential architecture. This architectureminimizes noise coupling from digital parts of a highly-integrated chipinto a sensitive analogue VCO. The added circuitry of a fully differentialarchitecture typically comes at the cost of increased power levels, butSiGe achieves this result with minimum increase in power consumption.In the case of SiGe, the VCOs are fully monolithic and contain noexternal components, such as inductors or varactor diodes. Recently, IBMhas reported a VCO operating at 17.1 GHz, an ultrahigh transmissionfrequency recently allocated for wireless uses in Europe (HiperLAN). Therecord setting VCO, operating on a single 3.3 V supply, could be tunedover a 600 MHz range and exhibited a phase noise of −104 dBc Hz−1 ata 1 MHz offset from centre frequency, with an output power of −5 dBm,dissipating only 65 mW. Another VCO, tuned for a new American standardof 5.x GHz (U-NII), has also performed exceptionally well, with a tuningrange of 840 MHz and a phase noise of −115 dBc Hz−1 at 1 MHz offset atthe centre frequency of 5.6 GHz [63].

10.6. PASSIVE COMPONENTS

The demands placed on portable wireless communication equipmentinclude low cost, low voltage, low power dissipation, low noise, highfrequency of operation and low distortion for bandwidth reduction. Thesedesign requirements cannot be met satisfactorily without the use ofRF inductors. Spiral inductors have found an important place in thewireless communications market, where they can be used to improve theperformance of key RF building blocks.

Since the introduction of spiral inductors, many authors have reportedhigher performance inductors on Si substrates, using advances in processingtechnology [64]. Inductors up to about a 10 nH range in a reasonable area,with Q limited to about 5 at 1 GHz and 10 at 2 GHz by metal seriesresistance for standard technologies have been achieved. This has included:

(i) higher conductivity metal layers to reduce the loss of the inductor;(ii) multi-layer metal to either shunt inductors to reduce loss, or to reduce

the area;(iii) low loss substrates to reduce losses in the substrate at high frequency;

and(iv) thick oxide to isolate the inductor from the lossy substrate.

Passive components 387

Table 10.6. Passive components and diodes realized in SiGe BiCMOStechnology for RF communication systems. (Source: IBM.)

Spiral inductors

2-turn: Q (12 GHz) = 10, 1.5 nH4-turn: Q (2 GHz) = 7.5, 4.2 nH6-turn: Q (1 GHz) = 5.8, 9.8 nH8-turn: Q (1 GHz) = 5.2, 16.6 nH

Capacitors

MIS capacitor C = 1.5 fF µm−2

MIM capacitor C = 0.7 fF µm−2

Resistors

Polysilicon resistors 340 Ω/square and 220 Ω/squareImplant resistors 1.7K Ω/square, 23 Ω/square and 8 Ω/square

Diodes

Schottky barrier diode Vf = 300 mV@100 µAPIN Vf = 790 mV@100 µAVaractor 1.4 fF µm−1 @ 0 V, Vf = 810 mV @ 100 µAESD 2000 VHBM

In table 10.6, the performances of several passive components anddiodes realized in IBM’s SiGe BiCMOS technology for RF communicationsystems are shown. Self-resonance due to the large parasitic capacitanceto the substrate is a substantial problem, and Q drops to about 2 for a10 nH inductor in a typical technology. Since the inductor is usually usedto match impedance or to tune a gate or base diffusion capacitance, theparasitic capacitance can usually be incorporated in the design process, aslong as the self-resonant frequency is far above the frequency of interest.

The lossy silicon substrate makes the design of high Q reactivecomponents difficult. Despite this difficulty, the low cost of silicon ICfabrication over GaAs IC fabrication and the potential for integration withbaseband circuits make silicon the process of choice. Accordingly, theuse of silicon spiral inductors has proliferated in recent years [65]. On-chip inductors are necessary for matching networks and LC resonators forsilicon-based RFICs for wireless communication ICs. Transmission lineswith losses of less than 1.5 dB cm−1 measured up to 20 GHz have beenrealized. This value is comparable to III–V technologies and is an order ofmagnitude better than conventional silicon.


Another important issue is whether microwave transmission linelosses caused by the conductive silicon substrate will limit the high-frequency response of SiGe HBT amplifiers. Several research groups haveexplored the use of high-resistivity Si substrates for the realization of SiGeMMICs, but very high resistivities (>20 Ω cm−1) of the substrate leadto severe processing problems associated with such wafers (specifically slipdislocations and warpage).

10.7. COMMERCIALLY AVAILABLE PRODUCTS

IBM and Daimler–Chrysler have been involved in the SiGe area for along time. Corporations such as Lucent, Motorola, ST-Microelectronics,Philips, Infineon, Maxim, Temic, Hitachi and many others have recentlybegun development or deployment of SiGe-based HBT processes, and arelikely to make the transition from present efforts in discrete technology tointegrated SiGe BiCMOS technology. SiGe-based mixed-signal technologyis rapidly making its way into the consumer mainstream, at the highend of the telecommunications market. Present trends indicate that SiGetechnology will find applications in the frequency range 2–30 GHz, abovewhich GaAs is well established. Components for personal communicationservices devices operating between 1.8–2.2 GHz are a fast growing marketsegment, along with pagers and wireless local area networks. Otherwireless opportunities might include direct-broadcast satellite TV andlocal multipoint distribution services (LMDS). Devices based on SiGetechnology will be able to move data across networks at speeds traditionallyconsidered beyond the reach of silicon technology. This will bring betterperformance at low costs to fibre transport networks, high-speed cellularvoice/data phones and wireless devices such as global positioning satellite(GPS) receivers. Another application is a differential global positioningsystem (DGPS) satellite receiver that uses several GPS channels centred on1.5 GHz. A related product is targeted for the automobile industry, whichhas significant potential to use wireless technology for traffic managementand control, and collision avoidance systems. Inexpensive 24 GHz collisionwarning radar systems for mainstream automobiles are also needed.

10.7.1. TEMIC Semiconductors

Temic Semiconductors supplies integrated circuits to the communications,automotive, data processing and aerospace markets. As a leader inSiGe technology, it provides high-performance SiGe solutions in high-volume production. Its SiGe process is a suitable technology for RF chipapplications. It provides significant cost benefits on the component andsystem level side versus GaAs and, in a market where prices are falling,this will be the key issue for manufacturers. The SiGe process for high-

Commercially available products 389

volume production was set up on a well-proven ultrahigh-frequency (UHF)process. The wafer fabrication uses a progressive and widely automated6 in wafer line, high-volume quantities can be provided reliably.

Temic Semiconductors replaced the usual GaAs PA and LNA devicesby SiGe integrated solutions in the frequency range of 400–2400 MHz.Thanks to SiGe, the U7004B, U7006B, T7024 and T0980 provide extremelylow noise figures (e.g., 1.6 dB at 1.9 GHz in 50 Ω systems) and highintegration. Figure 10.12 shows a typical application circuit using theU7004B SiGe front-end IC. As the LNA, PA and transmit–receive switchdriver are included, a large number of external components, and thussystem cost, can be saved. They also provide very efficient power amplifiers.The PAE of the T0980 front-end for 400 MHz reaches a typical value of60%.

Figure 10.12. Application circuit using U7004B SiGe front-end IC. (After TemicSemiconductors, Germany.)


Solutions using GaAs devices are expensive and normally require anegative auxiliary voltage. The front-end ICs U7004B, U7006B, T7024 andT0980 manufactured in SiGe technology need only a single, positive 3 Vsupply voltage. This results in lower system and production costs as wellas extended talk and standby times due to the low current consumption.

The TST091x family members enable the cost-effective production ofa new mobile phone generation. End products are expected to be smallerand lighter as 3 V operation makes use of a single battery cell. The highPAE and low-power operation of SiGe PAs allow for longer talk times.Since SiGe does not require negative supply voltage or a battery disconnectswitch as needed by competing devices using GaAs technology, both systemand production costs will be reduced. Temic Semiconductors offers SiGePAs for single-band operation in the 900 MHz frequency range (GSM 900)and GSM 1800/1900, as well as for dual-band operation (GSM 900 and1800/1900).

With the CW capable T0930, Temic provides a high-performance,SiGe integrated solution with maximum efficiency for two-way pagers. Apower amplifier, RF power control and a standby circuit are included.With SiGe, the current consumption in power-down mode is significantlyreduced, eliminating the need for a high-side switch. This results in lessexternal components—board space, and thus overall size can be reduceddramatically.

The LNAs TST095x with a two-stage amplifier and switchable gainprovide the perfect combination of low noise (NF = 2.2 dB in high gainmode), large signal capability (IIP3 = −7 dBm in low gain mode) and highreverse isolation (minimum −40 dB). Both the low current consumptionand power-down function help to extend battery lifetime.

10.7.2. IBM

The mainstream SiGe chips introduced by IBM include basic buildingblocks—low noise amplifiers, voltage controlled oscillators, power amplifiersand discrete transistors. SiGe is well suited to realize innovative high-frequency products, e.g. antenna switches for the transmit/receive path,satellite communication applications or wireless local area networks.Several of the chips are designed as low-cost, highly-reliable directreplacements for gallium arsenide parts for a broad spectrum ofcommunications applications and are listed below. Several system-levelhardware and software products [66] are now in production and a brief listis given in table 10.7:

• SiGe 3 V GSM tri-band low-noise amplifier• SiGe 3 V tri-band image reject mixer with low-noise amplifier• SiGe 3 V GSM tri-band voltage controlled oscillator• SiGe PDC linear power amplifier

Commercially available products 391

• SiGe high dynamic range 1900 MHz low-noise amplifier• SiGe high dynamic 900 MHz low-noise amplifier• SiGe high dynamic range low-noise transistor

IBM has also been a partner in a number of collaborative ventures,involving application of their SiGe technology to other companies products.Alcatel has developed several 40 Gb s−1 SONET optical data transmissionsystems operating with the bit decision circuit based upon the IBM 50 GHzSiGe technology. A Harris Prism II chip set, a low-cost wireless localarea network (WLAN) product operating on the IEEE 802.11 standard at2.4 GHz, has been converted to SiGe technology. A factor of two reductionin chip count and cost, a factor of four improvement in range and a fivefoldincrease in bit rate have been achieved. A recent announcement by Siemensrevealed the use of the IBM SiGe technology in developing third-generation(3G) cellular base station electronics. As 3G is a wideband CDMA protocol,the combination of high linearity at low power makes SiGe technologyextremely well suited to this application.

Table 10.7. A brief listing of mixed-signal SiGe-based product offerings andtheir market status. (After Meyerson B S 2000 IBM Res. Dev. J. 44 391–420.)

Company Product Descriptioncategory

AMCC Wired 3.2 Gb s−1 17× 17 differential crosspoint switchOC-192 SONET/SDH transimpedance amplifierOC-48 multi-rate clock and data recovery solutionmulti-rate OC-48 transceiver2.5 Gb s−1 multi-rate clock recovery and limitingamplifier device3.3 V OC-48 transimpedance amplifier forWDM and TDM applications

Alcatel Wired Complete 10 Gb s−1 SONET system with allelectronics

Harris Wireless PRISM II chip set 11 Mb s−1

Intersil (5 ICs 5 complete data comm radio operating at2.4 GHz bands up to 11 Mb s−1)Power amplifier and detector (SiGe)RF-to-IF converter (SiGe)I/Q modulator/demodulator and synthesizer (SiGe)

IBM Wireless Direct-conversion digital GPS receiver andLeica GPS engineSiemens Wireless Third-generation mobile cellular base station


10.8. SUMMARY

In applications, SiGe-based devices and circuits represent an outstandingextension of conventional Si technologies, opening up frequency rangeswhich have previously only been the domain of III/IV compoundsemiconductors such as GaAs. SiGe HBT technology has the potentialto revolutionize high-frequency transceiver design in a way comparable tothe revolution in digital integrated circuit technology brought about byCMOS in the 1970s. Its unique combination of outstanding high-frequencyperformance, low manufacturing cost and high yield will provide abundantopportunities for new architectures and new systems in the near future.

Many semiconductor companies, other than IBM and TEMIC, haverecently begun development or deployment of SiGe-based technology andare likely to make the transition from discrete technology, particularlyin BiCMOS applications. In the longer term, heterostructure CMOStechnology may well take over at even higher frequencies.

For mobile applications, the recent announcement of commerciallyviable implementation of silicon-on-insulator technology will have farreaching consequences in the semiconductor industry. The harnessing ofSOI technology will result in faster chips that also require less power—akey requirement for extending the battery life of small handheld devicesthat will be pervasive in the future. Research on fabricating SiGe devicesin a thin layer of silicon on top of an insulator (such as silicon oxide) hasbeen initiated. If it becomes successful, this breakthrough may advancethe microelectronics technology one or two years ahead of where it wouldhave been with conventional bulk-Si technology.

As early as 1995, IBM reported at the Bipolar/BiCMOS Circuits andTechnology Meeting (BCTM) that they believed an important applicationof SiGe technology will be a ‘single chip solution’ for wireless applications.Such a chip which will handle both RF and digital functions is now a reality!

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Index

Acoustic scattering, 60Activation energy, 34, 58Alloy scattering, 39, 60–62, 112,

197, 214Atmospheric pressure CVD, 48Auger electron spectroscopy, 44,

274, 282Auger recombination, 82, 117,

337Avalanchebreakdown, 99, 316multiplication, 82, 317photodiode, 316, 317

Band offset, 38, 51, 52, 54, 56, 58,60, 90, 197, 203, 328

Bandgap narrowing, 59, 74, 115,117, 118, 176

Barrier effect, 90, 95Base design, 122Base resistance, 4, 5, 7, 8, 13, 75,

82, 99, 119, 120, 125, 135,136, 142, 144, 157, 185,186

Base transit time, 8, 13, 14, 83,84, 92, 100, 120, 129, 139,140, 158, 165, 177

Base width modulation effect, 85BICFET, 20BiCMOS technology, 2, 9, 24,

120, 186, 188–190, 260,364, 365, 368, 375, 377,387, 388

Bipolar technology, 3, 5, 8, 9, 13,

18, 25, 153, 161, 166, 174,370

Boltzmann statistics, 108Boltzmann transport equation,

105, 108, 162Breakdown voltage, 99Buffer layer, xiv, 17, 18, 21, 40,

41, 50, 198, 201, 206, 213,219

Bulk recombination, 117

Carrier freeze-out, 173Chemical vapour deposition, 11,

42, 46, 48CMOS, 2, 16, 18, 196, 204, 226,

228, 238, 245, 367, 370,372, 375

Collectorbreakdown voltage, 130design, 129Transit time, 97, 139

Conduction banddiscontinuity, 32, 55, 77

Critical thickness, 13, 35–38, 64,88, 197, 276, 314, 351

Cross section TEM, 41Current crowding, 136Current gain, 7, 10, 11, 13, 74,

77, 83, 87, 89, 94, 120, 158,173–175, 365

Cut-off frequency, 3, 14, 84, 96,110, 120, 123, 131, 140,143, 157, 163, 177, 222,364

397

398 Index

δ-doping, 252Density of states, 80, 113, 116Deposition techniques, 42, 274Dielectric constant, 34, 112, 117,

159, 288, 289, 311Direct bandgap, 311, 337Drift–diffusionequation, 108model, 105, 107, 158, 162, 163simulation, 152, 336

Early voltage, 13, 85, 87, 143,157, 158, 175

ECL gate delay, 9, 99, 133, 141–144, 174

Effective mass, 34, 59, 61, 116Electron gas, 213Emitterdesign, 126transit time, 84, 97, 139, 163

Energy balanceequation, 216model, 162, 163simulation, 162

Epi-base technology, 152, 156,174

Fermi–Dirac statistics, 104, 250Field-effect transistor, xiv, 2, 6,

16, 263, 361, 380Figure-of-merit, 87, 96, 98, 99,

109, 154, 316, 365, 380Flicker noise, 385Forward active mode, 75, 77Freeze-out effect, 60, 62, 175

Gas source MBE, 46, 50GeC, 314, 315, 334Gummel method, 104, 108Gummel–Poon model, 134

HCMOS, 17, 227, 231Heavy doping effect, 59, 80, 82,

118

Heterojunction, 10, 13, 19, 35, 42,50, 57, 58, 90, 96, 152, 180,226, 232, 318

Heterojunction bipolar transis-tor, 2, 9, 73, 76, 77, 119,120

HFET, xv, 17, 196, 198, 213, 227,238–242, 245, 250, 252,254, 257, 263, 265, 268

High electron mobility transistor,17, 25, 220

High level injection effect, 94Hole gas, 60, 62, 217Hot carrier, 239, 242, 314Hot electron, 7, 20Hydrodynamic model, 105, 107,

216, 227

Ideality factor, 274, 276, 277, 288,293, 296–298, 306

Impact ionization, 99, 183, 314,317

Impurity scattering, 111, 113, 199Inductors, 361, 363, 364, 368,

385–387Infrared detector, 305, 325, 327,

329Injection efficiency, 9, 10, 74, 75Input impedance, 183, 196, 369Inter-valley scattering, 198, 199Interface state density, 241, 274,

291, 293, 300–302Interface traps, 188Intermodulation distortion, 380Ionized impurity scattering, 60,

62, 198, 221, 230, 252Ionizing radiation, 188, 336

Kirk effect, 94–96, 131

Lattice constant, 13, 32–35, 38,49, 50, 54, 112, 197, 314

Lattice scattering, 198Limited reaction processing, 47

Index 399

Limited reaction processing CVD,42, 47

Low-noise amplifier, 360, 363,378–380

Low-temperature simulation, 152,172, 175

Mason’s gain, 109Maximum available gain, 109,

110Maximum oscillation frequency,

xiii, 8, 75, 96, 98, 143, 152,220, 221

Metal–organic CVD, 10Metallization, 11, 183, 272, 277,

363Metastable layer, 38, 49, 51Misfit dislocation, 35, 36, 38, 41,

51, 52, 94, 118, 314Mobility, 59, 63, 112, 113, 198,

200MODFET, xv, 17, 217, 219–222,

224, 374Modulation-doped heterostructures,

63, 201, 203, 218Molecular beam epitaxy, xiii, 10,

37, 42, 44Moll–Ross current relation, 79Monolithic microwave integrated

circuit, 361, 362, 388Monte Carlo method, 105Monte Carlo simulation, 112, 199MOS capacitor, 52, 57, 245MOSFET, xiv, xv, 5, 7, 17, 18,

188, 190, 199, 206, 209,212, 214, 238, 249, 251,257, 260, 263–265, 374

MSM, 315, 316, 318, 320, 334,345–348

Multiple quantum well, 58, 331

Neutral base recombination, 92Noise figure, 185, 186, 365, 368,

369, 372, 378, 379

Numerical methods, 108

Ohmic contact, 272, 276, 278Optical absorption, 58, 321–323,

325Optical detectors, 325Optoelectronic devices, 20Optoelectronic integrated circuits,

310, 311, 315, 328Out-diffusion effects, 90, 92, 120Oxidation, 51, 241, 264, 276

p–i–n diode, 315, 318, 325, 332,334, 335, 341, 343, 363

Parasitic channel, 202, 212, 213,216, 228

Passive component, 25, 363, 386,387

Phase noise, 23, 265, 365, 372,384–386

Phonon scattering, 60, 61, 63,111, 113, 199, 200, 213

Photoconductor, 315Photodetector, 306, 310, 315,

317–320, 325, 328, 329,332, 334, 336–338, 341,345, 346, 350

Photodiodes, 315, 318, 320, 332,334, 335, 342

Photoluminescence, 50, 57, 312Phototransistor, 314Plasma processing, 48, 241Poly-SiGe, 259–261Power added efficiency, 364, 365,

382, 383Power amplifier, 12, 23, 24, 363,

367, 377, 381–384Power delay product, 174, 228,

231Propagation delay, 4, 99, 141,

142, 154

Quality factor, 385Quantum device, 20, 239

400 Index

Quantum efficiency, 316–318, 321,328, 329, 332, 334, 337,338, 350

Quantum well, 17, 44, 218, 222,239, 242, 245, 247, 255,328

Radiation effect, 186Radiation hardness, 190, 256Raman spectroscopy, 51Rapid thermal CVD, 47, 175Remote plasma CVD, 48Responsivity, 320, 325, 327, 331,

332, 338, 343, 345, 347,348, 353

RF communication, xiii, 21, 359,387

RFIC, 360, 367, 383Rutherford backscattering spectro-

metry, 279

Scattering mechanisms, 105, 110,198, 199

Scattering parameters, 109Schottky barrier diode, 293, 317Schottky barrier height, 293Schottky gate FET, 204, 221,

222, 228Secondary ion mass spectro-

metry, 41Self-aligned technology, 8, 120,

142, 159, 221Self-heating effect, 152, 167, 206,

371Setback layer, 230Shockley–Read–Hall recombina-

tion, 117, 337Shot noise, 183, 185, 320SiC, 1, 10, 241, 314, 327SiGe, xiii, 1, 2, 9, 13–15, 35, 40,

42, 54, 59, 77, 115, 254,263, 321, 325

SiGeC, xiv, 13, 15, 18, 32, 42, 49,50, 56, 59, 241, 257, 260,

264, 277, 310, 314, 321,327, 334

SiGeSnC, 314, 352Silicides, 272, 274, 276–278SIMOX, 242, 250, 255, 256, 329,

362, 371Small-signal analysis, 109, 134,

139, 338SOI, 7, 142, 152, 161, 166, 172,

241, 254, 328, 370–372,392

Solid phase epitaxy, 49Space-charge recombination, 36Spacer layer, 92, 94, 100, 143,

173, 174, 221SPICE parameter, 140, 142–144Strain compensation, 60, 259Strain relaxation, 36, 40, 258,

276, 277, 286, 375Strained layer epitaxy, 33Strained silicon, 36, 196Superlattice, 311, 313, 328, 351Surface passivation, 47Surface recombination velocity,

188, 288Surface scattering, 111, 242, 256

Technology comparison, 367Tensile strain, 60, 209Thermalnoise, 183, 185stability, 52, 257

Thermal oxidation, 51Thermal stability, 51Thermionic emission, 276, 288,

292, 297, 317, 320Thermionic field emission, 288,

292, 297Thin-film technology, 261, 274Third-order intermodulation, 380Transmission electron microscope,

285Transport, 60, 105, 107, 217Tunnelling, 94, 99, 290, 336

Index 401

Tunnelling current, 8, 75, 173,260

ULSI, 196, 241Ultrahigh vacuum CVD, 13, 46

Valence band, 58, 330discontinuity, 55, 77, 203, 216,

291Valence band offset, 39, 49, 52,

53, 57, 58, 90, 94, 197, 203Velocity overshoot, 162, 199, 216

Velocity saturation, 94, 100, 111,199, 217

Vertical transistor, 181, 241, 263,264

Very low pressure CVD, 48Voltage controlled oscillator, 24,

366, 384, 386

Wireless communication, 363

X-ray diffraction, 51, 274

application of sige hetero structure

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