application of scientific method to ic design flow.pdf
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By Srinivas Siripurapu
May 2011
Seer Akademi2011
Application of Scientific problem
solving method to IC design flow
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Scientific method of problem solving
:basic steps
State the problem
Formulate a hypothesis
Test the hypothesis
Collect the data
Analyze the data and decide what to donext.
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Apply these steps to the IC design
flow
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Step # 1: State the Problem A problem can't be solved if it isn't understood.
Observe that your chip lacks something. It might be not
floor planned, un-routed, or it perhaps it has DRC violations.
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Step # 2: Form a Hypothesis This is a possible solution to the problem formed after
gathering information about the problem. The term"research" is properly applied here.
Standard cell overlapping? Possible because core utilization isspecified is more or even the core area is less.
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Step # 3: Test the Hypothesis An experiment is performed to determine if the hypothesis
solves the problem or not. Experiments are done to gatherdata. It is very important that good observations and recordsare made during an experiment.
Re initialize the floorplan with the constraints that youthought as near to the solution.
Redesign the power / ground straps.
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Step # 4: Collect the Data This is where you record your observations,
measurements, or information from experiment.
Collect the data to be analyzed that decides whetheryour hypothesis failed or passed.
verify_pg_nets -pad_pin_connection all
Verify_drc > ../reports/drc_check.rpt
Report_congestion > ../reports/congestion.rpt
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Step # 5 : nalyze the Data Just what does all that data indicate about answering the
problem you are solving?
Information: Reporting global route congestion data from Milkyway...
Both Dirs: Overflow = 27 Max = 0 (0 GRCs) GRCs = 0 (34.00%)
H routing: Overflow = 27 Max = 27 (0 GRCs) GRCs = 27 (34.00%)
V routing: Overflow = Max = 0 (0 GRCs) GRCs = 0 (0.00%)
This report shows that there is congestion in Horizontal sections
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Step #6 : Draw Conclusions After examining the data from the experiment,
conclusions can be drawn. In it's simplest form, theconclusion will be "yes" the hypothesis was correct, or"no" the hypothesis was not correct.
Based on the results in previous step you may want toredesign your floorplan, or to choose another routing
options etc..
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Control your design flow
Chip design is an iterative process.
The design flow is run repeatedly as it is extended andrefined into a program that can automatically build the entirechip.
Your flow needs software to make sure that only thenecessary steps are executed, in the correct order, on thecorrect data.
Different hierarchical blocks must be constructed similarly,yet differently.
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Flow steps
Dont tempt to write huge script to run EDA tool from
start to finish.
Separate the flow into smaller steps that performindividual tasks.
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Reentrant step
Each step must be reentrant.
This means that you can safely restart the flow at any step.
The most basic requirement for reentrance is that the stepreads data from one database at the beginning, and saves theresult in a database with a different name at the end.
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Descriptive names
Give each step a short, yet descriptive name.
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Input to Output
Where reasonable and efficient, the inputs and outputs of astep use independent/proprietary formats.
Tip:
Use vendor independent formats like Open-Access, LEF,DEF or Verilog most of the times.
But many steps are best saved as a proprietary database,
particularly in place and route. Milkyway database in ourcase.
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Commit and Exit safely
End steps at points where you have a meaningful, stableresult that will allow you to make an informed decision aboutwhat to do next.
For example, produce a legal placement, create a timingreport, and then end the step.
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Fine grained steps
The more iterations required to get a step right, theshorter the step should be.
An example of this is power routing, where you oftentweak your power routing script, run, and observe theresults several times before it works correctly.
Note: However, starting and stopping EDA tools, reading and writingdatabases takes time and space. For the sake of economy, you want fewer steps.
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Flow control architecture
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Flow controller
Flow controller is the boss. It manages the execution of flow steps like placement or
timing analysis.
It may be a simple shell script or a well organizedsoftware program.
Sample shell script is shown in next slides. See how toexecute the flow iteratively.
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Run the same command over and over
Run the same shell script(flow controller) at any time.
Unix % ./run
Comment out the commands that we dont want whenexecuting a particular step.
Once all steps are finished remove comments and executethe full design flow.
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When floor planningAll other statements are commented
#! /bin/sh
export flowPath=../../flow
# icc_shell -f ${flowPath}/icc/scr/netlistIn.tcl | tee netlistIn.log
icc_shell -f ${flowPath}/icc/scr/floorplan.tcl | tee floorplan.log
# icc_shell -f ${flowPath}/icc/scr/pgRoute.tcl | tee pgRoute.log
# icc_shell -f ${flowPath}/icc/scr/setupTiming.tcl | tee setupTiming.log
#icc_shell -f ${flowPath}/icc/scr/placement.tcl | tee placement.log
#icc_shell -f ${flowPath}/icc/scr/cts.tcl | tee cts.log # and so on...
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Now P/G routing
#! /bin/sh
export flowPath=../../flow
# icc_shell -f ${flowPath}/icc/scr/netlistIn.tcl | tee netlistIn.log
# icc_shell -f ${flowPath}/icc/scr/floorplan.tcl | tee floorplan.log
icc_shell -f ${flowPath}/icc/scr/pgRoute.tcl | tee pgRoute.log
# icc_shell -f ${flowPath}/icc/scr/setupTiming.tcl | tee setupTiming.log
#icc_shell -f ${flowPath}/icc/scr/placement.tcl | tee placement.log
#icc_shell -f ${flowPath}/icc/scr/cts.tcl | tee cts.log # and so on...
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Now setup timing
#! /bin/sh
export flowPath=../../flow
# icc_shell -f ${flowPath}/icc/scr/netlistIn.tcl | tee netlistIn.log
# icc_shell -f ${flowPath}/icc/scr/floorplan.tcl | tee floorplan.log
# icc_shell -f ${flowPath}/icc/scr/pgRoute.tcl | tee pgRoute.log
icc_shell -f ${flowPath}/icc/scr/setupTiming.tcl | tee setupTiming.log
#icc_shell -f ${flowPath}/icc/scr/placement.tcl | tee placement.log
#icc_shell -f ${flowPath}/icc/scr/cts.tcl | tee cts.log # and so on...
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Now placment
#! /bin/sh
export flowPath=../../flow
# icc_shell -f ${flowPath}/icc/scr/netlistIn.tcl | tee netlistIn.log
# icc_shell -f ${flowPath}/icc/scr/floorplan.tcl | tee floorplan.log
# icc_shell -f ${flowPath}/icc/scr/pgRoute.tcl | tee pgRoute.log
# icc_shell -f ${flowPath}/icc/scr/setupTiming.tcl | tee setupTiming.log
icc_shell -f ${flowPath}/icc/scr/placement.tcl | tee placement.log
#icc_shell -f ${flowPath}/icc/scr/cts.tcl | tee cts.log # and so on...
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Now clock tree synthesis
#! /bin/sh
export flowPath=../../flow
# icc_shell -f ${flowPath}/icc/scr/netlistIn.tcl | tee netlistIn.log
# icc_shell -f ${flowPath}/icc/scr/floorplan.tcl | tee floorplan.log
# icc_shell -f ${flowPath}/icc/scr/pgRoute.tcl | tee pgRoute.log
# icc_shell -f ${flowPath}/icc/scr/setupTiming.tcl | tee setupTiming.log
#icc_shell -f ${flowPath}/icc/scr/placement.tcl | tee placement.log
icc_shell -f ${flowPath}/icc/scr/cts.tcl | tee cts.log # and so on...
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Conclusion
IC design is an iterative process. Scientific method of problem solving applies for
IC design flow too.
Use creativity to design your flow.
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Personal appeal to my friends
Use your common sense to organize your work. Know your problems before starting your work otherwise
you simply wasting your time by running monotonouscommands all the time without any results, and results in
frustration.icc_shell
icc_shell .
Bore Bore ..
Then solve your problems on your time not on others.
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All the best for your projects
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Explore more reference flows
http://www.tsmc.com/english/c_services/c01_design/c0105_reference.htm
(this link is subjected to change)
http://www.cadence.com/Community/blogs/di/archive/2009/01/29/demo-and-interview-the-encounter-foundation-flow.aspx
http://theasicguy.com/2009/03/16/synopsys-lynx-design-system-debuts-at-snug
Srinivas Siripurapu Seer Akademi 2011
http://www.tsmc.com/english/c_services/c01_design/c0105_reference.htm(thishttp://www.tsmc.com/english/c_services/c01_design/c0105_reference.htm(thishttp://www.cadence.com/Community/blogs/di/archive/2009/01/29/demo-and-interview-the-encounter-foundation-flow.aspxhttp://www.cadence.com/Community/blogs/di/archive/2009/01/29/demo-and-interview-the-encounter-foundation-flow.aspxhttp://www.cadence.com/Community/blogs/di/archive/2009/01/29/demo-and-interview-the-encounter-foundation-flow.aspxhttp://theasicguy.com/2009/03/16/synopsys-lynx-design-system-debuts-at-snughttp://theasicguy.com/2009/03/16/synopsys-lynx-design-system-debuts-at-snughttp://theasicguy.com/2009/03/16/synopsys-lynx-design-system-debuts-at-snughttp://theasicguy.com/2009/03/16/synopsys-lynx-design-system-debuts-at-snughttp://theasicguy.com/2009/03/16/synopsys-lynx-design-system-debuts-at-snughttp://theasicguy.com/2009/03/16/synopsys-lynx-design-system-debuts-at-snughttp://theasicguy.com/2009/03/16/synopsys-lynx-design-system-debuts-at-snughttp://theasicguy.com/2009/03/16/synopsys-lynx-design-system-debuts-at-snughttp://theasicguy.com/2009/03/16/synopsys-lynx-design-system-debuts-at-snughttp://theasicguy.com/2009/03/16/synopsys-lynx-design-system-debuts-at-snughttp://theasicguy.com/2009/03/16/synopsys-lynx-design-system-debuts-at-snughttp://theasicguy.com/2009/03/16/synopsys-lynx-design-system-debuts-at-snughttp://theasicguy.com/2009/03/16/synopsys-lynx-design-system-debuts-at-snughttp://theasicguy.com/2009/03/16/synopsys-lynx-design-system-debuts-at-snughttp://theasicguy.com/2009/03/16/synopsys-lynx-design-system-debuts-at-snughttp://theasicguy.com/2009/03/16/synopsys-lynx-design-system-debuts-at-snughttp://www.cadence.com/Community/blogs/di/archive/2009/01/29/demo-and-interview-the-encounter-foundation-flow.aspxhttp://www.cadence.com/Community/blogs/di/archive/2009/01/29/demo-and-interview-the-encounter-foundation-flow.aspxhttp://www.cadence.com/Community/blogs/di/archive/2009/01/29/demo-and-interview-the-encounter-foundation-flow.aspxhttp://www.cadence.com/Community/blogs/di/archive/2009/01/29/demo-and-interview-the-encounter-foundation-flow.aspxhttp://www.cadence.com/Community/blogs/di/archive/2009/01/29/demo-and-interview-the-encounter-foundation-flow.aspxhttp://www.cadence.com/Community/blogs/di/archive/2009/01/29/demo-and-interview-the-encounter-foundation-flow.aspxhttp://www.cadence.com/Community/blogs/di/archive/2009/01/29/demo-and-interview-the-encounter-foundation-flow.aspxhttp://www.cadence.com/Community/blogs/di/archive/2009/01/29/demo-and-interview-the-encounter-foundation-flow.aspxhttp://www.cadence.com/Community/blogs/di/archive/2009/01/29/demo-and-interview-the-encounter-foundation-flow.aspxhttp://www.cadence.com/Community/blogs/di/archive/2009/01/29/demo-and-interview-the-encounter-foundation-flow.aspxhttp://www.cadence.com/Community/blogs/di/archive/2009/01/29/demo-and-interview-the-encounter-foundation-flow.aspxhttp://www.cadence.com/Community/blogs/di/archive/2009/01/29/demo-and-interview-the-encounter-foundation-flow.aspxhttp://www.cadence.com/Community/blogs/di/archive/2009/01/29/demo-and-interview-the-encounter-foundation-flow.aspxhttp://www.cadence.com/Community/blogs/di/archive/2009/01/29/demo-and-interview-the-encounter-foundation-flow.aspxhttp://www.cadence.com/Community/blogs/di/archive/2009/01/29/demo-and-interview-the-encounter-foundation-flow.aspxhttp://www.cadence.com/Community/blogs/di/archive/2009/01/29/demo-and-interview-the-encounter-foundation-flow.aspxhttp://www.tsmc.com/english/c_services/c01_design/c0105_reference.htm(thishttp://www.tsmc.com/english/c_services/c01_design/c0105_reference.htm(thishttp://www.tsmc.com/english/c_services/c01_design/c0105_reference.htm(this