apple macbook m42b
TRANSCRIPT
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8/9/2019 Apple Macbook M42B
1/83
ANGLES
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPCK
ECNZONEREV
DO NOT SCALE DRAWING
X.XXX
X.XX
XX
DIMENSIONS ARE IN MILLIMETERS
THIRD ANGLE PROJECTIOND
SIZE
APPLICABLE
NOTED AS
MATERIAL/FINISH
NONE
SCALE
DESIGNER
MFG APPD
DESIGN CK
RELEASE
QA APPD
ENG APPD
DRAFTER
METRIC
SHT
DRAWING NUMBER
TITLE
NOTICE OF PROPRIETARY PROP
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PII NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSTHE INFORMATION CONTAINED HEREIN IS THE P
Apple Computer
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A
B
C
D
DESCRIPTION OF CHANGE
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TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)BOM OPTION
TABLE_5_HEAD
QTY DESCRIPTIONPART#
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
3/22/2007
M42B MLB NO_LDO SCHEMATIC
LD-LINDA DUNN
LT-LAWRENCE TANSchematic / PCB #s
DK
DRI
EE DRIS:
RX-RAYMOND XU
ES
RX
MK
DK-DINESH KUMAR
RC-RAY CHANG
MK-MARC KLINGELHOFER
MK
LT
MKMK
DK
LT
MK
DK
DK
ES
MKMK
MK
MKDK
RX
ES
MKLD
MKESESESESESESES
ES
ESDKDKLTLTLT
RX
ES
RXRX
RX
DK
RX
RX
MK
RX
MK
RX
DK
MK
DK
MK
DK
ESRX
RX
MK
RX
MKRX
RX DK
ES
RXDK
DK
DRI
PBUS Supply/Battery Charger SMC83
66 08/19/2005
TEMPERATURE SENSE ENET6249 11/09/2005
Contents Sync(.csa) Date
Page(.csa)
ContentsPage SyncDate
SCHEM,M42B,MLB NO_LDO051-7374 SCH1
PCBF,M42,MLB NO_LDO820-1889 PCB1
1 N/A
N/A1
Table of ContentsSPI BOOTROM MASTER
6350 5/23/05
Fan ENET6551 11/10/2005
SMS SMC66
52 08/23/2005
TPM SMC67
53 07/18/2005
AUDIO: CODEC M42AUDIO68
54 08/05/2006
AUDI0: SPEAKER AMP M42AUDIO7255 08/05/2006
AUDIO: JACK M42AUDIO73
56 08/05/2006
AUDIO: JACK TRANSLATORS M42AUDIO74
57 08/05/2006
IMVP6 CPU VCore Regulator POWER75
58 07/13/2005
5V / 3.3V Power Supply POWER76
59 07/13/2005
2.5V/1.2V Regulator ENET77
60 12/06/2005
1.8V Supply POWER78
61 07/13/2005
1.5V / 1.05V Power Supply POWER79
62 07/13/2005
S3/S0 FETS, G3H SUPPLY ENET80
63 08/30/2005
ENET81
64 11/16/2005
Power Conn / Alias
DC-In & Battery Connectors POWER82
65 07/13/2005
INVERTER,LVDS,TMDS GRAPHIC94
67 06/06/2005
GRAPHIC95
68 06/06/2005
EXTERNAL TMDS
MINI-DVI CONNECTOR EUGENE9869
05/21/05
Cross Reference Page9970
Cross Reference Page10071
Cross Reference Page10172
Cross Reference Page10273
Cross Reference Page10374
Cross Reference Page10475
Cross Reference Page10576
Cross Reference Page10677
Cross Reference Page10778
Cross Reference Page10879
2 5/23/05
MASTER2
SYSTEM BLOCK DIAGRAM
3 06/30/2005
POWER3
Power Block Diagram
4 07/18/2005
SMC4
CONFIGURATION OPTIONS
5 07/25/2005
TP5
FUNC TEST 1 OF 2
6
08/19/2005
ENET
6
SIGNAL ALIAS /RESET7 05/03/2005
MASTER7
CPU 1 OF 2-FSB
8 05/03/2005
MASTER8
CPU 2 OF 2-PWR/GND
9 08/19/2005
SMC9
CPU DECAPS & VID
10 08/19/2005
ENET10
CPU MISC1-TEMP SENSOR
11 5/23/05
MASTER11
CPU ITP700FLEX DEBUG
12 07/25/2005
NB12
NB CPU Interface
13 07/25/2005NB13 NB PEG / Video Interfaces14 08/15/2005NB14 NB Misc Interfaces15 07/25/2005NB
15
NB DDR2 Interfaces
16 07/25/2005NB16
NB Power 1
18 07/25/2005
NB18
NB Grounds
19 06/22/2005
NB19
NB (GM) Decoupling
20 06/28/2005
NB20
NB Config Straps
21 08/05/2005
SB21
22 11/16/2005
ENET22
23 11/28/2005
ENET23
24 08/05/2005
SB24
25 06/28/2005
SB25
26 07/26/2005
NB26
SB Misc
28 06/20/2005
MEMORY28
DDR2 SO-DIMM Connector A
29 06/20/2005
MEMORY29
DDR2 SO-DIMM Connector B
30 06/20/2005
MEMORY30
Memory Active Termination
31 (MASTER)
(MASTER)31
Memory Vtt Supply
32 06/03/2005
CLOCK33
CLOCKS
33 06/06/2005
CLOCK34
CLOCK TERMINATION
34 11/01/2005
ENET38
PATA CONNECTOR
35 11/14/2005
ENET39
SATA CONNECTOR
36 12/06/2005
ENET41
ETHERNET CONTROLLER
37 11/14/2005
ENET42
ETHERNET CONNECTOR
38 08/30/2005
ENET44
FIREWIRE CONTROLLER
39 11/16/2005
ENET45
FIREWIRE PORT
40 11/16/2005
ENET49
CONNECTOR MISC
41 11/09/2005
ENET51
IR CONTROLLER
42 11/01/2005
ENET52
43 08/19/2005
ENET53
44 08/29/2005
ENET54
BLUETOOTH INTERFACE
45 08/18/2005
SMC58
SMC
46 08/23/2005
SMC59
SMC SUPPORT
47 06/30/2005
NB60
LPC+ Debug Connector
48 08/30/2005
ENET61
CPU Current & Voltage Sense
27 08/30/200527
M42 SMBUS CONNECTIONS ENET
17 07/25/2005
NB17
NB Power 2
SCHEM,MLB NO_LD
051-7374
355269 12/07 ENGINEERING RELEASED
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8/9/2019 Apple Macbook M42B
2/83
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSTHE INFORMATION CONTAINED HEREIN IS THE P
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A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
IR_RX_OUT
SATA
IR
HDDConnector
P.35
USB
USB
P.41
CONTROLLER
66MHZ
P.34
Connector PATA
AZALIA
TP CONNECTOR
INTERNAL KB
ODD16BITS
P.54-57
P.40
AUDIO
P.64
SMBUS
SPI
SPI FLASH
P.51
P.50
P.45
P.52
P.53P.47
P.58~P.66
P.44
P.43
P.68
P.42
P.69
P.67
P.67
LCD Panel
INVERTER
CONNECTOR
MINI DVI &
CRT CONNECTOR
ETHERNET
CONNECTORP.37
FW CONNECTOR
DMIX4
PCIEX1
SDVO
P.12-20
609 BGA
CHIPSET-SB
FSB
479 BGA
PROCESSORCLOCKING
THERMAL
LVDS
ENET CONTROLLER
P.36
FAN
CONNECTOR
P.27
1466UFCBGA
CHIPSET-NB
P.39
LPC 33MHZ
P.26
TO WIRELESS
CONNECTOR TO
CH.B
BATTERIES
& Charger
CONNECTOR
CARD
SMBUS
REGULATOR
P.31
Config
USB 2.0
SMS
DDR2 VTT
P.29
SO-DIMM Connector
J2900
J2800
DDR2 SDRAM DIMM B
SO-DIMM Connector
DDR2 SDRAM DIMM A
P.28
CONNECTOR
P.7-9
SENSOR
CPU
P.32-33
AND SPECTRUM
POWER SUPPLY
USB
FW
PCI
DEBUG
CONNECTOR
CH.ATV+CRT
TMDS TMDS
P.10
5VUSB
ENET
PCIEX1
P.38
FW CONTROLLER
BLUETOOTH
LPCTPM
SB MISC.
P.21-26
SMCBOOTROM
2
051-7374
SYSTEM BLOCK DISYNC_MASTER=MASTER SYNC
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8/9/2019 Apple Macbook M42B
3/83
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSTHE INFORMATION CONTAINED HEREIN IS THE P
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A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
VOUT
(PAGE 68)
PP2V5_S0
(0.3A MAX CURRENT)
PP2V5_S0_NB_DISP_PLL
CURRENT)
17
(0.3A MAX CURRENT)
VOUT
(PAGE 59)
U7701
MAX8887
VIN
(PAGE 59)
VOUT
Q8005
R=100k
c=0.1uf
R=10k
Q8030 Q8030
DELAY
(S0)
1V5S0_RUNSS
DELAY
P1V2S0_EN
c=0.01uf
(S3)
R=10k
c=2.2nf
DELAY
DELAY
PP3V3_S0
(S0)ENA
S0PWRGD_OK
VR_PWRGOOD_DELAY
POWER ON SEQUENCE LIST
VADJ1(1.2V)
V1(1.8V)
V1(2.5V)
(S3)
1.8V
LTC2908
SLP_S4_L
(S3)
(S0)
START
SOFT
(S5)
02
02
1V5S0_RUNSS
PBUSB_VSENSE
01
ENA11.5VVIN
VOUT1
1.05V
LTC3728U7900
(PAGE 61)
02
ENA2
SMC_BATT_ISENSE
(PAGE 19)
(PAGE 65)
DELAY
Q8061
Q8061
ISL6269
ENA
U1900
P5VS0_EN_RC
U7800(PAGE 60)
(S0)
PPBUS_S5_FWPWRSW
(6A MAX CURRENT)
ENA
U7700
ALL_SYS_PWRGD
RESET*
RSMRST_IN(P13)
(PAGE 62)
CY28445-5
(PAGE 33)
CLKEN#
CHGR_EN
PP1V2_S3_ENET
(PAGE 44)
U2603
VR_PWRGD_CK410
U3301
CLOCK
RSMRST*
Q8025Q8031
SLP_S3_L
ICH
(S0)
Q8062
SMC
RSMRST_OUT(P15)
99ms DLY
IMVP_VR_ON(P16)
PWRGD(P12)
P25
P60
SLP_S3_L(P93)
SLP_S4_L(P94)
(PAGE 44)U5800
NO AC/BATTERY
STEP
01-04
H(S5 ON)
H(S5 ON)
01,05-09
L(S5 OFF)
L(S5 OFF)
U2601
PWROK HCPURST*
PM_SLP_S4_L
3S2P / 3S3P
VR_ON
U8070
V1(5V)
RST*
04
DCIN
ENABLES
(S5)
U5900
MC33465N_30ATR
PBUS CONVERTER/
AC
INADAPTER
ENABLE
PP3V42_G3H_REG
VOUT
VIN
VOUT
PGOOD
SMC
U1901
PP1V5_S0
SMC PWRGD
SMC_RST_L
PWRGD
MCH
CK410_PD_VTT_PRGD_L
PWRGOOD
(PAGE 62)
3.425V G3HOTLT3470
PM_PWRBTN_L
PLTRST*
PWRBTN*ICH
VOUT
06
6A FUSE
6-1
200ms
7ms
VIN
ENA
CPU
PLT_RST*
P17(BTN_OUT)
99ms
VIN
(8A MAX CURRENT)
VIN
(S5)
A ISL6255
U8300
A
03
(PAGE 45)
U8090
VPPBUSA_G3HA
SMC_DCIN_ISENSE
01
BATTERY
BATTERY CHARGER
7A FUSE
VRMPWRGD
CPUPWRGD(GPIO49)
(S0)SOFT
U5800
Q8031
LOGIC
ENA1
START
U7600
SLP_S5_L
(S0)
PP1V2_S0
2.5V
BATT_POS_F
U8370
U8375
U8310Q6150
U6100
ENA
PPVBAT_S5_CHGR_REG
A
VOUT1
ENA
(S3)
8
VOUT2
(4A MAX
VIN
Q8010PP3V3_S3
SLP_S3_L
VADJ2(0.9V)
09
BATTERY ONLY:
SLP_S5_L
SLP_S4_L
10-13
14-18
17,19-24
25-27
2
SLP_S3_L
15
16
1V05S0_RUNSS
PGOOD
16
P3V3S0_EN_RC(S0)c=0.1uf
16
P1V8S0_EN_L_RCc=0.01uf
16
R=100k 16
11
SLP_S4_L
R=100k 12
12PP5VS3_EN_L_RC
SMC_PM_G2_ENABLE
CHGR_EN
Q805907
VIN
3.3V
LTC3728
PGOOD
3V3S5_RUNSS
5V3V3S5_PGOOD
9
12RSMRST_PWRGD
PP3V3S3_EN_L_RC
VIN
2.5VMAX8887
(S0)
P3V3S0_EN_RC
Q8015
16
17
08
P5VS0_EN_RC(S0)8
5VENA2
2
Q80595VS5_RUNSS(S5)
Q8060
16
PP5V_S5_REG
(5A MAX CURRENT)
PP3V3_S5_REG
VOUT1
12
PPBUSB_G3H
07
13(PAGE 58)
(S3)
VIN
(PAGE 19)
PP3V3_S5
18
PP1V5_S0_DPLL 18_1
PP1V8_S0
1.2V
(PAGE 59) 17
PP0V9_S0VOUTENA
VOUT
BATTERY ONLY,PRESS PWR BUTTON
ACIN WITH/WITHOUT BATTERY
BATTERY ONLY
STEP 06 (S5 POWER STATUS)TRUTH TABLEPLATFORM,CPU RESET
SMC_RST_LRST*
08-1ADAPTER IN :
19
S0PWRGD_OK
PWR/RST STATUS
G3H POWER ON
S5 POWER ON
S3 POWER ON
S0 SYSTEM POWER ON
S0 CPU POWER ON
IMVP_VR_ON
SIGNAL DELAY TIME
17-1
MM157
TV 3.3V
AUDIO 4.5V
08
14
PP2V5_S3
PP3V3_S0_AUDIO
17
PGOOD
PP5V_S3
16(S0)
16(S0)
1V05S0_RUNSS
PP5V_S0
CPUVCOREPGD_IN
17
PP1V05_S0VOUT2 17
Q8000
18
VIN
SMC_CPU_VSENSE
1V51V05S0_PGOOD
13
ISL6262
VR_PWRGD_CK410_L
SMC_CPU_ISENSE
V
VOUT
IMVP_VR_ON
(S0)P5VS3_EN_L_RC
22
PPVCORE_CPU_S0
(36A MAX CURRENT)
PP5V_S5
23
(PAGE 57)U7500
21(S3)
24
TPS79501VR6800
PP3V3_S0_NB_TVDAC
25
PM_SB_PWROK
26PWROK
17-1
27
PLT_RST_L
CPU_PWRGD
PP4V5_AUDIO_ANALOG
28
FSB_CPURST_L
19U808010
PWR_BUTTON(P90)
V1(3.3V)
21IMVP_VR_ON
PM_RSMRST_L
VR_PWRGOOD_DELAY
RSMRST_PWRGD
SMC_ONOFF_L
05
SLP_S5_L(P95)
16
P3V3S3_EN_L_RC
17
MCH DPLL 1.5V
TPS73115
(PAGE 31)
12
PP1V8_S3_REG
13
16 P1V2_S0_EN
PP5V_S0_MEMVTT
U3100BD3535FVM
VIN
0.9V
16P1V8S0_EN_L_RC
17
(8A MAX CURRENT)
18
Q8063U7720
MAX8516
ENA
M42A POWER SYSTEM ARCHITECTURE
051-7374
3
SYN
Power Block Diag
SYNC_MASTER=POWER
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8/9/2019 Apple Macbook M42B
4/83
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_HEAD
QTY DESCRIPTIONPART#
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_HEAD
QTY DESCRIPTIONPART#
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_HEAD
QTY DESCRIPTIONPART#
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
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A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
BOTTOM
L9 SIGNAL
L11-L12
L11 GROUND
L8-L9
SIGNAL(High Speed)
L4 SIGNAL
L2 GROUND
(MM)
0.018
L1-L2
L1 SIGNAL(TOP)
CONFORMAL_COAT
BETTER-ST
BEST-KIONIX
BEST-ST
POST-RAMP-DIMM35
>
>
>
>
>
>
>
TRACE WIDTH
ACCEL_KIONIX
ACCEL_ST
INVERTER_BUF
5V3V3S3_CONT
1V51V05S0_SKIP
1V51V05S0_CONT
BOMOPTION
NBCFG_DMI_X2
BOM OPTION
5V3V3S3_SKIP
INVERTER_UNBUF
MEMVTT_EN_PU
ITP
NBCFG_DMI_REVERSE
>
>
NBCFG_VCC_1V5
>
>>
EVT630-7795
>
>
M42
M42A >> >>
>
0.031
L8 GROUND
1.276
SIGNAL(High Speed)
GROUND
3
6
10
FET_FDN6296
3V3_IND_3MM
ONEWIRE_ALWAYSON
ONEWIRE_PULLUP_OLD
>>>>
NBCFG_DYN_ODT_DISABLE
>
>
PVT-DIMM
TPM
BETTER-KIONIX
GOOD-ST
FANCY
NORMAL
STANDOFF
ONEWIRE_PU_ACOK
ONEWIRE_PU_PROT
ONEWIRE_PWRCTL
BETTER
GOOD
BEST
USB_C_OC_PU
USB_D_OC_PU
USB_E_OC_PU
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> >
>
>
>
>
>
>
>
>
>
>
>
>>
M42A GOODST MICRO
>
>>
630-7796
EVT
>
>
EVT
>
>
>
ST MICROM42A BETTER
630-7799
M42A BESTKIONIX
>
>
630-7798EVT
KIONIX
>
>
>
630-7736
EVT
>
>>
KIONIXM42A BETTERM42A GOOD
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
EVT
ST MICRO630-7797
M42A BEST
0.047
MLB STACKUPLAYER THICKNESS
0.014
L2-L3
0.076
0.079
---
0.014
0.156
0.076
0.014
0.014
(MM)
0.07
0.1
L5 GND
0.076
0.1
0.1
0.1
0.014
L6 POWER
L7 POWER
0.079
---
0.07
---
L7-L8
L6-L7
L4-L5
0.014
0.156
0.018
0.076
0.031
0.014
0.07
0.07
0.047 0.1
---
---
---
9
8
7
5
4
Top SIGNAL
GROUND
POWER
POWER
GROUND
BOM options provided by this page:
Signal aliases required by this page:
Power aliases required by this page:
(NONE)
(NONE)
(NONE)
Page Notes
3V3_IND_2MM8
NO_REBOOT_MODE
NBCFG_SDVO_AND_PCIE
NBCFG_PEG_REVERSE
>
ONEWIRE_PULLUP
M42A_PGM0.076
L5-L611
>
>
>
L3 SIGNAL
L3-L4
>
>
>
>
>
>
>
>
GOOD-KIONIX
FET_STL8NH3LL
> > > > >
>
>
>LEMENU
SIGNAL
GROUND
SIGNAL(High Speed)
SIGNAL(High Speed)
2
BOARD STACK-UP AND CONSTRUCTION
0.014L10 SIGNAL
L9-L10
341S2132 FOR M42B LOCKED BOOTROM
L12 SIGNAL(BOTTOM)
CONFORMAL_COAT
TOTAL
L10-L11
U44001 LEMENU338S0268 IC,FW32306,1394A LINK,BGA,129P
M42A_PGMU58001341S2133 IC,SMC,176P BGA,HS8/2116
EEE:YCT826-4393 LBL,P/N LABEL,PCB,28MMX6MM1 CRITICAL BEST-KIONIX
IC,EEPROM,SERIAL IIC,8KBIT,SO8 M42A_PGMU41021341S1797
GOODIC,MEROM,CPU L2 1.83GHZ,479 PGA U07001337S3450
BETTER337S3389 IC,MEROM,CPU 2.0GHZ,479 PGA U07001
BESTIC,MEROM,CPU 2.16GHZ,479 PGA1337S3391 U0700
EEE:YCSLBL,P/N LABEL,PCB,28MMX6MM1 CRITICAL826-4393 BETTER-KIONIX
GOOD-KIONIXEEE:YCRLBL,P/N LABEL,PCB,28MMX6MM1826-4393 CRITICAL
IC,PSOC+W/USB,56P,MLF,CY8C24794 U5100 M42A_PGM1341S1890
U4101 LEMENU338S0270 1 IC,88E8053,GIGABIT ENET XCVR,64P QFN, NO
1 LEMENUU3301359S0109 IC,SLG8LP436,CLOCK GEN,68PIN QFN
IC, 16MBIT 8-PIN SPI SERIAL FLASH,SOIC8 M42A_PGM1341S2131 U6301
PAGE_BORDER=TRUE
SYNC_DA
051-7374
4
SYNC_MASTER=SMC
CONFIGURATION OP
-
8/9/2019 Apple Macbook M42B
5/83
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
CLOCK NO_TESTS
Power Supply NO_TESTsNO_TEST
INVERTER CONNECTOR FUNC_TEST
Battery charger FUNC_TEST
DC-JACK FUNC_TEST
USB FUNC_TEST
Battery Digital ConneFUNC_TEST
LPC+ Debug Connector
Battery FUNC_TEST
SMC FUNC_TEST
FUNC_TEST
Functional Test Points
Audio FUNC_TEST
NO_TEST
NO_TEST
Power Supply FUNC_TEST
FUNC_TEST
FIREWARE NO_TESTS
NO_TEST
SLEEP LED FUNC_TEST
FIREWIRE FUNC_TEST
SMBus FUNC_TEST
Other Func Test Points
Fan ConnectorsFUNC_TEST
LVDS NO_TESTS
NO_TEST
ETHERNET NO_TESTS
NO_TEST
I1
I10
I101
I102
I103
I104
I105
I106
I107 I11
I111
I112
I113
I114
I115
I116
I117
I118
I119
I12
I120
I121
I122
I123
I124
I125
I15
I151
I152
I153
I154
I155
I156
I157
I158
I159
I16
I160
I161
I162
I163
I164
I165
I166
I167
I168
I169
I17
I170
I171
I172
I173
I174
I175
I176
I177
I178
I179
I18
I180
I181
I182
I183
I184
I185
I186
I187
I188
I189
I19
I190
I191
I192
I193
I194
I195
I196
I197
I198
I199
I2
I20
I200
I201
I202
I203
I204
I205
I206
I207
I208
I209
I21
I210
I211
I212
I213
I214
I215
I216
I217
I218
I219
I22
I220
I23
I24
I25
I29
I3
I31
I32
I33
I36
I38
I4
I44
I45
I46
I47
I48
I57
I58
I59
I60
I61
I63
I71
I72
I73
I74
I75
I76
I77
I78
I79
I80
I81
I82
I83
I84
I85
I86
I87
I88
I89
I9
I90
I91
I92
I93
I94
I95
I96
FUNC TEST 1 OF
051-7374
5
TRUE LVDS_B_DATA_N2_SPN
TRUE CK410_SRC8_N
TRUE CK410_SRC5_P
TRUE CK410_LVDS_P
TRUE CK410_DOT96_27M_PTRUE CK410_DOT96_27M_NTRUE CK410_CPU2_ITP_SRC10_P
TRUE CK410_CPU1_N
TRUE 1V05S0_FSETTRUE 1V05S0_COMP
3V3S5_FSETTRUE
TRUE CK410_SRC6_N
TRUE CK410_SRC_CLKREQ8_LTRUE CK410_SRC_CLKREQ3_L_SPNTRUE CK410_SRC_CLKREQ1_L_SPN
TRUE CK410_SRC6_P
TRUE SMC_BATT_CHG_EN
IMVP6_RBIASIMVP6_COMP
1V8S3_FSET
3V3S5_COMPTRUE
TRUE PP1V05_S0TRUE PPVCORE_CPU_S0TRUE ALL_SYS_PWRGD
5VS5_RUNSS
1V8S3_COMP
1V5S0_RUNSS
TRUE INV_BKLIGHT_PWM_L
TRUE PPBUS_ALL_INV_CONN
TRUE INV_GND
TRUE PP5V_INV_F
TRUE PPVBAT_G3H_CHGR_OU
TRUE ACIN_ENABLE_GATE
TRUE TP_USBN_F
TRUE TP_USBN_E
TRUE TP_USBP_F
TRUE TP_USBP_E
TRUE SMC_BS_ALRT_L
PP5V_S0_AUDIO_PWRTRUE
TRUE ACZ_SDATAOUT
TRUE ACZ_BITCLK
TRUE ACZ_RST_L
TRUE SMC_BATT_ISET
TRUE SMC_BC_ACOK
TRUE SMC_PS_ON
SMC_NMITRUE
SMC_RST_LTRUE
SMC_MD1TRUE
PM_CLKRUN_LTRUE
TRUE SYS_ONEWIRE
TRUE ACZ_SYNC
TRUE ACZ_SDATAIN
TRUE SMBUS_BATT_SCL_F
SMC_TRST_LTRUE
DEBUG_RST_LTRUE
P3V42G3H_FBTRUE
TRUE =PP5V_S0_LPCPLUS
TRUE SMC_BATT_TRICKLE_EN
LPC_ADTRUE
TRUE GND_AUDIO_CODECTRUE GND_AUDIO_PWR
PP5V_S0_AUDIOTRUE
TRUE BATT_NEGTRUE BATT_POSTRUE BATT_IN
TRUE CK410_CPU0_N
TRUECK410_CPU0_P
TRUE CK410_CPU1_P
TRUE CK410_CPU2_ITP_SRC10_N
TRUE CK410_LVDS_N
TRUE CK410_SRC1_P_SPN
TRUE CK410_SRC7_N_SPN
TRUE FW_B_TPA_N_SPN
TRUE FW_B_TPA_P_SPN
TRUE FW_B_TPBIAS_SPN
TRUE CK410_SRC7_P_SPN
TRUE CK410_SRC8_P
TRUE CK410_PCI4_CLK_SPN
TRUE PP2V5_S3TRUE PP1V8_S3TRUE PP1V2_S3
TRUE PP1V5_S0
=PP1V05_S0_REGTRUE
TRUE PP5V_S0TRUE PP3V3_S0TRUE PP2V5_S0TRUE PP1V8_S0
TRUE PP0V9_S0TRUE PP18V5_G3H
TRUE PPBUSB_G3HTRUE PPBUSA_G3HTRUE PP3V42_G3HTRUE PP5V_S5TRUE PP3V3_S5TRUE PP5V_S3TRUE PP3V3_S3
CK410_SRC1_N_SPNTRUE
TRUE CK410_PCIF1_CLK
CK410_SRC2_NTRUECK410_SRC2_PTRUECK410_SRC3_N_SPNTRUECK410_SRC3_P_SPNTRUECK410_SRC4_NTRUECK410_SRC4_PTRUE
TRUE CK410_SRC5_N
TRUE FW_B_TPB_N_SPN
TRUE LVDS_B_CLK_P_SPN
SMC_TCKTRUE
TRUE FW_C_TPBIAS_SPNTRUE FW_C_TPA_P_SPN
PM_SUS_STAT_LTRUE
PCI_CLK_PORT80_LPCTRUE
FWH_INIT_LTRUE
SMC_TX_LTRUE
TRUE FW_B_TPB_P_SPN
TRUE FW_C_TPA_N_SPN
LVDS_B_DATA_N1_SPNTRUE
TRUE LVDS_B_CLK_N_SPN
TRUE FW_C_TPB_N_SPN
TRUE SYS_LED_ANODE
TRUE PPFW_SWITCH
SMBUS_SMC_MLB_SDATRUE
SMBUS_SMC_MLB_SCLTRUE
SMC_RX_LTRUESV_SET_UPTRUE
SMC_TDITRUE
INT_SERIRQTRUE
LPC_ADTRUE
LPC_ADTRUE
SMC_TDOTRUE
SMC_TMSTRUE
BOOT_LPC_SPI_LTRUE
LPC_FRAME_LTRUE
TRUE LPC_AD
=PP3V42_G3H_LPCPLUSTRUE
TRUE SMBUS_BATT_SDA_F
TRUE SMC_FAN_1_TACHTRUE SMC_FAN_1_CTL
=PP3V3_S0_FAN_RTTRUE
FAN_RT_TACHTRUE
FAN_RT_PWMTRUE
=PP5V_S0_FAN_RTTRUE
TRUE LVDS_B_DATA_P1_SPN
TRUE FW_C_TPB_P_SPN
TRUE LVDS_B_DATA_N0_SPN
TRUE SMC_LID
SMC_MANUAL_RST_LTRUE
TRUE SMC_CPU_VSENSE
LVDS_B_DATA_P2_SPNTRUE
ENET_MDI_TRAN_PTRUEENET_MDI_TRAN_NTRUE
SMC_FAN_3_TACHTRUEALS_LEFTTRUE
ENET_MDI_TRAN_PTRUE
53C6
53C6
47C6
53C6
47C5
47B6
47B5
53C6
53C6
53C6
53C6
53C6
65A8
63B1
47C5
45D5
47C6
47C5
46D3
47C5
46D6
46D6
47B5
47C5
47C5
47C5
47C5
47B6
47C6
47C6
47C6
47C6
46C6
33C5
33C5
33A5
33B5
33B5
33D5
33D5
33C5
33A5
33D5
58B7
58B7
45D8
63C7
63B7
47B5
46D7
47B6
38A5
47C6
47C6
64D3
45D8
33D5
33D5
33D5
33D5
33A5
33C5
64D8
33D8
33C5
33C5
33B5
33B5
33C5
46C6
45D5
47C5
21C4
46B2
46A3
46B2
23C3
46C6
45C8
45D8
45D8
46C6
46C6
45C8
45C8
45D8
64D1
51C4
51B4
64A6
64D3
45B5
48B1
46C3
46C3
6D5
32A4
32B4
32B4
32A4
32A4
32C4
32C4
32B4
32A4
6B3
6B3
32B4
58A4
58A4
61C6
64D7
64D7
26A5
59B4
61B6
62B5
45C1
45C3
45C2
23C8
45C1
26B1
63D2
47C6
21D4
32C4
32C4
32C4
32C4
32B4
6B3
6B3
6D1
6D1
6D1
6B3
32A4
64C4
64C4
64C4
64C7
62B1
64D4
64B7
64B7
64C7
64D7
64C1
64C1
64D1
64A4
64A4
64B4
64B4
6B3
32B6
32B4
32B4
6B3
6B3
32B4
32B4
32B4
6D1
6D5
45C5
6D1
6D1
23C5
33D6
6B2
45C8
6D1
6D1
6D5
6D5
6D1
35C5
39D4
27B5
27C5
45C8
23B6
45C5
23C8
21D4
21D4
45C5
45B5
22B3
21C5
21D4
47C6
45B8
45B8
51C4
51C3
51B3
51C4
6D5
6D1
6D5
40C4
46D8
45D5
6D5
37B5
37B5
45B8
45A8
37B5
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8/9/2019 Apple Macbook M42B
6/83
REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_HEAD
QTY DESCRIPTIONPART#
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
DIGITAL GND SCREW HOLE
Ethernet ALIASES
NO-CONNECT UNUSED CLOCK INTERFACE PORTS
(EMI PAD FOR INVERTER GONNECTOR)
I/O CONNECTOR CHASSIS GND
BATTERY,AUDIO,DIP DIMM CONNECTOR CHASSIS GND
NC
NC NC
CHASSIS GND
NO-CONNECT UNUSED SDVO INTERFACE PORTS
PCI_EXPRESS GRAPHICS ALIASES
LVDS ALIASES
NO-CONNECT UNUSED LVDS INTERFACE PORTS
USB PORT "H" = PCI-E Mini Card
USB PORT "F" = IR CONTROLLER
USB PORT D = CAMERA
USB PORT "E" = Unused
USB PORT C = External USB2.0 Port B
ANALOG SWITCH GPIO
USB PORT B = Trackpad(Geyser)
USB PORT A = External USB2.0 Port
USB PORT "G" = BLUETOOTH
FIREWIRE ALIASES
NO-CONNECT UNUSED FIREWIRE INTERFACE PORTS
NB CFG ALIASES
NO-CONNECT UNUSED CFG INTERFACE PORTS
SO-DIMM ALIASESNO-CONNECT UNUSED ADDRESS INTERFACE PORTS
CLOCK ALIASES
SB ALIASESNO-CONNECT UNUSED CLOCK INTERFACE PORTS
NO-CONNECT UNUSED PCI_EXP INTERFACE PORTS
NO-CONNECT UNUSED SATA INTERFACE PORTS
PCI_EXP ALIASES
SATA ALIASES
DIP DIMM CONNECTOR CHASSIS GND
DIP DIMM CONNECTOR CHASSIS GND
SATA,LVDS CONNECTOR CHASSIS GND
DCIN CONNECTOR CHASSIS GND
Z06065R2P3-7SQB
OMIT
1
Z06025R2P3-7SQB
OMIT
1
CERM16V10%
C06080.01uF
1
2
402
16VX5R
1 C06070.1UF10%
2
402
Z06015R2P3-7SQB
1
OMIT
402CERM
10%16V
1
2
0.01uFC0611
X5R16V10%0.1UFC0610
402
1
2
OMIT
5R2P3-7SQBZ0609
1
10%16VCERM402
0.01uFC06131
2
5R2P3-7B
OMITZ0611
1
16VCERM402
0.01uF10%
1
2
C06190.1UF
402X5R16V10%
C06121
2 X5R
C06181
2
402
16V10%0.1UF
05%1/16W
402MF-LF
1
2
R0610
10%16V
C06151
2
402CERM
0.01uF
Z06105R2P3-7SQB
OMIT
1
10%16V
1
2 X5R402
0.1UFC0614
C06170.01uF10%16V
402CERM
1
2
2
1R0611
1/16WMF-LF402
5%0
0.1UF
X5R
10%16V
402
C06161
2
05%
402MF-LF1/16W
R06121
2
1
Z0613STDOFF-4.2OD2.15H-1.2-TH
OMIT
1
STDOFF-4.2OD2.15H-1.2-THZ0612OMIT
1/16WMF-LF
5%0R06211
2402
OMIT
5P0R2P3-7BLBZ0608
1
10%0.1UFC0630
16VX5R402
2
1
EMI-SPRINGZS0620CLIP-SM-M42
11 ZS0621
SM
SPKR-MIC-CLIP-M42
1
Z0604STDOFF-4.5OD3.95H-1.1-3.7-TH1
OMIT
1
Z0621STDOFF-4.5OD3.95H-1.1-3.7-TH1
OMIT
1
Z0603STDOFF-4.5OD3.95H-1.1-3.7-TH1
OMIT
1
Z0605STDOFF-4.5OD3.95H-1.1-3.7-TH1
OMIT
I393
6P5R2P6-5P5BZ0607
1
OMIT
SYNC_MASTER=ENET
6
051-7374
SIGNAL ALIAS /RE
STANDOFFZ0603,Z0604,Z0605,Z0621860-0722 4 THE RMAL STANDOFF
STANDOFFZ0612860-0723 STANDOFF WIRELESS1
STANDOFF860-0749 1 STANDOFF W/THRU HOLES,WIRELESS Z0613
MAKE_BASE=TRUE
ENET_CTRL12_SPN
MEM_B_A15_SPNMAKE_BASE=TRUE
MEM_A_A15_SPNMAKE_BASE=TRUE
SUS_CLK_SB_SPNMAKE_BASE=TRUE
CK410_SRC1_N_SPNMAKE_BASE=TRUE
ENET_CTRL25_SPNMAKE_BASE=TRUE
ENET_CTRL25
=GND_CHASSIS_FW_UPPER
TP_NB_CFG14MAKE_BASE=TRUE
PEG_R2D_C_P
PEG_R2D_C_P
PEG_R2D_C_N
PEG_D2R_P
=GND_CHASSIS_DIPDIMM_LEFT
=GND_CHASSIS_AUDIO_SHIELD3
GND_CHASSIS_IO
=GND_CHASSIS_DIPDIMM_CENTER
GND_CHASSIS_FANSCREW
CPU_THERMAL_SCREW_UP
=GND_CHASSIS_AUDIO_SPKRCONN
INVT_CHGND
PEG_D2R_N
PEG_D2R_N
PEG_D2R_N
PEG_D2R_N5_SPNMAKE_BASE=TRUE
PEG_D2R_N4_SPNMAKE_BASE=TRUE
PEG_R2D_C_P9_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUE
PEG_R2D_C_N8_SPN
PEG_D2R_P6_SPNMAKE_BASE=TRUE
PEG_D2R_P2_SPNMAKE_BASE=TRUE
=GND_CHASSIS_AUDIO_SHIELD2
=GND_CHASSIS_AUDIO_MIC
=GND_CHASSIS_DIPDIMM_RIGHT
=GND_CHASSIS_AUDIO_SHIELD1
PEG_R2D_C_P6_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUE
PEG_R2D_C_P7_SPN
PEG_R2D_C_P
LVDS_B_CLK_P_SPNMAKE_BASE=TRUE
LVDS_B_DATA_N0_SPNMAKE_BASE=TRUE
LVDS_B_DATA_N1_SPNMAKE_BASE=TRUE
LVDS_B_DATA_N2_SPNMAKE_BASE=TRUE
LVDS_B_DATA_P0_SPNMAKE_BASE=TRUE
LVDS_B_DATA_P2_SPNMAKE_BASE=TRUE
GND_CHASSIS_CPU
MAKE_BASE=TRUE
PEG_D2R_P14_SPN
PEG_D2R_P
PEG_D2R_P
PEG_R2D_C_N
PEG_D2R_P
PEG_R2D_C_N
PEG_R2D_C_N
PEG_R2D_C_N
PEG_R2D_C_N
PEG_D2R_P
PEG_D2R_P
PEG_D2R_N
PEG_D2R_N
MAKE_BASE=TRUE
PEG_R2D_C_N9_SPN
MAKE_BASE=TRUE
PEG_R2D_C_P10_SPN
PEG_D2R_N
PEG_R2D_C_N
PEG_D2R_N
PEG_D2R_N
PEG_D2R_P
PEG_D2R_P
PEG_D2R_N11_SPNMAKE_BASE=TRUE
PEG_R2D_C_P
PEG_D2R_N
LVDS_B_DATA_P1_SPNMAKE_BASE=TRUE
PEG_R2D_C_P
PEG_R2D_C_P
PEG_R2D_C_P15_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUE
PEG_R2D_C_P14_SPN
MAKE_BASE=TRUE
PEG_R2D_C_N11_SPN
PEG_D2R_P8_SPNMAKE_BASE=TRUE
PEG_D2R_P7_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUE
PEG_D2R_P4_SPN
PEG_D2R_N13_SPNMAKE_BASE=TRUE
PEG_D2R_N10_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUE
PEG_D2R_N0_SPN
MAKE_BASE=TRUE
PEG_D2R_P10_SPN
PEG_D2R_P5_SPNMAKE_BASE=TRUE
PEG_D2R_N6_SPNMAKE_BASE=TRUE
PEG_D2R_N
PEG_D2R_N8_SPNMAKE_BASE=TRUE
PEG_D2R_N7_SPNMAKE_BASE=TRUE
PEG_D2R_N3_SPNMAKE_BASE=TRUE
PEG_D2R_N2_SPNMAKE_BASE=TRUE
PEG_D2R_N
PEG_D2R_N
LVDS_B_CLK_N_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUE
PEG_D2R_P12_SPN
PEG_D2R_P
MAKE_BASE=TRUE
PEG_R2D_C_P4_SPN
PEG_D2R_N
PEG_R2D_C_N
PEG_D2R_P
PEG_D2R_N
=GND_BATT_CHGND
=GND_CHASSIS_AUDIO_JACK
PEG_D2R_N9_SPNMAKE_BASE=TRUE
PEG_D2R_P9_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUE
PEG_D2R_P11_SPN
MAKE_BASE=TRUE
PEG_D2R_P15_SPN
MAKE_BASE=TRUE
PEG_R2D_C_N5_SPN
MAKE_BASE=TRUE
PEG_R2D_C_N7_SPN
MAKE_BASE=TRUE
PEG_R2D_C_N13_SPN
PEG_R2D_C_N14_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUE
PEG_R2D_C_N15_SPNPEG_R2D_C_N
PEG_R2D_C_P
PEG_R2D_C_N
PEG_R2D_C_N
PEG_R2D_C_N
PEG_R2D_C_P
PEG_R2D_C_P
PEG_R2D_C_P
PEG_D2R_N
LVDS_B_DATA_P
LVDS_B_DATA_N
LVDS_B_DATA_N
LVDS_B_CLK_P
PEG_D2R_N12_SPNMAKE_BASE=TRUE
PEG_D2R_N14_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUE
PEG_D2R_N15_SPN
PEG_D2R_P0_SPNMAKE_BASE=TRUE
PEG_D2R_P3_SPNMAKE_BASE=TRUE
PEG_D2R_P13_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUE
PEG_R2D_C_N6_SPN
PEG_R2D_C_N10_SPNMAKE_BASE=TRUE
PEG_R2D_C_N12_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUE
PEG_R2D_C_P5_SPN
MAKE_BASE=TRUE
PEG_R2D_C_P8_SPN
MAKE_BASE=TRUE
PEG_R2D_C_P11_SPN
MAKE_BASE=TRUE
PEG_R2D_C_P12_SPN
MAKE_BASE=TRUE
PEG_R2D_C_P13_SPN
PEG_R2D_C_P
PEG_R2D_C_P
LVDS_B_CLK_N
LVDS_B_DATA_P
LVDS_B_DATA_P
LVDS_B_DATA_N
CPU_THERMAL_SCREW_RIGHT
NB_RIGHT_DOWN_SCREW
CPU_THERMAL_SCREW_DOWN
PEG_D2R_P
PEG_D2R_P
PEG_D2R_P
PEG_D2R_P
=GND_DCIN_CHGND
=GND_CHASSIS_LVDS
=GND_CHASSIS_RJ45
=SB_GPIO22
=USB2_AIRPORT_N
=USB2_AIRPORT_P
=USB2_BT_N
=USB2_BT_P
=USB2_IR_N
=USB2_IR_P
=USB2_CAMERA_N
=USB2_CAMERA_P
=USB2_EXTB_N
=EXTBUSB_OC_L
=USB2_GEYSER_N
=USB2_EXTB_P
=USB2_GEYSER_P
=EXTAUSB_OC_L
=USB2_EXTA_N
=USB2_EXTA_P
SMC_CPU_INIT_3_FWH_INIT_LMAKE_BASE=TRUE
DIMM_OVERTEMP_LMAKE_BASE=TRUE
PM_EXTTS_L
TP_SB_GPIO22SB_GPIO22
MAKE_BASE=TRUE
USB_H_NMAKE_BASE=TRUE
USB2_AIRPORT_N
USB_H_PUSB2_AIRPORT_P
MAKE_BASE=TRUE
USB_G_N
MAKE_BASE=TRUE
USB_BT_N
USB_G_PUSB_BT_P
MAKE_BASE=TRUE
USB_F_NUSB_IR_N
MAKE_BASE=TRUE
USB_F_PUSB_IR_P
MAKE_BASE=TRUE
USB_E_N
MAKE_BASE=TRUE
TP_USBN_E
USB_E_PMAKE_BASE=TRUE
TP_USBP_E
USB_D_NUSB2_CAMERA_NMAKE_BASE=TRUE
USB_D_PUSB2_CAMERA_P
MAKE_BASE=TRUE
USB_C_NMAKE_BASE=TRUE
USB2_EXTB_N
USB_C_OC_LEXTBUSB_OC_LMAKE_BASE=TRUE
USB_B_N
MAKE_BASE=TRUE
USB2_GEYSER_N
USB_C_PMAKE_BASE=TRUE
USB2_EXTB_P
USB_B_P
MAKE_BASE=TRUE
USB2_GEYSER_P
USB_A_NMAKE_BASE=TRUE
USB2_EXTA_N
USB_A_OC_LEXTAUSB_OC_LMAKE_BASE=TRUE
USB_A_PUSB2_EXTA_PMAKE_BASE=TRUE
FW_B_TPBIAS_SPNMAKE_BASE=TRU
FW_B_TPBIAS
FW_B_TPA_P_SPNMAKE_BASE=TRU
FW_B_TPA_P
FW_B_TPA_N_SPNMAKE_BASE=TRU
FW_B_TPA_N
FW_B_TPB_P_SPNMAKE_BASE=TRU
FW_B_TPB_P
FW_C_TPBIAS_SPNMAKE_BASE=TRU
FW_C_TPBIAS
FW_B_TPB_N_SPNMAKE_BASE=TRU
FW_B_TPB_N
MAKE_BASE=TRU
FW_C_TPA_P_SPNFW_C_TPA_P
FW_C_TPA_N_SPNMAKE_BASE=TRU
FW_C_TPA_N
FW_C_TPB_P_SPNMAKE_BASE=TRU
FW_C_TPB_P
NO_TEST=TRUE
NC_FWPWR_PWRON
MAKE_BASE=TRUE
=FWPWR_PWRON
FW_C_TPB_N_SPNMAKE_BASE=TRU
FW_C_TPB_N
TP_NB_CFG4MAKE_BASE=TRUE
NB_CFG
TP_NB_CFG3MAKE_BASE=TRUE
NB_CFG
MAKE_BASE=TRUE
TP_NB_CFG8NB_CFG
TP_NB_CFG6MAKE_BASE=TRUE
NB_CFG
TP_NB_CFG10MAKE_BASE=TRUE
NB_CFG
TP_NB_CFG12MAKE_BASE=TRUE
NB_CFG
TP_NB_CFG11MAKE_BASE=TRUE
NB_CFG
NB_CFG
TP_NB_CFG13MAKE_BASE=TRUE
NB_CFG
TP_NB_CFG15MAKE_BASE=TRUE
NB_CFG
TP_NB_CFG17MAKE_BASE=TRUE
NB_CFG
MAKE_BASE=TRUE
SATA_A_D2R_N_SPNSATA_A_D2R_N
SATA_A_R2D_C_N_SPNMAKE_BASE=TRUE
SATA_A_R2D_C_N
SATA_A_D2R_P_SPNMAKE_BASE=TRUE
SATA_A_D2R_P
MAKE_BASE=TRUE
SATA_A_R2D_C_P_SPNSATA_A_R2D_C_P
MAKE_BASE=TRUE
PCIE_C_D2R_N_SPNPCIE_C_D2R_N
PCIE_C_D2R_P_SPNMAKE_BASE=TRUE
PCIE_C_D2R_P
MAKE_BASE=TRUE
PCIE_C_R2D_C_N_SPNPCIE_C_R2D_C_N
PCIE_C_R2D_C_P_SPNMAKE_BASE=TRUE
PCIE_C_R2D_C_P
MAKE_BASE=TRUE
PCIE_D_D2R_P_SPNPCIE_D_D2R_P MAKE_BASE=TRUE
PCIE_D_D2R_N_SPNPCIE_D_D2R_N
PCIE_E_D2R_N_SPNMAKE_BASE=TRUE
PCIE_E_D2R_N
PCIE_D_R2D_C_N_SPNMAKE_BASE=TRUE
PCIE_D_R2D_C_N
PCIE_D_R2D_C_P_SPNMAKE_BASE=TRUE
PCIE_D_R2D_C_P
MAKE_BASE=TRUE
PCIE_E_D2R_P_SPNPCIE_E_D2R_P
MAKE_BASE=TRUE
PCIE_E_R2D_C_N_SPNPCIE_E_R2D_C_N
PCIE_F_D2R_P_SPNMAKE_BASE=TRUE
PCIE_F_D2R_P
PCIE_F_D2R_N_SPNMAKE_BASE=TRUE
PCIE_F_D2R_N MAKE_BASE=TRUE
PCIE_E_R2D_C_P_SPNPCIE_E_R2D_C_P
MAKE_BASE=TRUE
PCIE_F_R2D_C_N_SPNPCIE_F_R2D_C_N
MAKE_BASE=TRUE
PCIE_F_R2D_C_P_SPNPCIE_F_R2D_C_P
CK410_SRC1_N
CK410_SRC3_P_SPNMAKE_BASE=TRUE
CK410_SRC3_N_SPNMAKE_BASE=TRUE
CK410_SRC3_N
CK410_SRC1_P_SPNMAKE_BASE=TRUE
CK410_SRC1_P
MAKE_BASE=TRUE
CK410_SRC7_P_SPNCK410_SRC7_P
CK410_SRC7_N_SPNMAKE_BASE=TRUE
CK410_SRC7_N
MAKE_BASE=TRUE
CK410_SRC_CLKREQ1_L_SPNCK410_SRC_CLKREQ1_L
MAKE_BASE=TRUE
CK410_SRC_CLKREQ3_L_SPNCK410_SRC_CLKREQ3_L
SUS_CLK_SB
MEM_A_A
MEM_A_A14_SPNMAKE_BASE=TRUE
MEM_A_A
MEM_B_A
MEM_B_A14_SPNMAKE_BASE=TRUE
MEM_B_A
ENET_CTRL12
MAKE_BASE=TRUEVOLTAGE=0VGND_CHASSIS_IO1
=GND_CHASSIS_TMDS_DOWN
=GND_CHASSIS_FW_DOWN
=GND_CHASSIS_USB
VOLTAGE=0VMAKE_BASE=TRUE
GND_CHASSIS_CENTER
GND_CHASSIS_IO
MAKE_BASE=TRUEVOLTAGE=0V
MAKE_BASE=TRUEVOLTAGE=0V
GND_CHASSIS_RIGHT
PEG_D2R_P
=GND_CHASSIS_TMDS_UPPER
CK410_SRC3_P
MAKE_BASE=TRUE
PEG_R2D_C_N4_SPN
VOLTAGE=0VMAKE_BASE=TRUE
GND_CHASSIS_DCIN
MAKE_BASE=TRUE
GND_CHASSIS_SATA
VOLTAGE=0V
42C4
47C5
42C2
29A5
67B2
21C4
45B8
22
22
42A4
69C3
5C7
36C8
39A1
13A3
13B3
13B3
13C3
28A5
6C7
28D5
67C2
13D3
13D3
13D3
57A6
29D4
13A3
5A7
5A7
5A7
5A7
5A7
13C3
13C3
13B3
13C3
13B3
13B3
13B3
13B3
13C3
13C3
13C3
13C3
13C3
13B3
13C3
13C3
13C3
13C3
13A3
13D3
5A7
13B3
13A3
13D3
13D3
13D3
5A7
13C3
13C3
13B3
13C3
13D3
65A6
56B8
13B3
13B3
13B3
13B3
13B3
13B3
13B3
13B3
13D3
13C5
13C5
13C5
13C5
13B3
13B3
13C5
13C5
13C5
13C5
13C3
13C3
13C3
13C3
65C8
67A2
37A4
69A6
43B4
43B4
44C6
44C6
41C6
41C6
67A4
67B4
42B5
42C8
40C7
42B5
40C7
42C8
42C5
42C5
5C2
14B7
22C2
22C2
22C2
22C2
22C2
22C2
22C25C1
22C25C1
22C2
22C2
22C2
22C4
22C2
22C2
22C2
22C2
22C4
22C2
538B3
538B3
538B3
538B3
538B3
538B3
538B3
538B3
538B3
39C6
538B3
14C6
14C6
14C6
14C6
14C6
14C6
14C6
14C6
14C6
14C6
14C6
21B6
21B6
21B6
21B6
22D4
22D4
22D4
22D4
22D4
22D4
22C4
22D4
22D4
22C4
22C4
22C4
22C4
22C4
22C4
22C4
32B4
5C7
5C732B4
5C732B4
5C732B4
5C732B4
5B732B4
5B732B4
23C3
28C4
28C4
29C4
29C4
36C8
69A3
39A1
42A2
6D7
13C3
69A4
32B4
35C8
-
8/9/2019 Apple Macbook M42B
7/83
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
IN
IN
IN
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
A7*
RSVD14
RSVD15
BCLK1
BCLK0
RSVD20
RSVD17RSVD18
RSVD19
RSVD16
RSVD13
RSVD12
THERMTRIP*
THERMDC
THERMDA
PROCHOT*
DBR*
TRST*
TMS
TDO
TDI
TCK
PREQ*
PRDY*
BPM3*
BPM1*
BPM2*
BPM0*
HITM*
HIT*
TRDY*
RS2*
RS1*
RS0*
RESET*
LOCK*
INIT*
IERR*
BR0*
DBSY*
DRDY*
DEFER*
BPRI*
BNR*
ADS*
RSVD11
RSVD6
RSVD7
RSVD8
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD9
RSVD10
SMI*
LINT0
LINT1
STPCLK*
IGNNE*
FERR*
A20M*
ADSTB1*
A30*
A31*
A27*
A28*
A29*
A26*
A25*
A24*
A22*
A23*
A21*
A20*
A19*
A18*
A17*
REQ4*
REQ3*
REQ1*
REQ0*
REQ2*
ADSTB0*
A14*
A15*
A16*
A13*
A12*
A11*
A10*
A9*
A8*
A6*
A5*
A4*
A3*
(1 OF 4)
THERM
HCLK
RESERVED
ADDR
GROUP1
ADDR
GROUP0
CONTROL
XDP/ITP
SIGNAL
S
PSI*
SLP*
PWRGOOD
DPRSTP*
DPSLP*
DPWR*
COMP2
COMP3
COMP1
COMP0
DSTBP3*
DSTBN3*
DINV3*
D63*
D62*
D61*
D60*
D59*
D58*D57*
D56*
D55*
D54*
D52*
D53*
D51*
D50*
D49*
D48*
DINV2*
DSTBN2*
D47*
DSTBP2*
D45*
D46*
D44*
D43*
D42*
D41*
D40*
D39*
D38*
D37*
D36*
D35*
D34*
D33*
D32*
BSEL2
DSTBN1*
BSEL0
BSEL1
TEST2
TEST1
DINV1*
DSTBP1*
D31*
D30*
D29*
D26*
D27*
D28*
D24*
D25*
D23*
D21*
D22*
D20*
D19*
D18*
D16*
D17*
DINV0*
DSTBP0*
DSTBN0*
D15*
D14*
D13*
D12*
D11*
D10*
D9*
D8*
D7*
D6*
D5*
D4*
D3*
D2*
D1*
D0*
GTLREF
NC
(2 OF 4)
MISC
DATA
GRP0
DATA
GRP2
DATA
GRP1
DATA
GRP3
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
CPU IS HOT
AND CPU VR TO INFORM
WITHOUT T-ING (NO
CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9
WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD--ECM*50
SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM
TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE)
PLACE GND VIA W/IN 1000 MILS
FSB_IERR_L WITH A GND
PLACE TESTPOINT ON
LAYOUT NOTE: 0.5" MAX LENGTH
ICH7-M AND GMCH
TRACE LENGTH SHORTER THAN 0.5
TRACE LENGTH SHORTER THAN 0.5
COMP0,2 CONNECT WITH ZO=27.4O
LAYOUT NOTE:
COMP1,3 CONNECT WITH ZO=55OHM
CPU_PROCHOT_L TO SMC
SHOULD CONNECT TO
PM_THRMTRIP#
STUB)
SPARE[7-0],HFPLL:
ROUTE TO TP VIA AND
0.1" AWAY
2
1R07021%54.9
MF-LF402
1/16W
2
1R070468
1/16W5%
402MF-LF
2
1R07051K
MF-LF402
1%1/16W
2
1R07062.0K
MF-LF402
1%1/16W
21
R0719
1%402
54.9
21
R071827.4
21
R0717
1% 402
54.9
21
R071627.4
402
21
R0730NOSTUFF
402
0
2
1R0707
1/16W5%
402MF-LF
1K
NOSTUFF
2
1R071251
1/16W5%
402MF-LF
2
1R0703
402MF-LF1/16W1%54.9
21
R0720
1%402
54.9
21
R072154.9
4021%
21
R0722
1%402
54.9
AB6
G2
AB5
C7
A25
A24
AB3
AA6
AC5
D5
A3
B2
V3
T2
N5
M4
AA3
AB2
C24
AA4
C23
D22AF1
C1
D3
F6
D2
T22
B25
C3
AA1
G3
F4
F3
B1
L5
J3
K2
H2
K3
D21
AC1
AC2
H4
B4
C6
B3
C4
D20
E4
G6
A5
F21
H5
E1
C20
F1
G5
AC4
AD1
AD3
AD4
E2
A21
A22
V4
L2
H1
J1
N2
M1
K5
M3
L4
Y1
W2
J4
Y4
W5
W3
T3
T5
R4
U2
Y5
U4
A6
W6
R3
U5
Y2
R1
P1
P4
L1
P2
P5
N3
U0700
OMIT
CPU
YONAH
BGA
D25
C26
D7
D6
AE6
A2
AD26
AE24
Y25
N25
G22
AD23
W24
M24
H23
D24
B5
E5
AC20
V23
M26
J26
G24
K24
E23
AF26
AF22
AF25
AE25
E25
AD21
AE21AD24
AF23
AE22
AD20
AC25
AB21
AA21
AB22
G25
AC23
AC22
AA24
AC26
Y22
Y26
AA26
Y23
W22
AB25
F23
U22
U25
U23
W25
V26
V24
AB24
AA23
N24
T25
H22
L26
R24
T24
P23P22
P25
M23
L23
L22
L25
E26
R23
P26
K25
N22
H25
K22
F26
H26
J23
J24
F24
E22
V1
U1
U26
R26
C21
B23
B22
U0700
OMIT
BGA
YONAHCPU
CPU 1 OF 2-FSYNC_MASTER=MASTER
7
051-7374
SYN
FSB_RS_L
FSB_RS_L
XDP_BPM_L
FSB_HITM_L
FSB_HIT_L
FSB_RS_L
FSB_TRDY_L =PP1V05_S0_CPU
XDP_BPM_L
FSB_DBSY_L
=PP1V05_S0_CPU
=PP1V05_S0_CPU
=PP1V05_S0_CPU
XDP_TMS
XDP_TDI
XDP_TCK
FSB_A_LFSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_LFSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_ADSTB_L
FSB_REQ_L
FSB_REQ_L
FSB_REQ_L
FSB_REQ_LFSB_REQ_L
FSB_A_L
FSB_A_LFSB_A_LFSB_A_L
FSB_A_L
FSB_A_LFSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_ADSTB_L
CPU_A20M_L
CPU_FERR_L
CPU_IGNNE_L
CPU_STPCLK_L
CPU_NMI
CPU_INTR
CPU_SMI_L
TP_CPU_APM1_LTP_CPU_APM0_L
TP_CPU_A36_L
TP_CPU_A35_L
TP_CPU_A34_L
TP_CPU_A33_L
TP_CPU_A32_L
TP_CPU_A39_L
TP_CPU_A38_L
TP_CPU_A37_L
TP_CPU_HFPLL
FSB_DEFER_L
FSB_DRDY_L
FSB_BREQ0_L
FSB_IERR_L
CPU_INIT_L
FSB_LOCK_L
FSB_CPURST_L
XDP_BPM_L
XDP_BPM_L
XDP_BPM_L
XDP_BPM_L
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
XDP_DBRESET_L
CPU_PROCHOT_L
CPU_THERMD_P
CPU_THERMD_N
PM_THRMTRIP_L
TP_CPU_EXTBREF
TP_CPU_SPARE0
TP_CPU_SPARE3
TP_CPU_SPARE6
TP_CPU_SPARE5TP_CPU_SPARE4
TP_CPU_SPARE7
FSB_CLK_CPU_PFSB_CLK_CPU_N
TP_CPU_SPARE2
TP_CPU_SPARE1
FSB_A_L
CPU_GTLREF
FSB_D_LFSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_DSTBN_LFSB_DSTBP_L
FSB_DINV_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_DSTBP_L
FSB_DINV_L
CPU_TEST1
CPU_TEST2
CPU_BSEL
CPU_BSEL
FSB_DSTBN_L
CPU_BSEL
FSB_D_LFSB_D_L
FSB_D_L
FSB_D_LFSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_DSTBP_L
FSB_D_L
FSB_DSTBN_L
FSB_DINV_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_LFSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_DINV_L
FSB_DSTBN_L
FSB_DSTBP_L
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
FSB_DPWR_L
CPU_DPSLP_L
CPU_DPRSTP_L
CPU_PWRGD
FSB_SLPCPU_L
CPU_PSI_L
FSB_ADS_LFSB_BNR_L
FSB_BPRI_L
64D6
64D6
11C5
64D6
64D6
11C5
11B3
11C5
11C5
11B3
9C8
11B3
11B3
9C8
8C7
9C8
9C8
8C7
7D5
8C7
8C7
7D5
11B3
11B3
58C8
46B3
7B6
7D5
7D5
7B6
11B2
11B3
11B2
12C4
11B2
11B3
11B2
26C6
46C2
21C2
33D3
33D3
58C7
12A4
12A4
11B2
12B4
12B4
12A4
12A4 7B5
11B2
12B4
7B5
7B6
7B5
7C6
7C6
7C6
12D4
12D4
12D4
12D4
12D4
12D4
12D4
12D4
12D4
12D4
12C4
12D4
12D4
12C4
12A4
12B4
12B4
12A4
12A4
12C4
12C4
12C4
12C4
12C4
12C4
12C4
12C4
12C4
12C4
12C4
12C4
12C4
12C4
12C4
12C4
21C4
21C2
21C4
21C4
21C4
21C4
21C4
12B4
12B4
12C4
21C4
12B4
11B5
11B2
11B2
11B3
11B2
7A8
7B8
11B5
7B8
11B3
11B4
46B5
10B6
10B6
14B6
33C2
33C2
12D4
12D6
12D6
12D6
12D6
12D6
12D6
12D6
12D6
12D6
12D6
12D6
12D6
12D6
12C6
12C6
12C6
12B4
12B4
12B4
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12B4
12B4
33B6
33C6
12B4
33B6
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B4
12B6
12B4
12B4
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B4
12B4
12B4
12B4
21C4
21C4
21C4
12A4
58C7
12C4
12C4
12C4
-
8/9/2019 Apple Macbook M42B
8/83
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
VSS_82
VSS_83
VSS_84
VSS_85
VSS_87
VSS_86
VSS_88
VSS_89
VSS_90
VSS_92
VSS_91
VSS_93
VSS_94
VSS_95
VSS_97
VSS_96
VSS_100
VSS_98
VSS_99
VSS_102
VSS_101
VSS_105
VSS_103
VSS_104
VSS_106
VSS_107
VSS_110
VSS_109
VSS_108
VSS_111
VSS_112
VSS_115
VSS_114
VSS_113
VSS_116
VSS_117
VSS_118
VSS_120
VSS_119
VSS_123
VSS_121
VSS_122
VSS_124
VSS_125
VSS_128
VSS_126
VSS_127
VSS_129
VSS_130
VSS_133
VSS_131
VSS_132
VSS_134
VSS_135
VSS_138
VSS_136VSS_137
VSS_139
VSS_140
VSS_141
VSS_143
VSS_142
VSS_146
VSS_144
VSS_145
VSS_147
VSS_148
VSS_151
VSS_150
VSS_149
VSS_152
VSS_153
VSS_156
VSS_155
VSS_154
VSS_157
VSS_158
VSS_159
VSS_161
VSS_160
VSS_162
VSS_1
VSS_2
VSS_3
VSS_5
VSS_4
VSS_6
VSS_7
VSS_8
VSS_10
VSS_9
VSS_11
VSS_12
VSS_15
VSS_13
VSS_14
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_23
VSS_22
VSS_21
VSS_24VSS_25
VSS_28
VSS_27
VSS_26
VSS_29
VSS_30
VSS_33
VSS_32
VSS_31
VSS_34
VSS_35
VSS_38
VSS_37
VSS_36
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_46
VSS_44
VSS_45
VSS_47
VSS_48
VSS_51
VSS_49
VSS_50
VSS_52
VSS_53
VSS_56
VSS_54
VSS_55
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_63
VSS_62
VSS_64
VSS_65
VSS_66
VSS_69
VSS_68
VSS_67
VSS_70
VSS_71
VSS_74
VSS_73
VSS_72
VSS_75
VSS_76
VSS_79
VSS_78
VSS_77
VSS_80
VSS_81
(4 OF 4)
VCC_67
VCC_64
VCC_66
VCC_65
VCC_63
VCC_62
VCC_61
VCC_59
VCC_60
VCC_58
VCC_57
VCC_56
VCC_54
VCC_55
VCC_53
VCC_51
VCC_52
VCC_49
VCC_50
VCC_48
VCC_47
VCC_46
VCC_44
VCC_45
VCC_43
VCC_41
VCC_42
VCC_40
VCC_39
VCC_38
VCC_36
VCC_37
VCC_33
VCC_35
VCC_34
VCC_31
VCC_32
VCC_29
VCC_30
VCC_28
VCC_26
VCC_27
VCC_23
VCC_25
VCC_24
VCC_22
VCC_21
VCC_20
VCC_18
VCC_19
VCC_17
VCC_16
VCC_15
VCC_13
VCC_14
VCC_12
VCC_10
VCC_11
VCC_8
VCC_9
VCC_7
VCC_6
VCC_5
VCC_3
VCC_4
VCC_2
VCC_1 VCC_68
VCC_69
VCC_71
VCC_70
VCC_72
VCC_74
VCC_76
VCC_75
VCC_78
VCC_77
VCC_79
VCC_81
VCC_80
VCC_84
VCC_82
VCC_83
VCC_86
VCC_85
VCC_87
VCC_89
VCC_88
VCC_90
VCC_91
VCC_92
VCC_94
VCC_93
VCC_95
VCC_96
VCC_97
VCC_99
VCC_98
VCC_100
VCCP_1
VCCP_2
VCCP_3
VCCP_4
VCCP_5
VCCP_6
VCCP_7
VCCP_9
VCCP_8
VCCP_11
VCCP_10
VCCP_12
VCCP_13
VCCP_14
VCCP_16
VCCP_15
VCCA
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VSSSENSE
VCCSENSE
VCC_73(3 OF 4)
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
VCCA=1.5 ONLY
LAYOUT NOTE: CONNECT R0803
PULL-DOWN
IF NO USE, NEED PULL-UP OR
VID FOR CPU POWER SUPPLY
TRANSMISSION LINE
RESISTORS TERMINATE THE 55 OHM
LAYOUT NOTE:
(CPU CORE POWER)
(CPU IO POWER 1.05V)
STUB.
LAYOUT NOTE:
VCCSENSE AND VSSSENSE LINES
SHOULD BE OF EQUAL LENGTH
LOCATION WHERE THE TWO 54.9 OHM
BETWEEN VCCSENSE AND VSSSENSE AT THE
TO CONNECT A DIFFERENCTIAL PROBE
PROVIDE A TEST POINT (WITH NO STUB)
LAYOUT NOTE:
TO TP_VSSSENSE WITH NO
(CPU INTERNAL PLL POWER 1.5V)
ZO=27.4 OHM DIFFERNTIAL TRACE ROUTING.
CPU_VCCSENSE_P/CPU_VCCSENSE_N USE
9C3
9C3
9C3
9C3
9C3
9D3
2
1R0803
1/16W1%
402MF-LF
100
9D3
58A4 58A5
58A4 58A5
2
1R0802100
MF-LF402
1%1/16W
V22
V5
V2
U24
U21
U6
U3
T26
T23
T4B6
T1
R25
R22
R5
R2
P24
P21
P6
P3
N26
A26
N23
N4
N1
M25
M22
M5
M2
L24
L21
L6
A23
L3
K26
K23
K4
K1
J25
J22
J5
J2
H24
A19
H21
H6
H3
G26
G23
G1
G4
F25
F22
F2
A16
F19
F16
F13
F11
F8
F5
E24
E21
E19
E16
A14
E14
E11
E8
E6
E3
D26
D23
D19
D16
D13
A11
D11
D8
D4
D1
C25C22
C2
C19
C16
C14
A8
C11
C8
C5
AF24
AF21
AF19
B24
AF16
AF13
AF11
AF8
AF6
AF3
AE26
AE23
AE19
AE16
B21
AE14
AE11
AE8
AE4
AE1
AD25
AD22
AD19
AD16
AD13
B19
AD11
AD8
AD5
AD2
AC24
AC21
AC19
AC16
AC14
AC11
B16
AC8
AC6
AC3
AB26
AB23
AB19
AB16
AB13
AB11
AB8
B13
AB4
AB1
AA25
AA22
AA19
AA16
AA14
AA11
AA8
AA5
B11
AA2
Y24
Y21
Y6Y3
W26
W23
W4
W1
V25
B8
A4 U0700
OMIT
BGA
YONAHCPU
AE7
AE2
AF2
AE3
AF4
AE5
AF5
AD6
AF7
N21
M21
K21
J21
M6
K6
J6
G21
W21
V21
T6
T21
R6
R21
N6
V6
B26
AF18
AF17
AF15
AF14
AF12
AF10
AF9
AE20
AE18
AE17
A20
AE15
AE13
AE12
AE10
AE9
AD18
AD17
AD15
AD14
AD12
A18
AD10
AD9
AD7
AC18
AC17
AC15
AC13
AC12
AC9
AC7
A17
AB7
AB20
AB18
AB17
AB15
AB14
AB12
AB10
AC10
AB9
A15
AA20
AA18
AA17
AA15
AA13
AA12
AA10
AA9
AA7
F20
A13
F18
F17
F15
F14
F12
F10
F9
F7
E20
E18
A12
E17
E15
E13
E12
E10
E9
E7
D18
D17
D15
A10
D14
D12
D10
D9
C18
C17
C15
C13
C12
C10
A9
C9
B20
B18
B17
B15
B14
B12
B10
B9
AF20
B7
A7U0700
OMIT
BGA
YONAHCPU
CPU 2 OF 2-PWRSYNC_MASTER=MASTER
051-7374
8
SYN
=PPVCORE_S0_CPU
=PP1V05_S0_CPU
=PP1V5_S0_CPU
CPU_VID
CPU_VID
CPU_VID
CPU_VID
CPU_VID
CPU_VID
CPU_VID
CPU_VCCSENSE_N
CPU_VCCSENSE_P
=PPVCORE_S0_CPU
64D611C5
64D6
11B3
64D6
48B3
9C8
48B3
48A5
7D5
48A5
9B8
7B6
64C6
9B8
8B5
7B5
9D8
8D7
-
8/9/2019 Apple Macbook M42B
9/83
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORP AR T N UM BE R B OM O PT IO N REF DES COMMENTS:
TABLE_ALT_HEAD
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
THIS 470UF FOR CPU,GMCH FSB BUS 1.05V
VCCA DECOUPLING
# VCCLFM: VCORE AT LOWEST FREQUENCY MODE
(CPU INTERNAL PLL POWER 1.5V)
PLACE NEAR THE NORTH BRIDGE
SV CPU
R0921~R0927 FOR CPU VOLTAGE MANUAL SETTING
DUAL CORE 1.0
# TWO PROCESSORS AT THE SAME FREQUENCY MAY HAVE DIFFERENT SETTIN
1.30
1.301.1625
TBD
# REFER TO YONAH PROCESSOR EMTS REV 1.0
WITH THE VID RANGE(VCORE VOLTAGE)!
1.1625
# ALL PROCESSOR DEFAULT VCORE FOR INITIAL POWER UP IS 1.2V
# VCCHFM: VCORE AT HIGHEST FREQUENCY MODE
VCCHFM
SV CPU
TYP
TBD
TBD
TBD
SINGLE CORE
ULV CPU
VCCHFM
UNIT: V
LV CPU
DUAL CORE
MAXMIN
VCCLFM
TBD
1.1625
VCCHFM
VCCLFM TBD
VCCHFM
VCCLFM
TBD
VCCLFM
ON BOTTOM SIDE
CPU CORE VID SETTINGS
ON BOTTOM SIDE
PLACE NEAR THE CPU
(10 PCS ON NORTH SIDE
10 PCS ON SOUTH SIDE)
(2 PCS ON NORTH SIDE
2 PCS ON SOUTH SIDE)
(CPU CORE POWER)VCC CORE DECOUPLING
IF WE USE LOW ESL CAP,THEN WE CAN USE 20 PCS 22UF CAP
(CPU IO POWER 1.05V)
VCCP CORE DECOUPLING
5% 1/16W 4020
MF-LFR0922 1 2
4020
MF-LF5%1/16WR0923 1 2
5% 4020MF-LF1/16WR0924 1 25% 402
0MF-LF1/16W
R0925 1 2
5%1/16W 402MF-LF0R0926 1 2
4020
5% MF-LF1/16WR0927 1 2
20%10UF6.3VX5R603
C09511
2402
10%0.01uF
CERM16V
C0950 1
2
3 2
1C0940
D2TTANT2.5V20%
CRITICAL
470UF
NOSTUFF
3 2
1 C0941
D2T
2.5V20%
CRITICAL
POLY
470UF-8MOHM
3 2
1C0942
D2T
CRITICAL
2.5V20%
POLY
470UF-8MOHM
3 2
1C0943
D2T
CRITICAL
20%2.5VPOLY
470UF-8MOHM
3 2
1 C0944
D2T
20%2.5V
CRITICAL
POLY
470UF-8MOHM
3 2
1 C0946
D2T
CRITICAL
2.5V20%
POLY
470UF-8MOHM
CRITICAL
CERM-X5R
1
2805
6.3V20%22UFC0911 C0910
CRITICAL
CERM-X5R
1
2805
6.3V20%22UF
C090822UF20%6.3V
8052
1
CERM-X5R
CRITICAL
22UF20%6.3V
8052
1
CERM-X5R
CRITICAL
C0901 C092822UF20%6.3V
8052
1
CERM-X5R
CRITICAL
C0900
CRITICAL
CERM-X5R
1
2805
6.3V20%22UF
C090922UF20%6.3V
8052
1
CERM-X5R
CRITICAL
C0907
CRITICAL
CERM-X5R
1
2805
6.3V20%22UF
C0929
CRITICAL
CERM-X5R
1
2805
6.3V20%22UF
CRITICAL
CERM-X5R
1
2805
6.3V20%22UFC0924
22UF20%6.3V
8052
1
CERM-X5R
CRITICAL
C0918
CRITICAL
CERM-X5R
1
2805
6.3V20%22UFC0913
22UF20%6.3V
8052
1
CERM-X5R
CRITICAL
C0912
CRITICAL
CERM-X5R
1
2805
6.3V20%22UFC0904
22UF20%6.3V
8052
1
CERM-X5R
CRITICAL
C0930
CRITICAL
CERM-X5R
1
2805
6.3V20%22UFC0902
22UF20%6.3V
8052
1
CERM-X5R
CRITICAL
C0931
CRITICAL
CERM-X5R
1
2805
6.3V20%22UFC0939
CRITICAL
CERM-X5R
1
2805
6.3V20%22UFC0920
C092322UF20%6.3V
8052
1
CERM-X5R
CRITICAL
20%0.1UFCERM10V
402
C09261
2 CERM10V20%
402
0.1UFC09341
2 CERM
0.1UF20%10V
402
C09351
2
1C09360.1UF
402
10V20%CERM2
10V
402
20%CERM
1
2
C09370.1UF
2
1C0938
402CERM10V20%0.1UF
5% 4021/16W MF-LF0R0921 1 2
138S0602 ALL?138S0606 USE TAIYO
?138S0603 138S0602 ALL USE SAMSUNG AND MURATA ONLY
051-7374
9
CPU DECAPS & V
=PP1V05_S0_CPU
=PP1V5_S0_CPU
CPU_VID
CPU_VID
CPU_VID
CPU_VID
CPU_VID
CPU_VID
CPU_VID
CPU_VID_R
CPU_VID_R
CPU_VID_RCPU_VID_R
CPU_VID_R
CPU_VID_R
CPU_VID_R
=PPVCORE_S0_CPU
64D6 11C5 11B3
64D6
8C7
48B3
7D5
48A5
7B6
64C6
58C7
58C7
58C7
58C7
58C7
58C7
58C7
8D7
7B5
8B7
8B7
8B7
8B7
8B7
8B7
8B7
8B7
58A4
58A4
58A4
58A4
58A4
58A4
58A4
8B5
-
8/9/2019 Apple Macbook M42B
10/83
D+
D-
ALERT*/
THM*
SCLK
SDATA
VDD
GND
THM2*
IO
IO
IN
OUT
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
LAYOUT NOTE:
PLACEHOLDER ADT7461A
(TO CPU INTERNAL THERMAL DIODE)
CPU_THERMD_N
LAYOUT NOTE:
CPU ZONE THERMAL SENSOR
ROUTE CPU_THERMD_P AND
10 MIL TRACE
LAYER.
10 MIL SPACING
F OR CP U_ TH ER MD _P AN D C PU _T HE RM D_ N O N S AM E
ADD GND GUARD TRACE
PLACE U1001 NEAR THE U1200
CRITICAL
MSOP
ADT7461
U1001
6
2
3
5
8
7
4
1
MF-LF
499
1/16W
402
1%
R1001
1 2
402
1
2 CERM50V
0.001uF10%
C1001
X5R
0.1UF
16V10%
402
1 C1002
2
499
1%
MF-LF402
1/16W
R1002
1 2
5%1/16W
402
10K
MF-LF
1R1005
2
10K
1/16W
402MF-LF
5%
1R1006
2
051-7374
10
SYNC_MASTER=ENET SYN
CPU MISC1-TEMP SEN
SMB_THRM_DATA
SMB_THRM_CLK
THRM_ALERT
THRM_ALERT_L
=PP3V3_S0_THRM_SNR
CPU_THERMD_N
CPU_THERMD_P
THRM_CPU_DX_N
THRM_CPU_DX_P
64A6 49D3
27B3
27C3
49B3
7C6
7C6
-
8/9/2019 Apple Macbook M42B
11/83
OUT
IN
OUT
IN
OUT
OUT
OUT
IN
IN
OUT
IO
IO
IO
IO
IO
IO
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
ITP TCK SIGNAL LAYOUT NOTE:
CONNECTORS FBO PIN.
(AND WITH RESET BUTTON)
NC
NC
516S0416
INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSE(DBA#)
(DEBUG PORT ACTIVE)
TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC(DBR#)
(DEBUG PORT RESET)
(TCK)
TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX
ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTORS TCK PIN TO CPUS
(FBO)
(FROM CK410M HOST 133/167MHZ)
CPU ITP700FLEX DEBUG SUPPORT
22.6
MF-LF
1%1/16W
402
ITP
R11001 2
R110222.6
21
MF-LF1/16W1%
402
ITP
54.9
1/16W1%
402MF-LF
R11031
2
C1100ITP
2
1
0.1UF10%16VX5R402
R1104
2
1
5%
MF-LF402
240
1/16W
54.9
1/16W
402
1%
MF-LF
R11011
2
680
402
5%1/16WMF-LF
R11061
2
ITP
J1102
3029
2827
2625
2423
2221
2019
1817
1615
1413
1211
109
87
65
43
21
F-ST-5047
CRITICAL
SM1
CPU ITP700FLEX SYNC
051-7374
11
SYNC_MASTER=MASTER
ITPRESET_L
XDP_TRST_L
ITP_TDOXDP_TDO
FSB_CPURST_L
=PP1V05_S0_CPU
=PP3V3_S5_SB_PM
XDP_BPM_L
XDP_BPM_L
XDP_TMS
XDP_TCKXDP_BPM_L
XDP_BPM_L
XDP_BPM_L
XDP_TCK
XDP_TDI
=PP1V05_S0_CPU
XDP_BPM_L
CPU_XDP_CLK_PCPU_XDP_CLK_N
XDP_DBRESET_L
64D6
64D6
11B3
11C5
9C8
9C8
8C7
8C7
7D5
64A3
11B2
7D5
12C4
7B6
26C5
7C6
7C6
7C6
7B6
33D3
33D3
26C6
7C6
7C6
7D6
7B5
23D1
7C6
7C6
7B8
7C6
7C6
7C6
7A8
7B8
7B5
7C6
33D2
33D2
7C6
-
8/9/2019 Apple Macbook M42B
12/83
IO
IO
IO
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
IO
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IN
IO
IN
IO
IO
HD4*
HD6*
HD16*
HTRDY*
HSLPCPU*
HRS1*
HRS0*
HHITM*
HLOCK*
HHIT*
HDSTBP2*
HDTSBP3*
HDSTBP1*
HDSTBP0*
HDSTBN3*
HDSTBN1*
HDSTBN2*
HDSTBN0*
HDINV2*
HDINV3*
HDINV1*
HDINV0*
HDVREF
HDRDY*
HDPWR*
HDEFER*
HDBSY*
HCPURST*
HBREQ0*
HBPRI*
HBNR*
HAVREF
HCLKIN*
HCLKIN
HYSWING
HYRCOMP
HYSCOMP
HXSWING
HXSCOMP
HXRCOMP
HA13*
HADS*
HADSTB0*
HD3*
HD2*
HD1*
HD0*
HD63*
HD62*
HD61*
HD60*
HD59*
HD58*
HD57*
HD56*
HD55*
HD54*
HD53*
HD52*
HD51*
HD50*
HD49*
HD48*
HD47*HD46*
HD45*
HD44*
HD43*
HD42*
HD41*
HD40*
HD39*
HD38*
HD37*
HD36*
HD35*
HD34*
HD33*
HD32*
HD31*
HD29*
HD28*
HD27*
HD26*
HD25*
HD24*
HD23*
HD22*
HD21*
HD20*
HD19*
HD18*
HD17*
HD15*
HD10*
HD11*
HD12*
HD13*
HD14*
HD5*
HD7*
HD8*
HD9*
HA30*
HA29*
HA28*
HA27*
HA26*
HA25*
HA24*
HA23*
HA31*
HA20*
HA19*
HA18*
HA16*
HA15*
HA14*
HA21*
HA22*
HA17*
HA9*
HA8*
HA7*
HA6*
HA5*
HA4*
HA3*
HA10*
HA11*
HA12*
HADSTB1*
HREQ0*
HREQ1*
HREQ2*
HREQ3*
HD30*
HREQ4*
HRS2*
(1 OF 10)
HOST
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
DSIZE
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PRO
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PA
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSTHE INFORMATION CONTAINED HEREIN IS THE P
12345678
12345678
A
B
C
D
APPLE COMPUTER INC.SCALE
NONE
2
1C1211
402X5R
16V10%
0.1uF
2
1R12112001%
1/16W
MF-LF402
2
1R12101001%1/16W
MF-LF402
2
1R1220
54.91%
1/16WMF-LF
402
2
1R1221
402MF-LF
1/16W
1%
24.9
2
1R12252211%
1/16WMF-LF
402
2
1R1226
1%
1/16W
MF-LF402
100
2
1 C12260.1uF
402X5R
16V10%
2
1 C1236
402X5R
16V10%
0.1uF
2
1R12352211%1/16W
MF-LF
4022
1R1230
54.91%
1/16W
MF-LF
402
2
1R1236
1%1/16WMF-LF
402
100
2
1R1231
402
MF-LF1/16W
1%
24.9
W1
U1
Y1
E4
E2
E1
E7
E3
D6
E6
B4
A8
F8
B8
G8
D8
B3
D4
D3
K13
AC5
AA5
T6
K3
AC4
Y5
T7
K4
H8
J9
AB10
U3
W8
J7
C3
A7
K1
K9
G2
AC8
AD4
AD10
AB5
G1
AC6
AD7
AC1
AD9
AD1
AC2
AB3
AC11
AB11
AC9
K2
AB4
AA1
Y8
AA10
AA6
AA2
AA7
AA4
W2
AB8
H3
Y10
W5
Y7
Y3
W3
W4
AA9
AB7
T5
W6
J6
T9
U5
W7
T4
T8
T1
W9
T11
U11
U9
H1
U7
T3
W11
T10
G4
K11
J3
H4
J8
K7
J1
F1
B7
AG1
AG2
C7
F6
C6
J13
C13
B9
E8
F9
G12
F11
G11
E11
C9
D14
C14
H9
A14
C12
B14
B12
F12
G13
E13
A13
A12
C11
A11
D12
F14
J15
H13
J14
D9
G14
J12
H11
U1200
BGA
LEMENU
NB
945GM
S YN C_ MA ST ER =N B S YN
NB CPU Interfac
12
051-7374
FSB_D_L
FSB_DSTBN_L
FSB_DSTBN_L
FSB_DSTBP_L
FSB_DSTBP_L
FSB_DSTBP_L
FSB_DINV_L
FSB_DSTBN_L
FSB_DINV_L
FSB_DINV_L
NB_FSB_VREF
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_TRDY_L
FSB_SLPCPU_L
FSB_RS_L
FSB_RS_L
FSB_HITM_L
FSB_LOCK_L
FSB_HIT_L
FSB_DSTBP_L
FSB_DSTBN_L
FSB_DINV_L
FSB_DRDY_L
FSB_DPWR_L
FSB_DEFER_L
FSB_DBSY_L
FSB_CPURST_L
FSB_BREQ0_L
FSB_BPRI_L
FSB_BNR_L
FSB_CLK_NB_N
FSB_CLK_NB_P
NB_FSB_YSWING
NB_FSB_YRCOMP
NB_FSB_YSCOMP
NB_FSB_XSWING
NB_FSB_XSCOMP
FSB_A_L
FSB_ADS_L
FSB_ADSTB_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_LFSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_ADSTB_L
FSB_REQ_L
FSB_REQ_L
FSB_REQ_L
FSB_REQ_L
FSB_D_L
FSB_REQ_L
FSB_RS_L
=PP1V05_S0_FSB_NB
=PP1V05_S0_FSB_NB
=PP1V05_S0_FSB_NB
NB_FSB_XRCOMP
64D6
64D6
64D6
33C8
33C8
33C8
33C7
33C7
33C7
33B8
33B8
33B8
19D7
19D7
19D7
33D3
33D3
12C2
12C2
12B7
7C4
7C3
7B3
7B4
7C3
7B3
7C4
7C4
7B4
7C3
7C4
7C4
7C4
7C4
7C4
7C4
7C4
7C4
7C4
7C4
7C4
7C4
7D6
7A3
7D6
7D6
7D6
7D6
7D6
7C4
7B4
7B3
7D6
7B3
7D6
7D6
7D6
7D6
7D6
33C2
33D2
7D8
7D6
7D8
7B3
7B3
7B3
7B3
7B3
7B3
7B3
7B3
7B3
7B3
7B3
7B3
7B3
7B3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7B4
7B4
7B4
7B4
7B4
7B4
7B4
7B4
7B4
7B4
7B4
7B4
7B4
7C4
7C4
7C4
7C4
7C4
7C8
7C8
7C8
7C8
7C8
7C8
7C8
7C8
7C8
7C8
7C8
7C8
7D8
7D8
7D8
7C8
7C8
7C8
7D8
7D8
7D8
7D8
7D8
7D8
7D8
7D8
7D8
7D8
7C8
7D8
7D8
7D8
7D8
7B4
7D8
7D6
12A7
12B7
12A7
-
8/9/2019 Apple Macbook M42B
13/83
CRT_BLUE*
CRT_BLUE
CRT_GREEN*
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_RED*
HSYNC
CRT_DDC_DATA
CRT_VSYNC
CRT_IREF
TV_IRTNC
TV_IRTNB
TV_IREF
TV_IRTNA
TV_DACB_OUT
TV_DACC_OUT
TV_DACA_OUT
LB_DATA2
LB_DATA1
LB_DATA0
LB_DATA2*
LB_DATA1*
LB_DATA0*
LA_DATA2
LA_DATA1
LA_DATA0
LA_DATA2*
LA_DATA1*
LA_DATA0*
LB_CLK
LB_CLK*
LA_CLK
LA_CLK*
L_VDDEN
L_VREFL
L_VREFH
L_VBG
L_IBG
L_DDC_CLK
L_DDC_DATA
EXP_A_COMPI
EXP_A_COMPO
EXP_A_RXN0
EXP_A_RXN1
EXP_A_RXN2
EXP_A_RXN3
EXP_A_RXN4
EXP_A_RXN5
EXP_A_RXN6
EXP_A_RXN7
EXP_A_RXN8
EXP_A_RXN9
EXP_A_RXN10
EXP_A_RXN11
EXP_A_RXN12
EXP_A_RXN13
EXP_A_RXN15
EXP_A_RXN14
EXP_A_RXP0
EXP_A_RXP1
EXP_A_RXP2
EXP_A_RXP4
EXP_A_RXP3
EXP_A_RXP5
EXP_A_RXP6
EXP_A_RXP7
EXP_A_RXP10
EXP_A_RXP9
EXP_A_RXP8
EXP_A_RXP11
EXP_A_RXP12
EXP_A_RXP14
EXP_A_RXP13
EXP_A_RXP15
EXP_A_TXN1
EXP_A_TXN0
EXP_A_TXN3
EXP_A_TXN2
EXP_A_TXN6
EXP_A_TXN5
EXP_A_TXN4
EXP_A_TXN7
EXP_A_TXN8
EXP_A_TXN9
EXP_A_TXN10EXP_A_TXN11
EXP_A_TXN12
EXP_A_TXN14
EXP_A_TXN13
EXP_A_TXN15
EXP_A_TXP0
EXP_A_TXP2
EXP_A_TXP1
EXP_A_TXP3
EXP_A_TXP4
EXP_A_TXP5
EXP_A_TXP7
EXP_A_TXP6
EXP_A_TXP8
EXP_A_TXP9
EXP_A_TXP10
EXP_A_TXP12
EXP_A_TXP11
EXP_A_TXP13
EXP_A_TXP14
EXP_A_TXP15
L_CLKCTLB
L_BKLTEN
L_CLKCTLA
L_BKLTCTL
(3 OF 10)
LVDS
TV
V
GA
PCI-EXPRESS
GRAPHICS
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
IO
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN