Appendix ISynthesizable and Non-SynthesizableVerilog Constructs

The list of synthesizable and non-synthesizable Verilog constructs is tabu-lated in the followingTable

VerilogConstructs

Used for Synthesizableconstruct

Non-SynthesizableConstruct

module The code inside the module andthe endmodule consists of thedeclarations and functionality ofthe design

Yes No

Instantiation If the module is synthesizablethen the instantiation is alsosynthesizable

Yes No

initial Used in the test benches No Yes

always Procedural block with the regtype assignment on LHS side.The block is sensitive to theevents

Yes No

assign Continuous assignment withwire data type for modeling thecombinational logic

Yes No

primitives UDP’s are non-synthesizablewhereas other Verilog primitivesare synthesizable

Yes No

force andrelease

These are used in test benchesand non-synthesizable

No Yes

delays Used in the test benches andsynthesis tool ignores the delays

No Yes

fork and join Used during simulation No Yes

ports Used to indicate the direction,input, output and inout. Theinput is used at the top module

Yes No

parameter Used to make the design moregeneric

Yes No

time Not supported for the synthesis No Yes(continued)

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(continued)

real Not supported for synthesis No Yes

functions andtask

Both are synthesizable. Providedthat the task does not have thetiming constructs

Yes No

loop The for loop is synthesizable andused for the multiple iterations.

Yes No

VerilogOperators

Used for arithmetic, bitwise,unary, logical, relational etc aresynthesizable

Yes No

Blocking andnon-blockingassignments

Used to describe thecombinational and sequentialdesign functionality respectively

Yes No

if-else, case,casex, casez

These are used to describe thedesign functionality dependingon the priority and parallelhardware requirements

Yes No

Compilerdirectives(‘ifdef,‘undef,‘define)

Used during synthesis Yes No

Bits and partselect

It is synthesizable and used forthe bit or part select

Yes No

400 Appendix I: Synthesizable and Non-Synthesizable Verilog Constructs

Appendix IIXilinx Spartan Devices

• Xilinx Spartan 3 Devices

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• Spartan 3 Family Architecture

• Xilinx Spartan 3 Package information for Part no XC3S400-4PQ208C

402 Appendix II: Xilinx Spartan Devices

For more information please use the following link http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf.

• Xilinx FPGA Spartan 3E Devices

• Xilinx Spartan 3E Architecture

Appendix II: Xilinx Spartan Devices 403

• Xilinx Spartan 3E package information

For more information please use the following link http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf.

404 Appendix II: Xilinx Spartan Devices

Appendix IIIDesign For Testability

The Design For Testability (DFT) and its necessity is discussed in summarized

In the practical ASIC design, the DFT is used to find out various kinds of faults inthe design. For FPGA designs this step is excluded. The necessity of DFT is forearly detection of the faults in the design using scan chain insertions. The func-tional abstraction of defects is called as fault and the abstraction of the fault is thesystem level error. Physical testing is carried out after manufacturing of chip tounderstand the fabrication-related issues or faults.

The defects in the design can be physical or electrical. Physical defects are due tosilicon or defective oxide. Electrical defects are short, open, transistor defects andchanges in the threshold voltage.

Few of the faults in the design are following

1. Stuck at faults: Stuck at one or Stuck at zero2. Memory faults or pattern-sensitive faults3. Bridging faults4. Cross point faults5. Delay faults

Testing process is the process of test pattern generation, test pattern applicationand output evaluation.

Generally, the test flow includes the following:

1. Identify the target faults2. Test generation3. Fault Simulation4. Testability5. DFT

• Design For Testability (DFT)The DFT is required to reduce the defect level in the design. Consider thefollowing design; in this design it is not possible to give the test input so designis not testable. The DFT uses the concept of controllability and observabilty.The key steps are

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1. RTL design2. Simulation3. Synthesis4. Insert scan chain5. Layout

If every data input of the register need to be forced to the known value during thetest, then the design is controllable.

Observability indicates the ability to observe the node at primary output. Thede-sign needs to be controllable and observable.

As shown in the following design, the design input of comb_logic1 is control-lable and the output from comb_logic3 is observable. But comb_logic1 andcomb_logic2 are not observable. So for detection of faults, it is essential to makecomb_logic1, comb_logic2, and comb_logic3 controllable as well as observable.

• The basic DFT techniques are: Ad-HOC DFT and Structured DFT. The struc-tured DFT includes the scan-based DFT which is again classified as MUX -based DFT and level–sensitive, element-based DFT. An-other structured DFTtechnique is MBIST and LBIST. JTAG is used for boundary scan.

Basic MUX-based technique is described below.

• MUX-based scan cellThe MUX-based scan cell is shown below and it has additional inputs asTest_data, Scan_en. The MUX is inserted at the input of the D flip-flop andduring testing Scan_en=1 the D input is Test_data. During normal operation, theScan_en=0 and Data_in can pass through the combinational logic to the D input.Thus, the following cell works both in the test and normal modes. The clk canbe scan_clk during the test mode.

comb_l

ogic1

comb_l

ogic2

comb_l

ogic3

clk

406 Appendix III: Design For Testability

• MUX-based scan chain:Normally used method is insertion of scan by using MUX logic. MUX-basedscan cell shown in the above figure is used to replace the sequential elementsfrom the design. Depending on the requirements the design team decideswhether to use partial scan method or full scan method.In the partial scan method few of the sequential elements are replaced by theMUX based scan cell. In the full scan method, all the sequential elements arere-placed by the MUX-based scan cell.Due to scan insertion, the area and timing of the design has significant impact.Scan insertion increases the area of the design and due to added MUX-basedlogic even it affects on the timing of the design. The following example showsthe scan chain using MUX-based scan cells.Most of the time, the partial scan is recommended if area and timing is theconstraint but this reduces overall fault coverage. If full scan is used then itincreases area and has significant impact on timing but this improves overallfault coverage.

D

comb_l

ogic2

clk

Scan _en

Data_in

Test_data

Q_out

D

comb_

logic1

clk

Scan _en

Data_in

Test_dataD

comb_

logic2comb_

logic3

Appendix III: Design For Testability 407

• Scan Design rulesFollowing are few of the scan design rules need to be considered:

1. Generated clocks in the design: There should not be generated clocks in thedesign as they are not controllable

2. Combinational feedback loop: There should not be any combinational loop inthe design as it creates issues in the timing analysis and hence it is essential tobreak the combinational loop

3. Gated clocks: Gated clocks need to be avoided as they are not controllable4. Asynchronous Control signals: There should not be any internally generated

asynchronous control signals5. Do not mix the positive and negative edge triggered flip-flops6. Avoid use of latches in the design7. If shift registers are used then do not replace them by using scan enabled flip-

flops but only ensure the enable control8. Do not use the clock input as data9. Bypass the memories during DFT

408 Appendix III: Design For Testability

Index

Symbols#0delay assignments, 80$display, 229$finish, 229$monitor, 80, 229$strobe, 801 line to 2 or (1:2) decoder, 6114 nanometer (nm), 261100 K gates, 3002 line to 4 or (2:4) decoder, 662:1 MUX, 5420 nanometer (nm), 2614 line to 16 or (4:16) decoder, 674:1 MUX, 5740 nanometer (nm), 26150% duty cycle, 266

AAcknowledgment or notification, 329Active, 80Active event queue, 80Active power, 364Adders, 38Addition, 179AHB, 386Algorithms, 386Altera, 242ALU, 392ALU architecture, 172always, 11, 222, 369Analyze, 264AND, 173AND logic, 32Antifuse, 234Arbiters, 172, 391Architecture, 3, 237, 259, 289Area, 369Area minimization, 30Area optimization, 246

Area utilization, 98Arithmetic logic unit (ALU), 172Arithmetic operations, 11, 39ASIC chip designs, 2ASIC design, 197ASIC library, 389ASIC porting, 383Asynchronous, 322Asynchronous counters, 138Asynchronous design, 249Asynchronous path, 295Asynchronous pulse generator, 169, 248Asynchronous reset, 109, 156, 157Asynchronous reset ‘reset_n’, 200Attribute, 308

BBarrel shifter, 192Basic cell or base cell, 257Baud rate control block., 396Begin-end, 150Behavior, 9Behavioral, 7Bidirectional, 10Bidirectional IO, 395Bidirectional shift register, 130Binary counter, 114Binary encoding, 244Binary-to-Gray, 49, 342Bit-stream, 238Bitwise operations, 16Blocking (=), 10, 80, 217Blocking assignments, 146, 243Block level, 389Bluetooth, 382Boolean algebra, 2Bottom-up, 3, 300BRAM, 235Buses, 397

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CCadence RTL Compiler, 259Capture flip-flop, 282case, 57, 369case construct, 92case-endcase, 57, 93Case equality, 97Case inequality, 97Cell library, 263Characterize, 312Check_design, 265, 318Check_timing, 318Checker, 187, 228Chip level, 389CLB, 232, 235clk initalization, 229clk generator, 229Clock balancing, 370Clock buffer, 370Clock definitions, 286Clock domain, 161Clock domain crossing (CDC), 250, 322Clocked-based logic, 104Clocked logic, 192Clock gating, 251, 363, 364, 366, 390Clock gating structure, 161Clocking boundary, 341Clock path group, 285Clock skew, 242, 387Clock to ‘q’ delay, 280Clock tree, 363, 364, 387Clock tree synthesis, 260CMOS, 360CMOS logic, 2Code converters, 49Coding guidelines, 79Combinational logic, 10, 27Combinational loop, 245Combinational path, 286Combinational path group, 284Combinational shifters, 192Comparators, 46Compile, 267Compile-characterize, 302Compiler, 314Computational blocks, 386Concentration and replication, 18Concurrent, 10Concurrent execution, 161Conditional assignments, 55Configuration data, 239Consolidated control signal, 334Constant folding, 272Constants, 10

Constraints, 260Continuous assignment, 82, 92Control and timing unit, 392Control path, 165, 392Control signals, 325Coverage goals, 388CPLD, 230CPU, 256create_clock, 265, 287Cumulative delay, 160Current simulation time, 80Current_state, 198Cycle accurate, 187Cycles, 390Cycle stealing, 154

DData arrival time, 278, 281Database, 263Data buffers, 396Data integrity, 322Data path, 280, 364, 392Data path synchronizer, 340Data propagation, 390Data rate, 258Data required time, 281DCM, 235, 242DDR, 241DDR II, 382DDR III, 382Dead zone code, 273Debug, 303Decoder, 58Decrement, 179default, 93, 217, 369Defining hierarchy, 390Delay operators, 185Deserializer, 391Design compiler, 263Design constraints, 5, 300Design environment, 302Design implementation, 252Design object, 264, 301Design partitioning, 274, 306, 346, 386Design performance, 79, 162, 163, 386Design rule constraints, 300Design rule library, 261Design rules, 302Design specification, 257DesignWare, 262Device utilization summary, 239DFT, 259, 389DFT friendly RTL, 390Differential IOs, 387

410 Index

Different phases, 324DLL, 239, 242DMA controller, 391DRC violations, 315Drivers, 228Drive strength, 302DSP, 192, 382DSP algorithms, 389DSP blocks, 235DSP filtering, 389DUV, 226Dynamic, 278Dynamic power, 251, 360Dynamic voltage and frequency scaling, 365

EEDA, 238, 387EDA tool, 4, 300, 364Edge triggered, 107EDIF, 238Efficient synthesis, 215Effort level, 252Efforts levels, 267Eight-bit parameterized counter, 130Elaborate, 264Empty and full flag, 341Enable, 67, 104Encoder, 68Encoding, 174, 291Encounter from Cadence., 261End point, 284Equality operators, 11Ethernet, 382Even parity, 187Events, 390Exclusive OR, 34

FFabrication techniques, 258False path, 295, 327Fast debugging, 215Faults, 263Feasibility study, 385FFT, 386FIFO, 386, 396FIFO memory buffer, 338, 345FIR, 386Flash memory, 233Flip-flop, 103, 107Floor planning, 260Four as to one MUX, 56FPD, 230

FPGA, 230, 382FPGA designs, 228FPGA prototyping, 382Frequency synthesis, 242FSM, 197, 244, 314FSM coding, 200FSM control, 340Full adder, 39, 98, 181Full-case, 174Full-case statement, 91Full-custom, 256Full subtractors, 41Functional and timing proven., 386Functional design specifications, 3Functionality, 257Functional model, 3Functional simulation, 238Functions, 172, 184

GGated clock, 161Gate level netlist, 3, 260, 278, 303GDSII, 360GDSII file, 261General purpose, 387Geometric, 260Glitches, 111, 157, 199Glitches or hazards, 343Glitch free, 216, 244Global clock buffers, 247Glue logic, 274, 306Gray counter, 123, 210, 342Gray encoding, 341Gray-to-binary, 50, 341group, 307group_path, 310

HHalf adder, 38Half subtractor, 41Handshaking, 338Handshaking mechanism, 391Handshaking signals, 329Hazards, 111, 390HDL, 370Hierarchical design, 302Hierarchies, 290High impedance, 11High speed, 257High-speed interfaces, 241High speed IOs, 387Hold, 160

Index 411

Hold time, 260Hold time violations, 278, 346Hold violation, 280, 315

II2C, 382IC Compiler from Synopsys, 261IEEE 1364-2005, 80IEEE 1801, 371if-else, 57, 369if-else construct, 92IIR, 386Inactive, 80Increment, 179Incremental compilation, 309initial, 11, 220, 222Input and output delay, 267Input argument, 185Input register path group, 284Input string, 185Input to reg path, 284Instantiation, 8Instruction register and decoder logic, 392Inter-assignment delays, 222Interconnect, 232Interface, 258Internally generated clock, 157Intra-assignment delays, 224IO blocks (IOB), 235, 238IO high performance standards, 235IO interfaces, 387IPs, 258, 382Isolation, 371Isolation cell, 365, 371, 390Isolation control, 371

JJohnson counter, 127

LLatch-based designs, 163Latches, 103, 217Late arrival, 332Late arrival signal, 291Latency, 249, 297, 327, 340, 360Launch flip-flop, 282Layout, 257Leakage current, 360Legal converging, 329Level shifter, 371, 374, 390Level synchronizers, 325Level-to-pulse, 329Level triggered, 154Libraries, 5, 302

Library models, 366Link library, 263Linting tool, 250Load, 302Logical equality, 97Logical flattening, 309Logical inequality, 97Logical operators, 11Logic capacity, 232Logic cells, 238Logic density, 232Logic duplication, 246, 291Logic gates, 27Longer runtime, 305Loss of correlation, 347LUTs, 239

MMacrocells, 238Macros, 258Map, 262Map_effort, 309Master mode, 233Master-slave flip-flops, 368Maximum area, 257Maximum operating frequency, 280Mealy, 198Mealy level to pulse, 200Memory storage element, 107Metastability, 248, 324Micro-architecture, 3, 172, 259, 289, 300, 388Microprocessors, 256Minimization techniques, 27Minimum bus width, 369The min, max corner analysis, 287Min or max, 267Missing ‘else’ clause, 95Modeling levels, 390Monitor, 80, 228Moore, Gordon, 2, 198Multibit adders and subtractors, 44Multi-bit signals, 338Multi-Cycle Path (MCP), 295, 331, 343Multi phase clock, 165Multiple “always” block, 150Multiple Vth, 364Multiple clock domain, 163Multiple clocks, 274Multiple control signals, 332Multiple Driver Assignment, 102Multiple driver error, 102Multiple drivers, 245Multiple power domain, 382Multiplex decoding, 390

412 Index

Multiplex encoding, 292Multiplexers, 53, 98, 367Multiplier, 235, 386MUX, 53MUX Synchronizer, 331

NNAND logic, 33NBA, 80NBA queue, 88, 150Negative clock skew, 283Negative edge, 104Negative level sensitive D latch, 106Nested if-else, 244Netlist, 238Nets, 308Next_state, 198Next state logic, 199Nonblocking, 10, 217, 243Non-blocking (<=), 80Non-blocking assignments, 80, 150, 189Nonconverging, 328Nonsynthesizable, 219Non-synthesizable constructs, 11NOR logic, 28

OOdd parity, 187One-hot encoding, 212, 244Opcode, 172Operand, 181Operand Isolations, 364Optimization, 5, 184Optimization constraints, 300Optimize, 262Optimized netlist, 263OR, 173OR logic, 28Oscillatory behavior, 85Output register path, 284Output to reg path, 284

PPackaging, 258Packets, 386Parallel and multiplexing logic, 173Parallel execution, 386Parallel input parallel output logic., 132Parallelism, 391Parallel logic, 57, 157Parameterized binary and gray counter, 123Parameters, 10Parasitic (RC), 260Parasitic capacitance, 361

Parentheses, 273Parity checker, 189Parity detectors, 48Parity generator, 187Partitioning of design, 172Path groups, 315Performance, 232Performance constraints, 257Performance improvement, 177Phase Shifting, 242Photo lithography, 261Physical verification, 261Pipelined design, 391Pipelined processor, 389Pipelined register, 163Pipelined stage, 313Pipelining, 154, 161, 177, 290, 390PIPO registers, 132PLA, 230Place and route, 252, 389PLL, 242, 382Port interfaces, 306Ports, 308Positive clock skew, 282Positive edge, 104Positive level sensitive latch, 104Positive slack, 290The post-synthesis verification, 246Power, 184, 238, 259Power compiler, 366Power domains, 371Power gating, 365Power management, 363Power planning, 260Power rails, 371Power Shut-Off (PSO), 365Power state tables, 371Power switches, 371Pre layout STA, 260Prime Time, 278Priorities, 308Priority encoders, 69The priority encoding, 292Priority logic, 57, 92, 157Procedural assignments, 83Procedural Block “always”, 146Process, 302Processing algorithms, 389Process node, 360Processor, 392Program and stack pointer, 392Program Language Interface (PLI), 11Programmable interconnects, 238Programmable logic devices (PLD), 230, 382

Index 413

Programmable Switch, 232PROM, 230Propagation delay, 280, 313Protocol, 172, 386, 391Prototype, 230, 382Pulse stretcher, 329Pulse synchronizers, 330

RRace around conditions, 87Race condition, 85RAM, 140Random test, 388Read, 264Readability, 79, 198Read empty logic, 352Read synchronization, 352Reduction operators, 19References, 308Reg, 83Register balancing, 290, 291, 313, 390Register duplications, 290Register retiming, 390Registered inputs and outputs, 174Register logic, 199Register output logic, 160Register-to-register path, 174Register-to-register timing path, 313Reg to reg path, 284Relational operator, 18Report_constraints, 315Report_constraints_all, 315Report_timing, 310Reset deassertion, 109, 346Reset recovery, 157Reset synchronizer, 346Reset tree, 156Resource sharing, 47, 98, 174, 246Retention, 371Retention cell, 373, 390Retention control, 373Reusability, 79Ring counter, 125, 226Ripple counter, 140Robust verification, 390ROM, 140Round robin, 393RTL, 3, 259, 306RTL code, 9RTL design, 284, 358RTL synthesis, 3

SSATA, 382Scan insertions, 263SDC, 287, 295, 327Sdc commands, 300SDF, 246Search_path, 263Semiconductor, 383Semi-custom, 256Sensitivity, 10Sensitivity list, 81, 245Sequence detector, 212Sequential, 10Sequential logic, 10, 103Serial data, 396Serializer, 391Set_clock_latency, 287Set_clock_uncertainty, 287Set_dont_touch, 305Set_input_delay, 287, 288Set_output_delay, 287Set and reset, 370Set-don’t_touch_network, 369Setup, 160Setup time, 278Setup violation, 310Shift operators, 20Shift register, 127, 130, 146, 240Short-circuit power, 362Sign operands, 13Silicon wafer, 257Simulation, 220Simulation and synthesis mismatch., 90Simulator, 5, 390Single port RAM, 241Skew, 266, 334Slack, 279, 310Slave mode, 233Slowest path in the design, 154SOC, 172, 359, 382SOC components, 391SOC design, 228SOC validation, 387SPI, 382SPLD, 230SRAM, 233SRAM memory cell, 233SRPG, 366STA, 238, 278Standard cell, 256, 360State encoding, 215

414 Index

State machines, 274State register, 199State transition, 200State transition table, 210Static, 278, 397Stratified event queue, 80Stratified event queuing, 146Stray capacitance, 361Structural, 7Structural design, 7Structured ASIC, 232Stuck at fault coverage, 389Subroutine, 184Subtraction, 179Subtractors, 41Switches, 371Switching activity, 362Switching power, 161Switch level design, 3Symbol_library, 263Synchronization, 156, 391Synchronization failure, 324Synchronized asynchronous resets, 250Synchronizers, 274Synchronous, 114, 198Synchronous design, 114, 248, 286Synchronous reset, 111, 157Synopsys, 367Synopsys_dc.setup, 263Synopsys DC, 300Synopsys Design Compiler, 259Synopsys PT, 278, 300Synthesis, 199, 238, 259, 387Synthesizable, 7Synthesizable constructs, 392Synthesizable RTL, 383Synthesized logic, 200Synthesizer, 259System C, 388System Verilog, 388

TTarget library, 262Task, 172, 184Technology constraints, 258Technology library, 262Temperature, 302Testability, 260Testbench, 5, 219, 390Test plan, 388Test vectors, 388Three-bit down counter, 118Three-bit up counter, 114Three-bit up-down counter, 120

Three-procedural block FSM, 200Throughput, 360, 386Time borrowing, 154Time budgeting, 154Time control, 185Time to market, 257Timing analysis, 198, 277, 303Timing analyzer, 286Timing closure, 278Timing goals, 286Timing issues, 247The timing optimization, 308Timing or area, 238Timing parameters, 287Timing paths, 260Timing performance, 238Timing proven IPs, 383Timing sequence, 327Timing summary, 315Timing violation, 160, 174, 260, 280Toggle flip-flop, 200Toggle synchronizer, 330Too tight constraints, 278Top-down, 3, 300Top level, 274Transactions, 390Transistor, 2Transitions in the state diagram, 217Translate, 262Transport and inertial, 390Tri-state, 37, 102, 240Two-level synchronizer, 250Two stage level synchronizer, 109, 157

UUART, 382, 396Unified Power Format (UPF), 370, 389Unintended latches, 88Unintentional combinational loops, 85Universal logic, 35, 55Unknown, 11USB, 382User constraints, 315

VVendor-specific power formats, 370Verification, 259, 343Verification methodologies, 5Verification planning, 388Verilog, 2Verilog IEEE standards, 6Verilog RTL, 3Video decoders, 386Virtex, 239

Index 415

Virtual clock, 266Voltage, 302Voltage level, 374

WWeight factor, 310Wire, 82Working directory, 263Write command, 267

Write full logic, 352Write synchronization, 352

XXilinx, 242XILINX Spartan, 239XNOR, 34XOR, 34, 173XOR logic, 55

416 Index