“systems integration” –integrating power electronics · 2018. 10. 15. · this tutorial...

PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS

©2018 DOUGLAS C [email protected]

Prof. Douglas C Hopkins, Director, Laboratory for

Packaging Research in Electronic Energy Systems (PREES)

Caveat –Integrating across all voltage ranges,

Functional Integration through packaging

“Systems Integration” – Integrating Power Electronics

PACKAGING RESEARCH IN ELECTRONIC ENERGY SYSTEMS©2018 DOUGLAS C HOPKINS

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AbstractToday power electronics has strong growth across a board range of power levels.

This particularly applies to increases that improve lives versus enhancing entertainment.

However, increasing density and reducing cost still are the primary goals for all designs, and brings focus on Functional Integration at the Systems Level.

This tutorial highlights areas of change ranging from heterogeneous integration at the SiP level to high voltage systems for automotive and smart grid. Much of the change is in materials, particularly highly thermally conductive organics, such as dielectric laminates with up to 10W/mK that can now be the basis for our new designs.


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The challenge in thermal management will broaden to address essentially point-source heat generation due to higher power capabilities

with shrinking dies size compared to Si die.

Significant problem with much smaller WBG devices



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Shrinking power die challengeHuang in 2004 developed three pertinent figures of merit [1].

[1] “New Unipolar Switching Power Device Figures of Merit,” Alex Q. Huang, IEEE Electron Device Letters, Vol. 25, No. 5, May 2004

The HMFOM tracks the losses. !"#$" = &' (The HCAFOM tracks the chip area. !)*#$" = &'+ , (The HTFOM tracks the thermal conductance. !-#$" = ./0 / &' ,

Ec is critical electric breakdown field, µ is electron mobility, ε is dielectric constant, σth is thermal conductivity

0

1

2

3

4

5Breakdown Field (MV/cm)

Bandgap Energy

(eV)

Thermal Conductivity

(W/cm-K)

SaturationDrift Velocity(x10⁷ cm/s)

Electron Mobility

(x10³ cm²/Vs)

Si SiC GaN

High Voltage

CapabilityLow On-State

Resistance

Hig

h

Switc

hing

Freq

uenc

y

High

Temperature

Capability

SiC

GaN

Si

Values for the FOMs are calculated following Huang’s development.


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Shrinking Die Size (so to speak)

“New Unipolar Switching Power Device Figures of Merit,” Alex Q. Huang, IEEE Electron Device Letters, Vol. 25, No. 5, May 2004.

• The FOM for GaN & SiC show substantial performance as die size can shrink, OR the power rating increases.

• Small die are preferred for higher and higher frequencies.

Ec: critical fieldµ: mobilityε: dielectric constantσ: thermal conductivity


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High Frequency Potential (e.g. Unipolar - MOSFET)

Comparison is based on hard switched converters with fixed f, I, and V. ZVS for high voltage provides other advantages for SiC.

Since current does not scale, the speed ~ I/C, is significantly increased in WBG devices. Speed measured as dI/dt or dV/dt

Graph excerpt w/ permission, A. Q. Huang, “Wide Bandgap Power Devices: Die Size Shrinking and Its Impact on Power Delivery Architecture,” PSMA Webinar,Feb25,2016

The reduction in size supports

high frequency operation, but

creates a greater challenge in

heat dissipation and Integration.



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Small Die for High Voltage – 9kV design in airSmall Die experiences breakdown at

1,800 V. (Experimental design at NCSU)Packaging materials have always needed to passivate the chip for

voltages greater than ~150V.

A great emphasis to develop “Medium Voltage” power electronic systems is underway for large and small systems, e.g. portable x-ray equipment to large autonomous trucks.

BACKSIDE• Drain• Collector• Anode

3 mm to 1 cm

3 mm to 1 cm

Guard RingsTOPSIDE

• Gate• Base

50 µm to 350 µm

• Source• Emitter• Cathode

THE THOUGHT METRIC


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E.G. SiC MOSFET Dimensions – 1.2kV/36A 3.1X3.4mmCPM2-1200-S080B, 2016

Parameter Typ Value Unit

Die Dimensions (L x W) 3.10 × 3.36 mm

Exposed Source Pad Metal Dimensions (LxW) Each 1.04 × 1.43 mm

Gate Pad Dimensions (L x W) 0.80 × 0.50 mm

Die Thickness 180 ± 40 µm

Top Side Source metal (Al) 4 µm

Top Side Gate metal (Al) 4 µm

Bottom Drain metal (Ni/Ag) 0.8/0.6 µm

VDS = 1200 VID @ 25 ̊C = 36 ARDS(on) = 80 mΩ


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Fundamental Power Electronics Problem –Inductive switching


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Fundamental Power Electronic Switching

V1 D

S

SW-Top

SW-BottomV1 D

S

D

S

DrainSource

Gnd

Gnd


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Identifying the metrics in HIP


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System Integration in Deisgn


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50kW Inverter and Power Module Assembly

1 - low-profile inductors2 - cold plate3 - module interface4 - four SiC modules5 - local ceramic capacitors6 - connectors and busbar

1

2

3

4

5

67

8

9

1011

12

7 - gate driver board8 - film capacitors9 - film capacitors10 - structural component11 - structural component12 - inlet and outlet

!

50kW SiC Traction Drive



Xin Zhao1, Yifan Jiang1, Bo Gao1, Kenji Nishiguchi2, Yoshi Fukawa3, Douglas C. Hopkins1

1North Carolina State University, 2Risho Kogyo Co., LTD, 3TOYOTech LLC

“Novel Polymer Substrate-Based 1.2kV / 40A Double-Sided Intelligent Power Module”


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Introduction – (EV, HEV, etc.)Improvement at System-level• Device Ruggedness• High temperature capability• Electrical performance

• Dynamic characteristics• Overload capability• Operation Frequency

• Power Density

From Xin Zhao Presentation: “Novel Polymer Substrate-Based 1.2kV / 40A Double-Sided Intelligent Power Module,” Xin Zhao, Yifan Jiang, Bo Gao, Kenji Nishiguchi, Yoshi Fukawa, Douglas C. Hopkins, IEEE 67th ECTC, Orlando, FL May 30 – Jun 02, 2018

Electrical Design• Magnetics with lower profile• Layout for less noise and higher density• Topology selections for specific applicationsPhysical Design• Mechanical robustness• Low parasitics for high frequency operationThermal Design• Cooling technique for lower profile• Lower thermal impedanceMaterials Developments• Dielectric performance• Temperature capability• Attachment ReliabilitySystem-level overall cost

Requirement on Packaging

for Implementation

PACKAG ING RESEARCH IN ELECTRON IC ENERGYSYSTEM S


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State-of-art development of WBG power module

SiC Module w/ double-sided cooling by ORNL [1]• 2.6 nH extracted parastics inductance• Bus up to 600V with >40A capability• Kelvin connections implemented• Gate bonding wire required

[1] F. Yang, et al. Design of a Low Parasitic Inductance SiC Power Module with Double-sided Cooling. APEC 2017, Tampa, FL.[2] S. Hauser. Direct Pressed Die Technology: Increased Power Density and Reliability in Standard Power Module Packages. APEC 2017, Tampa, FL.

SKiN and Direct Pressed Die technology by Semikron[2]• >20% thermal resistance reduction• 10% reduction in parasitic inductance• >25% improvement in surge current• Improved thermal-cycling based reliability• 1700V/1800A• Challenge on the Press Unit design and implementation



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[3] M. Roming, et al. 3D packaging advancements drive performance, power and density in power device. White Paper, Junly 2011.[4] Y. Kaji, et al. Novel IGBT Modules with Epoxy Resin Encapsulation and Insulating Metal Baseplate. ISPSD 2016.[5] T. Takahashi, et al. A 1700V-IGBT module and IPM with new insulated metal baseplate (IMB) featuring enhanced isolation properties and thermal conductivity. PCIM Europe 2016.

PowerStack packaging technology by Texas Instruments[3]

• Lower Parasitics between high- and low-side switches• Improved Power Efficiency• Better Thermal performance• Applicable for lower voltage applications for now

• Insulated-Metal-Baseplate based IPM by Mitsubishi [4, 5]• CTE of insulating resin layer ~17ppm, close to Copper, with better

mechanical stress management• 35% thermal impedance reduction from development of resin • Less interconnection layers for lower profile, up to 55% size reduction

from traditional DBC based module• Better thermal cycling reliability with less cracks during cycling• Depends on the resin interface material heavily

State-of-art development of WBG power module



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Integration Objectives

1. Investigation of Epoxy-resin Thin Dielectric as Power Module Substrate2. Design of a High-density SiC Power Module for High-Frequency Applications3. (Development of Fabrication Process for Double-side Solderable SiC Devices)


ImplementationsUltra-low Parasitic PackagingDouble-side Cooling Function More Integrated Electrical Functionality


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Target Application: 1200V / 40A SiC MOSFET and Schottky Diode based Power Module

Investigation of Flexible Thin Dielectric as Substrates

Criterion for thin dielectric selection for power module substrate applicationsThermal conductivity need not be high, due to thin dielectric

Sufficient breakdown voltage for adequate margin for 1200V SiC MOSFETsLow leakage current to be comparable with SiC devices at the same conditions, such

as temperatureBeing able to operate at high temperature similar to SiC devices

High processing temperature to leave enough margin for the assembly-related

processes

Parameters Unit ValueThermal Conductivity W/mK > 3

Breakdown Voltage kV > 3Leakage Current µA ~ 10

Dielectric Constant 1 < 8Operation Temperature oC > 175Processing Temperature oC > 250



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Target Material: Recently developed Epoxy-resin based dielectric by Risho Kogyo Co., Ltd.

Properties of the Thin Dielectric (measured at 120 µm)

Better Stress Management• CTE closer to copper than traditional

ceramic (4.5 ppm/K ~ 7 ppm/K)• Flexible allowing for stress release

during assembly and service of the module


Parameter Unite ValueThermal Conductivity W/mK 8

Tg oC 270Modulus GPa 30

Bending Strength MPa 94CTE ppm/oC 9/22Dk / 6.3Df / 0.009

Water Absorption % 0.27Dielectric Strength kV 5.6 @ 120 µm

Parts Thickness/µm

Thermal ConductivityW/m·K

Unit Thermal ConductanceW/m2·oC

Epoxy-resin 80 8 1E5Al2O3 254 23 0.9E5AlN 254 170 0.67E6

Comparable thermal performance with alumina• Better unit area thermal conductance than alumina• 1/5 unit area thermal conductance of AlN• Lower cost for epoxy-resin substrate



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• Capable of bonding with Copper on both sides• Copper thickness up to > 0.6 µm• 80 µm dielectric thickness is available


Leakage current measured on 80 µm sample with Cu bonded on both sides• 20 µA leakage even at 250 ºC with 1200 V voltage applied• 1 nA leakage at room temperature with > 4kV voltage applied

1.00E-11

1.00E-10

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

0 500 1000 1500 2000 2500 3000 3500 4000

Leak

age

Curr

ent,

A

Reverse Voltage, V

Leakage Current

25C 50C75C 100C125C 150C175C 200C225C 250C



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Microstructure of the dielectric at 20,000 magnification• O is corresponding to alumina particles, distributed almost everywhere, N is the AlN

particles, with limited number, C is from the polymer, Cu is from the bonding interface• AlN and alumina particles are also identified by XRD analysis• High thermal conductivity is from the widely distributed alumina particles and few AlN

particles


Al O C

CuN



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Properties during reliability experiments (Thermal aging and thermal cycling)Thermal aging is conducted at 150 ºC

Thermal cycling is from -55ºC to 125 ºC

Peel strength (35µm copper on 120µm dielectric with 1mm Al) is not as high as DBC interface

(4N/mm for 0.3mm Cu on alumina)

Limited degradation during thermal aging up to 200 Hr in breakdown voltage and peel strength

The properties do not change much during thermal cycling up to 1000 cycles

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

0 500 1000 1500 2000

Peel

stre

ngth

, kN

/m

Bre

akdo

wn

volta

ge, k

V

Treating time, Hr

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

0 250 500 750 1000

Peel

stre

ngth

, kN

/m

Bre

akdo

wn

vplta

ge, k

V

Cycle Number




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SiC IPM Design

SiC MOSFET and diode

Moly Spacer

Main Bus TerminalsTerminals for Auxiliary Power Supply

FunctionalityGate Driver

Digital IsolatorLDO

Substrates on Double Side

• Volume: 35 mm × 15.5 mm × 3mm• Power Devices: CPM2-1200-0025B / CPW5-1200-Z050B• Rating: 800 V/ 40 A• Auxiliary terminals on single side of the module, allowing for

both side heat sink attachment, with terminals able to attached on PCB for interconnectionsFrom Xin Zhao Presentation: “Novel Polymer Substrate-Based 1.2kV / 40A Double-Sided Intelligent Power Module,” Xin Zhao, Yifan Jiang, Bo Gao, Kenji Nishiguchi, Yoshi Fukawa, Douglas C. Hopkins, IEEE 67th ECTC, Orlando, FL May 30 – Jun 02, 2018


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SiC IPM DesignCircuit Schematic Design

Schematic Design forSiC half bridge IPM• Boostrap Power Supply• Digital Isolator• LDO• Gate driver Circuits• -5V turn-off power supply• Single switch pair IPM is developed as initial investigation




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SiC Integrated Power Module (IPM) Design

Layout design for the SiC half bridge IPMInterconnections are applied to both top and bottom side of substratesInterconnection metal in the main power loop is a copmprise between thermal spreading and EMI nosie reductionOnly the layout (c) and (d) are discussion in the presentation for the single switch moduleThe layout design is not optimized and the long gate loop trace on the plane, results in excessive noise during switchingJumper wire minimizes gate loop length during the fabrication for demonstration of the design

25 mm ×× 15 mm


Circuit Layout Design


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Simulation of the SiC IPM Design

• Inductance in the entire loop is 0.6 nH.• Diode inductance is larger, since it parallels the MOSFET drain to source.• Applicable for lower losses and higher operation frequency.

Current distribution inthe power loop

Summary of extracted parasitics


Simulation for Parasitics ExtractionPower stage 3D model


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Simulated Transient Characteristics - SiC IPM DesignSimulations on Switching Transient Behaviors

Simulated turn-on and turn-off waveforms with no parasitics



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SiC IPM DesignSimulations on Switching Transient Behaviors

Simulated turn-on and turn-off waveforms with parasitics according to Q3D simulation results

• Current and voltage waveform takes longer time to settle with parasitics

• No significant difference is found between two groups of waveforms

• Id=40A, Vds=800V



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SiC IPM Fabrications & MeasurementsModule Assembly & Driver Circuits Test

• Flip-chip assembly for SiC MOSFET and Diode

• Underfill applied for 1200V isolation• Large terminals for testing

25 mm ×× 15 mm


• Gate pad is on same plane as gate driver, output signal verified for -5V turn-off and 20V turn-on of MOSFET


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SiC IPM Fabrications & Measurements

SiC MOSFET and diode within designed module for Static tests

The forward and reverse characteristics of SiC diode is similar with data shown on the datasheet[[6].Module Assembly & Diode Statics Test

0.00E+00

5.00E-06

1.00E-05

1.50E-05

2.00E-05

2.50E-05

0 200 400 600 800 1000 1200

Cur

rent

/ A

Voltage / V

Reverse Characteristics of SiC Diode in IPM

05

1015202530354045

0 0.5 1 1.5 2 2.5

Cur

rent

/ A

Voltage / V

Forward Characteristics of SiC diode in IPM

[6] CPW5-1200-Z050B DATASHEET



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SiC IPM Fabrications & MeasurementsModule Assembly & MOSFET Statics Test

0.00E+00

1.00E-09

2.00E-09

3.00E-09

4.00E-09

5.00E-09

6.00E-09

7.00E-09

0 500 1000 1500

Id /

A

Vds / V

Blocking Characteristic of SiC MOSFETVgs = 0 V

05

1015202530354045

0 2 4 6 8 10 12

Id /

A

Vds / V

Output Characteristics of SiC MOSFET in IPM

Vgs=0Vgs=5VVgs=10VVgs=15VVgs=20V

The forward and reverse characteristics of SiC MOSFET is similar with data shown on the datasheet[7].

The proposed module fabrication and assembly process, including the topside metallization process of SiC devices, can fully exhibits the initial performance of the SiC devices


[7] CPM2-1200-0025B DATASHEET


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Conclusions• Selection Criterion of Thin dielectric substrate material is set up based on design

requirements of 1200V WBG device based IPMs.• A 120µm recently developed flexible epoxy-resin based dielectric, by Risho Kogyo Co.,

Ltd., is investigated, and proved to be suitable for power module substrate in terms of electrical, thermal, mechanical properties, cost, and reliability.

• A high-density half-bridge SiC power module is designed with ultra-low parasitics, utilizing epoxy-resin based dielectric, for high-frequency and low-loss applications.

• Fabrication process of Double-side solderable SiC MOSFETs and diodes is developed, capable of deposition of metallization layer up to 2µm.

• A single-switch SiC power module with more functionality is fabricated, allowing for double-side cooling functions, verified by static measurements.

• The proposed substrate material, and designed WBG IPM with ultra-low parasitics, high functionality and double-side cooling is verified and show potential for high frequency and high power density applications.

[7] CPM2-1200-0025B DATASHEET



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Acknowledgement• PREES Lab for support on power module fabrication • Risho Kogyo Co., Ltd., for epoxy-resin thin material supply and customized

copper bonding and etching process• TOYOtech LLC for the materials information and business interactions• FREEDM Systems Center for support on electrical characterizations • SMiF center of Duke University, for cleanroom fabrication processes• MSE department of NC State University, for material thermal characterizations• Materials Research Institute of Penn State University, for dielectric properties

characterizations



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By Xin ZhaoUniv. of Texas, Austin

End paper ReviewFrom Xin Zhao Presentation: “Novel Polymer Substrate-Based 1.2kV / 40A Double-Sided Intelligent Power Module,” Xin Zhao, Yifan Jiang, Bo Gao, Kenji Nishiguchi, Yoshi Fukawa, Douglas C. Hopkins, IEEE 67th ECTC, Orlando, FL May 30 – Jun 02, 2018


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Dissertation work of Haotao Ke, September 2017“3-D Prismatic Packaging Methodologies for Wide Band Gap Power Electronics Modules”

3D Prismatic Packaging – True 3D


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State of Art WorksPlanar 2D power packaging technology

Flex circuit structurePOL package, SKiN package, etc.

Embedded structure AT&S GaNPX, PCB embedded, etc.

Sandwiched structure Planar Bond All package, etc.

SKiN module [5]Power Overlay package [4]

GaNPX package[7] PCB embedded module[6]

Planar Bond All[8] ABB Stacked DBC [1]


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State of Art Works3D power packaging technology

Device level Quilt dies, stacked / vertical dies

Module level 3D CSP, Power chip on chip, 3D power circuit .

Power chip on chip[11]

Stacked device[13] Vertical connected device[14]3D CSP module[12]

3D Power module[10]

Quilt packaging[9]


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3-D Prismatic PackageObjective

Investigation of power module topologies in >2D3-D Prismatic package should have:

Low parasitic inductanceGood thermal performanceHigh power densityCapability to handle thermal stress brought by high temperature operation, if properly designed


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The 3D Power Path ConceptElectrical Criteria for Integration


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The 3D Power Path ConceptLow inductance is desired for WBG module

Minimize voltage overshootReduce switching loss

1

2

3

4

LL

LL

L

é ùê úê ú=ê úê úë û

1

1 12

2 2

3 33

4 4

4

di diLdt dt

v L di diLv L dt dtv L di diL

dt dtv Ldi diLdt dt

é ù é ùê ú ê úê ú ê úé ù é ù ê ú ê úê ú ê ú ê ú ê úê ú ê ú= =ê ú ê úê ú ê ú ê ú ê úê ú ê ú ê ú ê úë û ë ûê ú ê úê ú ê úë û ë û

1 2 3 4 1 2 3 4( ) diV v v v v L L L Ldt

D = + + + = + + +

POSITIVE

NEGATIVE

OUTPUT

sdiV Ldt

D =


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The 3D Power Path ConceptOptions to lower inductance in 2D

Minimize each element (L1 ~ L4)Bring in mutual inductance (M14 & M23)

sdiV Ldt

D =

1 14

1 1 142 23

2 2 23

3 32 33 32

4 41 4

4 41

( )

( )

( )

( )

di diL Mdt dt

v L M di diL Mv L M dt dtv M L di diL M

dt dtv M Ldi diL Mdt dt

é ù é ù-ê ú ê úê ú ê ú-é ù é ù ê ú ê ú-ê ú ê ú- ê ú ê úê ú ê ú= =ê ú ê úê ú ê ú- ê ú ê ú-ê ú ê ú ê ú ê ú-ë û ë û ê ú ê úê ú ê ú-ë û ë û

1 2 3 4

1 14 2 23 3 32 4 41

1 2 3 4 14 23

( ) ( ) ( ) ( )

( ) 2( )

V v v v vdi di di diL M L M L M L Mdt dt dt dt

di diL L L L M Mdt dt

D = + + +

= - + - + - + -

= + + + - +

1 14

2 23

32 3

41 4

L ML M

LM L

M L

-é ùê ú-ê ú=ê ú-ê ú-ë û

ld

0 2[log 1 ]2

l lM ld d

µp

= - +


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The 3D Power Path Concept3D Power path to lower inductance

Fold output terminal to P/N terminal sideBring in more mutual inductance cancelation

sdiV Ldt

D =

1 14 12 13

1 12 13 1412 23 21 24

21 2 23 242

31 32 3 3433 32 34 31

41 42 43 44

( ) ( )

( ) ( )

( ) ( )

di di diL M M Mdt dt dt

L M M Mv di di diL M M MM L M Mv dt dt dtM M L Mv di di diL M M M

dt dtM M M Lvdidt

é ù - - -ê úê ú- -é ùé ù ê ú - - -ê úê ú - - ê úê úê ú = =ê úê úê ú - - ê ú - - -ê úê ú ê ú- -ë û ë û ê úê úë û 4 41 43 42( ) ( )

dtdi diL M M Mdt dt

é ùê úê úê úê úê úê úê úê úê ú- - -ë û

1 2 3 4

1 14 12 13 2 23 21 24

3 32 34 31 4 41 43 42

1 2 3 4 14 23 12 13 43 42

( ) ( ) ( ) ( )

( ) ( ) ( ) ( )

( ) 2( ) 2( ) 2( )

V v v v vdi di di diL M M M L M M Mdt dt dt dtdi di di diL M M M L M M Mdt dt dt dt

di di di diL L L L M M M M M Mdt dt dt dt

D = + + +

= - - - + - - - +

- - - + - - -

é ù é ù= + + + - + - - + -ê ú ê úë û ë û

ld

0 2[log 1 ]2

l lM ld d

µp

= - +

1 12 13 14

21 2 23 24

31 32 3 34

41 42 43 4

L M M MM L M M

LM M L MM M M L

- -é ùê ú- -ê ú=ê ú- -ê ú- -ë û

.

.1 4

32

M12 M13

M14

12 13M M>

1

2

3

4


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The 3D Power Path ConceptSimulation verification (Ansoft Q3D)

Cu trace cross section: 12mil (0.3mm) by 15 mmCurrent return point: 60 mmSpacing: 10mm lateral & 2mm vertical Extract inductance between Positive (P) and Negative (N) terminals at 1MHz

41.2 nH 28.3 nH

POWEREX CM150DX-24A

PACKAG ING RESEARCH IN ELECTRON IC ENERGYSYSTEM S


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HB Module Fabrication Half bridge schematic as 1st prismatic Module

4 Devices, 7 terminalsElectrical – 3D Power path Thermal – 5 sided cooling

Schematic 2D path in power module 3D path in module

Courtesy of Curamik


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True-3D Module (Phase leg)L2

L1

L3

L4

OUTPUT

POSITIVE

NEGATIVE

S1

S2

.

.1 4

32

M12 M13

M14

Current path in 3D, and Mutual inductance seen

from L1

1 12 13 14

21 2 23 24

31 32 3 34

41 42 43 4

L M M MM L M M

LM M L MM M M L

- -é ùê ú- -ê ú=ê ú- -ê ú- -ë û

Inner post

SiC MOSFET& Diodes

Orthogonal DBC Substrate


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Positive

Output

Device

Simulated v. Measured Inductance for HB Module

Impedance test with vector network analyzerTest with a 3mm wire (1nH) – 7 nHTest with module – 12 nHModule inductance between Positive (P) and Output (O) is ~6nH

ANSYS Q3D impedance extractorAC RL simulation @ 100MHzModule inductance between Positive (P) and Output (O) is 9nH


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Half Bridge Module 3D prismatic structure vs Planar Bond All structure

Similar electrical performance (resistance / inductance / symmetric current path)Competitive thermal performancePotentially better mechanical performanceMuch smaller footprint


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True-3D Mounting and Electrical Testing

Impedance test with vector network analyzer

•Test w/ 3mm wire(1nH): 7nH•Test w/ module:12nH•3D module L from Pos and Out is ~6nH

-20.00

-10.00

0.00

10.00

20.00

30.00

40.00

50.00

60.00

6.795E-05

6.800E-05

6.805E-05

6.810E-05

6.815E-05

6.821E-05

6.826E-05

6.831E-05

6.836E-05

6.841E-05

6.846E-05

6.851E-05

6.856E-05

6.861E-05

6.866E-05

6.872E-05

6.877E-05

6.882E-05

6.887E-05

6.892E-05

Current/A

Time/s

-10.000.0010.0020.0030.0040.0050.0060.0070.0080.0090.00

7.795E-5

7.800E-5

7.805E-5

7.810E-5

7.815E-5

7.821E-5

7.826E-5

7.831E-5

7.836E-5

7.841E-5

7.846E-5

7.851E-5

7.856E-5

7.861E-5

7.866E-5

7.872E-5

7.877E-5

7.882E-5

7.887E-5

7.892E-5

Current/A

Time/s

50A-to-0Atf=~5ns

50A-to-0Atr=~3ns

Double Pulse Testing

1200V/50ASiC MOSFETs& JBS Diode


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Simulation for half bridge moduleHeatsink simulation (COMSOL)

Material: 85Cu15Zn (UNS 23000 red brass)Heat source: 15W per chipAmbient: 25˚C air at 7m/sDimension: 1.5 x 1.5 x 7.5 mm pins with 1.5 spacing.

Simulation resultMax temperature for 3D heatsink: 100 ˚CMax temperature for planar heatsink: 196 ˚C with 10 ˚C difference between two chips

Thermal Simulation of HB Module


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Thermal Test of HB ModuleTest of half bridge module

Thermal test set up:20A through L-SBDMeasurement points:

Tj – ThermistorTheatsink – Thermal couple / IRTambient – Air flow sensor

Test result:Thermal resistance:

˚C/W

20.020.521.021.522.022.523.023.524.024.525.0

0.002.004.006.008.00

10.0012.0014.0016.0018.0020.00

0 10 20 30 40 50 60 70

Tem

pera

ture

(C)

Velo

city

(m/s)

Time (s)

Velocity (m/s)

Temperature (C)

90 46 1.6920 1.3

j a

loss

T TR

Pq

- -= = =

´


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Mechanical Simulation of HB Module Ctr PostSimulation for half bridge module

Inner post simulation (COMSOL)Material: 85Cu15Zn (UNS 23000 red brass)Heat source: 200˚C at chip contactAmbient: 100˚C at bottomConstrains: Prescribed displacement

Simulation resultMax von Mises stress: 3 x 108 N/m2Yield strength of red brass 69-434 Mpa(depending on post process)

Properties(UNS23000) Metric Imperial

Tensile strength 269-724 MPa 39-105 ksi

Yield strength 69-434 MPa 10-70 ksi

Elongation 55% 55%

Poisson's ratio 0.34 0.34

Elastic modulus 117 GPa 16969 ksi


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3ø Bridge ConceptExample: 3-phase full bridge prismatic module

POSITIVE

NEGATIVE

ABC

A B C

POS NEGNEG POS



END SEMINAR

Douglas C. Hopkins, Ph.D.Director – PREES Laboratory

FREEDM System CenterNorth Carolina State Univ.1791 Varsity Dr., Suite 100Raleigh, NC 27606-7571

[email protected]

www.prees.org

“systems integration” –integrating power electronics · 2018. 10. 15. · this tutorial...

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