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Annual Report (Sept. 2000 – Aug. 2001)

Foreword

IHP in a Nutshell

Update 2001

Overview

Technology Transfer

Deliverables and Services

Selected Projects

Collaborators & Partners

Selected Visitors

Guest Scientists

Seminars and Colloquia

IHP/BTU Joint Lab

Publications

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Aufsichtsrat

Staatssekretär Dr. Christoph HelmVorsitzenderMinisterium für Wissenschaft, Forschung und Kultur,Land BrandenburgMinDir Dr. Wolf-Dieter DudenhausenBundesministerium für Bildung und ForschungMinR Klaus FeilerMinisterium der Finanzen, Land BrandenburgDr. Harald RichterIHPProf. Dr. Matthias SchefflerFritz-Haber-Institutder Max-Planck-Gesellschaft, BerlinProf. Dr. Ernst SigmundBrandenburgische Technische Universität CottbusDr. Wolfgang WinklerIHP

Governing Board

Undersecretary of State Dr. Christoph HelmChairMinistry for Science, Research, and Culture,State of BrandenburgDr. Wolf-Dieter DudenhausenFederal Ministry for Education and ResearchKlaus FeilerMinistry of Finance, State of BrandenburgDr. Harald RichterIHPProf. Matthias SchefflerFritz Haber Instituteof the Max Planck Society, BerlinProf. Ernst SigmundTechnical University of Brandenburg, CottbusDr. Wolfgang WinklerIHP

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Wissenschaftlicher Beirat

Prof. Dr. Ulrich GöseleVorsitzenderMax-Planck-Institut für Mikrostrukturphysik, HalleProf. Dr. Leonard C. FeldmanDept. of Physics and AstronomyVanderbilt University, USAProf. Dr. Gerhard FettweisFakultät ElektrotechnikTechnische Universität DresdenMartin K. JacksonVirata, GroßbritannienDr. T. Mark LiuTaiwan Semiconductor Manufacturing Company,TaiwanDr. Tyler LowreyOvonyx Inc., USAProf. Dr. Dieter SchmeißerBrandenburgische Technische Universität Cottbus(als Gast)Dr. Martin V. SchneiderBell Labs, New Jersey, USAProf. Dr. Wolfgang SchröterIV. Physikalisches InstitutUniversität Göttingen

Scientific Advisory Council

Prof. Ulrich GöseleChairMax Planck Institute for Microstructure Physics, HalleProf. Leonard C. FeldmanDept. of Physics and AstronomyVanderbilt University, USAProf. Gerhard FettweisFaculty of Electrical EngineeringDresden University of TechnologyMartin K. JacksonVirata, United KingdomDr. T. Mark LiuTaiwan Semiconductor Manufacturing Company,TaiwanDr. Tyler LowreyOvonyx Inc., USAProf. Dieter SchmeißerTechnical University of Brandenburg, Cottbus(guest)Dr. Martin V. SchneiderBell Labs, New Jersey, USAProf. Wolfgang SchröterIV. Physical InstituteUniversity of Göttingen

Management

Prof. Abbas OurmazdDirector

Franz WeinlAdministrative Director

Annual Report Editors

Heidrun FörsterDr. Wolfgang Mehr

Leitung

Prof. Dr. Abbas OurmazdWissenschaftlich-Technischer Geschäftsführer

Franz WeinlAdministrativer Geschäftsführer

Redaktion des Jahresberichtes

Heidrun FörsterDr. Wolfgang Mehr

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Foreword

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Vorwort

Abbas OurmazdWiss.-techn.Geschäftsführer

Franz WeinlAdministrativerGeschäftsführer

Abbas OurmazdDirector

Franz WeinlAdministrativeDirector

„Ein bisschen schwanger ist nicht schlimm“, sagte dergroßzügige Vater, „aber ich werde darauf achten, dasses nicht außer Kontrolle gerät“.

Durch ganz Deutschland bewegt sich eine Welle, umden Technologietransfer aus Forschungsinstituten undUniversitäten in den Markt zu erleichtern. Es gibt eineMenge Fördermittel, Ratschläge, Workshops und Aus-schreibungen und schließlich sollen insbesondere imOsten, Arbeitsplätze aus Forschung und Entwicklunggeschaffen werden. Das sind bedeutende Entwicklun-gen.

Ein kurzer prüfender Blick auf die zugehörigen Vor-schriften zeigt jedoch, dass man nicht zu früh jubelnsollte.

Forderungen nach ungewöhnlichen Informationsrechtenund Privilegien sind nur Anfangsärgernisse. Das Haupt-problem ist, dass man beides haben möchte: Einerseitsgibt es den Wunsch, aus der Forschung heraus Arbeits-plätze zu schaffen, andererseits wird alles getan, umdie erforderliche Zusammenarbeit zwischen den öffent-lichen und privaten Institutionen zu begrenzen, selbstwenn sie gesetzlich erlaubt ist.

Das Forschungs- und Entwicklungspotential in Deutsch-land ist gewaltig. Die neuen Mechanismen, dies zurSchaffung von Arbeitsplätze zu nutzen, sind willkom-men. Kombiniert man dies mit der Erkenntnis, dassman nicht ein bisschen schwanger sein kann, wird derSchwung nicht zu stoppen sein.

Foreword

“A little pregnancy is not a bad thing” said the broad-minded father, “but I’ll make sure it does not get outof hand.”

Across Germany, moves are afoot to facilitate the flowof technology from research institutions and universi-ties to the market. Funding, advice, workshops, ad-vertisements, talks abound. After all, jobs, parti-cularly in the east, are to stem from R&D. These areimportant developments.

A cursory examination of the accompanying regu-lations, however, cautions against celebrating toosoon.

Issues such as demanding unusual information rightsand privileges are teething nuisances. The fundamen-tal problem stems from wanting to have it both ways.On the one hand, there is a wish to turn research intojobs. On the other, everything is done to limit theessential interaction between public and privateinstitutions, even when it is fully permissible underthe law.

The R&D potential in Germany is enormous. The newmechanisms for transforming this into jobs are im-portant. Combine them with a recognition that youcannot be a little pregnant, and the momentum be-comes unstoppable.

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IHP in a Nutshell

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Das IHP auf einen Blick IHP in a Nutshell

Zahlen & Fakten

Das Institut

- Gegründet 1991; Neugründung aus dem früherenAkademieinstitut mit langjährigerErfahrung in der Mikroelektronik auf Silizium-Basis

- 200 Mitarbeiter aus 16 Ländern- Mitglied der Wissenschaftsgemeinschaft Gottfried

Wilhelm Leibniz (WGL)

Aufgabe

- Ausbau der Region als Standort für Hochtechnologie- Katalyse innovativer Entwicklungen der

deutschen und europäischen Mikroelektronik- Erhöhung der Wettbewerbsfähigkeit der deutschen

und europäischen Industrie

Strategie

- Wertschöpfung durch Innovation- Konzentration auf drahtlose & Breitband-

kommunikation- Demonstration zukunftsweisender Prototypen auf

Systemebene mit gesichertem Weg zum Markt durchAusgründungen oder strategische Partnerschaften

Infrastruktur

- Vollständige Innovations-Kette vom Material bis zuSystemen, einschließlich 0,18/0,13 µm Pilotlinie mitReinstraum Klasse 1

Kompetenzen

- Systemorientierte Erweiterung der Silizium-CMOS-Technologie, insbesondere für drahtloseund Breitband-Anwendungen

- SiGe:C BiCMOS Technologien- RF-Schaltkreisentwurf- Kommunikationssysteme

Facts & Figures

The Institute

- Founded in 1991; successor institution tothe former institute of the East German Academywith extensive experience in silicon microelectronics

- 200 employees from 16 countries- Member of the Gottfried Wilhelm Leibniz Society

(WGL)

Mission

- Establish the region as a high-tech location- Catalyze innovative developments in German

and European microelectronics- Enhance the competitiveness of German and

European industry

Strategy

- Create value through innovation- Focus on solutions for wireless & broadband

communications- Prototype forward-looking, system-level solutions- Secure migration paths to the market through

start-ups or strategic partnerships

Facilities

- Complete innovation chain from materials tosystems, including class-1, 0.18/0.13 µm capablepilotline.

Competencies

- System-driven extension of silicon CMOS processtechnology, particularly for wireless and broadbandapplications

- SiGe:C BiCMOS technologies- RF circuit design- Communication systems

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Update 2001

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Update 2001

It was an interesting year. Technologically, we de-monstrated beyond doubt that we are world-class. Interms of business model, we showed that innovationexcellence can indeed bring major opportunities toregions euphemistically called “structurally weak.”And politically, we experienced first-hand how largeprojects are not subject to basic rules of commonsense, but a “higher logic” of their own.

Every institution believes they are wonderful. Thequestion is whether others agree. The IHP is now aninternationally acknowledged leader in high per-formance, modular process technologies. Our SiGe:C“communications” process module is in worldwidedemand, with the latest generation now licensed toIntel. Our LDMOS “power management” and “poweramplification” modules won accolades at IEDM, thetechnology world championships, and the phone hasbeen ringing since. Far from having to worry wherethe next “SiGe:C” will come from, we have establisheda steadily expanding, CMOS-based, modular tech-nology platform. With its “cut-and-paste” possi-bilities, it is a key enabler for systems-on-chip. Thiswill be one of our key technology assets in the future.But we remain far too cautious in setting technologygoals, preferring to let others set the pace. This hasto change.

Our RF Circuits activity is making good progress to-ward delivering useful frontend transceiver solutionsfor the 2 and 5GHz regimes. An extensive library of RFmacros has been assembled. However, both the indi-vidual macros and the complete transceivers must befurther refined. And we need working modules that“wink and blink.”

In Systems, we have reached the stage where visitorshave seen and liked our papers. Our project pallet isimaginative, attracting significant external funding.Within a year, we should be in a position to demons-trate our first complete wireless engine solution forthe 5GHz range; a good example of synergy betweenprocess technology, RF design, and systems. Moregenerally, we have all agreed that the “chrysalis” oftraining is finally gone, and everything we now do is“for real.”

“Breakthrough” has continued to extend its portfolio,with projects ranging from high-k dielectrics andelectron holography to indoor positioning systems.These build on our excellence in materials and diag-nostics, or address so-called “white spaces”. Inte-restingly, this activity is also stimulating high-riskprojects in other departments.

The “Joint Lab” is now in full swing. With staff num-bers exceeding 20 and significant external funding, itis becoming a unit to reckon with. But it is essentialthat the research processes routine at the IHP alsobecome firmly accepted and established at the JointLab.

Finally, is “synergy“ real? The answer is surprisinglysimple: It depends on people, particularly the leaders.Given a solution focus and a problem-rich environ-ment, it often occurs naturally, provided it nurturedand promoted by the leaders. From a purely technicalpoint of view, we have all the competencies andprocesses in place for excellent synergy, and someprojects are relying on “cross-border” interactions.

Oh, and by the way, we need to make sure Commu-nicant, our $1.3B start-up, succeeds - an interestingundertaking, given our approvals procedures.

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Overview

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Process Technology

The IHP technology is focused on developing keyvalue-adding technology modules for wireless andbroadband communication, integration of these mo-dules into high performance CMOS platforms, andenabling advanced SiGe:C BiCMOS prototyping.

Recent achievements include:a) Qualification - including all reliability tests - of

the 0.25 µm CMOS & SiGe:C BiCMOS technologies,and offering a MPW/Prototyping service.

b) Further development of our SiGe:C HBT modulewith fmax/fT =140/110 GHz.

c) Development of an LDMOS RF transistor forintegrated power amplifiers up to fT/fmax=30/50GHz.

d) Development of a best-in-class isolated PNPtransistor module for driving laser diodes(fT/fmax=20/14 GHz at BVCEO~5 V).

Development of the next technology platform basedon the Intel 0.18 µm CMOS backbone has begun.

Breakthrough

Breakthrough is an incubator for ideas to stimulatelong-term innovation with “breakthrough” character.

Current activities include following projects:- High-K materials;- Indoor positioning systems;- Isolated pnp module;- 130nm HBT integration.

Any member of IHP staff with innovative and highrisk ideas can work in this department for two years.Successful Breakthrough projects are expected tomature into standard projects, or start-ups within alimited (initially two-year) time window.

Overview

The IHP innovates in communication technologies,the key driver for the microelectronics industry. Wehave all the core competencies needed for demons-trating complete solutions. An update on each corecompetency is provided below.

System Design

Our systems work is focused on projects in mobileinternet applications and systems:1. Mobile Computing defines the architecture of a

context-aware mobile middleware platform.2. Wireless Internet Protocols develops new

mechanisms for vertical optimization of protocolstacks to achieve the best possible performance/energy ratio.

3. Wireless Broadband Networks designs a single-chip wireless modem for broadband wirelessaccess (54 Mb/s).

4. Wireless Bus develops enables the construction anew system for use in body area networks,cars, and home network applications.

Our deliverables consist of:a) IP cores, programs, or behavior models;b) Library elements that add value to our design kits;c) Working system prototypes and chips.

Circuit Design

Our Circuit Design effort is directed at developing keyRF components for wireless communication in the2-10 GHz frequency range, including complete trans-ceiver solutions. Specific applications range fromBluetooth, to Hiperlan and 802.IIa,b. A migrationpath to single-chip solutions is being systematicallydeveloped, often on the basis of the IHP modulartechnology platform, with CMOS, SiGe:C BiCMOS &LDMOS modules.

The deliverables consist of:a) RF macros for key communication standards;b) Complete transceiver solutions capable of single-

chip integration with baseband solutionsdeveloped in the Systems Department.

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Highlights 2001

1. Three IHP papers accepted at IEDM 2001 Aug. 2001

2. Best-in-class integrated LDMOS transistor for power June 2001transmission & management in a standard CMOS platformwith fmax/fT=50/30 GHz

3. SiGe:C BiCMOS integration concept for 130 nm technology June 2001

4. Viterbi chip fabricated with the IHP’s in-house 0.25 µm technology June 2001

5. Technology exchange with Intel May 2001

6. CeBIT Oscar for lesswire AG March 2001

7. Communicant Semiconductor Technologies launched Feb. 2001with IHP and Intel as strategic partners

8. New high performance SiGe:C HBT with Jan. 2001fmax/fT = 95/80 GHz for 40 Gbit/s fiber optics

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Technology Transfer

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Technology Transfer

0.18 µm CMOS Technology Transfer from Intel

Goal

Establish a world-class system-enabling process plat-form for next-generation communication technolo-gies.

Motivation

Develop a unique, modular technology platform withfull design re-use capability to enable sophisticatedSystem-on-Chip communications solution.

Fig. 1: “Inside Intel”: IHP team at Intel, Santa Clara, California.

Parameter nMOS pMOS

Threshold Voltage 0.4 V 0.38 VSaturation Current@1.3 V 815 µA/µm 320 µA/µmPoly Gate Length 0.13 µmGate Oxide Thickness 1.8 nmYield vehicle 16 M SRAM

Table 1: 0.18 µm CMOS parameters.

Results

Transfer started in May 2001, and included a 3-monthstay of an IHP team at an Intel site.

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Fig. 2: Fair Guide for PDA.

Fig. 3: Wireless plant surveillance and maintenance system.

Selected Projects

lesswire demonstrated the first large scale Bluetoothnetwork in cooperation with the Deutsche Messe AG,covering 25,000 m² of hall 13, and operated a radio-connected fair guide for PDAs, allowing visitors toidentify their current position and be guided to anexhibitor of their choice. This demonstration wasawarded the CeBIT Oscar 2001 for Internet & Commu-nication.The lesswire offline mobile fair guide for PDAs, usingthe LocalNavigator software, was used by more than100,000 visitors.

In cooperation with EISENMANN, a leading systemsprovider of surface technologies, automated materialflow, ceramics, and environmental technology, less-wire AG has developed an innovative plant surveil-lance and maintenance system. This application en-ables comprehensive plant control and visualizationon mobile devices such as palmtops, or tablet PCs.This facilitates industrial plant setup, operation,shutdown and maintenance.

lesswire AG

lesswire AG is a high-tech company, founded in 1999as an IHP spin-off. The company has now more than30 members of staff. It is the world’s Number Oneprovider of Bluetooth wireless base-stations.

Product Portfolio

Under the brand name LocalNavigator, lesswire pro-vides a complete technology platform consisting ofhardware and software products to enable mobile,location- and context-aware services.The hardware platform consists of a number of pro-ducts enabling local wireless access to the internet,including best in class Bluetooth wireless gateways.The software platform consists of server and clientproducts. Key components on the server side are theLocalNavigator core and the WebTag server. The corehandles a wide range of explicit location queries from

the client, and delivers notifications when a desiredlocal event occurs. The WebTag server enables thelinking of web-based, URL-specified resources toparticular places, objects, or conditions. The WebTagserver extends the core query and location eventservices with the capability to provide clients withinformation appropriate to their location, or othercontexts, such as time, identity, and preferences.The LocalNavigator client software provides a genericengine for a wide variety of guide applications, suchas museums, trade fairs, etc. on PDAs or mobile phoneplatforms.

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Regional Job Creation throughTechnology Innovation

Communicant Semiconductor Technologies AG, a dif-ferentiated “pure-play” foundry, was launched onFeb. 7, 2001, with Intel and the IHP as technologypartners. Based on a combination of best-in-classtechnologies from its partners, Communicant willserve the market at the intersection between com-puting and communication.

The $1.3B facility under construction in Frankfurt(Oder) will employ 1,500 people. It is within walkingdistance of the IHP. We are proud to have developedsome of the key technologies that led to the creationof Communicant, and wish the company much suc-cess.

Photo taken June 2001

IHP

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Deliverables and Services

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IHP offers a high performance, low power, and lowcost silicon-germanium-carbon process. This techno-logy can be integrated in a modular fashion intoexisting CMOS processes, with no changes to theCMOS process or device characteristics. The additionof carbon enhances the performance of the HBT sig-nificantly above the pure SiGe variant.

HBT

Passives

CMOS

Deliverables and Services

Qualified 0.25 µm SiGe:C BiCMOS ProcessTechnology

Fig. 4: Schematic cross-section of 0.25 µm SiGe:C BiCMOS.

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MPW & Prototyping Service

In order to allow prototyping and technology evalu-ation, IHP provides:

- Cadence-based design kit with analog and digitallibraries;

- 0.25 µm SiGe:C BiCMOS technology with localinterconnect, four metal layers, and highperformance passives (resistors, capacitors, andhigh-Q inductors);

- 200 mm wafers;

- 8-week cycle time.

Design Kit

CAD Platform (Cadence Mixed Signal):

- Design Framework II (Cadence 4.4.3);

- Behavioral Modeling (Verilog HDL);

- Logic Synthesis & Optimization (VHDL/HDL Compiler, Design Compiler/Synopsys,Power Compiler/Synopsys);

- Test Generation/Synthesizer/Test Compiler(Synopsys);

- Simulation (RF: SpectreRF, Analog: SpectreS,Behavioral/Digital: Leapfrog/NC-Affirma/Verilog-XL/ModelSim);

- Place & Route (Silicon Ensemble & Preview);

- Layout (Virtuoso Editor-Cadence);

- Verification (Diva: DRC/LVS/Extract/Parasitic Extraction, Dracula: DRC).

RF Macro Cells/IP

We offer a wide range of IP for wireless & broadbandcircuits and systems, including:

- Macrocells for Bluetooth (transceivers, LNAs, mixers,VCOs, dividers, prescalers, demodulators, frequencysynthesizers, IF amplifiers, etc.);

- Macrocells for Hiperlan (5 GHz VCOs, polyphasefilters, IF down mixers, gain controled amplifiers,etc.);

- Macrocells for RF base stations (e.g., poweramplifiers);

- Macrocells for baseband applications (e.g., Viterbidecoders);

- Abstract SDL model of MAC layer for IEEE802.11acompliant modem with testbenches for variousdeployment scenarios;

- Implementation (C code) model of the MAC layerfor an IEEE802.IIa compliant modem;

- SPW model of a digital baseband processor for anIEEE802.IIa compliant modem, including thesynchronization and channel estimation units;

- Synthesizable VHDL models for selected blocks ofthe baseband processor of a Hiperlan/2 orIEEE802.11a compliant modem (Viterbi decoder,FFT/IFFT processor, QAM mapper/demapper, Cordicprocessor, etc.).

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For more information please contact:

Dr. Wolfgang MehrDirector, MarketingIHPIm Technologiepark 2515236 Frankfurt (Oder), GermanyEmail: mehr@ihp-microelectronics.comTel: +49 335 5625 154Fax: +49 335 5625 327

Failure Mode Analysis and Diagnostics

We offer support for yield enhancement through failuremode analysis with state-of-the-art equipment, in-cluding AES, AFM, FIB, LST, SEM, SIMS, STM and TEM.

Training and Retraining

Training and retraining in advanced BiCMOS technolo-gies, RF circuit design, and system design for broad-band and wireless communication can be arranged tomeet your needs.

Process Module Support

IHP support advanced process module research anddevelopment & small volume prototyping for standardprocess modules and process steps.The process module support is based on IHP‘s ad-vanced 0.25 µm CMOS and SiGe:C BiCMOS technologies.

Available process modules include:

- Standard processes (etching, CMP & deposition ofstandard layers and layer stacks, such as thermalSiO2, PSG, Si3N4, Al, TiN, W);

- Standard and low-temperature epitaxy(Si, Si:C, SiGe, SiGe:C);

- Short-flow processing.

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Selected Projects

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Selected Projects

SystemsOverview

In a few years, most appliances will be networked viawireless access. This involves the following key chal-lenges:1.

2.

3.

In order to solve these challenges we are proceedingas follows.1.

2.

3.

Fig. 5: Module architecture for a body area system.

Our deliverables consist of:- IP cores, programs, or behavior models of the

designed components;- Library elements that add value to our design kits

and are available for users of our technologies;- System prototypes and chips.

We are currently working on four projects:1.

2.

3.

4.

We consider the wireless engine a key enabler forfuture internet systems. The IHP technology platformmakes it possible to integrate all functions into asingle chip, including complex digital designs andanalog circuits. Each of the projects contributes tothis vision by providing prototypes and core libraryelements. All processors and modules will be availableto external and internal customers via an IP corelibrary.

New context-aware wirelessEnhancing the usefulness of information deliveredby “always on” wireless internet services requiresintelligent filters. Location awa-reness is widelyseen as a promising approach to achieve this goal.More context information must be included to allowthe design of dedicated applications.Bandwidth utilisationMost licensed bands are overcrowded. New wirelessinternet services the bandwidth requirem 10 xmore bandwidth. New bandwidth is becomingavailable in higher frequency bands of 5 GHz andabove. Innovative access and re-use mechanisms(both baseband and medium access protocols) arenecessary to allow co-existence of several appli-cations in the same band.Energy utilisation“Always on” devices require extended stand-bytime. New intelligent energy management methodsand innovative terminal architectures are requiredto make best use of available battery power.

Develop context-aware applications based on intel-ligent, scalable, distributed, and configurable eventmanagement components. They allow customizedfiltering based on personal profiles. A platformapproach allows the rapid development of newcontext-aware wireless internet solutions in lesstime and with less knowledge of the details of theunderlying technologies.Investigate and realize new architectures for extre-me short-range communication, e.g., in body areanetworks (see Fig. 5). The modular approach allowsthe rapid development of new virtual devices thatcommunicate internally via a wireless bus.Design and implement a new single-chip multipro-cessor architecture for a wireless engine that rea-lizes vertical energy management by optimizing theconfigurable parameters of the different layer pro-cessors.

Mobile ComputingDefines the architecture of a context-aware mobilemiddleware system.Wireless Internet ProtocolsDesigns new mechanisms for vertical optimization ofprotocol stacks to achieve the best possible per-formance/energy ratio.Wireless Broadband NetworksDesigns a single-chip wireless modem for broadbandwireless access (54 Mb/s).Wireless BusDesigns a wireless bus system to allow the cons-truction of new systems for body area networks, carapplications and home networks.

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Wireless Broadband Networks (WBN)

Goals

1.

2.

Motivation

Broadband communication systems will allow a va-riety of new applications ranging from wireless videotransmission to high-speed internet access. A signi-ficant market segment will be served by IEEE802.11aand Hiperlan/2 capable modems soon.

For mobile applications, low-power and cost-efficientsolutions are needed. This can be achieved by de-ploying dedicated processors supporting real-timeoperation of complex, lower layer communicationalgorithms.Our focus on cross-layer optimization and integrationof a complete modem into a single chip is aimed atsignificantly improving power dissipation, cost andperformance [Grass 01]. Crosstalk is considered amajor issue for a single-chip solution. A number ofstrategies to tackle this problem are under investigation.These include technology modifications, as well ascircuit design techniques such as asynchronous designs.

Results

1.

2.

3.

4.

5.

Demonstrate a single-chip wireless broadbandcommunication system in the 5 GHz band. Thedesign to include analog frontend, data conver-ters, digital baseband processor, and the mediumaccess control layer (MAC) for Hiperlan/2 andIEEE802.11a. The IHP 0.25 µm SiGe:C BiCMOStechnology will be used to fabricate this mixed-signal chip.

Generate IP cores for complex mobile commu-nications systems suitable for future internal pro-jects and external customers. In particular, verifyand demonstrate all components of an OFDM base-band processor (BB), and the protocol layer (MAC).Make results generally available as IP cores.

A VHDL model of the datapath of the basebandprocessor has been developed, successfully simu-lated, and demonstrated to be compliant with theIEEE802.11a standard. This VHDL model allows abit-true and cycle-true verification of the basebandfunctionality, and is suitable for circuit synthesis.It is a significant milestone towards a single-chipimplementation.

A VHDL model of the synchronizer unit of the base-band processor suitable for circuit synthesis hasbeen developed. Together with the datapath unit,it fulfills the complete functionality of the digitalpart of the IEEE802.11a physical layer [Troya 01].Implemented in an FPGA and combined with thedatapath unit, it allows field experiments for finetuning of synchronization algorithms and para-meters.

A Coordinate Rotation Digital Computer (CORDIC)was designed in VHDL and fabricated using the in-house 0.25 µm CMOS process. The CORDIC pro-cessor deploys a novel, potentially power efficientarchitecture [Maharatna 01]. In order to allow theinvestigation of effects of cross-talk, our designcan operate synchronously and asynchronously.This is the first ever design that supports bothmodes of operation. Depending on application andenvironment, the most suitable mode can be selected[Grass 02].

A basic model of the Data Link Control Layer (DLC)for Hiperlan/2 has been designed in SDL, and simu-lated. This model is the basis for a real-time imple-mentation of the Hiperlan/2 protocol stack.

A complete model of the Medium Access Controllayer (MAC) for an IEEE802.11a based broadbandcommunication system has been generated, tested,and verified. This model has been implemented onan ARM processor connected with external hard-ware accelerators. The hardware accelerators aredesigned in VHDL, and implemented on an FPGA,linked via the processor bus to the ARM board (Fig. 6).

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Fig. 6: Test setup for IEEE802.11a MAC implemented on ARM processor supported by hardware accelerators on an FPGA board (twoterminals shown).

References

[Troya 01] A. Troya, “On the Performance of aDecision-Directed Channel Estimatorfor OFDM” 6th International OFDMWorkshop, Hamburg, September 18-19(2001).

[Grass 01] E. Grass, K. Tittelbach, U. Jagdhold,A. Troya, G. Lippert, O. Krüger,J. Lehmann, K. Maharatna,K. Dombrowski, N. Fiebig, andR. Kraemer, P. Mähönen (University ofOulu), “On the Single-Chip Implemen-tation of a Hiperlan/2 and IEEE802.11a Capable Modem”, IEEEPersonal Communications Magazine,Vol.8, No. 6, pp.48-57, Dec. 2001.

[Grass 02] E. Grass, B. Sarker, K. Maharatna,“A Dual-Mode Synchronous/Asynchronous CORDIC Processor”,ASYNC’2002, Manchester,8-11.04.2002, accepted forpublication.

[Mahartna 01]K. Maharatna, E. Grass, S. Banerjee,A.S. Dhar, “CORDIC-Einheit”, filed20.12.2001, Reg: 101 64 462.0.

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Wireless Internet

Goals

1. Implement the standard internet protocols(TCP/IP) in hardware.

2. Improve the performance of TCP/IP on handheldwireless devices by in-layer optimization and byallowing the protocol layers to interact.

Motivation

The wireless internet is expected to play a dominantrole in future communications technology. The termdenotes the convergence of mobile communication(currently mainly mobile phones) with access to theinternet (currently mainly via large stationary PCs).

Internet technology is built on two protocol stan-dards: TCP to ensure reliable data transport, and IP toroute data between the subnetworks to the properdestination. Although developed for fixed-wire net-works, these standards are solidly entrenched, and areunlikely to change, despite difficulties in wirelessenvironments.

The current trends present the following key chal-lenges:- Minimizing the effects of the error-prone

wireless channel on the performance of TCP/IP.- Moving the handling of the TCP/IP protocol to a se-

parate low-cost unit. This allows the CPU of ahandheld device to support internet access withouta large overhead.

- Optimizing the protocol stack to save energy andincrease performance, specifically for handhelddevices with limited resources.

Results

The Wireless Internet project addresses the problemsposed by wireless terminals and pervasive internetaccess in two ways.

TCP/IP in hardware: Support TCP/IP by dedicatedhardware, either as a separate chip or by hardwareimplementation of several protocol layers. A hardwareTCP/IP module has the potential to support high datarates needed for MAC standards, such as IEEE 802.11a,with a power consumption typically one-tenth that ofa software solution. The following steps have beencompleted:

1. TCP/IP was implemented in C as a basis forhardware implementation and optimization. Theimplementation is flexible, as it is decoupled fromspecific operating system features (e.g., blockingfunction calls, multiple processes or threads), issmall (about 40 kB compiled), and is one-thirdfaster than the commercial ARM TCP/IP, even as asoftware implementation.

2. The TCP/IP implementation has passed extensiveinteroperability tests for communication withother TCP/IP variants (BSD, Linux, Microsoft).

3. The implementation was successfully ported to aNetARM board as a first step towards a hardwareimplementation.

4. In parallel, an equivalent TCP implementation inSDL (Software Description Language) wasdeveloped. SDL has the potential for faster andmore reliable protocol implementation, and bettersupport for hardware/software codesign.

27

Protocol optimization: To reduce power consumptionand to improve key parameters such as throughput,algorithms can be optimized on a layer-by-layerbasis, or the layers can be permitted to interact tosome extent. The following results were obtainedduring the last year:

1. The simulation of the protocol stack was used tostudy the way in which the IEEE 802.11 MACprotocol for a lossy wireless link interferes withthe TCP layer. The results show that successfultransmission can still be achieved at a bit errorrate one order of magnitude larger, using a „nevergive up“ strategy in which the MAC layer is givenfull responsibility to retransmit packets lost in thewireless channel (Fig. 7). However, to avoid delaysand jitter, this should not be done for streamingdata. Vertical interaction between the applicationand the MAC layer is required to exploit thisoptimization.

2. Modifications were made to the TCP imple-mentation to improve performance. For example,by eliminating the receive buffer, one copyoperation could be avoided for incoming packets.

These results form the groundwork for a systematicoptimization of mobile devices used to access a wire-less local-area network (WLAN). In the approachpursued here, and in contrast to other efforts with thesame aim, performance improvements will be attainedby modifying only the handheld device. The majoradvantage of this solution is that it integrates intoexisting networks without the need to change thesein any way.

Fig. 7: Simulated results for the throughput of TCP over an IEEE 802.11 MAC layer. Data are transmitted over a lossy wireless link followedby a delay, which models the internet. The parameter aLongRetryLimit determines the maximal number of retransmission attempts by theMAC layer. When this parameter is small, performance stays well below the limiting curve as TCP responds to packet loss by reducing thedata rate.

28

Fig. 9: The PLASMA service platform is an additional layerbetween the Java virtual machine and the application.

Mobile Computing

Goals

1.

2.

3.

Fig. 8: European Wireless Location Services, The Strategis Group,2000.

Develop, demonstrate, and test a scalable softwareservice platform for location-aware mobile appli-cations based on Java/Jini software technology.Evaluate the platform scalability and performanceby means of theoretical studies and measurements.Demonstrate the platforms efficiency and perfor-mance using a realistic application scenario.

Motivation

Mobile multimedia represents the “next frontier” ininternet. As shown in Fig. 8, a rapid increase of re-venue from location-based mobile data services isanticipated.

Mobile communication, including new systems likeUMTS and W-LANs require advanced mobile multi-media applications to be succcessful.Location- and context-aware applications are likely toplay a significant role in mobile computing. The closeconnection of content with the mobile’s position is akey value-adder for future data services.

The applications developed and investigated up tonow demonstrate the potential of taking location andcontext into account. However, these applications arecomplex and lack scalability and reusability. Theapplication programmer must have special skills anddetailed knowledge of the underlying communicationinfrastructure. There is also a lack of a clearly definedframework for creating new services using locationinformation. Instead of concentrating on prototypingone more location-aware service, our project is fo-cused on defining such a framework.A generic service platform is needed to achieve reusa-bility, scalability, and performance.

Results

We have developed a service platform, which operatesas an additional layer between the Java virtual ma-chine and the application (Fig. 9). This middlewareapproach has the potential to hide the complexity ofthe network from the application.

A well-defined API enables an efficient implemen-tation of new services and service maintenance. Itallows the developer to rapidly create new appli-cations. Implemented in 100 % pure Java, our serviceplatform is independent of the underlying operatingsystem and the communication network.

PLASMA serverJava VM

Operating system

Platform comm.

Sightings

ApplicationPLASMA client

Java VMOperating system

29

The platform can operate with any type of positioningsystems, such as infra-red beacons for indoor and GPSfor outdoor applications.

The concept of objects and auras introduced in ourplatform enables the application designer to definephysical spaces of interest independently from theunderlying communication infrastructure. An aura canhave any shape and nearly any size. Each object canhave several auras, which are totally independent ofeach other. The number of messages to and fromauras is drastically reduced by means of optimizedcommunication algorithms.

In order to ensure the scalability, the workload isdistributed over a number of identical central units.The platform is organized in a hierarchical structure,building several trees of platform servers. Each treecan be configured to the requirements of the deploy-ment scenario. The service platform infrastructure canbe efficiently managed on the basis of a hierarchy ofseveral Jini lookup servers. All information needed forthe platform server’s operation (e.g., all neighbors,the root server, the next object register etc.) areoffered by the look-up service related to one domainof a given hierarchy level.

An efficient hand-over mechanism of shared objectsbetween several platform units has been introduced.This enables true multi-server scenarios with an effi-cient implementation of searching algorithms forobjects in a global environment.

An event mechanism, using algorithms for trackingand firing events was successfully implemented.

A messaging concept allowing the users to exchangedata such as text and images has been implemented,and successfully tested.

The functionality of the service platform was verifiedby means of the in-house testbed “Discover IHP”.

A quantitative overall performance evaluation of theplatform was carried out measuring the maximumsighting update rate a single server can process, andthe average response time for a typical platformfunction (locate a person). As a result, the sightingupdate rate is more than 2000 sightings per secondper server, and the mean response time for locatinga person is 45 ms.The delivery rate for user events was evaluated. Usinga previously defined scalability metric, the platformwas quantified with regard to an efficient operationon various scales. Finally, remaining bottlenecks wereidentified and suggestions for platform performanceimprovements formulated. The results obtained provethe platform concept, and place it amongst the bestin its class.

To demonstrate the use of the platform, a sampleapplication was developed giving a flavor of valueadded services, like navigation or entertainment, forfuture mobile applications.

Fig. 10: Sample application to demonstrate location awarenes.

30

Circuit Design

Vision

Based on a high performance BiCMOS + LDMOS in-house technology platform, our circuit design activi-ties are focused on wireless transceivers in the fre-quency range 2 - 6 GHz, where key systems such asBluetooth, UMTS, Hiperlan are located . State of theart transceivers in this frequency range are usuallyrealized with several chips in different technologies(GaAs, Si Bipolar, LDMOS and CMOS) and many dis-crete components, such as power transistors, RF di-odes, R, C and L’s, leading to a cost-intensive block.Our vision of the future transceiver is a macro, in-cluding all the necessary RF functions, ready to beplaced on a single chip with the baseband.Since some transceiver blocks work close to thetechnology limits, it is a challenge to find the rightprocess technology and circuit design solutions. Toreach the goal of a single chip solution, substantial,multi-year effort in design and characterization of on-chip RF components is needed.

Single-Chip Bluetooth Transceiver

Goals

Design and prototype a single-chip 2.4 GHz trans-ceiver in a standard CMOS technology for Bluetoothapplications. Develop reusable RF building blocks fora CMOS IP library.

Motivation

The new Bluetooth standard in the 2.4 GHz ISM bandis well-suited to short-range, ad-hoc radio connec-tions between mobile PCs, mobile phones, and manyother portable devices. Bluetooth-enabled deviceswill replace cables in offices, at home, in cars, and inindustrial equipment.

Bluetooth devices require low-cost solutions with asmall form factor. Fully integrated CMOS solutionswith very few external components are preferred. Ourultimate goal is the complete integration of the RFtransceiver together with the digital baseband. Thisinvolves challenges due to substrate coupling andlosses inherent to standard CMOS technologies.

Results

We have designed, prototyped, and evaluated a sin-gle-chip 2.4 GHz transceiver for Bluetooth appli-cations in a standard CMOS process. Our solutioncontains all necessary RF components for receivingand transmitting, the frequency synthesizer, and thedigital circuitry establishing the interface betweenthe external baseband processor and the RF part.

31

The main results are as follows.

1.

2.

3.

New prototypes of the transceiver fabricated with thelayout shown in Fig. 14. All subcircuits (except thedigital interface) have been tested successfully. Tab. 2summarizes our primary results.

A conventional superheterodyne receiver architec-ture with one intermediate frequency at 111 MHzwas implemented (Fig. 11). The receiver consistsof an LNA, a down-conversion mixer, an IF am-plifier, and a demodulator with an external LCtank. In the transmit path, a direct up-conversionscheme with open-loop modulation is used. Thesame fully integrated frequency synthesizer is usedin both receive and transmit modes, covering alarge frequency range from 2291 MHz to 2480 MHzin 1 MHz steps. A digital interface between theexternal baseband processor and the RF part is in-cluded. It contains registers for channel selection,control logic for the RF part, and a virtual framerate oscillator.

A major challenge in RF CMOS design is the low-noise amplifier (LNA). We used a two-stage trans-impedance amplifier with a measured gain of about9 dB in the desired ISM band and a noise figure of5 dB. This result is a compromise between powerdissipation (15 mW) and noise performance. Themoderate values for the noise figure are achievedon highly doped epi-wafers. The IP3 of –1 dBm issufficient. The measurement results are shown inFig. 12.

The IF section of the transceiver consists of anlimiting amplifier providing up to 60 dB gain, anda GFSK demodulator operating at the intermediatefrequency (IF) of 111 MHz. At this frequency, anexternal LC tank is required to achieve the neces-sary Q factor of the filter. Fig. 13 shows the mea-sured bit-error-rate (BER) as a function of thesignal input power of the entire IF section.

Fig. 11: Block diagram of a Bluetooth single-chip CMOStransceiver.

Fig. 12: Measured gain and noise figure of the CMOS LNA forBluetooth as a function of frequency.

32

Fig. 14: Layout of a single-chip, all CMOS Bluetooth transceiver.

Subcircuit Main parameter Supply current Remarks

Low-noise Amplifier gain: 10.9 dB; NF: 4.5 dB functioningDown-conversion Mixer conv. gain: 9 dB; IIP3: -1 dBm meets specsIF Amplifier gain: 56 dB; NF: 14 dB meets specsDemodulator dynamic range: -20 to +10 dBm meets specsVoltage-controlledOscillator tuning range: 1.8 to 2.7 GHz meets specsDivide-by-two Circuit working range: 0.11 to 3.1 GHz meets specsPrescaler 15/16 working range: 0.3 to 1.46 GHz meets specsCounter, Phase-lockedLoop - functioningBaseband interface - integrated

Table 2: Overview of key measured results on the single-chip Bluetooth transceiver.

Fig. 13: Measured Bit-Error-Rate (BER) of the IF section of theBluetooth transceiver as a function of signal input power.

6.1 mA3 mA

10 mA2.1 mA

12 mA7 mA

15 mA

5 mA-

33

Transceiver for 5 GHz Wireless BroadbandNetworks

Goals

1. Design and prototype an entire transceiver chipfor 5 GHz wireless network applications usingIHP’s SiGe:C BiCMOS technology.

2. Extend the reusable cell library for circuit designand technology and generate IP.

Motivation

Demand for high data rate wireless transmission israpidly increasing. The IEEE 802.11a standard isappearing in combination with, or as extention to theIEEE 802.11b in the 2.4 GHz band. A cost effective,single-chip RF frontend would be a significant ad-vance.

Results

All blocks of the radio and intermediate frequencysections of a 5 GHz transceiver have been designedand fabricated. Previously designed circuits wererefined and merged into larger blocks. Most circuitswere functional first time with the IHP 0.25 µmSiGe:C BiCMOS technology. Some earlier blocks werealso implemented in a 0.25 µm CMOS TSMC techno-logy.

Considering spurious behavior for the transmit pathand weak rejection opportunities, we decided to shiftthe intermediate frequency (IF) to a higher value of810 MHz.

Our key results can be summarized as follows.

1.

The poly phase filter allows the VCO to work at therequired oscillator frequency with lower phasenoise and power consumption, but a smaller band-width for accurate operation. The divider-basedsolution has superior bandwidth but an inherentlyhigher phase noise and power.Measurements for 810 MHz and 280 MHz show nosignificant difference between these approaches.Future measurements with a complete transceiverare needed to identify the best approach.

All circuits of the RF down-converter are now avai-lable in our 0.25 µm BiCMOS technology. The VCOwas redesigned to 4.4 GHz center frequency witha new type of varactor. It operates down to below2 V supply with a tuning range of about 200 MHz.At 2.5 V, the power consumption is about 15 mW(see Table 4). The area is 550 x 400 µm² (Fig. 16).The LNA shows a broadband behavior with a mo-derate noise figure. Further improvements are un-der way.The down-mixer was evaluated and redesigned forimproved dynamic parameters. Results of this re-design will be obtained with the next chips avai-lable in late 2001.

Other circuits that were designed and evaluatedinclude:

- 5 GHz dual modulous prescalers (32/33 and16/17);

- 60 dB CMOS gain-controlled IF amplifier(280 MHz);

- 5 GHz up-converter.

The IF down converter block is now available for280 MHz and 810 MHz. The chip photo of the 810MHz version with poly phase filter is shown in Fig.15. It has a 550 x 550 µm² area. Table 3 sum-marises the main parameters.One of the primary challenges in modern trans-ceivers with digital modulation schemes is mat-ching their I and Q channel signals. Proper quadra-ture shifted oscillator signals are essential. Twodifferent approaches for this quadrature gene-ration were investigated:

- poly phase filters and- divider-based topologies.

2.

3.

34

Fig. 15: Layout of the IF down-converter with poly phase filter. Fig. 16: Layout of the 4.4 GHz CMOS VCO.

Table 4: Results of 5 GHz oscillators.

Table 3: Measured parameters of the IF down-converter.

Parameter IHP Best in Class Unit Remarks

Supply voltage 1.5 - 2.5 2.7 - 5.25Supply current 22 22 @ 3.0 VConversion gain 10 12 dB Conversion gain1dB Compression Point 1 0 dBm 1dB Compression Point3rd order Intercept Point 11 10 dBm 3rd order Intercept Point

Parameter Bipolar CMOS Best in Class Unit Remarks(SiGe 1999) (IHP 2001)

Supply voltage 5 1.5 – 3.6 1.5 VSupply current 7 4.4 4 mA @ 3.0 VCenter frequency 5.5 4.4 4.9 GHzTuning range 950 200 500 MHz @ 0 - 3 VSSB Phase noise -101 -105 - 101 dBc/Hz @ 1 MHz

35

Base-Station RF Components

Goals

1.

2.

Motivation

The growing number of mobile phone users and de-mand for higher data rates force the tech-nology todevelop multi-channel systems with higher band-width. This requires new base-stations with new com-ponents, especially multi-channel power amplifiers.Our SiGe:C technology offers the possibility to deve-lop chip solutions with advantages in price, noise,and thermal conductivity compared to other highpower technologies.

Results

1.

2.

3.

Fig. 17: Phase shifter operating at 0.5 W@2.1 GHz,gain 5-40 dB.

Fig. 18: Feedforward power amplifier error loop, operating at lowpower levels.

Develop a base-station power amplifier for thirdgeneration mobile communication systems basedon SiGe:C power transistors with an output powerof above 100 W.Develop medium power bipolar and LDMOS tran-sistors in the frequency range 2 - 6 GHz.

The first LDMOS power transistors developed by thetechnology show excellent performance and achievePower Added Efficiency (PAE) of 70 and 60 percentat 2.0 and 5 GHz, respectively, and the maximumoutput power above 550 mW. No LDMOS transistorshave been reported with such high PAE at thesefrequencies and output power.We can now perform automatic load-pull measure-ments and characterize transistors and amplifiers innormal and pulsed modes with a minimum pulsewidth of 10 µs. The characterization can be per-formed on-wafer, or on-board. The setup is con-trolled by a PC via a GPIB bus measuring DC and RFcharacteristics of the devices.Prototypes of amplifiers for 25 W and 120 W outputpower for the frequency range 2.1 - 2.2 GHz, anda programmable vector attenuator have been built.A novel idea for a programmable phase shifter hasbeen realized. The phase shifting is performed bya hybrid-attenuator-hybrid combination. The sys-tem has to be calibrated and controlled by a DSP.

36

Testchip Design and BenchmarkingCircuits

Goals

Design and investigate standard and innovative testcircuits for benchmarking advanced in-house andexternal technologies.

Motivation

a) Facilitate technology developmentb) Evaluate & compare capabilities of competing

technologies (e.g. SiGe bipolar vs. advancedCMOS)

c) Provide early link between technology and circuitinnovation.

Results

Test chips were developed to enable process deve-lopment from early process R&D, and device researchto qualification & circuit implementation.All structures for design rule tests, SPICE modeling,process control monitor, yield analysis, process quali-fication etc. were developed (Fig. 19).

Examples include:- More than 200 test transistors placed in RF bond

pad configuration for optimization of bipolar, MOSand LDMOS transistors;

- Arrays of 16k transistors in parallel for yieldanalysis of SiGe:C bipolar transistors;

- A wide variety of structures for optimization ofintegrated inductors;

- Bipolar and LDMOS power transistors.

The benchmarking circuits include:- Ring oscillators;- Static and dynamic divider circuits;- Multiplexers;- Amplifiers.

Measurement utilities for on-wafer ( > 40 GHz) andboard level tests (up to 40 GHz) were established.Fig. 21 shows the measurement setup for on-boardmeasurement of divider circuits.

The main measurement results are as follows.

- CML Ring oscillator gate delay in SiGe:CBiCMOS technology are below 6 ps with a currentconsumption of about 1 mA per gate.

- Static and dynamic divider speeds for bipolarcircuits are well above 40 GHz (0.25 µm SiGe:CBiCMOS).

- Static and dynamic divider speeds for CMOS circuitsare ~ 20 GHz (0.13 µm lithography).

- Record power added efficiency of integrated LDMOStransistors were reached for 2 and 5 GHzapplications.

37

Fig. 20: Module for on-board measurements of frequency dividercircuit with results shown on an oscillograph.

Fig. 21: Measurement setup for high speed circuits. The highfrequency input (36 GHz) and the divide by 8 output signals areshown.

Fig. 19: Part of the testchip T53 for development of 0.25 µm SiGe:C BiCMOS technology.

Viterbidecoder

Signal isolation

Qualificationdevices

Inductors

Transmission lines

Customer circuits

Benchmarking circuitsRF Transistors

Power transistors

Technology teststructures

Inductors

LDMOStransistors

38

Technology

Vision

Develop high-value, CMOS compatible, modular tech-nologies for wireless and broadband.

Motivation

A microelectronic solution requires the followingcapabilities: computing, data storage, communica-tion, and power management. At present, these areimplemented in a variety of different, often stand-alone technologies, as shown in Fig. 22a.

We are developing a unified technology platform toenable all these capabilities on chip, as shown inFig. 22b. The process technology offering is aug-mented with specific design tools and IP libraries thatfacilitate rapid, high-yield production, and hencesuperior time-to-market.

Platform

Our next-generation technology platform will consistof the following key elements.1. The Intel digital CMOS process with industry

standard parameters as backbone, to allowre-use of existing digital IP.

2. Proprietary process modules as keysolution-enablers. These will include: SiGe:C HBTs;a variety of LDMOS devices for power amplificationand management; and non-volatile memory.

3. Associated circuit and system IP to allow rapiduse of the technology platform.

The advantages of this platform are as follows.1. A variety of different system applications can be

served from the same digital backbone, offeringrelative immunity to market changes, and significantsavings in development and fabrication costs.

2. The fully modular approach allows“mix-and-match” system development with fullre-use of existing designs, thus reducing cost andcycle time.

3. The solutions can be implemented on an optimumnumber of chips, with the ability to migrate to asingle-chip solution, should that make technicaland economic sense.

Fig. 22: Required system capabilities, and supportingtechnologies. (a) Today; (b) Next-generation IHP processtechnology platform.

Status

- Modular SiGe:C HBT bipolar technology withfT/fmax exceeding 100/130 GHz, including ringoscillator gate delay times of less than 6 ps/stage.

- Best in class LDMOS technology- Close-to-industry performance of the pilot line,

despite the one-of-a-kind tool set. Introduction of7 day/24 hr. operation with cycle time for a full0.25 µm BiCMOS flow of less than 1.7 days/masklevel

- Start of Intel 0.18 µm CMOS transfer

39

1) Advanced technologies

HBT before CMOS - A novel integration scheme for the0.13 µm generation and beyond

The major challenge for integrating state-of-the-artCMOS technologies with high-performance HBTs is thecontrol of the impact of one process on the charac-teristics of the other device type. In current appro-aches to SiGe HBT and CMOS integration, HBTs areprepared immediately after implanting the S/D exten-sions, or later in the CMOS flow. Such integrationschemes make it difficult to migrate an HBT modulefrom one CMOS generation to another. This is be- Fig. 23: HBT before CMOS integration flow.

Communication Modules

Goal

Develop modular, cost effective communication mo-dules for advanced industry standard CMOS platforms.

Motivation

The convergence of communication and computingtechnologies call for modular, cost-efficient inte-gration of different circuits in order to enable System-on-Chip integration.

Results

The results can be divided into the following cate-gories.

1) Advanced technologies:- Integration schemes for 0.13 µm CMOS

2) Advanced modules:- Integrated RF LDMOS power amplifiers- Isolated PNP- Devices beyond the Johnson limit

(fT * BVCEO > 200 GHzV)

3) 0.25 µm SiGe:C BiCMOS technology platform:- Quad metal process, R,C,L, varactor, high voltage

SiGe:C NPN and high performance SiGe:C NPN asmain features

4) Design kit:- Mixed-mode Cadence-based design kit.

5) Reliability & diagnostics

coming increasingly acute, because highly scaledMOSFETs are sensitive to any additional thermal stepafter S/D extension and halo implantation. We havesuccessfully demonstrated an “HBT before CMOS”integration scheme, which decouples the fabricationof the CMOS transistors from the HBT’s thermal bud-get. The basic process flow is shown in Fig. 23.This scheme takes full advantage of the increasedthermal stability of C-doped SiGe HBTs. Our primaryresults can be summarised as follows.

1. The impact of the HBT thermal budget on CMOScharacteristics is entirely eliminated, making itpossible to integrate the HBT module in a wideclass of CMOS technologies without any changesin the CMOS process, with full re-use of existingCMOS design libraries.

2. State of the art HBTs can be fabricated in theHBT-before-CMOS scheme [1].

40

2) Acvanced modules

LDMOS RF transistors for integrated power amplifiers

RF LDMOS transistors are important candidates forintegrated power amplifiers and power management.The key challenge involves achieving high power-added efficiency, excellent RF characteristics, andhigh breakdown voltages in an integrated BiCMOSprocess with thin gate oxides and highly scaled MOSdevices. We have demonstrated high performance RFLDMOS transistors integrated into an advanced in-dustrial 0.25 µm BiCMOS process with only one ad-ditional mask level. These devices have minimum 0.25 µmphysical gate lengths, use the 5 nm standard gateoxide of the logic transistors, and show fT and fmaxvalues of up to 30 and 50 GHz, respectively. Thebreakdown voltages are between 26 V and 13 V, depen-ding on layout. The power-added efficiency (PAE) is70 % at 560 mW / 2 GHz and 340 mW / 5 GHz [2].

Fig. 24 a: LDMOS fT and fmax vs. drain current at a drain voltageof 20V.

Fig. 24b: Output power, Gain, and Power-add efficiency (PAE) vs.input power for a VBR =15 V, 739 µm wide LDMOS device at 5 GHzand VDS=4.5 V .

HBTs beyond the Johnson Limit

Fig. 25: Collector-emitter breakdown voltage BVCEO vs. peak fT forthe high performance and high voltage HBTs.

RF applications often need transistors with low inter-modulation distortion. High voltage (HV) transistorswith low base-collector capacitance and reducedavalanche multiplication can fulfill this requirement.Realizing large BVCEO x fT values is particularly diffi-cult for high breakdown voltage devices due to non-equilibrium transport effects. Using the same processflow as for the high performance HBTs, we have ob-tained, on the same chip, high voltage HBTs withBVCEO values between 4 V and 9 V, and BVCEO x f T

products above 220 VGHz with typical current gains of120-150 [3]. Table 5 shows the breakdown voltageand the corresponding fT, fmax values. Fig. 25demonstrates the figure of merit exceeding thetheoretical frequency and power limit described byJohnson in 1965.

41

Collector Well Doping Unit NPN NPN NPN NPN NPNversion 1 version 2 version 3 version 4 version 5

Emitter Area µm² 10x(0.42x0.84) 32x(0.42x1.68)BVCEO @ 10µA/µm2 V 2.5 2.6 3.0 4.0 5.1 7.6 9.1peak fT @ VCE = 2V GHz 103 101 74 56 49 32 26peak fmax @ VCE = 2V GHz 130 130 110 105 110 81 59

Table 5: RF parameters and collector-emitter breakdown voltages for high performance and high voltage HBTs with high and low collectorwell dopings.

Isolated PNP module

A high performance PNP would have advantages overcurrent best-in-class PMOS devices for driving a newgeneration of laser diodes. Specifically in the commu-nications area, an RF PNP provides a circuit per-formance achieved only with a PMOS with twice thefT of an PNP device. In addition, one can achieve asignificantly higher breakdown voltage.We have demonstrated fT/fmax of 20/14 GHz at a break-down voltage of BVCEO ~ 5 V. This results in a BVCEO*fT

product of 100 GHzV, which is among the best pub-lished values for complementary bipolar-only pro-cesses maintaining the original NPN HBT and CMOSdevice characteristics, a must for true modular PNPintegration.

Fig. 26 a: fT and fmax vs collector current for the isolated PNPdevice.

Fig. 26 b: Gummel plot for the PNP device.

42

Parameter Value Units Remarks

Substrate 50 Ωcm p- substrateMetal layers 4 Thick top metalSupply voltage 2.5 VThreshold voltage n:0.6; p:0.55 V @VDS= 0.05 VEffective channel length 0.23 µm LDRAWN = 0.28 µmGate oxide thickness 5.0 nm physical thicknessSRAM cell size 3.6 x 4.3 µm² 6 transistor cellMIM capacitor 1.0 fF/µm²Resistors 100, 130, 350 Ohm/[] unsalicided n+, p+, base polyInductor quality factors 15@2 nH, 5.8 GHz

5@15 nH, 2.4 GHzHV - NPN fT >50 GHz @VCE=2.0 VHV - NPN fmax >90 GHz @VCE=2.0 VHV - BVCEO >3.0 VHV - Early voltage VA >50 V @IB~5 nA, VCE~1.2 VHP - NPN fT >80 GHz @VCE=1.0 VHP - NPN fmax >95 GHz @VCE=1.0 VHP - BVCEO >2.4 GHz

Table 6: Main parameters of the 0.25 µm SiGe:C BiCMOS technology. Process features: CoSi, AlCu, W & oxide CMP, deep n-well(insulated nmos).

4) Design kit

A flow for full digital and analog designs based onSynopsis/Cadence design environment is supportedfor the 0.25 µm SiGe:C BiCMOS technology. The de-sign kit was improved and extended throughout theyear.

3) 0.25 µm SiGe:C BiCMOS platform

The 0.25 µm SiGe:C BiCMOS platform was frozen inthe first quarter of 2001 and qualified to industrystandards. This is essential for technology deve-lopment. Table 6 shows a summary of the key para-meters. The technology is open to designers via aregularly shuttle service.

43

Fig. 27: Tools and design flows supported for the 0.25 µm SiGe:C BiCMOS process.

[1] D. Knoll et al. HBT before CMOS, a New ModularSiGe BiCMOS Integration SchemeTo be published in IEDM Tech. Dig. 2001.[2] K.E. Ehwald et al. High Performance RF LDMOSTransistors with 5 nm Gate Oxide in a 0.25 µm SiGe:CBiCMOS Technology. To be published in IEDM Tech.Dig. 2001.[3] B. Heinemann et al. Cost-Effective High-Perfor-mance High-Voltage SiGe:C HBTs with 100 GHz fT andBVCEO x fT Products Exceeding 220 VGHz. To be pub-lished in IEDM Tech. Dig. 2001.

44

HTOL (125°C, 2.5 V core/ 4.0 V io);Acc./Rej. per lot: 1/2—————————————————————wafer lot 168 504 1008 fail

(hours)—————————————————————IHPPA21 0/68 1/68 0/67 Lkg @ 504IHPPA23 0/55 0/55 1/55 Lkg @ 1008IHPPA24 0/71 0/71 1/71 Lkg @ 1008IHPPA25 0/71 0/71 0/71IHPPA27 1/87 0/86 0/86 Funct @ 168

5) Reliability & diagnostics

Technology qualificationGoal

Qualify advanced process technologies according tointernational norms.

Motivation

Qualification demonstrates the reliability of a techno-logy according to international industrial standards.This is essential for value-creation. Unqualified tech-nologies are of little value.

Results

0.25 µm CMOS

A series of device stress tests including HTOL (hightemperature operation life time), EFRS (early failurerate study), static bake, autoclave, AATC (air to airtempe-rature cycling), and THB (temperature hu-midity bias) were carried out on five different pre-paration lots. Additional intrinsic stress tests cha-racterized the general behavior of EM (electromi-gration), SM (stress migration), TDDB (time depen-dent dielectric break-down) and HCI (hot carrierinjection). The results of the device stress tests aresummarized below.

The Certificate of Qualification was received in April2001 (Fig. 28).

Fig. 28: Certificate of Qualification for the IHP 0.25µm CMOSprocess.

Static Bake (150°C); Acc./Rej.: 1/2—————————————————————wafer lot 504 1008 (hours)—————————————————————IHPPA24 0/100 0/100

AUTOCLAVE (121°C, 100% RH, 15psig); Acc./Rej: 1/2—————————————————————wafer lot MSL3 96 144 288 (hours) fail—————————————————————IHPPA24 0/65 0/65 0/65 1/65 Lkg @ 288

AATC (-65°C to 150°C) ; Acc./Rej: 1/2—————————————————————wafer lot MSL3 500 1000 2000 (cycles)—————————————————————IHPPA24 0/115 0/115 0/115 0/113

THB (85°C, 85 %RH, Vdd) ; Acc./Rej: 1/2—————————————————————wafer lot MSL3 504 1008 2016 (hours)—————————————————————multiple 0/132 0/132 0/132 -/—-

Lkg - leakage fortFunct - functional face

45

0.25 µm BiCMOS technology

A special bipolar qualification chip including tran-sistor arrays of different size (4, 256, and 4k tran-sistors) and ring oscillators (503 and 103 stages) wasused to prove the reliability of the SiGe:C BiCMOSunder static and dynamic stress. Single transistorswere also tested.

All qualification activities were organized by the IHPin collaboration with different partners. This includedthe test methodology (IHP), chip assembling (MAF,Frankfurt (Oder)), stress board design and manufac-turing (Melexis, Erfurt), stress tests (MegaXess, Frank-furt (Oder)), and intrinsic reliability tests (SERMATestlab, Grenoble).

Single transistors and transistor arrays were characte-rized by Gummel plot measurements at VBE = 0.1 –0.8 V and VCB = 1 V at constant temperature.As an example, Fig. 29 shows the behavior of col-lector (IC) and base current (IB) of five single tran-sistors (including the worst cases out of 32) afterforward stress with 4 mA/µm² at 175°C. Only twodevices show a significant increase of IB.

The device stress tests were carried out under thefollowing conditions:

HTOL: T=135°C effective junction temperature;emitter current (IE) = 2 mA/µm2 for each transistorin the 4 and 256 transistor arrays and 10 µA/µm2 inthe 4k array, respectively, ring oscillators in perma-nent operation;Static bake: T=150°C;AATC: T= -65°C, 150°C; 15 minutes each;Pressure cooker: T=121°C, 2 bar, 100 % R.H.

The test results for the transistor arrays are as follows.

- HTOL test passed with 1/238 fails after 1000 hours.- Static bake test passed with 0/77 fails after 1000

hours.- AATC test passed with 0/77 fails after 500 cycles.- Pressure cooker test passed with 1/66 fails after

240 hours.

The ring oscillator frequency was measured at IEE =170 mA at room temperature with a temperaturestability of ±1 K. Fig. 30 shows as an example thestability of the average frequency of 103-stage ringoscillators on five wafers, each with 48 devices underHTOL stress conditions.No significant drift of the average ring oscillatorfrequency, no total fails (no oscillation), and nofrequency change of an individual device by morethan ±5 % was observed.

Fig. 29: IB and IC @ VBE = 0.55 V vs. stress time for five singletransistors (including the worst cases out of 32 devices) afterforward stress test at 175°C with 4 mA/µm2 measured at roomtemperature. (The initial state (t = 0) was marked at t = 0.05hours.).

Fig. 30: Average frequency of 5 x 48 ring oscillators vs. stresstime of HTOL test.

46

Failure Mode Analysis (FMA)

Goals

a) Process and yield optimization.b) Construction analysis for a 0.25 µm BiCMOS tech-nology as necessary for detection of possible processdeviations, and as a required document for processqualification.c) Support qualification by characterization of failedmodules.d) Optimize ToF-SIMS for contamination analysis.

Motivation

FMA is an essential tool for advanced technologydevelopment and qualification.

Results

New reference samples were developed for ToF-SIMSanalysis of process induced contamination, based onthe following approach.Craters with well-defined depths and flat bottoms areetched into reference samples with known implan-tation profiles. The surface of the sputter crater hasan exactly known impurity concentration suited forcalibration measurements. The sensitivity of the ToF-SIMS measurements fits the ITRS roadmap for up-coming technology generations. Fig. 31 shows themeasured and quantified alkali concentrations forcalibration of process-induced alkali contamination.Measurements of alkali contamination in qualificationlots show values for Na, K, Li far below the criticallimits (1013 cm –2).

Fig. 31: Quantification of alkali surface contamination based onnew reference samples. The detection limit and the ITRS roadmaprequirements are indicated.

A detailed construction analysis was performed forthe 0.25 µm BiCMOS technology. The results are usedas a reference document for FMA to detect deviationsfrom frozen geometries and technology parameters. Itprovides a platform for reverse engineering, andallows fine tuning of the technology. An example forprocess characterization is shown below.Fig. 32 is a TEM analysis of SiGe:C HBT stuctures inthe 0.25 µm BiCMOS technology. Fig. 32a is an over-view of the base, emitter, and collector contacts(from left to right). Fig. 32b shows the result ofinterface optimization of the emitter layer. A partiallyepitaxial Si emitter below the contact is realized withimproved performance compared with pure poly-crystalline Si emitter layers. The interface and thestructure of this layer need to be carefully controlled.

Fig. 32: Cross-sectional TEM micrograph of SiGe:C bipolar transistor contacts; (a) overview of base, emitter, and collector contact;(b) detail of the emitter contact.

(b)

(a)

47

Fig. 33: TEM micrographs of a part of a pnp bipolar transistor from 0.25 µm BiCMOS technology. (a) Conventional bright field image in the(110) pole. p-n junctions are not visible. (b) Phase image reconstructed from hologram taken in the same region. The contrast changesindicate the p+ n p stack.

TEM Holography

Goals

Establish holography as a routine diagnostic tool atthe IHP.Push capability of 2D potential measurements to thephysical limits.

Motivation

ULSI critically relies on dopant control on the nmscale. ITRS roadmap calls for 2D dopant profilingtechniques with high spatial resolution.

Electron holography can reveal dopant distributionsin 2D, with ~ 10 nm spatial resolution. However, itneeds to be established as a routine analytical tool.

Results

We have successfully applied electron holography asfollows.- First mapping of lateral broadening of steep boron

profiles in Si/SiGe/Si heterostructures [1].- Investigation of devices from 0.25 µm BiCMOS

technology.

Substantial methodological progress was achievedregarding:- Deconvolution of effects in holograms caused by

specimen tilt [2];- Targeted specimen preparation;- Upgrading the CM 300 microscope with a Lorentz

lens.

References[1] P. Schwander et al., Final report of a projectsupported by the Volkswagen-Stiftung, June 2001,Part: Mapping local composition and electrostaticpotential in semiconductors.[2] P. Formanek et al., Report at Herculas projectmeeting held in Grenoble, October 2001.

48

Breakthrough Department —an Incubator for Ideas

The Breakthrough Department was established in1999 to stimulate long-term innovation. The depart-ment is multidisciplinary, spanning all the institute’score competencies: materials, process technology,circuits, and systems. It houses high-risk/high-rewardprojects, sometimes addressing “white spaces” in ourportfolio. The Breakthrough Department serves as anincubator for ideas and projects that:- Have “breakthrough” character- Have the potential to add high value- Identify new directions- Bring high reward at high riskAny member of staff with innovative and high riskideas can work in this department, initially for twoyears. Successful Breakthrough projects are expectedto mature into standard projects, or start-ups withina limited (initially two-year) time window.

Current project portfolio:- High-K dielectrics- Indoor positioning system- TEM holography- 130nm HBT integration- Reduction of mechanical stress- Isolated pnp module- Multicrystalline silicon for solar cells- 300 mm silicon

Results

The Department has succeeded in stimulating threebreakthrough projects within the Department, threein other departments, and has filed four patents.

Fig. 34: Pseudopotential calculations in Local DensityApproximation (LDA) for the band structure of Pr2O3. Note thenarrow sub-band forming the conduction band bottom. Electronsin this f-type sub-band have large masses.

High-K Dielectrics

Goals

Develop and evaluate a promising-gate insulator forfuture CMOS transistors below 100 nm channel lengthwith the following characteristics:

- Dielectric constant between 15 and 40- High thermal stability- Electrical parameters (leakage, breakdown, etc.) as

defined in the latest roadmap for 70 nm CMOS- Reliability as required by CMOS demands

Motivation

Advanced CMOS devices require gate oxide-equivalent-thicknesses below 2 nm (tox-eq < 2 nm) for MOSFETchannel length of 70 nm and below. Since direct tun-neling increases exponentially with decreasing oxidethickness, this necessitates introduction of alterna-tive insulator with dielectric constant > SiO2.

49

Results

We have shown that crystalline praseodymium oxidefilms can be grown on silicon (001). They have pro-mising dielectric properties. Our primary results canbe summarized as follows.

- Thin Pr2O3 films have an effective dielectric constantKeff ~ 30, independent of the substrate doping type.

- Films with Equivalent Oxide Thickness EOT of1.4 nm have leakage current densities below10-8 A/cm² at Vg = ± 1.0 V. This is significantly lowerthan the best published values for other metaloxides films with the same EOT.

- The ultra-low leakage current is due to localized andflat f states in the conduction band leading toheavy electron masses in the oxide.

- Pr2O3 exhibits ∆Eg ~ 3.5 eV with nearly symmetricband offsets with respect to Si.

- Negative fixed charges lead to VFB ~ + 250 mV.- Pr2O3 films show excellent J-V characteristics, even

after stress-induced electrical breakdown.- Praseodymium oxide layers survive CMOS anneals.- They are unstable in contact with air.

Oxygen indiffusion leads to interfacial SiOx layerformation.

- The intrinsic dielectric constant of Pr2O3 is largerthan 40.

- On Si(001) oriented surfaces, crystalline Pr2O3

grows as (110).

Fig. 35: Scanning tunneling spectroscopy data on Pr2O3

submonolayer coverage. Shown is the normalized differentialconductivity versus the applied voltage integrated over an area of20 nm x 20 nm. Note that the value of the measured surface-state bandgap agrees with theoretical predictions.

Fig. 36: (a) Empty state STM images of the clean reconstructed Si(001) (2 x 1) surface. After praseodymium oxide deposition at 6000C:(b) 15 nA flux for 1 min, (c) 15 nA flux for 3 min.

50

Reduction of Mechanical Stress in theIHP BiCMOS Process

Goals

Identify the primary sources for stress generation inthe BiCMOS process flow. Determine process con-ditions, which prevent plastic deformation in IC fabri-cation, and find out stress related restrictions fordesign rules.

Motivation

Process induced mechanical stress can lead to devicedegradation. Further scaling of device dimensionsbrings strongly stressed regions near stress sensitivedevice areas. Mechanical stress may affect conduc-tivity, leakage currents, and dopant diffusion. Shallowtrench isolation is one source of major stress. Un-derstanding the mechanisms for stress generationhelps optimize process parameters.Measuring stress in submicron device structures is achallenge. UV micro-Raman spectroscopy was demons-trated as a valuable non-destructive method with thepotential for fast measurements and sufficient spatialresolution also in submicron IC technologies.

Results

Two different trench fill processes were characterisedby UV micro-Ramanspectroscopy combined with stressfield simulations in sub-0.25 µm transistors. Themeasured stress maxima differ by factor of nearly twofor different filling and densification processes.

Stress during BiCMOS process flow was measured onwafers after selected processes. The major sources ofstress are: (1) the nitride layer; (2) liner oxide; (3)trench fill; and (4) gate module (Fig. 37).Most sources of stress were removed during chemical-mechanical polishing (CMP). Stress in the IHP BiCMOSprocess is non-critical for dislocation generation.Stress from the trench-fill survives CMP, and increasesduring further processing.

The influence of different trench-corner radii on stresswas simulated with finite element methods. Top andbottom corner radii are well chosen in the IHP pro-cess.

The stress field below the gate was simulated usingthe process simulator DIOS in combination with thestress solver. This shows a nearly stress-free channelbelow the gate.

UV micro-Raman spectroscopy was improved to deter-mine stress values from volume elements of 200 nmdiameter and 12 nm depth, despite the geometricalresolution of 690 nm, as follows. Spectra from sub-micron CMOS device structures were measured in thefocus of the microscope. Broadened, not Lorentz-likeRaman lines were subsequently deconvoluted. Thespectral components could be ascribed to an inhomo-geneous strain field in the focus area (Fig. 38). Theintensity is proportional to the fraction of the scat-tering volume experiencing that strain. This methoddetects strongly stressed regions of opposite sign insubmicron areas, previously undetected in visiblelight measurements due to averaging.

51

Fig. 37: Formation of stress in active areas for the IHP BiCMOS process flow. Cross-sections through active areas are simulated using theDIOS simulator for different process steps (left panels). Stress values in active areas belonging to the same process steps are derived fromUV micro-Raman measurements (right panel).

Fig. 38: Deconvoluted UV micro-Raman spectrum reveals detailsof the stress field in the active area surrounded by an etched andoxidised trench. A transmission electron micrograph of the activearea and the simulated stress field are shown on top. Thediagram shows the measured (black) and deconvoluted (red) UVmicro-Raman spectra. The shifted maxima originate from tensileand compressive stressed regions smaller than the focused opticalprobe.

TEM micrograph FEM calculated

-0.5 GPa 1.1 GPa100 nm

52

Collaborators & Partners

53

Collaborators & Partners

Industry

Abakus Software GmbH, Germany

ABB-Lenzburg, Switzerland

advICo microelectronics GmbH, Germany

Alcatel SEL AG, Germany

Alpha Microelectronics, Germany

Altera Corp., USA

AMD, Germany

ASM, USA

Austriamicrosystems AG, Austria

Avanti Corp., USA

Cadence Design Systems Inc., USA

Catena Software GmbH, Germany

Centellax, USA

CISCO Systems, UK

Crystal Growing Systems GmbH, Germany

DaimlerChrysler Research Center, Germany

DCA Instruments, Finland

Deutsche Solar GmbH, Germany

Gärtner Electronic Design GmbH, Germany

Infineon Technologies Dresden & Munich, Germany

Intel Corporation, USA

lesswire AG, Germany

Matra Bae Dynamics Ltd., UK

MegaXess GmbH, Germany

MergeOptics, Germany

MEODAT GmbH, Germany

Motorola Limited, UK

Motorola S.A., France

Motorola SPS, USA

Philips Communication Systems B.V, The Netherlands

Plasma Analysis Systems, Germany

Quantum Semiconductor, USA

RWE Solar, Germany

Semiconductor 300, Germany

Sentech Instruments, Germany

Siemens & Shell Solar GmbH, Germany

Silicon Sensor, Germany

Silicon Wave Inc., USA

Spinnaker Systems, Japan

STMicroelectronics, France

Stratalight, USA

Sun Microsystems Inc., USA

Synopsis GmbH, Germany

Systemonic, Germany

Telecom Italia Lab, Italy

Wacker Siltronic AG, Germany

X-FAB, Germany

54

Research Institutes & Universities

ACCESS, Aachen, Germany

Belarussian State University, Minsk, Belarus

Charles University, Prague, Czechoslovakia

Dresden University of Technology, Germany

Eindhoven University of Technology, Netherlands

European Synchrotron Radiation Facility, Grenoble,France

Fraunhofer Institute for Integrated Circuits, Erlangen,Germany

Fraunhofer Institute for Reliability andMicrointegration, Berlin, Germany

Fraunhofer Institute for Silicon Technology, Itzehoe,Germany

Fraunhofer Institute for Solar Energy Systems,Freiburg, Germany

Humboldt University, Berlin, Germany

IMEC, Belgium

Indian Institute of Technology, Kanpur, India

Institut National Polytechnique de Grenoble, France

Institute for Automation and Control Processes,Vladivostok, Russia

Institute for Microelectronic and MechatronicSystems, Ilmenau, Germany

Institute for Semiconductor Physics, Kiev, Ukraine

Institute for Solar Energy Research, Emmerthal,Germany

Institute for Solid State and Materials ResearchDresden, Germany

Laboratoire d’Electronique, de Technologie del’Information (CEA-Leti), Grenoble, Switzerland

Loughborough University, UK

Max Planck Institute for Microstructure Physics,Halle, Germany

Monash University, Clayton, Australia

National Microelectronics Research Center, Cork,Ireland

National Technical University of the Ukraine, Kiev,Ukraine

Paul Drude Institute for Solid State ElectronicsBerlin, Germany

Philips Research Laboratories Aachen, Germany

Polytechnics Institute, Kiev, Ukraine

Ruhr University, Bochum, Germany

South Bank University, London, UK

Stanislaw Staszic University of Mining and Metallurgy,Cracow, Poland

Swiss Center for Electronics and Microtechnology,Switzerland

Taras Shevchenko National University of Kiev,Ukraine

Technical University Bergakademie, Freiberg, Germany

55

Technical University of Berlin, Germany

Technical University of Brandenburg, Cottbus, Germany

Technical University of Catalonia, Spain

Technical University of Darmstadt, Germany

Technical University of Denmark, Lyngby, Denmark

Technical University of Hamburg-Harburg, Germany

Technical University of Ilmenau, Germany

Technical University of Kharkov, Ukraine

Technical University of St. Petersburg, Russia

Technical University of Szczecin, Poland

Technical University of Vienna, Austria

Technion, Institute for Technology, Israel

Tohoku University, Sendai, Japan

Università degli Studi di Udine, Italia

University Ivanovo, Russia

University of Arts Berlin, Germany

University of Barcelona, Spain

University of Bremen, Germany

University of California-Los Angeles, USA

University of Catania, Italy

University of Erlangen-Nürnberg, Germany

University of Göttingen, Germany

University of Greifswald, Germany

University of Illinois, Chicago, USA

University of Kassel, Germany

University of Kiel, Germany

University of Konstanz, Germany

University of Linz, Austria

University of Manchester, UK

University of Minsk, Belarus

University of Newcastle, Australia

University of South Florida, Tampa, USA

University of Southampton, UK

University of Stuttgart, Germany

University of Ulm, Germany

University of Vladivostok, Russia

56

Selected Visitors

57

Selected Visitors

1. Industrial Visitors

AMI

ASM

Cadence Design Systems GmbH

Centellax

Chengdu Fortune Science & Technology

Crystal Growing Systems

Fujitsu

InChip Communications

Intel

MergeOptics

MiMOS

Mitsubishi

Motorola

National Semiconductor

O2Micro

Optillion

Philips

Quantum Semiconductor

RFWaves

Siemens

SiGe-Microelectronics

Sony

Stratalight

X-FAB

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2. Visitors

Sep. 13, 2000 Participants of the School for Crystal Growth

Sep. 14, 2000 Technical Tour ”Electronics Goes Green 2000+ Congress”

Oct. 10, 2000 Dr. Andreas Trunschke, Spokesman for Research Affairs, Parliamentary Group of Party of Democratic Socialism in the State Parliament of Brandenburg

Oct. 24, 2000 Johannes Rau, President of the Federal Republic of Germany Prof. Johanna Wanka, Minister for Science, Research and Culture of the State of Brandenburg, Prof. Gesine Schwan, President Europe University Viadrina, Mayor Wolfgang Pohl, and Delegation

Nov. 30, 2000 School Headmasters’ Group, Frankfurt (Oder)

Nov. 30, 2000 Dresden University of Technology Group

Dez. 7, 2000 Technical University of Berlin Group

Dez. 8, 2000 Prof. Brito, Undersecretary of State for Science, Venezuela Mr. Becker Becker, Ambassador of Venezuela

Jan. 29, 2001 H.H. Sheikh Mohammed bin Rashid alMaktoum, Crown Prince of DubaiH.E. Khalifa Ahmed Sulaiman,Director, The Ruler’s Court, DubaiDr. Mohammmed A Al Zarouni,Director General, Dubai Airport FreeZone AuthorityDr. Wolfgang Fürniß, Minister forEconomic Affairs of the State ofBrandenburg

Feb. 07, 2001 Michael R. Splinter,Senior Vice President, IntelGidu K. Shroff,Vice President, IntelHarish Utamsing,Director, Strategic Investments, Intel

Feb. 13, 2001 Dominic Schroeder, First Secretary andHead of Commercial Section,British Embassy BerlinHermann von Richthofen, State ofBrandenburg, and Delegation

Feb. 22, 2001 T.C. Yang, Taiwan Embassy BerlinLeonardo G. Noto, Director ZAB,Germany

Mar. 01, 2001 ”Tours d‘ Innovation“ 11Th gradeStudents from the OSZ Eisenhütten-stadt

Mar. 09, 2001 Urania e.V. Group

Mar. 13, 2001 Prof. Lothar Bisky, Chairman of theDemocratic Socialist Party in theState of Brandenburg, and the PDSParliamentary Group

Mar. 19, 2001 10Th grade Students from the2. Realschule, Frankfurt (Oder)

Mar. 29, 2001 7Th grade Students from the2. Realschule, Frankfurt (Oder)

Apr. 04, 2001 Brandenburg Technical UniversityGroup

Apr. 06, 2001 11Th grade Students from theWaldorfschule, Frankfurt (Oder)

Apr. 09, 2001 ”Tours d‘ Innovation“ 11Th gradeStudents from the Carl Friedrich GaußGymnasium, Frankfurt (Oder)

Apr. 20, 2001 Michael Ronis, Director Science andTechnology, French Embassy, Berlin

May 08, 2001 Dr. Liang-Han Hsieg, DirectorIndustrial Technology ResearchInstitute, Western EuropeOffice, Taiwan, and Delegation

May 08, 2001 Dr. Köhler, Director Deutsche Bank,Microtechnology Innovation Team

May 16, 2001 10Th grade Student from the OttoBrenner Gymnasium, Frankfurt (Oder)

May 23, 2001 Committee of European Region”Pro Europe Viadrina“

59

May 25, 2001 Dr. Christoph Helm, Undersecretary forScience, Research and Culture of theState of Brandenburg

May 31, 2001 Industry and Commerce Group fromthe City of Frankfurt (Oder)

Jun. 07, 2001 Participants of the ”Physics Olympics“from the State of Brandenburg

Jun. 12, 2001 Students from a science-technical courseat the 2. Realschule, Frankfurt (Oder)

Jun. 15, 2001 Seminar for Social Education from theWichern GmbH, Frankfurt (Oder)

Jun. 19, 2001 7Th grade students from the Otto Brenner Gymnasium, Frankfurt (Oder)

Jun. 19, 2001 Brandenburg Technical University Group

Jun. 21, 2001 Quality Group for IT Education, Frankfurt (Oder)

Jul. 11, 2001 Students of physics course at the OSZ School, Frankfurt (Oder)

Jul, 14, 2001 OPEN DAY with 600 Visitors

Jul, 17, 2001 8Th grade students from the 1. Gesamtschule, Frankfurt (Oder)

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Guest Scientists

61

Guest Scientists

Guest Institution Activity

13 Mr. S. Chernjavsky University of Ivanovo, Russia Materials & Diagnostics12 Mr. A. Cuadras University of Barcelona, Spain Process Technology11 Dr. S. Danilov Technical University of Materials & Diagnostics

St. Petersburg, Russia10 Dr. L. Houven Forschungszentrum Jülich, Materials & Diagnostics

Germany9 Prof. A. Kühhorn Brandenburg Technical Materials & Diagnostics

University, Cottbus, Germany8 Dr. V. Melnik Institute for Semiconductor Process Technology

Physics, Kiev, Ukraine7 Prof. J. Murota Tohoku University Sendai, Japan Process Technology6 Prof. B. Romanjuk Institute for Semiconductor Process Technology

Physics, Kiev, Ukraine5 Dr. I. Shevchenko Institute for Semiconductor Circuits

Physics, Kiev, Ukraine4 Dr. Z. Stamenkovic University of Nis, Jugoslavia Systems3 Prof. V. Stikanov National Technical University Circuits

of the Ukraine, Kiev, Ukraine2 Dr. W. Troutmann Bell Labs, USA Process Technology1 Dr. Y. Yamamoto Tohoku University Sendai, Process Technology

Japan

62

Seminars and Colloquia

63

Seminars and Colloquiaby External Speakers

Presenter Institution Topic

17 Mr. V. D. Akhmetov Russian Academy of Sciences, ”Infrared Tomography of the Charge CarrierInstitute of Semiconductor Lifetime and Diffusion Length in SiliconPhysics Novosibirsk, Russia Ingots“

16 Mr. S. Cristoloveanu Lab. de Physique des Composants ”Silicon-On-Insulator Materialsà Semiconducteurs, Grenoble, and Devices: Past, Present and Future“France

15 Prof. M. Daehne Technical University of Berlin, ”Spectroscopy and Microscopy ofGermany Semiconductor Interfaces“

14 Mr. V. Darbroodi Eindhoven University of ”Designing a Communication HardwareTechnology, Netherland Architecture based on TCP/IP Protocol

Suite“

13 Mr. T. Herfet Grundig AG, Fürth, Germany ”High Performance LAN Type 2(HiperLAN2) Baseband SignalProcessing Architecture“

12 Dr. L. Jackel AT&T Research, New Jersey, USA “Integrated Network CommunicationsServices”

11 Dr. J. Jackel Telcordia Technologies, “The MONET DC Network:New Jersey, USA What did we do and what have we learned”

10 Prof. J. Kaiser University of Ulm, Germany ”Towards a CommunicationArchitecture for Large Scale Systems“

9 Mr. A. Kanbach Elmeg Kommunikationstechnik ”Routing Aspects in DECT Networks andGmbH & Co. KG, Peine, Germany Wireless Internet Access“

8 Mr. H. Karstensen Infineon Technologies Munich, ”Broadband Communication Trends“Germany

7 Prof. H. Klar Technical University of Berlin, ”HF-CMOS für die drahtlose Kommunika-Germany tion“

64

Presenter Institution Topic

6 Mr. A. Korbel Ruhr University Bochum, “Modeling of Short Channel MOSFETsGermany for the Design of fast CMOS Circuits

using SPICE”

5 Prof. P. Mähönen University of Oulu, Finland ”Wireless Internet Applications &Technologies“

4 Dr. P. Möck University of Illinois, Chicago ”Materials Science Issues and StructuralUSA Studies of Certain Compound

Semiconductors with Technical Importance“

3 Mr. S. Ostapenko University of South Florida, ”Defect Diagnostics in MulticrystallineTampa, USA Si Using Scanning Techniques: With Special

Regard to Photoluminescence“

2 Prof. V. Senez University des Sciences et “Modeling and Simulation of MechanicalMr. T. Hoffmann Technologies de Lille, France Stresses Induced in Advanced Silicon

Technologies”

1 Mr. K. Wefelmeyer DFG Bonn, Germany “Tips for Applying for DFG Projects”

65

66

IHP/BTU Joint Lab

67

IHP/BTU Joint Lab Courses

The following courses of lectures and seminars weregiven by IHP personnel at the BTU in 2001:- Distributed Systems (Prof. R. Kraemer)- RF Circuit Design (Prof. P. Weger)- Semiconductor Materials and Technology

(Dr. H. Richter, Dr. M. Kittler)- Solid State Physics (Dr. H. Rücker)- Practical Courses for Graduate Students

(Prof. A. Ourmazd)

In December 1998, a wide-ranging cooperation agree-ment was signed with the Technical University ofBrandenburg, Cottbus (BTU).

The primary objectives of this cooperation are topromote and enhance the efficiency of research andeducation in the State of Brandenburg, and stimulatestudent interest in the IHP.

In 2000, a Joint Laboratory (IHP/BTU Joint Lab) wasestablished on the BTU campus in Cottbus with thefollowing goals:- Establish strategic partnership with BTU in research;- Promote interdisciplinarity;- Nurture solution-focused research projects.

The research activities involve joint IHP/BTU teamsin the following areas:- Semiconductor materials and characterization;- Gate insulators;- Finite element methods.

The following BTU chairs are involved.Faculty 1:- Experimental Physics/Materials Science- Experimental Physics/Semiconductor Physics- Theoretical Physics- Systems

Faculty 2:- Microelectronics- Structural Mechanics and Vehicle Vibrations

Projects

Projects financed by outside sources (total income770 TDM) in 2001:BMWi:- “Low cost crystalline silicon wafers and foils for

solar cells”

State of Brandenburg:- “Establishing an IHP/BTU center of competency in

semiconductor materials science in Cottbus”- “Laser cleaning of semicondutor substrates”

Wacker Siltronic AG:- “Material characterization and application oriented

investigations on 200/300 mm ∅ wafers”,

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Conferences organized with contributions fromIHP Joint Lab staff:

(i) 9th International Autumn Meeting GADEST 2001“Gettering and Defect Engineering in SemiconductorTechnology”, Catania, Italy, October 2001Conference chairman: Dr. V. Rainieri (CNR-IMETEM)Conference Co-chairman: Dr. H. Richter (IHP)Programm-chairman: Prof. F. Priolo (University ofCatania)Programm Co-chairman: Dr. M. Kittler (IHP)

Results:GADEST 2001 took place September 30 to October 04,2001, in Catania, Italy. 195 participants from 23countries and 100 institutions (20 % from industry),128 contributions (56 oral and 73 poster presen-tations). The conference proceedings are published inSolid State Phenomena Vol. 82-84, 2001 (823 pages).

(ii)E-MRS Spring Meeting 2001, Symposium E“Crystalline Silicon for Solar Cells”, Srasbourg, June2001Symposium organizers:Dr. M. Kittler (IHP)Prof. S. Martinuzzi (University of Marseille)Dr. W. Koch (Bayer AG)Dr. T. Bruton (BP Solar)

Results:Symposium E took place June 6 - 8, 2001 in Stras-bourg, France. More than 80 participants from 20countries, 81 contributions (48 oral and 33 posterpresentations).The conference proceedings are published in SolarEnergy Materials & Solar Cells (Elsevier), Vol. 72(1-4) 2002 (628 pages).

Guest Scientists at the Joint Lab

Name Organisation

Dr. P. Möck University of Illinois,Chicago, USA

Mr. R. Schindler FhG ISE, FreiburgProf. J. Niklas TU Bergakademie, FreibergDr. K. Knobloch Infineon, DresdenDr. E. Zschech AMD, DresdenMr. N. Kraus Wacker Siltronic, FreibergDr. T. Müller Wacker Siltronic, BurghausenDr. A. Witek SENTECH, StockdorfMr. S. Ostapenko University South Florida,

Tampa, USA

Seminars and guest presentations:

P. Möck (University of Illinois, Chicago, USA)”Materials science issues and structural studies ofcertain compound semiconductors with technicalimportance”, Cottbus, May 14, 2001

V. D. Akhmetov (Russian Academy of Sciences, Insti-tute of Semiconductor Physics Novosibirsk)”Infrared tomography of the charge carrier lifetimeand diffusion length in silicon ingots”, Cottbus, July6,2001

S. Ostapenko (University of South Florida, Center ofMicroelectronics Research Tampa, USA)”Defect diagnostics in multicrystalline Si using scan-ning techniques: With Special Regard to Photolumi-nescence”, Cottbus, July 24, 2001

Company presentations:

SENTECH Gesellschaft für Sensortechnik mbH, Stock-dorf, Germany, Cottbus, May 15, 2001

69

70

Publications

71

Publications

Published Papers

75) Interaction of Vacancies with InterstitialOxygen in SiliconR.A. Casali , H. Rücker, M. MethfesselApplied Physics Letters 78(7), 913(2001)

Based on first-principle total-energy calculations, weshow that the majority of vacancies are trapped byinterstitial oxygen in silicon wafers with a typicaloxygen concentration of about 1018 cm-3. Vacanciesand interstitial oxygen form so called A centers witha binding energy of 1.7±0.4 eV. As a consequence, thedensity of bound vacancies exceeds the equilibriumdensity of free vacancies by several orders of mag-nitude and effective vacancy diffusion coefficients inSi are reduced in comparison to the diffusion coef-ficient of free vacancies. However, we find that trap-ping of vacancies alone cannot account for the largediscrepancies between previously reported diffusioncoefficients for vacancies.

74) Mechanism of Dopant Segregationto SiO2/Si(001) InterfacesJ. Dabrowski, H.-J. Müssig, R. Baierle,M.J. Cladas, V. ZavodinskyJournal of Vacuum Science B 18(4),2160 (2000)

Dopant atoms segregate to SiO2/Si(001) interfacesand are deactivated there. This can cause problems infabrication of submicron microelectronic devices. Onthe basis of ab initio calculations, we propose amechanism for donor segregation and deactivation.We argue that donor species (P and As) are trappedas threefold-coordinated atoms at interface defectsites (dangling bonds and Si vacancies) and, mostsignificantly, in form of dopant pairs at defect-freeinterfaces. This pairing will dominate when dopantconcentration exceeds approximately 1019 cm-3.

73) Pseudopotential Study of PrO2 and HfO2 inFluorite PhaseJ. Dabrowski, V. Zavodinsky, A. FleszarMicroelectronics Reliability 41(7), 1093(2001)

Praseodymium and hafnium oxides are prospectivecandidates to substitute SiO2 in decanano MOSFETtransistors. We report first ab initio pseudopotentialband structure calculations for these materials. We

find that fluorite phases of PrO2 and HfO2 have similarelectronic structures. The important difference is anarrow sub-band forming the conduction band bot-tom in PrO2 but absent in HfO2. Electrons in this f-type sub-band have large masses. This explains whyultrathin epitaxial Pr oxide films have low leakage inspite of a relatively small conduction band offset(1 eV) between the oxide and the Si substrate.

72) Investigation of Stress in Shallow TrenchIsolation using UV Micro-Raman-SpectroscopyK.F. Dombrowski, B. Dietrich, I. de Wolf, R.Rooyackers, G. BadenesMicroelectronics Reliability 41, 511 (2001)

We present an investigation of local mechanical stressin shallow trench isolation by UV micro-Raman spec-troscopy. UV light (364 nm) penetrates only 15 nminto silicon. In contrast to conventional micro-Ramanspectroscopy using visible light only the stress veryclose to the surface is monitored. In this way, localareas of high stress can be detected, that are notseen with longer wavelength light due to averaging.We demonstrate the advantages of the UV method byan investigation of the influence of different trenchoxide densification ambients on the amount of me-chanical stress in the silicon substrate, We find, thatlarge mechanical stress up to 800 MPa is introducedat the active area edges during densification in steamambient. This stress is caused by the formation andgrowth of a bird’s beak, which may lead to defectcreation especially in small trenches. This investi-gation demonstrates the capability to use UV micro-Raman spectroscopy in ULSI technology.

71) Upper Yield Point of Large DiameterSiliconA. Fischer, H. Richter, A. Shalynin, P.Krottenthaler, G. Obermeier, U. Lambert,R. WahlichMicroelectronic Engineering 56, 117(2001)

The temperature and shear strain rate dependence ofthe upper yield point of a few kinds of large diametersilicon crystals was studied. Crucial material attri-butes, such as doping level, initial oxygen content,and the state of oxygen aggregation after thermaltreatment, were taken into account. Overall experi-mental results show that the deformation behavior ofthe materials studied here is similar; there is nodifference observed between high and low boron-doped 200-mm-diameter and 300-mm-diameter sili-

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con crystals. Further, the right choice of sample orien-tation and shear strain rate used in experiments havebeen proved to be significant for the characterizationof mechanical strength of silicon wafers subjected toprocess load. Very low strain rates and forces lying incrystallographic (110) directions generate local re-gions of plastic flow caused by an extremely low yieldstress. The results allow the optimization of criticalhigh temperature processes used for materials tech-nology and device fabrication.

70) Out-diffusion and Precipitation of Copper inSilicon: An Electrostatical EffectC. Flink C, H. Feick, S.A. McHugo, W. Seifert,H. Hieslmair, T. Heiser, A.A. Istratov,E.R. WeberPhysical Review Letters 85, 4900 (2000)

Concentrations of mobile interstitial copper and pre-cipitated copper in silicon were studied after a hightemperature intentional contamination and quench toroom temperature. It was found that below a criticalcontamination the copper predominantly diffuses outto the surface, while for higher initial copper con-centrations it mainly precipitates in the bulk. Thecritical copper contamination equals the acceptorconcentration plus 1016 cm–3. This behavior can beexplained by the electrostatic interaction between thepositively charged interstitial copper and the formingcopper precipitates.

69) Band Offset Predictions for Strained GroupIV Alloys: Si1-x-yGexCy on Si(001) and Si1-xGexon Si1-zGez(001)S. Galdin, P. Dollfus, V. Aubry-Fortuna,P. Hesto, H.-J. OstenSemiconductor Science Technology 15, 565(2000)

The band offsets for strained Si1-x-yGexCy layers grownon Si(001) substrate and for strained Si1-xGex layersgrown on fully relaxed Si1-zGez virtual substrates areestimated. The hydrostatic strain, the uniaxial strainand the intrinsic chemical effect of Gex and C areconsidered separately. Unknown material parametersrelative to the latter effect are chosen to give thebest agreement with the available experimental re-sults for Si1-xGex and Si1-yCy layers on Si. As a generaltrend concerning carrier confinement opportunities,it is found that a compressive strain is required toobtain a sizeable valence band offset, while a tensilestrain is needed to obtain a conduction band dis-continuity. In most cases the strain is responsible fora bandgap narrowing with respect to that of the

substrate. The obtained results are in very good agree-ment with available experimental determinations ofband offsets and bandgap changes for ternary alloyson Si(001).

68) Raman Scattering in Strained Si1-xGex LayersUnder Hydrostatic Pressure.M. Gerling, B. DietrichSemiconductor Science and Technology16(7), 614 (2001)

The Si-Si Raman mode in Si1-xGex layers pseudomor-phically strained to Si and in bulk Si1-xGex was investi-gated as a function of externally applied hydrostaticpressure. The experiments demonstrate that bulkelastic properties can be derived from the pressure-dependent Raman investigations of thin strainedhetero-epitaxial layers. Our experimental results arefavourably analysed using linear interpolation for thecomponents of elastic stiffness tensor of the Si1-xGex

compounds. It was found that the pressure derivati-ve of strained Si1-xGex increases with the Ge concen-tration. Our analysis suggests that the Gruneisenparameter for strained Si1-xGex is higher than expectedfrom linear interpolation between the Si and the Gevalues and that it has slight negative pressure depen-dence.

67) A Current-Folded Up-Conversion Mixer anda VCO with Center-Tapped Inductor in aSiGe-HBT Technology for 5 GHz WirelessLAN ApplicationsG. Grau, U. Langmann, W. Winkler, D. Knoll,H.-J. Osten, K. PresselIEEE Journal of Solid State Circuits 35(9),1345 (2000)

This paper describes a 5.8-GHz up-conversion mixercore based on a current-folded architecture and a 5-GHz differential emitter-coupled voltage-controlledoscillator (VCO) utilizing a center-tapped inductorand a substrate shield. Both circuits are fabricated ina 0.8- µm 45-GHz fT SiGe heterojunction bipolartransistor (HBT) technology. The supply voltage rangeis between -2.3 V and -3.3 V to meet the require-ments of mobile circuits. Special care has been takenwith the inductor model. A distributed modelingapproach was used to generate an inductor modelfrom a geometrical description. This type of modelalso has the advantage that it can simulate RF effectsin both time and frequency domain.

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66) Comparative Analysis of Minority CarrierTransport in npn Bipolar Transistors with Si,Si1-xGex, and Si1-yCy Base LayersB. Heinemann, D. Knoll, G.G. Fischer, P. Schley,H.-J. OstenThin Solid Films 369(1-2), 347 (2000)

Here we present a comparative analysis of verticalminority carrier transport in Si, Si0.925Ge0.075,Si0.998C0.002, and Si0.99C0.01 base layers of bipolar tran-sistors. We show that a conventional transit timeanalysis for extracting the minority carrier mobilitiesfails for doping profiles containing a low doped emit-ter region. The contribution of locally compensatedcharge storage, called neutral charge storage, in theemitter-base depletion region must not be neglected.To overcome drawbacks of the simple transit timeanalysis, we use 2D device simulations to obtain animproved understanding of the measured high-fre-quency parameters. Taking into account the real do-ping profiles and device structures, and using a cali-brated parameter set for strained SiGe, the simulationresults for the Si, Si1-xGex, and Si1-yCy (y? 0.2 %) baselayer transistors reproduce very well the measuredtransit times (assuming the Si data for the electronmobility µ n) in the heteroepitaxial base layers. Inthe case of higher carbon concentration (y=1 %), theelectron mobility is reduced by a factor of two.

65) Integrated CMOS WidebandOscillator for RF ApplicationsF. Herzel, H.B. Erzgräber, P. WegerElectronics Letters 37(6), 330 (2001)

A fully integrated oscillator with a tuning range of800 MHz is presented. A combination of capacitiveand inductive tuning has been used to produce thelarge tuning range with a low-gain control input. Thephase noise at 1.9 GHz is as low as -120 dBc/Hz at500 kHz offset. Possible applications include integer-N PLLs with a low level of reference spurs.

64) Enhancement of Gettering Efficiencies ofDifferent Silicon Substrates During a 0.18µm LTB CMOS Process Simulation -Stratigraphy by a Novel Chemical Ultra-Trace Depth-ProfilingR. Hoelzl, L. Fabry, K.-J. Range, R. Wahlich,G. KissingerMicroelectronic Engineering 56, 153 (2001)

We have performed a gettering efficiency (GE) test atdifferent stages in a 0.18 µm LTB CMOS process simu-lation with maximum temperatures of 1000 0C. Four

sorts of wafer substrates (epi, polished) were pro-cessed to the point before the step to be studied andthen contaminated with 5x1012 atoms/cm2 Cu or Niwith a spin-on technique that was optimized forreproducibility. Afterwards, the wafers were processsimulated and analyzed by ICP-MS in combinationwith a novel chemical depth-profiling procedure.Although none of the wafers showed detectable BMDsby preferential etching and FTIR measurements, BMDscould be found by LST measurements. Epitaxial p/p+wafers exhibited an outstandingly high GE for Cu ateach studied process step due to segregation get-tering by the heavily boron doped substrate. Polishedwafers showed a lower GE which increased with theprocess time. Thus, Cu gettering was a function of thesize of oxygen precipitates. On the contrary, Ni get-tering was not enhanced in epi wafers compared tothe polished wafers. Also, no segregation gettering isassumed for Ni, however, a higher initial oxygenconcentration led to a higher GE. Thus, Ni getteringis strongly influenced by the oxygen precipitate size,too. A more stable Cu and Ni gettering was foundwith BMD-densities of 109 cm-3, measured by LST,although preferential etching and FTIR measurementswere below the detection limit.

63) Denuded Zone Evaluation in Rapid ThermalAnnealed WafersG. Kissinger, J. Vanhellemont, G. Obermeier,J. EsfandyariMaterials Science and Engineering B 73,106 (2000)

Oxygen outdiffusion by conventional annealing re-sults in well defined denuded zones and the dis-solution of grown-in oxide precipitate nuclei in theregion near the surface. During a rapid thermal anneal(RTA) the grown-in oxide precipitate nuclei shrink anddue to vacancy outdiffusion during cooling the sub-sequent growth of the precipitate nuclei is suppressedin the region near the surface. However, potentialdefects still exist in the region near the surface whichcan grow during ramping with 1 K min-1 starting from500 0C. A dissolution of grown-in oxide precipitatenuclei in the region near the surface seems onlypossible by RTA in argon/hydrogen atmosphere. Thedenuded zone defect density is much lower after RTAthan after conventional annealing for oxygen out-diffusion, while the depth profile of the defect den-sity is less steep. The use of the above mentionedconclusions for ‘ramp engineering’ in device pro-cessing allows the creation of excellent denudedzones during a device process itself without influ-encing the device characteristics.

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62) Electrical Behaviour of Crystal Defects inSilicon Solar CellsM. Kittler, W. Seifert, O. KrügerSolid State Phenomena 78-79, 39 (2001)

In this paper we report on the application of beaminjection techniques such as EBIC (Electron-Beam-Induced Current), SiPHER ® (Silicon-Photo-EmhancedRecombination) and Voltage Contrast to characterizecrystal defects in multicrystalline Si (mc-Si) for solarcells. Measurements of the EBIC defect contrast vs.Temperature, c(T), were used to assess the recom-bination properties of individual defects. The analysisof experimental data was based on a recently deve-loped model of Kveder et al.. Examples illustrating theaction of hydrogenation and phosphorus gettering onthe defect activity will be given. Phosphorus get-tering is found capable of reducing the contaminationlevel at dislocations by a factor of about 100. Hydro-genation was observed to passivate defects down toa depth of about 100 µm, for both grain boundariesand intragrain dislocations. For grains exhibiting highdefect density, we show that diffusion length vs.temperature data, L(T), can be utilized to assess themean defect activity and the contamination level ofdefects. Low-energy EBIC and Voltage Contrast areshown to visualise inhomogenieties of p-n junctionsof solar cells. Spikes exceeding the p-n junction depthby about 1/3 were observed along certain grain boun-daries and identified as being due to enhanced phos-phorus diffusion. Finally, we demonstrate that theSiPHER technique is a promising characterisationmethod for mc-Si.

61) Comparison of SiGe and SiGe:C :Heterojunction Bipolar TransistorsD. Knoll, B. Heinemann, K.-E. Ehwald,B. Tillack, P. Schley, H.-J. OstenThin Solid Films, 369(1-2), 342 (2000)

We compare the performance of heterojunction bipo-lar transistors with pure SiGe (SiGe HBTs) with thoseincorporating C-doped SiGe base layers (SiGe:C HBTs).The transistors were produced in a single-polysilicontechnology with implanted, epi-free wells. Doping theSiGe layers with low C concentration ( 0.2%) allowsus to use a higher base boron dose than for C-freeHBTs, without B outdiffusion from the heteroepitaxiallayer. As a result, the device RF performance can besignificantly improved. The higher base doping ofSiGe:C HBTs increases the peak fmax from around 50 upto more than 80 GHz, and reduces the minimum noisefigure (at 10 GHz) from >3 to 2 dB and ring oscillatordelays from 21-22 to 12-14 ps. The SiGe:C HBTs also

exhibit leakage currents, which are sufficiently low forreliable IC application.

60) Improving the Efficiency of AutomatedProtocol Implementations Using aConfigurable FDT CompilerH. König, P. Langendörfer, H. KrummComputer Communications 23(12),1179 (2000)

The integration of efficient implementation tech-niques, which have been proven in manual coding,into FDT compilers is difficult because of the semanticconstraints of the FDTs and the lack of languagemeans to flexibly adapt to a given implementationcontext. In this paper, we discuss ways to improvethe efficiency of automated protocol implementationsto make them applicable to real-life implementations.For solution, we introduce the concept of a con-figurable FDT compiler that supports the applicationof different implementation techniques and the ad-justment of the implementation to the given imple-mentation context. The paper discusses the semanticconflicts to be solved when applying optimizingimplementation techniques. It introduces a compiletime reordering of transitions to cope with theseproblems. Finally we present measurements that provea considerable efficiency gain of the generated codeas well as a comparison with the Cadvanced compilerof the SDT tool set.

59) Influence of Fluorine Contamination onIntrinsic Reliability of Thin Gate OxidesD. Krüger, P. Gaworzewski, R. Kurps,K. PomplunMicroelectronics Reliability 40, 1335, (2000)

We analyze diffusion and segregation kinetics offluorine atoms inpoly-Si/SiO2/Si structures with gateoxides of 5 nm by means of secondary ion mass spec-troscopy. Well defined doses of fluorine were intro-duced by ion implantation. Our results indicate flu-orine segregation at interfaces to the gate oxide. Thissegregation is diffusion limited with an effectiveactivation energy of 1.4 eV. The accumulation offluorine influences the intrinsic reliability of thinoxides. The breakdown behavior was studied usingconstant voltage, constant current, and stepwiseincreasing constant current stress, respectively. Wei-bull plots before and after the heat treatments wereanalyzed. At low fluorine concentrations up to dosesof 5 x 1015 cm-2 fluorine segregation is beneficial,improving, for example the tails of the Weibull plotsand slightly increasing the breakdown voltage. For

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fluorine doses higher than 1 x 1016 cm-2, detrimentalconsequences were found, degrading the charge tobreakdown values by about a factor of 5 after long-term thermal treatments.

58) Extension of Hydrogen Passivation ofIntragrain Defects and Grain Boundariesin Cast Multicrystalline SiliconO. Krüger, W. Seifert, M. Kittler, O.F. Vyvenkophysica status solidi b 222, 367 (2000)

The recombination activity of crystal defects wasstudied along cross-sections of cleaved multicrys-talline silicon wafers (Silso®) grown by block cas-ting. The temperature dependence of the electron-beam-induced current (EBIC) contrast c(T) was ana-lyzed to study defect passivation by remote hydrogenplasma treatment with respect to (i) the extensionand (ii) the degree of passivation. Based upon modelcalculations, the c(T) behavior allows estimating thedegree of contamination of recombination activecrystal defects. After hydrogen treatment of 1 h at310 0C the number of defect-related deep levels atgrain boundaries is reduced by a factor of three tofour. Low-temperature EBIC reveals that hydroge-nation also reduces the density of active centers atdefects which exhibit already very low or no (detec-table) EBIC contrast at room temperature such asintragrain defects. Both defects in intragrain regionsand grain boundaries are passivated down to about100 µm. No indications were found for significantlyenhanced hydrogen diffusion along grain boundaries.

57) Recombination Activity of ContaminatedDislocations in Silicon: A ModelDescribing the Electron-Beam-InducedCurrent Contrast BehaviourV. Kveder, M. Kittler, W. SchröterPhysical Review B 63(11), 115208/1-11(2001)

Existing experimental data give many evidences thatthe recombination rate of minority charge carriers atdislocations in silicon depends strongly on dislo-cation decoration by transition metal impurities.Here, we present a model that allows a quantitativedescription of the recombination of minority carriersat decorated dislocations. It assumes that shallowdislocation bands, induced by the strain field, anddeep electronic levels, caused by impurity atoms,which have segregated at the dislocation, or by coredefects, can exchange electrons and holes. As a con-sequence, the recombination of carriers captured atdislocation bands can be drastically enhanced by the

presence of even small concentrations of impurityatoms at the dislocation core. The model allows usnot only to explain experimentally observed depend-ences of the recombination rate on temperature andexcitation level, but also to estimate the concen-tration of deep level impurities at dislocations.

56) Epitaxial growth of Pr2O3 on Si(111) andthe observation of a hexagonal to cubicphase transition during postgrowth N2annealingJ.P. Liu, P. Zaumseil, E. Bugiel,H.-J. OstenApplied Physics Letters 79(5), 671(2001)

We demonstrate the epitaxial growth of hexagonalPr2O3(001) on Si(111), with X-ray omega-scan fullwidth at half maximum values as low as 0.06degrees, which is comparable with Si substrates.We find that a phase transition takes place duringthe anneal of the as-grown films in N2 below thegrowth tempe-rature. The annealed films display acubic structure isomorphic to manganese oxide,(111) oriented but 180 degrees rotated about theSi(111) surface normal. The phase transition can bedue to nitrogen incorporation.

55) Can Si(113) Wafers be an Alternative toSi(001)?H.-J. Müssig, J. Dabrowski, K.-E. Ehwald,P. Gaworzewski, A. Huber, U. LambertMicroelectronic Engineering 56, 195 (2001)

Si(113) may be a competitive substrate material forSi integrated Circuits. High-quality SiO2/Si(113) filmscan be produced by standard oxidation techniques.Based on investigations of the initial stages of oxi-dation by Scanning Tunneling Microscopy and abinitio calculations, we interpret this result as aneffect of tensile stress and reduced diffusivity ofoxidation by-products on Si(113). Breakdown be-havior (field and charge-to-breakdown) of 5 nm thickoxide layers on Si( 113) is better than on Si(001), atleast by a factor 2 for charge to breakdown. To evalu-ate the technological potential of Si(113), gate-controlled diodes were prepared on Si(113) and Si(001)under conditions optimized for Si(001). Electricalmeasurements demonstrate no significant differencesin the density of rechargeable interface states, thres-hold voltages, and charge carrier generation andrecombination. We believe that optimization of thepreparation conditions may lead to extremely reliablethin gate oxides on Si(113).

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54) Formation of Atomically Smooth UltrathinOxides on Si(113)H.-J. Müssig, J. Dabrowski, S. HinrichSolid State Electronics 45, 1219 (2001)

We report the first direct observation of dissociativechemisorption of oxygen molecules on a silicon sur-face at room temperature via a molecular precursorstate. We link this to the fact that smooth oxidelayers can be grown easily on Si(113). The process ofinitial oxidation is discussed in terms of surfacediffusion paths and surface stress. First ab initiocalculations elucidate the favored adsorption sitesand the oxidation mechanism. Experimental evidenceindicates bond geometries that lead to the quasi-epitaxial growth of an extremely thin SiO2 layer on thesubstrate at elevated temperatures (600 0C). In con-trast to Si(001) oxidation, neither defects nor theejection of Si atoms plays a significant role during theinitial oxidation of Si(113). Gate-controlled diodesprepared on Si(113) and Si(001) 4-in. wafers underoptimized conditions for Si(001) show no significantdifferences in the density of rechargeable interfacestates, threshold voltages, and charge carrier gene-ration and recombination.

53) Application of the Phase-Retrieval X-RayDiffractometry to an Ultra-High SpatialResolution Mapping of SiGe Films nearthe Absorption Edge of GeA.Y. Nikulin, K. Siu, J.R. Davis, P. Zaumseil,A.Y. Souvorov, A. Freundphysica status solidi (a) 184(1), 145 (2001)

A recently developed new experimental analytical X-ray diffraction method for the direct non-destructivecharacterization of single-crystal alloys is applied tomap the complex structure-factor of SiGe layers withan ultra-high spatial resolution of 5.8 AA. The tech-nique is based on analytical measurements of X-rayphase and amplitude changes in a narrow polychro-matic region of synchrotron radiation near the ab-sorption edge of the alloy impurity. These atomicspatial resolution studies have allowed observationand preliminary analysis of surface and interfacenanoscale sublayers, where the crystal structure-factor may noticeably differ from the bulk material.

52) Influence of Carbon Incorporation onDopant Surface Segregation in Molecular-Beam Epitaxial Growth of Silicon.H.-J. Osten, G. Lippert, J.P. Liu, D. KrügerApplied Physics Letters 77(1), 2000, (2000)

We describe the effect of carbon incorporation into Sion dopant surface segregation during molecular-beamepitaxial growth. Low concentration of carbon cansignificantly reduce the surface segregation of boronand phosphorus. Combining the surface diffusionmodel with a two-state exchange process, we are ableto model the experimental results over the wholetemperature range between 350 and 800 0C. Eachexchange process alone is not sufficient to describesurface segregation at all investigated temperatures.Our results show that the presence of carbon lowersthe energy difference for boron in subsurface andsurface states. The energy barriers for surface diffu-sion as well as for the two-state exchange process arenot affected by carbon.

51) MBE Growth and Properties ofSupersaturated, Carbon Containing Silicon/Germanium Alloys on Si(001)H.-J. OstenThin Solid Films, 367(1-2), 101 (2000)

The growth and properties of Si1-yCy and Si1-x-yGexCy

alloys pseudomorphically strained on Si(001) will bereviewed. Although the bulk solubility of carbon insilicon is small, epitaxial layers with more than 1% Ccan be fabricated by molecular beam epitaxy andvarious chemical vapor deposition techniques. One ofthe most crucial questions is the relation betweensubstitutional and interstitial carbon incorporation,which has a large impact on the electrical and opticalproperties of these layers. The carbon substitutio-nality (fraction of substitutional incorporated carbonatoms) is strongly influenced by the growth condi-tions, such as growth temperature and Si growth rate.The mechanical and structural properties, and theinfluence of C atoms on band structure and chargecarrier properties will be discussed. Further, we willshow how lower carbon concentrations can influencedopant diffusion, without affecting strain and bandalignment. We demonstrated that suppressed borondiffusion in carbon-rich epitaxial layers can be usedto increase the performance of SiGe heterojunctionbipolar transistors (HBTs). We demonstrate epitaxiallygrown SiGe:C HBTs with static and dynamic perfor-mance suitable for high frequency applications. Com-pared to SiGe technologies, the addition of carbonprovides significantly greater flexibility in process

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49) Epitaxial, High-K Dielectrics on Silicon:The Example of Praseodymium OxideH.-J. Osten, J.P. Liu, H.-J. Müssig,P. ZaumseilMicroelectronics Reliability 41(7), 991(2001)

We show the first results for crystalline growth ofpraseodymium oxide on Si as a potential high-K die-lectric with very promising electrical properties. Alllayer growth experiments were performed using solidsource molecular beam epitaxy. The initial growthphase was studied using scanning tunneling micros-copy. On Si(001) oriented surfaces, crystalline Pr2O3

grows as (110)-domains, with two orthogonal in-pla-ne orientations. Epitaxial silicon overgrowth seems tobe impossible. We obtain perfect epitaxial growth onSi(111). These layers can also be overgrown epi-taxially with silicon. Finally, we show that the struc-tural quality of epitaxial grown Pr2O3 on Si(001)degrades when the film is exposed to air due to sili-con oxide formation at the interface based on oxygenindiffusion. However, it can be stabilized by cappingwith Si.

48) Wider Latitude for Sophisticated Devicesby Incorporating Carbon into CrystallineSi or SiGeH.-J. Osten, H. Rücker, J.P. Liu,B. HeinemannMicroelectronic Engineering 56 (1-2), 209(2001)

Research on highly supersaturated, carbon-containingalloys on silicon substrates started only a few yearsago. Meanwhile, knowledge has been accumulated ongrowth, strain manipulation, thermal stability, carboneffects on band structure and charge carrier transport.We review basic mechanical and electrical materialproperties of Si1-yCy and Si1-x-yGexCy layers grown pseu-domorphically on Si(001). Adding carbon alleviatessome of the constraints for strainedSi1-xGex, and opens new possibilities for device appli-cation of heteroepitaxial Si-based systems. The incor-poration of carbon is beneficial for: (i) improving SiGelayer properties; (ii) creating layers with new proper-ties; and (iii) controlling dopant diffusion in micro-electronic devices. A large variety of applications inmicroelectronic devices appears likely. The first deviceapplication ready for production is the npn-SiGe:Cheterojunction bipolar transistor (HBT) with excellentstatic and high frequency.

design and offers wider latitude in process margins.The physical mechanism for suppressed boron dif-fusion in carbon-rich Si and SiGe (about 0.1% car-bon) is an undersaturation of Si self-interstitials dueto outdiffusion of carbon.

50) SiGe:C Alloys: Growth, Properties and HBTDevicesH.-J. OstenBulletin of the American Physical Society 45,585 (2000)

The growth and properties of Si1-yCy and Si1-x-yGexCy

alloys pseudomorphically strained on Si(001) will bereviewed. Although the bulk solubility of carbon insilicon is small, epitaxial layers with more than 1 %C can be fabricated by MBE and various CVD tech-niques. One of the most crucial questions is the rela-tion between substitutional and interstitial carbonincorporation, which has a large impact on the elec-trical and optical properties of these layers. Thecarbon substitutionality (fraction of substitutionalincorporated carbon atoms) is strongly influenced bythe growth kinetics. The mechanical and structuralproperties, and the influence of C atoms on bandstructure and charge carrier properties will be re-viewed. Further we will show, how lower carbon concen-trations can influence dopant diffusion, withoutaffecting strain and band alignment. We demons-trated that suppressed boron diffusion in carbon-richepitaxial layers can be used to increase the per-formance of SiGe heterojunction bipolar transistors(HBTs). We demonstrate epitaxially grown SiGe:C HBTswith static and dynamic performance suitable for highfrequency applications. Compared to SiGe techno-logies, the addition of carbon provides significantlygreater flexibility in process design and offers widerlatitude in process margins. The physical mechanismfor suppressed boron diffusion in carbon-rich Si andSiGe (about 0.1 % carbon) is an undersaturation ofSi self-interstitials due to outdiffusion of carbon. Weobserved experimentally a reduction of the diffusioncoefficient of boron by more than one order of mag-nitude due to incorporation of 0.1% carbon. Theexperimentally observed impact of carbon on dopantdiffusion is consistently described by coupled dif-fusion equations for Si point defects and dopantatoms.

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47) Low Temperature Si Epitaxy in a VerticalLPCVD Batch ReactorG. Ritter, J. Harrington, B. Tillack,T. Morgenstern, G.R. Dietze, Z.J. RadzimskiMaterials Science & Engineering B ,B73(1-3),203 (2000)

Silicon epitaxy on wafers is becoming more and moreimportant for substrates in CMOS mass production,and has traditionally been used for bipolar andBiCMOS devices. This paper presents a new processsolution in a vertical low-pressure chemical vapordeposition reactor allowing low cost batch processingfor deposition of thin Silicon epitaxial layers at tem-peratures not exceeding 800 0C. In situ cleaning ofwafers in the reactor prior to the SiH4 depositionprocess shows significant influence on the quality ofepitaxial layers. The problem of deposition on hotreactor walls has been solved by integration of re-mote plasma enhanced dry etching. We will presenttest results demonstrating the capabilities of theepitaxy process in this new tool. Finally, cost ofownership calculations will be presented showing theeconomic attraction of this new solution in com-parison with single-wafer high temperature tech-niques.

46) Modification of the Si AmorphizationProcess by In-Situ Ultrasonic TreatmentsDuring Ion ImplantationB. Romanyuk, V. Melnik, Ya. Olikh, V. Popov,D. KrügerSemiconductor Science and Technology 16,397, (2001)

We report the first study of the effect of in situ ultra-sound treatment (UST) during ion implantation onamorphization of crystalline silicon. Rutherford back-scattering spectroscopy, ion channelling and cross-section transmission electron microscopy measure-ments show that amorphization of Si during Ar ionimplantation is enhanced by UST, especially at ultra-sound frequencies around 2 MHz. The influence on theamorphization process depends mainly on ion flux,ion masses and ultrasound frequency. For implan-tation conditions without amorphization, for examplein the case of implantation with light atoms such asboron, defect concentrations are lower for wafersimplanted with UST compared to reference wafersimplanted without UST. The influence of ultrasoundis discussed in terms of its interaction with pointdefects and ultrasound-stimulated enhanced diffusionof interstitials.

45) Modeling the Influence of Dislocations onMinority Carrier Diffusion Length in Si asFunction of Dislocation ContaminationW. Seifert, M. KittlerSolid State Phenomena 78-79, 253 (2001)

Detailed insight into the recombination behavior ofdislocations is important to understand the recom-bination properties of solar-grade multicrystallinesilicon. We demonstrate that measurements of theminority carrier diffusion length as a function oftemperature allow to assess the recombination beha-vior of dislocations in highly dislocated areas, similarto contrast measurements at individual dislocations.Based on model of Kveder et al., the experimentaldata can be utilized to evaluate the contaminationstatus of the dislocations. The model is also used tostudy the influence of dislocation contamination onthe diffusion length. It is found that a given metalimpurity level in the sample is more harmful thehigher the dislocation density.

44) Recombination Current Measurements inthe Space Charge Region of MOS Field-Induced PN JunctionsR. Sorge, B. HeinemannMicroelectronics Reliability, 41(6), 789(2001)

Electrically active defects in the device region areroutinely monitored by CV measurements of reverse-biased field-induced (FI) pn junctions in MOS struc-tures. While useful, this approach is sensitive only tonear mid gap defects. Here, we demonstrate a methodfor interrogation of forward-biased FI pn junctions,which can reveal defect levels over a significantlywider region of the band gap. The method proposedis based on a simultaneous measurement of the gatecurrent and the high frequency gate capacitance innonequilibrium non-steady state in response to a li-near gate voltage ramp which drives the MOS capaci-tor from inversion equilibrium towards accumulation.This recombination-sensitive technique enables aself-consistent determination of the forward current-voltage characteristic of the FI pn junction. It makesa wider range of important impurities, especiallymetallic contaminants, accessible to detection byMOS CV approaches. Since the approach satisfies thelow-injection condition, the results can be directlyrelated to the properties of the defect centres, thusfacilitating defect identification and control.

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43) Atomic Layer Doping of SiGe - Fundamen-tals and Device ApplicationsB. Tillack, B. Heinemann, D. KnollThin Solid Films 369, 189 (2000)

The paper reviews results of atomic layer processingfor P and B doping of SiGe and for SiGe:C epitaxyusing LP(RT)CVD. Atomic layer processing for the basedoping of SiGe:C heterojunction bipolar transistors(HBTs) is demonstrated for the first time. P atomiclayer doping is self-limiting. The process is controlledby the dissociative adsorption of PH3 with an acti-vation energy of 0.3 eV. We find no self-limitation ofdiborane adsorption for B atomic layer doping. At lowdiborane partial pressures, the doping is dominatedby the dissociative adsorption of diborane at Si andGe surface sites. B doses below 1 ML can be deposi-ted. At high partial pressures of diborane the di-borane is adsorbed at B occupied surface sites, re-sulting in several monolayer equivalents of B. TheSiGe:C atomic layer epitaxy is found to be controlledby the dissociative adsorption of methylsilane with anactivation energy of 0.36 eV. Transit frequencies ofabout 45 GHz have been obtained for B atomic layerdoped SiGe:C HBTs. The HBT results demonstrate thecapability of atomic layer processing for doping ofadvanced devices with critical requirements for doseand location control.

42) Depth Profiling of the RecombinationActivity of Defects Measured byTemperature-dependent Cross-sectionalEBICO. Vyvenko, O. Krüger, M. KittlerSolid State Phenomena 78-79, 65 (2001)

The recombination activity of crystal defects wasstudied in the temperature range 80 –300 K alongcross-sections of cleaved multicrystalline siliconwafers (Silso®). A decrease of the Electron-Beam-Induced Current (EBIC) contrast from the samplesurfaces down to a depth of about 100 µm is foundafter hydrogen treatment of 1 to 310 0C for both grainboundaries and intragrain dislocations. Depending onthe initial activity of the defects, the effect of hydro-gen passivation id best visible at intermediate tempe-ratures of 160 – 250 K. The density of deep recom-bination levels in the vicinity of dislocations and thedegree of the passivation are estimated based onrecent model calculations of the temperature de-pendence of the EBIC contrast.

41) Inline Characterization of SiGe Structureson 8 Inch Si Wafers Using the Bede QC200X-Ray-DiffractometerP. Zaumseil, T.A. Lafford, M. TaylorJournal of Physics D 34(10A), A52 (2001)

Inline characterization of SiGe and SiGe:C heterobi-polar transistors places stringent requirements on x-ray diffraction set-ups: (i) precise mounting andpositioning of 8 inch wafers for single position scansand area mapping; (ii) high beam intensity in a smallspot; and (iii) low background to realize a dynamicrange better than five orders of magnitude for preciserocking curve simulation. The Bede QC200 x-ray dif-fractometer, which applies a novel micro-focus x-raysource and a novel beam conditioning optics to adouble-crystal x-ray diffraction system, meets theserequirements. Data collected on SiGe structures withthe QC200 are compared with data collected at asynchrotron source. We demonstrate that reliabledepth profiles of Ge content can be obtained in struc-tures of 500x500 µm2 size in an automatic operationmode at different positions over an 8 inch wafer in awell defined grid. Two automatic fitting programs,one involving a genetic algorithm, are used to extractmaterial information from simulation of the high-resolution diffraction scans. Rapid, reliable conver-gence on the global minimum gives objective fitting,suitable for quality control in a SiGe technology.Finally, we show how the lateral distribution of Gecontent and layer thickness can be mapped over an8 inch wafer.

40) Nitrogen Trapping of Boron and Phosphorusin SiliconV.G. Zavodinsky, A.V. Visikovski, I.A. Kuyanov,J. DabrowskiPhysics of Low-Dimensional Structures (3-4),13 (2000)

Using ab initio (Hartree-Fock and local density ap-proximation) and semiempirical (Austin Model 1)calculations we have studied the energetics and elec-tronic structures of N+B and N+P complexes. We havefound that these complexes are electrically inactive.The energy gains are 1.6 eV for the N+B coupling and2.4 eV for the N+P pairing. The N-P and N-B inter-atomic equilibrium distances are about 3.5 AA for theboth complexes.

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32) Investigation of Epitaxy Loading andGeometry Effects in a 8-inch Wafer,SiGe:C BiCMOS TechnologyD. Knoll, B. Heinemann, K.-E. Ehwald,D. Wolansky, P. Schley, B. TillackProc. 1st Int. Workshop on SiGe(C) 2001,Jan. 21-23, 2001, Tohoku University, Japan,p. IV-04

31) Evaluation of Well-known ProtocolImplementation Techniques for Applicationin Mobile NetworksP. Langendörfer, H. KönigProc. of the Int. Conference on InternetComputing. - Eds. P. Graham, M. Maheswaran,CSREA Press, 2000, p. 451

30) Success StoryG. LippertHomepage of Cadence, 04/01

29) Full-Potential LMTO Method Based onSmooth Hankel FunctionsM. Methfessel, M.V. Schilfgaarde, R. CasaliIn: Electronic Structure and Physical Propertiesof Solids/ ed. H. Dreysse, Lecture Notes inPhysics, Springer Verl., 2000

28) Optimizing the Cooperation between TCPand Wireless MACM. Methfessel, P. Langendörfer,H. Frankenfeldt, I. Babanskaja, I. Matthaei,R. KraemerProc. International Conference on InternetComputing, 26.06.01, Las Vegas/ eds:P. Graham, CSREA Press, 2001

27) Technologies for Wireless: A Value-addedApproachA. OurmazdProc. 1st Int. Workshop on SiGe(C) 2001,Jan. 21-23, 2001, Tohoku University, Japan,p. I-01

26) High-k Gate Dielectrics with Ultra-LowLeakage Current Based on PraseodymiumOxideH.-J Osten, J.P. Liu, P. Gaworzewski, E. Bugiel,P. ZaumseilProc. IEDM, p. 653, 2000

39) A Low-power Asynchronous VLSI FIRFilter.V.A. Bartlett, E. GrassProceedings 2001 Conference on AdvancedResearch in VLSI. ARVLSI 2001 Editor(s):Brunvand, E.; Myers, C. Loas Alamitos, CA,USA: IEEE Comput. Soc, (2001) p.29-39

38) Exploiting Data-dependencies in UltraLow-power DSP Circuits.V.A. Bartlett, E. GrassIEE Seminar Low Power IC Design (Ref.No.01/042).- London, UK: IEE, 2001, p.3/1-6

37) Accurate Determination of Ge DepthProfile in Si1-xGex/Si Epilayers of AdvancedHBT Structures by High Resolution X-rayDiffractometryG. Bhagavannarayana, S.K. Halder, G. LippertProc. Int. Workshop on Preparation andCharacterization of TechnologicallyImportant Single Crystals, Febr. 26-28,2001/ ed. S.K. Gupta. - New Delhi, Nat.Phys. Lab. 2001, p.655

36) A Scalable Location Aware Service Platformfor Mobile Applications Based on Java RMIO. Drögehorn, K. Singh-Kurbel, M. Franz,R. Sorge, R. WinklerTrends in Distributed Systems: Towards aUniversal Service Market, Lecture Notes inComputer Science 1890, p. 296,Springer (2000)

35) Latchup Immunity and Well Profile Designby a Deep Carbon-Doped LayerB. Heinemann, R. Barth, D. Bolze,K.-E. Ehwald, D. Knoll, D. Krüger, R. Kurps,H. Rücker, P. Schley, B. Tillack, D. WolanskyProc. IEDM, p. 471, 2000,

34) An Accurate, Experimentally VerifiedElectron Minority Carrier Mobility Model forSi and SiGeC. Jungemann, B. Heinemann, K. Tittelbach-Helmrich, B. MeinerzhagenProc. IEDM, p. 101, 2000

33) Emitter Scaling of Single-Polysilicon SiGe:CHBTs with Highly Doped Base LayersD. Knoll, B. Heinemann, K.-E. Ehwald,G.G. Fischer, B. HungerProc. ESSDERC 2000, Gif sur Yvette Cedex,Ed. Frontiers, p. 560

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Additional Papers Accepted for Publication

18) Segregation of Phosphorus to Si/SiO2InterfacesJ. Dabrowski, H.-J. Müssig, R. Baierle,M.J. Caldas, V. ZavodinskyMaterials Science in SemiconductorProcessing

17) Supporting Mobile Applications in WirelessAccess Networks- A Scalable Location AwareService PlatformO. Drögehorn, K.Singh-Kurbel, R. Winkler,M. Franz, R. Sorge, O. MayeMOMUC 2000, 7th Int. Workshop on MobileMultimedia Communications, Oct. 23-26, 2000

16) High Performance RF LDMOS Transistorswith 5nm Gate Oxide in a 0.25 µm SiGe:CBiCMOS TechnologyK.-E. Ehwald, B. Heinemann, H. Rücker,D. Knoll, R. Barth, W. Winkler, B. Hunger,H.E. Wulf, R. Pazirandeh, N. IlkovProc. IEDM 2001, Dec. 2001

15) Sub-Quarter-Micron Silicon Issues in the200/300 mm Conversion EraH. Fußstetter, H. Richter, M. UmenoE-MRS Symposium Proceedings Vol. 100(2001)

14) Improved Auger Electron SpectroscopySputter Depth Profiling of WNx and WSi2LayersA. Goryachko, D. Krüger, R. Kurps,G. Weidner, K. PomplunJournal of Vacuum Science and Technology A19(5), (2001)

13) On The Single-Chip Implementation of aHiperlan/2 and IEEE 802.11a CapableModemE. Grass, K. Tittelbach-Helmrich, U. Jagd-hold, A. Troya, G. Lippert, O. Krüger,J. Lehmann, K. Maharatna, K.F. Dombrowski,N. Fiebig, R. Kraemer, P. MähönenIEEE Personal Communications Magazine

12) A 5.8. GHz Si/SiGe VCO with AmplitudeControl for Wireless LAN ApplicationsG. Grau, U. Langmann, W. Winkler, D. Knoll,K. PresselIEICE Transactions on Electronics E84-C (9),(2001)

25) Dry Etching of Antireflective Coatings inSub-quarter Micron TechnologiesH.H. Richter, A. Wolff, S. Dietrich, H. Silz,R. Barth, I. Jürgensen, M. Stegemann, S. WegeProc. XIII. Int. Conf. on Gas Discharges andtheir Applications, /Ed. S.J. MacGregor, p.647

24) Plasma Etching in MicroelectronicsH.H. Richter, A. Wolffin : Low Temperature Plasma Physics,Berlin, Wiley-VCH, 2001Eds.: Hippler, K , S. Pfau, M. Schmidt,R.H. Schoenbach, p. 433

23) Optimization of ARC Etching inSub-quarter Micron TechnologiesH.H. Richter, H. Silz, R. Barth, S. Dietrich,I. Jürgensen, M. Stegemann, S. WegeRevue Le Vide: Science, technique etapplications, 315 (Mai 2001)

22) Ultrasound Effects on Radiation Damagein SiB. Romanjuk, D. Krüger, V. Melnik, Ya. Olikh,V. Popov, V. Soroka, O. OberemokSemiconductor Physics, Quantum Electronicsand Optoelectronics, 3, 59 (2000)

21) Suppressed Boron Diffusion in Carbon-Doped SiGe Heterojunction BipolarTransistorsH. Rücker, B. Heinemann, D. Knoll, H.-J. OstenInternational Physics Conference Series, 166,287 (2000)

20) Determination of the RecombinationLifetime in the Space Charge Region of MOSField Induced PN-JunctionsR. Sorge, B. Heinemann, H. Richter,J. Grabmeier, G. ObermeierProc. ESSDERC 2000, Gif sur Yvette Cedex,Ed. Frontiers, p. 484

19) SiGe:C Epitaxy for HBT ApplicationsB. Tillack, D. Knoll, B. Heinemann,K.-E. Ehwald, D. Wolansky, Y. Yamamoto,D. Krüger, P. SchleyProc. 1st Int. Workshop on SiGe(C) 2001,Jan. 21-23, 2001, Tohoku University, Japan,p. III-01

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4) High-K Dielectrics: Moving Beyond theSilicon Dioxide EraH.-J. OstenVacuum Solutions

3) Epitaxial Praseodymium Oxide: A NewHigh-K DielectricH.-J. Osten, E. Bugiel, J. Dabrowski,A. Fissel, T. Guminskaya, J.P. Liu,H.J. Müssig, P. ZaumseilProceedings of the Interational Workshop onGate Insulators (IWGI), Tokyo, Nov. 2001

2) Suppression of Boron Diffusion by Carbon:A New Route to Advanced HeterobipolarTransistorsH. Rücker, H.-J. OstenPhysics of SiGeC, ed. by S.T. Panelides,S. Zöllner, New York : Gordon and Breach

1) Über Möglichkeiten der Charakterisierungvon mc-Si durch SiPHERW. Seifert, O. Krüger, M. Kittler, V. HiggsFreiberger Forschungshefte

Invited Presentations

34) Die Elektronenmikroskopie am IHPzwischen Materialforschung undFehleranalyseE. BugielSeminar on AMD, 24.01.01, Dresden,Germany

33) Collaboration WSAG - IHP: Summary ofResults 2000A. FischerWacker Siltronic AG, 18.12.00, Burghausen,Germany

32) Interstitials, Nuclei, and Thermal Donorsthe Key Players in the 500 0C RegionG. Kissinger3rd Int. Symposium on Advanced Science andTechnology of Silicon Materials, Kona, Hawaii,USA, Nov. 20-24, 2000

31) Elektrische Aktivität von Kristalldefekten inmultikristallinem SiliciumM. KittlerKristallzüchtungsschule 2000 “ Von der Physikdes Kristallwachstums zum maßgeschneidertenWerkstoff, 11.-15.09.2000, BTU Cottbus,Germany

11) Cost-Effective High Performance High-Voltage SiGe:C HBTs with 100 GHz fT andBVCEO x fT Products Exceeding 220 VGHzB. Heinemann, D. Knoll, R. Barth, D. Bolze,K. Blum, J. Drews, K.-E. Ehwald, K. Köpke,R. Kurps, H. Rücker, P. Schley, W. Winkler,H.-E. WulfProc. IEDM 2001, Dec 01

10) On 2D/3D Numerical Oxidation Modeling:Calibration and Investigation of SiliconCrystal Orientation Effect on Stresses inShallow Trench IsolationsT. Hoffmann, K.F. Dombrowski, V. SenezProc. Modeling and Simulation ofMicrosystems Conference, 27.-29.3.2000,San Diego, USA

9) Elektrische Eigenschaften von Kristall-defekten in multikristallinen Si-Materi-alien und Solarzellen: Charakterisierungdes Einflusses unterschiedlicher Behand-lungen durch mikroskopische TechnikenM. Kittler, O. Krüger, W. SeifertFreiberger Forschungshefte

8) Room Temperature Luminescence andEBIC Recombination Behaviour of CrystalDefects in Multicrystalline SiM. Kittler, W. Seifert, T. Arguirov, I. Tarasov,S. OstapenkoProc. Solar Energy Materials and Solar Cells

7) HBT before CMOS, a New Modular SiGeBiCMOS Integration SchemeD. Knoll, H. Rücker , B. Heinemann,R. Barth, J. Bauer, D. Bolze, K.-E. Ehwald,T. Grabolla, U. Haak, B. Hunger, D. Krüger,R. Kurps, S. Marschmeyer, H.H. Richter,P. Schley, B. Tillack, W. WinklerProc. IEDM 2001, Dec. 01

6) Evaluation of Well-Known ProtocolImplementation Techniques forApplication in Wireless NetworksP. Langendörfer, H. König, R. KraemerJournal of Supercomputing (Special Issue)

5) Can Si(113) Wafers be an Alternative toSi(001)H.-J. Müssig, J. Dabrowski, K.-E. Ehwald,P. Gaworzewski, A. Huber, U. LambertSolid State Electronics

83

30) Electrical Behaviour of Crystal Defects inSilicon Solar CellsM. Kittler, W. Seifert, O. KrügerBIAMS 2000 6th Int. Workshop on BeamInjection Assessment of Microstructures inSemiconductors, Nov. 12-16, 2000, Fukuoka,Japan

29) Electrical Behaviour of Crystal Defects inSi: Influence of a ContaminationM. Kittler, W. Seifert, V. Kveder11th Workshop on Crystalline Solar CellMaterials and Processes, Ed. B.L. Sopori,NREL, Estes Park, Colorado, 20.08.2001, USA

28) Recombination Activity of IndividualCrystal Defects in Silicon: Influence of aContaminationM. KittlerNanomaterials Laboratory, National Institutefor Materials Science (NML/NIMS), Sengen,Tsukuba, 13.03.01, Japan

27) Modular, High-Performance BiCMOS byIntegration of SiGe:C HBTsD. Knoll, B. Heinemann, K.-E. Ehwald,H.- Rücker, B. Tillack, H.-J. Osten199th Electrochemical Society Meeting(2nd Int. Symposium on ULSI ProcessIntegration), March 25-30, 2001,Washington D.C., USA

26) Bluetooth : ein neuer Standard für „shortrange“ KommunikationR. KraemerM-Business Summer School, 18.09.00, Berlin,Germany

25) Wireless Internet : More Than Just InternetWithout WireR. KraemerDatacom-Kongress “Neue Wege in der Telekom-munikation”, 16.-17.10.00, Berlin, Germany

24) Technologies for Mobile Connectivity

R. Kraemer, A. OurmazdWorkshop Technologien für den Neuen Markt,05.12.00 Berlin, Germany

23) Wireless Engines for Wireless InternetR. KraemerConference on ICCCD, 14.-16.12.00,Kharagpur, India

22) Technologies for Mobile ConnectivityR. KraemerIndian Institute of Technology, 13.12.00,Kharagpur, India

21) ”Off-Line” Diagnostics for a 0.25 µmSiGe:C BiCMOS TechnologyD. KrügerInstitutsseminar - Institut for Solid Stateand Materials Research Dresden, 20.06.01,Dresden, Germany

20) IHP - Innovationen für die drahtloseKommunikation der ZukunftW. Mehr10. Technologietag Ostbrandenburg,September 2000, Frankfurt (Oder), Germany

19) Can Si(113) Wafers be an Alternative toSi(001)H.-J. Müssig, J. Dabrowski, K.-E. Ehwald,P. Gaworzewski, A. Huber, U. LambertThe 3rd Int. Symp. on Advanced Science andTechnology of Silicon Materials, AstonKeauhou Beach Resort, Kona, Hawaii,Society for Promotion of Science (JSPS) ,Nov. 20-24, 2000, Japan

18) Kann Si(113) eine Alternative zu Si(001)sein?H.-J. MüssigKolloquium des Institutes für Oberflächen-modifizierung Leipzig, 21.06.01, Germany

17) Silicon-based Technologies for Wireless:A Value-added ApproachA. Ourmazd4. Handelsblatt-Jahrestagung „Halbleiter-Industrie 2000“, 26.09.00, Berlin, Germany

16) The Viewpoint of Science: Using Perfor-

mance Measures to Optimise Cooperationwith Industry in a Large Public ResearchInstitutionA. OurmazdJoint German-OECD Conference onBenchmarking Industry-Science Relationships,17.09.00, Berlin, Germany

15) The Fight for TalentA. OurmazdStipendiatentreffen der Alexander-vonHumboldt-Stiftung, 26.10.00, Berlin,Germany

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14) Technologies for Wireless: A Value-addedApproachA. Ourmazd, B. Tillack1st Int. Workshop on SiGe(C) 2001,Jan. 21-23, 2001, Tohoku University, Japan

13) Silicon-based Technologies for WirelessA. OurmazdULSI Process Integration Symposia,28.03.01, Washington DC, USA

12) Von der Forschung zur InnovationA. OurmazdForum der Gesellschaft für Mikroelektronik,5.4.01, TU Wien, Austria

11) Business and Technology Trends inCommunication ICs, Plans for theCommunicant FabA. OurmazdInfineon-Workshop Leitungskreis DD200mm,27.5., Dresden, Germany

10) Is there Room for Defects inSemiconductorsA. OurmazdICDS-21, Plenarvortrag, 16.07.01, JustusLiebig Universität Giessen, I. PhysikalischesInstitut, Giessen, Germany

9) Entwicklungstendenzen der drahtlosenKommunikationA. Ourmazd, H. RichterInnovationsforum Drahtlose Kommunikation,10.4.01, BIC Frankfurt (O.), Germany

8) Mikroelektronik im Osten Deutschlands -Das IHP Frankfurt (Oder)H. RichterVDE/VDI Arbeitskreis Mikroelektronik Berlin-Brandenburg, 26.10.00, Berlin, Germany

7) Materialrelevante Herausforderungen fürdie perspektivische MikroelektronikH. RichterKristallzüchtungsschule 2000, “Von der Physikdes Kristallwachstums zum maßgeschneidertenWerkstoff”, 11.-15. Sept. 2000, Cottbus,Germany

6) Atomic Layer Doping of SiGe forHeterojunction DevicesB. TillackSelective and Functional Film DepositionTechnologies as Applied to ULSI Technology(IUVSTA Workshop), Nov. 19-24, 2000, Mie,Japan

5) SiGeC auf Silicium - Herstellung und Eigen-schaften eines neuen HalbleitermaterialsB. TillackKristallzüchtungsschule 2000 “Von der Physikdes Kristallwachstums zum maßgeschneidertenWerkstoff”, 11.-15.09.2000, BTU Cottbus,Germany

4) SiGe:C Epitaxy for HBT ApplicationsB. Tillack, D. Knoll, B. Heinemann,K.-E. EhwaldFront End Technologies, Semicon EuropeanMunich, 24.04.01, Germany

3) SiGe:C Epitaxy for HBT ApplicationsB. Tillack, D. Knoll, B. Heinemann,K.-E. EhwaldFront End Technologies, Semicon EuropeanMunich, 24.04.01, Germany

2) Modelling of the Medium Access ControlLayer of an IEEE 802.11 Wireless Local AreaNetwork Using the SDL LanguageK. Tittelbach-Helmrich, O. Krüger, J. LehmannCustomer Workshop of Company Telelogic,11.09.00, München, Germany

1) Basic System Simulator for the IEEE802.11a StandardA. Troya, G. LippertCadence User Group Meeting, 12.03.01,Munich, Germany

85

45) Segregation of Phosphorus toSi/O2/Si(001) InterfacesJ. Dabrowski, V. Zavodinsky, H.-J. Müssig,K. Ignatovich65. Physikertagung und Frühjahrstagung desArbeitskreises Festkörperphysik der DPG,March 26-30, 2001, Hamburg, Germany

44) Atomic Structure of HfO2(110)/Si(001)InterfacesJ. Dabrowski, V. Zavodinsky, H.-J. Müssig,K. Ignatovich65. Physikertagung und Frühjahrstagung desArbeitskreises Festkörperphysik der DPG,March 26-30, 2001 Hamburg, Germany

43) Chemical Composition of HfO2/Si(001)InterfacesJ. Dabrowski, V. Zavodinsky, H.-J. Müssig,K. IgnatovichICDS-21, July 16-20, 2001, Giessen,Germany

42) Segregation of Phosphorus toSiO2/Si(001) InterfacesJ. Dabrowski, V. Zavodinsky, H.-J. Müssig,K. Ignatovich, R. Baierle, M.J. CaldasICDS-21, July 16-20, 2001 Giessen,12.03.2001, Germany

41) Band Offsets and Electron TransportCalculation for Strained Si1-x-yGexCy/SiHeterostructuresP. Dollfus, S. Galdin, H.-J. Osten, P. Hesto3rd ICMM, Oct. 2000, Dublin, Ireland

40) WINEGLASS: A Scalable Location AwareService Platform for Ad-hoc andPre-installed NetworksO. Drögehorn, L. Schrix, C. CheungIST Mobile Communication Summit 2000,Oct. 1-4, 2000, Galway, Ireland

39) Supporting Mobile Applications in WirelessAccess Networks- A Scalable Location AwareService PlatformO. Drögehorn, K.Singh-Kurbel, R. Winkler,M. Franz, R. Sorge, O. MayeMOMUC 2000, 7th Int. Workshop on MobileMultimedia Communications, Oct. 23-26, 2000

Presentations

52) Exploiting Data-Dependencies in Ultra Low-Power DSP CircuitsV.A. Bartlett, E. GrassUK-Low-Power Forum, Oct 23-24, 2000,Manchester, UK

51) Light Diffraction Based OverlayMeasurementJ. Bischof, J. Bauer, U. Haak, R. BrunnerSPIE - Microlithography 20001, Febr. 26-March 02, 2001, Santa Clara, California, USA

50) Innovatives Prinzip zur Overlaymessung inder FotolithographieJ. Bischoff J, R. Brunner, J. Bauer, U. Haak102. Jahrestagung der DeutschenGesellschaft für angewandte Optik,06.-09.06.2001, Göttingen, Germany

49) Charakterisierung von lateralenNanometerstrukturen mit optischen undnichtoptischen MessverfahrenJ. Bischoff, R. Brunner, S. Gliech,A. Duparré, J. Bauer102. Jahrestagung der DeutschenGesellschaft für angewandte Optik,06.-09.06.2001, Göttingen, Germany

48) TEM Investigations of CrystallinePraseodymium Oxide on SiliconE. Bugiel, J.P. Liu, H.-J. OstenAdvances in Focused Ion Beam Microscopy,March, 30th, 2001, Oxford, UK

47) TEM Investigations of EpitaxialPraseodymium Oxide on SiliconE. Bugiel, J.P. Liu, H.-J. Osten12th Int. Conference on Microscopy ofSemiconducting Materials, 25.-29.03.2001,Oxford, UK

46) Reactive Ion Etching Characteristics ofCobalt Silicide and Tungsten Silicide inFluorine-based and Argon PlasmasS. Chernjavsky., A. Goryachko, D. Krüger,H.H. Richter15th International Conference on Ion-Surface Interactions (ISI-2001), Aug.-27-31,2001, Zvenigorod, Russia

86

38) Ion Sputtering Assisted Auger ElectronSpectroscopy Depth Profiling of TiN and itsInterfaces with Ti, W, Co, Si, and SiO2A. Goryachko, D. Krüger, R. Kurps, H. SchneiderIX Int. Workshop on Ion Beam SurfaceDiagnsostics, Zaporizhzhia (Ukraine),Oct. 3-7 2000

37) AES and XPS Study of Thermally ActivatedInter-diffusion in High-K Dielectric Pr2O3Deposited on SiA. Goryachko , J.P. Liu, D. Krüger,H.-J. Osten, E.- Bugiel, R. KurpsFrühjahrstagung der DPG, 26.-30.03.2001Hamburg, Germany

36) Investigations of Stress-Induced LeakageCurrent in Ultrathin Silicon OxidesT. Guminskaya , P. GaworzewskiFrühjahrstagung der DPG 2001, March 26-30Hamburg, Germany

35) Distribution of Barrier Heights inW/Si1-x-yGexCy Schottky DiodesA. Hattab, M. Barthula, F. Meyer, P. Warren,H.-J. Osten3rd ICMM, Oct. 2000, Dublin, Ireland

34) Latchup Immunity and Well Profile Designby a Deep Carbon-Doped LayerB. Heinemann, R. Barth, D. Bolze,K.-E. Ehwald, D. Knoll, D. Krüger, R. Kurps,H. Rücker, P. Schley, B. Tillack, D. WolanskyIEDM 2000, Dec. 11-13, 2000, San Francisco,USA

33) An Accurate, Experimentally VerifiedElectron Minority Carrier Mobility Model forSi and SiGeC. Jungemann, B. Heinemann, K. Tittelbach-Helmrich, B. MeinerzhagenIEDM 2000, Dez. 11-13, 2000, San Francisco,USA

32) Room Temperature Luminescence andEBIC Recombination Behaviour of CrystalDefects in Multicrystalline SiM. Kittler, W. Seifert, T. Arguirov, I. Tarasov,S. OstapenkoE-MRS Spring Meeting 2001, Symposium E,June 2001, Strasbourg, France

31) Emitter of Single-Polysilicon SiGe:C HBTswith Highly Doped Base LayersD. Knoll, B. Heinemann, K.-E. Ehwald,G.G. Fischer, B. HungerESSDERC 2000, Sept.-11-13, Cork, Ireland

30) Investigation of Epitaxy Loading andGeometry Effects in a 8-inch Wafer,SiGe:C BiCMOS TechnologyD. Knoll, B. Heinemann, K.-E. Ehwald,D. Wolansky, P. Schley, B. Tillack1st Int. Workshop on SiGe(C) 2001,Jan. 21-23, 2001, Tohoku University, Japan

29) Influence of Fluorine Contamination onIntrinsic Reliability of Thin Gate OxidesD. Krüger, P. Gaworzewski, R. Kurps,K. Pomplun11th European Symposium on Reliability ofElectron Devices, ESREF 2000, Dresden,2.-6.10.2000, Germany

28) SIMS Analysis of Dopant Diffusion inC-Doped Si and SiGeD. Krüger, R. Kurps, H. Rücker, B. HeinemannSIMS Europe 2000, 17.-20.09., 2000, Münster,Germany

27) Influence of In-situ Ultrasound TreatmentDuring Ion Implantation onAmorphization and Junction Formation inSiliconD. Krüger, R. Romanjuk, V. Melnik, Y. Olikh,R. KurpsFabrication, Characterization and Modelingof Ultra-Shallow Doping Profiles inSemiconductors (USJ’2001), April 22-26,2001, Napa, California, USA

26) MBE Growth of Binary Epitaxial Metal Oxideson Silicon: The Example of PraseodymiumOxideJ.P. Liu, H.-J. Osten, E. Bugiel, P. ZaumseilXI. MBE World Conf., 10.-15.09.00, Beijing,China

25) A Low-Power 64-point FFT/IFFT Architecturefor Wireless Broadband CommunicationK. Maharatna, E. Grass, U. Jagdhold5th OFDM Workshop, 12.-13.09, 2000,Hamburg, Germany

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18) High-k Gate Dielectrics with Ultra-LowLeakage Current Based on PraseodymiumOxideH.-J. Osten, J.P. Liu, P. Gaworzewski,E. Bugiel, P. ZaumseilIEDM 2000, Dec. 11-13, 2000, San Francisco,USA

17) Supersaturated Carbon in Si and SiGe : AStatus ReportH.-J. Osten, J.P. Liu, D. Knoll, H. RückerXI. International Conference on MolecularBeam Epitaxy, Sept. 2000, Beijing, China

16) Epitaxial, High-K Dielectrics on Silicon: TheExample of Praseodymium OxideH.-J. Osten, J.P. Liu, H.-J. Müssig, P. Zaumseil11thb Workshop on Dielectrics inMicroelectronics, Nov. 2000, Munich, Germany

15) Carbon Doped SiGe Heterojunction BipolarTransistor Module Suitable for Integrationin a Deep Submicron CMOS ProcessH.-J. Osten, D. Knoll, B. Heinemann,H. Rücker, K.-E. Ehwald2000 Asia-Pacific Microwave Conference,Dec. 2000, Sydney, Australia

14) Dry Etching of Antireflective Coatings inSub-quarter Micron TechnologiesH.H. Richter, A. Wolff, S. Dietrich, H. Silz,R. Barth, I. Jürgensen, M. Stegemann, S. WegeXIII. Int. Conf. on Gas Discharges and theirApplications, Sept. 3-8, 2000, Glasgow, UK

13) Plasma Etching of Organic ARC forQuarter-micron Si TechnologiesH.H. Richter, H. Silz, A. Wolff, I. Jürgensen,M. Stegemann, S. Wege10. Bundesdeutsche Fachtagung Plasma-technologie, 28.02.-02.03.2001 Greifswald,Germany

12) 11 GHz SiGe Circuits for Ultra WidebandRadarM. Roßberg, J. Sachs, P. Rauschenbach,P. Peyerl, K. Pressel, W. Winkler, D. KnollBCTM 2000, 24.-26.09.00, Minneapolis,Minnesota, USA

24) A Low-Power 64-point FFT/IFFTArchitecture for Wireless BroadbandCommunicationK. Maharatna, E. Grass, U. JagdholdMOMUC 2000, Waseda, Oct. 23-26, 2000,Tokyo, Japan

23) Optimizing the Cooperation between TCPand Wireless MACM. Methfessel, P. Langendörfer,H. Frankenfeldt, I. Babanskaja, I. Matthaei,R. KraemerInternational Conference on InternetComputing, 26.06.01, Las Vegas, USA

22) Depth Profiling Using SynchrotronRadiation With High Energetic Resolutionas Demonstrated for Si-, SiC-, SiGe-, andSiGeC-SamplesR.P. Mikalo, P. Hoffmann, D. Batchelor,D. Schmeißer, A. Lloyd-Spetz, I. Lundström,H. Wawra, K. PresselDPG Spring Meeting, Poster,26.03-30.03.2001, Hamburg, Germany

21) Initial Stages of Praseodymium Oxide FilmFormation on Si(001)H.-J. Müssig, J. Dabrowski, K. Ignatovich,J.P. Liu, V. Zavodinsky, H.-J. Osten11th Int. Conf. on Scanning TunnelingMicroscopy / Spectroscopy and RelatedTechniques, University of British Columbia,Vancouver, July 15-20, 2001, Canada

20) Initial Stages of PraseodymiumoxideDeposition on Si(001)H.-J. Müssig, K. Ignatovich65. Physikertagung und Frühjahrstagung desArbeitskreises Festkörperphysik der DPG,March 26-30, 2001, Hamburg, Germany

19) Boron-Stabilized c(4x8) Structure ofClean Si(001)H.-J. Müssig, K. Ignatovich, V. Zavodinsky,J. Dabrowski65. Physikertagung und Frühjahrstagung desArbeitskreises Festkörperphysik der DPG,March 26-30, 2001, Hamburg, Germany

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4) Depth Profiling of the RecombinationActivity of Defects Measured byTemperature-dependent Cross-sectionalEBICO. Vyvenko, O. Krüger, M. KittlerBIAMS 2000, Beam Injection Assessment ofMicrostructure in Semiconductors,Nov. 12-16, 2000, Fukuoka, Japan

3) Characterization of Crystalline-AmorphousTransition by Heavy C Doping of Poly Si(Si:C)Y. Yamamoto , O. Fursenko, K. Köpke,J. Bauer, E. Bugiel, D. Krüger, P. Zaumseil,B. TillackE-MRS Spring Meeting 2001 E, June 5-8,2001, Strasbourg, France

2) Inline Characterization of SiGe Structureson 8 Inch Si Wafers Using the Bede QC200X-Ray-DiffractometerP. Zaumseil, T.A. Lafford, M. TaylorX-Top, 2000, 13.-15.09.00, Ustron, Poland

1) Ab Initio Band Structures of HfO2 and PrO2V. Zavodinsky, J. Dabrowski, H.-J. Müssig,K. Ignatovich, A. Fleszar65. Physikertagung und Frühjahrstagung desArbeitskreises Festkörperphysik der DPG,March 26-30, 2001, Hamburg, Germany

11) Modeling the Influence of Dislocations onMinority-carrier Diffusion Length in Si asFunction of Dislocation ContaminationW. Seifert, M. KittlerBIAMS 2000, Beam Injection Assessment ofMicrostructure in Semiconductors, Nov. 12-16,2000, Fukuoka, Japan

10) Optimization of ARC Etching inSub-quarter Micron TechnologiesH. Silz, H.H. Richter, R. Barth, S. Dietrich,I. Jürgensen, M. Stegemann, S. Wege13th International Colloquium on PlasmaProcesses, June 10-14, 2001, Antibes,France

9) Determination of the RecombinationLifetime in the Space Charge Region of MOSField Induced PN-JunctionsR. Sorge, B. Heinemann, H. Richter,J. Grabmeier, G. ObermeierESSDERC 2000, Sept. 11.-13, 2000, Cork,Ireland

8) Digital Design Flow: A Case StudyZ. Stamenkovic, U. JagdholdConference for Electronics,Telecommunications, Computers, Automationand Nuclear Engineering, June 04-07, 2001,Arandjelovac, Yugoslavia

7) SiGe:C Epitaxy for HBT ApplicationsB. Tillack, D. Knoll, B. Heinemann,K.-E. Ehwald, D. Wolansky, Y. Yamamoto,D. Krüger, P. Schley1st International Workshop on SiGe(C) 2001,Jan. 21-23, 2001, Tohoku University, Japan

6) Fully Implemented IEEE 802.11a /Hiperlan2 Model IncludingSynchronizationA. Troya , G. LippertIEEE Int. Conference on 3rd GenerationWireless and Beyond, June 06-08, 2001,San Francisco, USA

5) Simulation Aspects of an OFDM-basedPhysical Layer of Wireless BroadbandNetworkA. Troya, G. Lippert, B. Stantchev5th Int. OFDM-Workshop, Sept. 12-13, 2000,Hamburg, Germany

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Technical Reports

13) Abschlussbericht zum Projekt Defekte inSiGeK.W. Benz, K. PresselReport - Kristallographisches InstitutFreiburg, IHP Frankfurt (O.), unterstützt vonder DFG

12) Mechanische Spannungen in 300 mmScheiben bei thermischen Prozessen -Teil II,A. Fischer, H. RichterAbschlussbericht zur Teilaufgabe M4 desVertrages zwischen WSAG und IHP, 18.12.00

11) Influence of Nitrogen Doping on the Forma-tion of Grow-in Oxide Precipitate Nuclei in300 mm CZ SiA. Fischer, G. KissingerAbschlussbericht zur Teilaufgabe M3 desVertrages zwischen WSAG und IHP, 18.12.00

10) Finite-Element-Analyse desVerspannungszustandes des Silizium-substrates durch Grabenisolations-strukturen und Regeln zur Minimierungder VerspannungA. FischerAbschlussbericht zum Projekt Material-technologischer Support von fortgeschritte-nen Si CMOS Technologiemodulen des IHP

9) Failure Analysis on Standard Test Wafersfrom SOI LotsG. KissingerForschungsbericht für Alpha-Microelectronics

8) Adsorption und Epitaxie auf Si(113)H.-J. MüssigAbschlussbericht zum DGF-Projekt

7) Strukturelle und elektrische Charakteri-sierung alternativer Gateoxide aufSiliziumoberflächenH.-J. Müssig,Fortsetzungsantrag zum DFG-Projekt

6) Technologien für gemischte-SiGe-HBT-CMOS-SchaltungenH.-J. Osten5. Zwischenbericht LOTUS: Fördervorhaben01 M 2419 F

5) Entwicklung neuer Isolatorprozesse fürdie 0,14 µm-Strukturierung auf Infineon-kompatiblen Anlagen(“Isolatorätzprozesse II”)H.H. Richter, H. Silz, St. Marschmeyer,S. Günther, D. KrügerDienstleistungsvertrag Nr. D 011 013 vom27.12.1999 zwischen Infineon Dresden undIHP

4) Modifizierung des implantationsinduziertenDiffusionsverhaltensB.N. Romanjuk, D. KrügerErfolgskontrollbericht Projekt 01 M 2976,Technical Report Transform-Projekt mit ISPKiev: 1997 - 1999

3) Diffusion von Dotierstoffen in kohlenstoff-reichem SiliziumH. RückerAbschlußbericht und Fortsetzungsantrag fürDFG-Projekt

2) Abschlussbericht zu dem von der VW-Stiftung geförderten Projekt im Schwer-punkt ‘Mikrocharakterisierung von Werk-stoffen und Bauelementen’P. Schwander, P. Formanek, M. Kittler(edititorial responsibility)

1) An SDL Model for a Wireless Local AreaNetwork, Complying to the Standard IEEE802.11K. Tittelbach-Helmrich, O. Krüger,J. LehmannIHP Technical Report

90

3) Statischer Frequenzteiler mitumschaltbarem TeilerverhältnisM. Pierschel, GustatUS-Patentanmeldung IHP.204.US, /IB 1042,Anm.AZ: US 09/805,488, am 13.03.01

2) Verfahren und Vorrichtung zum Herstellendünner epitaktischer HalbleiterschichtenB. Tillack, G. Ritter D. Wolansky, T. GrabollaIHP.208.01 / IB1061, Anm.-AZ:101 37 441.0, am 29.07.01

1) Hochfrequenz MOSW. WinklerIHP.192.01 / IB 1156, Anm.AZ:101 35 803.2, am 23.07.01

Books / Proceedings / Dissertations

2) Proceedings of Symposium E CrystallineSilicon for Solar Cells held at E-MRSSpring Meeting 2001, June 2001 inStrasbourg, FranceM. Kittler, S. Martinuzzi, W. Koch, T. Brutonin print

1) Gestaltung konfigurierbarer Code-generatoren für die automatischeErzeugung effizienter Protokoll-implementierungenP. LangendörferDissertation, BTU Cottbus

Patents Applications

14) CMOS kompatibler lateraler DMOS TransistorD. Knoll, B. Heinemann, W. WinklerPatentanmeldung IHP.183.00,Anm.-AZ: 100 63 135.5, am 18.12.00

13) CMOS kompatibler lateraler DMOS TransistorK.-E. Ehwald, D. Knoll, B. Heinemann,W. WinklerIHP.193.PCT, Anm.-AZ:PCT/DE00/01175,am 24.03.01

12) LDMOS TransistorK.-E. Ehwald, B. HeinemannIHP.209.01 / IB 1065, Anm.-AZ:am 17.08.01

11) Verfahren und Vorrichtungssystem zurDatenübertragungE. Grass, H. FrankenfeldtIHP.206.PCT / IB1055,Anm.-AZ: PCT/EP01/08068, am 12.07.01

10) Verfahren zur Herstellung von Substrat-scheiben für CMOS und BiCMOS-TechnologienB. HeinemannPatentanmeldung Dez. 2000, IHP.186.00,Anm-AZ: 100 61 191.5

9) Frequenzsynthesizer und FM-Demodulator mit definierterOszillatorsteuerspannungF. HerzelIHP.202.01/ IB1048, Anm.-AZ: 101 32128.7-35, am 28.06.01

7) MOS Transistor mit Praseodym-Silicid-Kontakten und Verfahren zu seinerHerstellung in CMOS- und Bi-CMOS-TechnologienD. Krüger , A. Goryachko, R. Kurps, L. P. Liu,H. J. OstenIHP.201.01/ IB1035, Anm.-AZ:101 27 234.0, am 26.05.01

6) Verfahren und Schaltungsanordnung zurDurchführung einer Fast Fourier Transfor-mation sowie Anwendung derselbenK. Maharatna, E. Grass, U. JagdholdPatentanmeldung IHP.189.00,Anm.-AZ: 100 62 759.5

5) Drahtloses Kommunikationssystem mitvorgeschaltetem AufwecksystemM. Methfessel, H. Frankenfeldt, I. Matthaei,R. KraemerPatentanmeldung IHP.176.00Anm.A-Z: 100 44 035.5

4) Elektronisches Bauelement undHerstellungsverfahren für einelektronisches Bauelement(Praseodymium)H.-J. Osten, J. P. LiuIHP.203.PCT, IB1063,Anm.-AZ: PCT/EP01/08830, am 31.07.01

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Impressum:

Photo: Winfried Mausolf, IHP

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