AD-A096 422 ARMY AVIATION RESEARCH AND DEVELOPMENT COMMAND ST LO--ETC FIG 9/2AN A IRBORNE PROGRAMMABLE DIGITAL TO VIDEO CONVERTER INTERFACE A--ETC(UIFEB Al V J ORGANIC, E A KARCHER

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I Technical Report-80-E-.

/j L AIRBORNE TROGRAMMABLE .IGITAL TO VIDEO CONVERTERINTERFACE AND OPERATION MANUAL.

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1c ,NCENT JORGANICELECTRONIC TECHNOLOGY & DEVICES LABORATORY

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EDWARD A. KARCHERI ADVANCED SYSTEMS DIVISION /I

C AVIONICS R&D ACTIVITY

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DISTRIBUTION STATEMENT M7ILApproved for public release;

distribution unlimited..,

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Research and Development Technical Report

, Aviation Research and Development Command

- i81 3 16205

NO0TiC E S

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I. REPORT NUMBER 2. 5OVT A,'.CESSION NO. 3. RECIPIENT'S CATALOG NUMBER

AVRADCOM TR 80-E-4 11\ TE

4. TITLE (and Subtitle) 5. TYPE OF REPORT & PERIOD COVERED

An Airborne Programmable Digital to VideoConverter-Interface and Operation Manual 6. PERFORMING ORG. REPORT NUMBER

7. AUTHOR(*) S. CONTRACT OR GRANT NUMBER(a)

Vincent J. Organic (ERADCOM)Edward A. Karcher (AVRADCOM)

9. PERFORMING ORGANIZATION NAME AND ADDRESS 10. PROGRAM ELEMENT, PROJECT, TASKAREA & WORK UNIT NUMBERS

Systems Integration and Evaluation Branch L.62202.AH85

Advanced Systems Division DAVAA-F 62202.H85

Avionics R&D Activity, Fort Monmouth, NJ 07703 612202.H85.18.12.04 YA20z-n

tt. CONTROLLING OFFICE NAME AND ADDRESS 12. REPORT DATEHeadfuarters FEB 81US A y Avionics R&D Activity 13. FE 81ATTN: DAVAA-F NUMBEROF PAGESFort Monmouth-. N.J 07703 r,7_____________

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Approved for public release; distribution unlimited

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IS. SUPPLEMENTARY NOTES

It. KEY WORDS (Continue on revere aide if necessary and Identify by block number)

SCAN CONVERTERVIDEO DISPLAYTELEVISION DISPLAY

20. ABSTRACT (Continue on reverse oide If necessary and Identify by block number)

This report describes the operational commands, data structure and storage, and

interface to an airborne programmable digital to video converter. It is intended

for use as a companion manual to the hardware description report No. AVRADCOM

TR 80-E-5.

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CONTFNTS

Page

INTRODUCTION I

DESCRIPTION OF DISPLAY SYSTEM I

DIGITAL TO VIDEO CONVERTER REQUIREMENTS 2

DESCRIPTION OF THE DIGITAL TO VIDEO CONVERTFR / 2

INTERFACE 3

DATA STORAGE 6

CONTROL WORDS 9

OPERATION 9

APPENDICES

A. TEMPORARY CENTRAL PROCESSING UNIT (TCPU) 13

B. MAP VIDEO PROGRAMMABLE READ ONLY MEMORY (PROM) 18

C. CONTROL WORDS-FUNCTIONAL DESCRIPTION 20

TABLES

1. DIGITAL TO VIDEO CONVERTER MEMORY ORGANIZATION 29

2. DISPLAY MEMORY ALLOCATION, FIELD 0, 512 PIXELS/LINE RESOLUTION 30

3. DISPLAY MEMORY ALLOCATION, FIELD 1, 512 PIXELS/LINE RESOLUTION 31

4. DISPLAY MEMORY ALLOCATION, 256 PIXELS/LINE RESOLUTION 32

5. ALPHANUMERIC MESSAGE STORAGE ALLOCATION IN DISPLAY MEMORIES 33

6. CPU/ALPHANUMERIC PAGE MEMORY ORGANIZATION 34

7. EXPANDED ALPHANUMERIC PAGE MEMORY ALLOCATION 34

P. MCM 6571AL DISPLAY PATTERN TABLE, SHIFTED ASCII CHARACTERSAND GREEK 35

Page

9. MCM 6574L DISPLAY PATTERN TABLE, MATH SYMBOLS AND PICTURES 35

Al. MAP DISPLAY MODE STATE TABLE 36

Bl. MAP VIDEO PROM TRUTH TABLE 37

FIGURES

1. Digital to Video Converter 432. Block Diagram of Display System 443. Simplified Block Diagram of Digital to Video Converter 454. Singer Kearfott Computer - Digital to Video Converter

Interface, for Operation with CPU 465. Map Display Format, 512 Pixels/Line Resolution 476. Map Display Format, 256 Pixels/Line Resolution 487. Alphanumeric Page Display Format, 64 Characters/Line,

15 Lines 49

8. Alphanumeric Message Data Word Format as Stored in DisplayMemory 49

9. Alphanumeric Character Data Format 50

10. Alphanumeric Character Dot Matrix Display Format 50

Al. Singer Kearfott Computer - Digital to Video Converter, Inter-face, for Operation with Temporary CPU 51

A2. Temporary CPU Block Diagram 52

Bl. Map Video PROM Block Diagram 53

Cl. Control Word 0, Display 54

C2. Control Word 1, Display 54

C3. Control Word 2, Memory Preset/Clear 55

C4. Control Word 3, Modify Alphanumeric Data 55

ii

AN AIRBORNE PROnfA! fABLE nIIOITAL TO VIDEO CONVFRTER

INTERFACE AND OPERATION MANUAL

INTRODUCTION

- -- This report describes the operational commands, data structure and stor-age, and interface to the Airborne Programmable Digital To Video Converter(DVC),"4wkch is shown in Figure 1. It is intended for use as a companionmanual t the hardware description report entitled An Airborne ProgrammableDigiTo Video Converter, Technical Report No. AVRADCOM TR 80-E-5.

The DVC accepts and converts data from an external digital computer intoa standard 525 line television format which can be displayed either in blackand white or color. The system was developed for night navigation/pilotaqeand nap-of-the-earth helicopter flight studies.,,

Survivability of Army helicopters under the' threat of radar-directedanti-aircraft weapons requires flying at or below tree top level during dayand night conditions. The pilot must be aware of the upcoming terrain char-acteristics. At present, low level operations are performed with the pilotdedicated to the task of piloting the vehicle. The copilot verbally informsthe pilot of upcoming terrain from hand-held maps. At night, this is ex-tremely difficult. Improving the method of informing the pilot of approachingterrain, thus reducing the hazards of low level night flight, are the desiredgoals of this project.

The design goal was to develop a general purpose computer-driven displaywhose information content and control functions could be determined by soft-ware. Contour maps displaying up to 16 shades of grey or color and variousaircraft symbology were the two main items to be displayed."

DESCRIPTION OF DISPLAY SYSTEM

Figure 2 is a block diagram of the Airborne Display System showing thelocation and functional interface of the Digital to Video Converter. Thedisplay system is under control of a Singer Kearfott SKC 2000 computer. Thecomputer generates the map data base based upon the selected operation pro-gram and the aircraft sensor inputs. A typewriter terminal is used as aninterface with the system operator for control and status information. Mapand alphanumeric data are entered into the converter via the SKC Computer Busconsisting of a 32-line data bus, a 16-line address bus, and a 9-line controlbus. The computer can also read data from the converter along with the con-verter status information. Under computer control, the converter will displaythe map and alphanumeric data on any combination of the three television mon-itors shown. Synchronization signals are also supplied to the monitors aswell as the other external video sources. The converter will also display ormix with the map data video from up to four external sources such as a tel-evision camera or symboloqy generation equipment upon control from the compu-ter.

I| . ... ~ i.... '- '-' ' i iB -| II *

DIGITAL TO VIDEO CONVERTER REQUIREMENTS

The converter is required to perform the following as part of anintegrated display system:

1. Be programmable from an external Singer Kearfott SKC 2000 computersystem in both data format and control function selection.

2. Provide output data which are compatible with a standard 525-lineinterlaced raster scan television format and operate with either 512 by 51?or 256 by 256 pixel/line resolutions.

3. Provide storage and operational capability for the display of mapsin 16 shades-of-grey or 8 color hues, with superimposed flight symbols, andalphanumeric characters.

4. The display memory must be available to the Singer Kearfott computerfor use as a stand alone auxiliary read/write memory when not in use fordisplay purposes.

5. Provide, under software control, synchronization to external videosources, mix external and internal video signals, and be synchronized fromexternal synchronization sources.

6. Output data selection inder software control for display on twoblack and white television monitors and/or a three gun color televisionmonitor.

7. Be packaged in an approved airborne enclosure and be capable of

being flight tested in a helicopter.

DESCRIPTION OF THE DIGITAL TO VIDEO CONVERTER

Figure 3 is a simplified block diagram of the DVC. The SKC Computer Busconsisting of 32 data lines, 16 address lines, and 9 control lines, inter-faces the converter with the host computer. The control lines consist ofhandshake and operational mode signals for controlling the flow of databetween the two units. These lines are routed to the Central Processing Unit(CPU) which controls the overall operation of the converter. The CPUcontains an 8085 microprocessor to permit versatile programmable operationof the converter. The CPU communicates with the rest of the converter viaits own CPU Bus consisting of a data, address, and control structure. Amemory for the CPU is located on the CPU Bus and contains the software anddata storage for operation of the converter. The data and address linesfrom the SKC Computer are routed to the SKC Data and Address Interface wherethey can be connected to the Input Bus data and address lines respectivelyunder control of the CPU. In the proper mode, the SKC Computer can read orwrite from the Display Memories which are also connected to the Input Bus inthe converter. This permits the computer to load map, alphanumeric, andsymbology data into the Display Memories for future display or utilize thesememories for bulk RAM storage. Five Display Memories are available in theconverter. Each memory contains 8K 32-bit words which is sufficient storage

2

A- ~~ ----

capacity to store one bit level of a 512 pixel/line by 525-line per frameraster scan television display. Four of these memories are used to storethe map data, thus permitting a 16 shades-of-grey map presentation on aconventional black and white interlaced television monitor. The fifthDisplay Memory is used for the storage of alphanumeric or flight symbol datawhich is only displayed in a black and white format. This data can beentered from the computer or can be locally generated by the converter CPU.The Input Bus Memory Controller provides two functions. The first is togenerate the necessary timing and interface signals for the Display Memorieswhen they are accessed by either the SKC Computer or CPU via the Input Bus.The second is to provide an 8-bit to 32-bit data bus interface along with anaddress interface to permit the CPU to access the Display Memories. TheDisplay Memories also have an additional port to the Display Bus. TheDisplay Bus is primarily used by the Map Generator to read data from theDisplay Memories for display. The CPU determines the bus, Input or Display,to which each of the five individual Displav Memories is connected, Thus, itis possible to have some of the Display Memories utilized for display whilethe balance of the memories are being accessed by the SKC Computer or CPUfor the loading of new data. The Display Bus Memory Controller functions ina similar fashion to the Input Bus Controller except that it provides timing,data, and address access functions for the CPU and Map Generator for accessof Display Memories via the Display Bus. The Map Generator reads data fromthe Display Memories, formats the data, and provides the necessary timingsignals for the display of maps and symbology on a television monitor. TheMap Generator contains a programmable cathode ray tube (CRT) controllerwhich is accessed by the CPU to permit operation in a wide variety of modes.The Alphanumeric Generator permits the converter to display alphanumericmessages on the television monitors. These messages can be generated by theCPU or entered from the SKC Computer to the Display Memories where they areaccessed by the CPU for display via the Alphanumeric Generator. The outputfrom the Alphanumeric and Map Generators are fed to the Video Mixer fortransmission to two black and white television monitors for display. TheVideo Mixer is also under program control of the CPU for selection of theconverter output video and optional mixing of the converter video with upto four external video signals. The output of the Map Generator is also fedto the Color Generator which converts the map and symbology data into red,blue, and green color monitor drive signals for optional display in color.The Sync Distribution circuitry provides standard television synchronizationsignals for use internal to the converter and distribution to externalequipment. This circuitry under CPU control can also receive sync signalsfrom an external source for subsequent synchronization of the converter anddistribution to external equipment. The Power Supply provides all necessaryoperating potentials for the converter circuitry.

INTERFACE

The interface to the DVC is described in two parts. The first partconcerns the interface to the host Singer Kearfott Computer over which dataand control commands are transferred. The second part describes theelectrical characteristics of the various input/output (I/0) ports of theDVC.

3

a. To The Singer Kearfott Computer (SKC) 1

(1) Hardware Description

A block diagram of the SKC Computer/DVC Interface is given inFigure 4. Electrical connection is made via plug 17Jl on the front panel ofthe DVC, Figure 1. There are nine twisted pair control signals between thehost SKC Computer and the DVC to permit the computer to direct and monitorthe operation of the DVC. Differential line drivers and receivers are usedon each control line pair to provide high noise immunity. The 9614 linedriver and 9615 line receiver manufactured by Fairchild are used for thesefunctions respectively and operate at standard TTL logic levels. A threestate 32-line data bus, DBUSSKC/, is used to transfer data on a bidirectionalbasis between the computer and the DVC. The data on the bus has a negativetrue polarity and utilizes DS7835 bus transceivers manufactured by NationalSemiconductor which operate at standard TTL logic levels. A unidirectional16 line address bus, ABUSSKC/, permits the computer to specify the locationin the DVC Display Memory for the desired memory access. The address on thebus has a negative true polarity and the DS7835 bus transceivers used on thisbus are connected for operation in a unidirectional manner.

This description covers the DVC interface when the CPU board isinstalled. The DVC interface for use when the Temporary CPU board is in-stalled is described in Appendix A.

(2) Functional Operation

The function of each SKC-DVC interface signal is describedbelow. Throughout the description, SKC will refer to the SKC Computer andDVC will refer to the Digital to Video Converter.

Controls Signals

Mnemonic Description

MCLRSKC Master Clear from the SKC, clears all circuitry in the DVC

logic 1 performs a master clearlogic 0 indicates no master clear

MCRSKC Memory Cycle Request from the SKC, indicates the SKC isrequesting an access of the DVC Display Memory

logic I indicates a cycle requestlogic 0 indicates no cycle request

MCACK Memory Cycle Acknowledge from the DVC, indicates to the SKC thata requested access of the Display Memory is in progress

logic 1 indicates a cycle acknowledgelogic U indicates no cycle acknowledge

4

The MCACK goes to a I upon the beginning of the memory cyclerequest service and is terminated by MCC

MCC Memory Cycle Complete from the DVC, indicates to the SKC that arequested access of the Display Memory is complete

logic I indicates completion of the memory cycle

logic 0 indicates the memory cycle is in progress

The MCC isa pulse of approximately 200 ns in length

DPSKC Data Processed from the SKC, indicates to the DVC that the datafrom the DVC has been accepted by the SKC after a Display Memoryread cycle is complete.

logic I indicates the data has been accepted the SKC

logic 0 indicates the data is being processed

The DPSKC is a pulse of approximately 500 ns in length

WRITSKC Memory Write Command from the SKC, determines if the DisplayMemory cycle requested is in the read or write mode

logic 1 indicates a memory write cyclelogic 0 indicates a memory read cycle

OMREQ Operational Mode Request from the SKC, indicates that the SKCrequesting a change in the operational mode of the DVC. Thissignal sets an interrupt request to the DVC CPU which will beserviced by the CPU when the present operating routine can beinterrupted. The CPU will then fetch and execute the instructionspecified by the Control Words stored in Display Memory I b, t!nSKC.

logic I indicates a OMREQ is presentlogic 0 indicates the OMREQ is off

OMACK Operational Mode Acknowledge from the DVC, indicates to the SKCthat an OMREQ has been received and is being serviced

logic I indicates the OMACK is presentlogic 0 indicates the OMACK is off

The OMACK will go to a 1 while the OMREQ is being serviced andreturn to 0 upon completion of service.

DMARDY Direct Memory Access (DMA) ready from the DVL, indicates to theSKC that the DVC is ready for a DMA operation. The DVC mustpresently be instructed to enter the DMA mode via a Control Wordfrom the SKC. The PMARDY indicates to the SKC when the DMA set-upis complete.

5

logic I indicates tthe DMARDY is present

logic 0 indicates the DMARDY is off

Data Bus

DBUSSKC/ A 32-line bidrectional bus used for the transfer of databetween the SKC and the DVC. The polarity of data on the busis negative true.

Address Bus

ABUSSKC/ A 16-line unidirectional bus from the SKC to the DVC which isused specify the Display Memory location for an access request.The polarity of the address on the bus in negative true.

b. Input/Output (I/0) Characteristics

All I/0 connections to the DVC are made from the front panel,Figure 1. The synchronization outputs, Horizontal Drive, Vertical Drive,and Composite Sync each have five outputs for driving external equipment atthe standard EIA voltage output levels. The external synchronization inputsprovide the capability to synchronize the DVC from an external source.There are two voltage levels for these inputs, TTL positive true levels forhorizontal and vertical drive, and standard EIA levels for horizontal drivevertical drive and composite sync. The external sync inputs are selectableunder software control form the host SKC Computer as described in AppendixC. There are four external video inputs which are also selectable undersoftware control (see Operation Section and Appendix C) from the SKC Computerfor mixing with the DVC video. There are also video outputs for the blackand white (B/W) monitors 1 & 2 and the three color drive signals for a colormonitor. All video I/0 signals operate at standard 0-to I-volt video levels.The prime power consisting of 28 VDC at 5 amperes for the DVC circuitry and120 volts AC at 400 Hz for the cooling fans enters through receptacle 17J6.A ground connection and six test points are provided to monitor the majorinternal power supply voltages for diagnostic purposes.

DATA STORAGE

a. Description

The organization of memory within the DVC is shown in Table 1.The address locations OOOOH to 5800H are reserved for the CPU within theDVC and are not accessible by the SKC Computer. This data field width is8 bits (I byte). The address locations OOOOH to 57FFH contain 22k bytes ofultraviolet erasable programmable read only memory (EPROM) which containthe DVC system operating program for the CPU. This portion of the memoryutilizes 2716 EPROM integrated circuits which must be externally programmedfrom appropriate EPROM programming equipment. The addresses 5800H to5BFFH contain 1k bytes of random access memory (RAM) for use by the CPU forthe temporary stirage of operational data and computations. This sectionof the memory utilizes 2114 static RAM integrated circuits. The ncxt block

6

of memory, addresses 5COOH to 5FFFH, contain ik bytes of RAM utilized for

the Alphanumeric Page Memory. The page memory can only be written into bythe DVC CPU and is used to store the alphanumeric message presently beingdisplayed. This section of memory utilizes 2114 static RAM integratedcircuits. The five Display Memories comprise addresses 6000H through FFFFH.Each Display Memory contains 8k addresses and has a 32-bit (4 byte) datafield width. These five memories are used to store both symbolic and shades-of-grey map data for display and are accessible from both the CPU and SKCComputer. These memories utilize 2108 dynamic RAM integrated circuits.

b. Display Memories

Data is written or read from the Display Memories by the SKC Computervia the 32-line data bus (DBUSSKC/) at the location specified on the 16 lineaddress bus (ABUSSKC/) from the SKC Computer as shown in Figure 3. Theaddress allocation for each Display Memory is shown in Table 1. Upon commandfrom the SKC Computer, the DVC CPU can also access the Display Memories viathe Input Bus Memory Controller. In the Display Mode, the Display Memoriesare utilized for display purposes and can not be accessed by the SKC Computer.Upon display, each data word is shifted out of the respective memory in aserial fashion such that bit I is accessed first and bit 32 last. DisplayMemory 1 is used to store black and white (B/W) data such as flight symbols,contour lines, or alphanumeric characters generated by an external source.The converter can be externally programmed (see Operation Section andAppendix C) to inset onto the display background either a white or a blacktrace when a logical "I" is read from this memory. The white and the blackintensity levels are set by hardware internal to the DVC. Data fromDisplay Memories 2-5 contains the map shades-of-grey information and isrouted to addresses AO - A3 respectively of the Map Video PROM. Thus,Display Memory 2 is the least significant bit and Display Memory 5 is themost significant bit of the map display brightness. The additional PROMaddresses A4 - A7, which are supplied by the CPU, determine the mapping modeof the DVC which is described in more detail in Operation Section andAppendices B and C.

(1) Map Data Storage Format for 512 Pixels/Line Resolution

In the 512 pixels/line operating mode, raster scanning isperformed in an interlaced pattern. Field 0 is the even field. Duringscanning of this field, 240 even numbered scan lines, No 0, 2, 4, to 478respectively are displayed. During the alternate odd field, Field 1, the240 odd numbered scan lines, No 1, 3, 5, to 479 respectively are displayed.Figure 5 is the map display format showing the order and location of thedisplayed memory words. The Display Memory allocation for Field 0 is shownin Table 2, and the allocation for Field I in Table 3. The odd field is thefirst displayed field upon initialization of the display.

(2) Map Data Storage Format for 256 Pixels/Line Resolution

In the 256 pixels/line operating mode, identical display datais presented for both the first displayed field, Field 0, and again for thealternate field, Field 1. Figure 6 is the map display format showing theorder and location of the displayed memory words on a field basis. TheDisplay Memory allocation for this mode of operation is shown in Table 4.

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• ; , , .09

(3) Alphanumeric Message Storage

In addition to the storage of map data, each of the fiveDisplay Memories contains a storage allocation for two alphanumericmessages for a total of 10 messages. These messages each have the 64characters/line, 15-line display format of Figure 7 and are called aLower Alphanumeric Message and an Upper Alphanumeric Message respectively.These messages are intended to be used for labeling or prompting purposesby the host SKC Computer. The source data for these messages is writteninto the Display Memories by the SKC Computer in the same 4-byte wordformat and manner as the map data. The storage allocation for thesemessages in the Display Memories is shown in Table 5. Addresses MOOOH toNDFFH are utilized for map data storage only. The next 240 words, addressesNEOOH to NEEFH, contain the Lower Alphanumeric Message and the Upper Alpha-numeric Message is located at addresses NFOOH through NFEFH in each DisplayMemory. The data format for each SKC Computer word in the alphanumericmessage is shown in Figure 8. Each word is divided into four bytes. Eachbyte specifies one alphanumeric character, hence, each SKC Computer wordspecifies four (4) alphanumeric characters. The lowest order character isspecified by byte 0 and the highest order character by byte 3. Upon ControlWord command (see Appendix C, either Display, Modify Alphanumeric Data)from the SKC Computer, a message can be selected by the DVC CPU and writteninto the Alphanumeric Page Memory for display. The messages in the DisplayMemories may also be selectively cleared by utilizing the Memory Preset/Clear Control Word from the SKC Computer.

c. CPU Memory Allocation

The CPU memory allocation contains a total of 24k bytes of memory.The field width is one byte/word. The CPU memory allocation is containedin addresses OOOOH to 5FFFH as shown in the DVC Memory organization ofTable 1. A further breakdown of the CPU memory is given in the CPU/Alpha-numeric Page Memory organization of Table 6. There is 6k bytes of EPROMmemory available at addresses OOOOH to IFFFH for storage of the DVC SystemOperating Program for the CPU. The EPROM memory consists of three (3)2716 EPROMs which are manufactured by Intel and are located in sockets onthe CPU memory board. The 2716s must be externally programmed on a suitablemicroprocessor development system. The 16k bytes of memory, addresses2000H to 57FFH, are not used at this time but can be hardwired at a futuretime to accommodate a combination of EPROM and RAM memory. There is 1kbytes of static RAM memory at addresses 5800H to 5BFFH which is availablefor temporary storage by the CPU during the execution of the SystemOperating Program.

d. Alphanumeric Page Memory Organization and Display Format

The Alphanumeric Page memory organization is shown in the lowerportion of Table 6. The 960 bytes of RAM memory at addresses 5COOH to5FBFH are locations of the Alphanumeric Page. The data field width is onebyte/word. The 64 addresses at 5FCOH to 5FFFH are also part of the Alpha-numeric Page but are not displayed. The displayed location of each data

8

. .... .... .. . .. . . ... _. ,a ,. . i,,* .. - , ,. . . . . .... , ''''"

" = . . . " , .. .. .

line and character is shown in the Alphanumeric Page display format ofFigure 8. The expanded Alphanumeric Page memory map with the memorylocation of each data line and character is given in Table 7. Each byte ofthe page stores one (1) alphanumeric character for display and has the dataformat shown in Figure 9. Note that bit 7 of each byte contains the char-acter generator ROM select code. An 0 specifies the MCM6571AL Shifted ASCIICharacters and Greek ROM, and a 1 specified the MCM6574L Math Symbols andPictures ROM. Data bits 0-6 correspond to ROM addresses AO-A6 respectively.Both ROMs are manufactured by Motorola and the display pattern tables foreach are given in Tables 8 & 9 respectively. The alphanumeric characterdot matrix display format is given in Figure 10.

CONTROL WORDS

Four Control Words are used to direct the operation of the DVC from thehost SKC Computer. The desired Control Word(s) are four bytes in width andare written into a non displayed section of Display Memory 1 by the SKCComputer when the Display Memories are made available to the computer forupdating. There are two storage locations for the Control Words:

Address No Memory Location

0 7FFOH1 7FF1H

When a single Control Word operation is requested by the computer, theControl Word must be written into memory location 7FFOH. For operationsrequiring two Control Words such as Display, Control Word 0 is writteninto location 7FFOH and Control Word 1 is written into location 7FFIH. Abrief discussion of each Control Word is given below. A detailed operationaldescription of each Control Word is given in Appendix C.

Control Words 0 & 1, Display Function

These two words set the DVC operational status in the display mode.They control the map, B/W symbology, and alphanumeric page display functionsalong with the external video mixer.

Control Word 2, Memory Preset/Clear

This word presets/clears all or segments of the DVC memory.

Control Word 3, Modify Alphanumeric Data

This word reads a selected message from the Display Memory andwrites the message into the Alphanumeric Page Memory.

OPERATION

a. Initialization

1. Prior to DVC power turn-on, all control lines should be placedin the logic 0 state to prevent the DVC from inadvertently performing anuninstructed operation after initialization.

9

2. Turn power on to the DVC, 28 VDC and 120 VAC 400 Hz.

3. Clear the DVC by setting MCLRSKC to a logic I and return to alogic 0 or push the MANCLR button located on the front panel of the DVC.The DVC will clear all circuitry and perform an initialization routine.After the initialization, all DVC Display Memories will be available to theSKC to accept data, and a OMACK will be sent to the SKC to indicate thatthe initialization is complete and the SKC may now enter data into theDisplay Memories.

b. FAM Memory Mode

The Display Memories in the DVC can be used as an auxiliary RAMmemory of 40 k words (4 byte word length) for the SKC Computer when operatedin the following manner:

Write Mode--To write data from the SKC into the DVC Display Memories:

1. Set WRITSKC to a logic I2. Place the data word on DBUSSKC/3. Place the memory address on ABUSSKC/4. Set the MCRSKC to a logic 15. The DVC will respond with a MCACK transition from a logic 0 to

a logic 1 to acknowledge the memory cycle request. The SKC maynow return MCRSKC to a logic 0.

6. The DVC will give a MCC transition from a logic 0 to a logic Ito indicate when the memory cycle is complete. MCACK and MCCwill then be returned to a logic 0.

7. The SKC can now write the next word into the DVC Display Memory.

Read Mode--To Read data from the DVC Display Memories to the SKC Computer:

1. Set WRITSKC to a logic 02. Place the desired address location on the address bus, ABUSSKC/3. Set the MCRSKC to a logic 14. The DVC will respond with a MCACK transition from a logic 0 to

a logic I to acknowledge the memory cycle request. The SKC maynow return MCRSKC to a logic 0.

5. The DVC will give a MCC transition from a logic 0 to a logic 1to indicate that the memory cycle is complete, and the memorydata is on the data bus, DBUSSKC/. The MCACK will then bereturned to a logic 0.

6. The DVC will hold the data on the DBUSSKC/ until a DPSKC isreceived from the SKC Computer to indicate that the data hasbeen retained by the computer. Upon receipt of the DPSKC, theDVC will release the DBUSSKC, and return MCC to a logic 0.

c. Display Mode

1. Initialize the DVC using the procedure of section a. above.2. Load data from the SKC into the DVC Display Memories. This is

done in following sequence:

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(1) Set WRITSKC to a logic 1(2) Place the data word on DBUSSKC/(3) Place the memory address of ABUSSKC/(4) Set the MCRSKC to a logic I(5) The VC will respond with a MCACK transition from a logic

0 to a logic to acknowledge the memory cycle request. TheSKC may now return MCRSKC to a logic 0.

(6) The DVC will give a MCC transition from a logic 0 to alogic I to indicate when the memory cycle is complete.MCACK and MCC will then be returned to a Ionic 0.

(7) The SKC can now write the next word into thi DVC DisplayMemory.

3. Load data in the format of the two Display Control Words 0 & 1into DVC Display Memory 1 at locations 7FFOH and 7FFIH re-spectively using the procedure of step 2. The functionalformat of these two Control Words is given in Appendix C.

4. Set OMREQ to a logic 1 to initiate the display turn-on. TheDVC will turn-on the display in the mode specified by theDisplay Control Words and respond with a OMACK transition froma logic 0 to I when turn-on procedure has been completed. TheSKC must then return OMREQ to a logic 0.

5. Set OMREQ to a logic I when it is desired for the DVC to leavethe display mode. The DVC will extinguish the map display andleave on the alphanumeric and external video mixer functions asinstructed in the Display Control Words 0 & 1, make all DVCDisplay Memories available to the SKC for updating, and respondwith a OMACK transition from a logic 0 to 1. The SKC must thenreturn OMREQ to a logic 0.

6. The SKC can then update the DVC Display Memories usinq the above

steps 2-4.

d. DVC Memory Preset/Clear

1. When the Display Memories are available to the SKC for access,the SKC writes into memory location 7FFOH data to perform thedesired memory preset/clear functions in accordance with theformat of Control Word 2 of Appendix C.

2. Set the OMREQ to a logic 1 to initiate the memory preset/clearfunction. The DVC will respond with a OMACK transition from alogic 0 to a logic 1 when the task is finished. The SKC mustthen return OMREQ to a logic 0.

e. Modify Alphanumeric Data

1. When the Display Memories are available to the SKC for access,the SKC writes into memory location 7FFOH data to perform thedesired modification of the alphanumeric data in accordance withthe format of Control Word 3 of Appendix C.

11

2. Set the OMREO to a logic I to initiate the modify alpha-numeric data function. The DVC will respond with a OMACKtransition from a logic 0 to a logic 1 when the task isfinished. The SKC must then return OMREQ to a logic 0.

12

.r

APPENDIX A

TEMPORARY CENTRAL PROCESSING UNIT (TCPU)

a. Introduction

The function of the TCPU is to provide an interface with the SKCComputer and a subset of control functions to permit limited operation ofthe DVC in the absence of the full microprocessor based CPU. The TCPU isintended to be utilized on a temporary basis until the full CPU is available.The TCPU will provide the following operational functions upon command fromthe SKC Computer:

(1) Initialization of the DVC to the following conditions:

I. Display of maps on monitor 12. Display of white contours or symbology on a black background

on monitor 23. Synchronization set to internal4. Resolution selectable from the SKC Computer to either 256

pixels/line or 512 pixels/line

(2) Display of maps in the following modes, selectable from theSKC Computer:

1. Eight (8) shades-of-grey (SOG) on a B/W monitor or eightcolor hues/intensities on a color monitor

2. Sixteen (16) SOG on a B/W monitor3. A sliding grey scale consisting of an 8 SOG map presentation

selected from the 16 SOG map data base

b. Hardware Description

A block diagram of the TCPU is shown in Figure A2. The TCPU containsa 4-bit counter which forms the lower four addresses of the data and addressPROMs. The outputs of these PROMs are routed through bus drivers to the CPUData Bus, DBUSCPU, and the CPU Address Bus, ABUSCPU, respectively. Thehigher order addresses for the PROMs are derived from the SKC computer inter-face based on the status of the control signals from the SKC. There is adivide by ten clock circuit which advances the counter and clocks thecounter control logic. The counter control logic permits the TCPU to performtwo functions, DVC initialization and setting of the map shades-of-greydisplay mode depending upon the logic level of the INIT/SHA signal from theSKC. In initialization mode, upon receipt of a trigger from the SKC, thecounter advances through all 16 states which produces the necessary data,addresses from the PROMs and the I/O strobe, (I/O)/, to set the controlregisters in the DVC to perform in the desired display mode and turn-on ofthe display. In the shades-of-grey mode, the counter is advanced one statefor each trigger received from the SKC which results in the data, address,and I/O strobe necessary to set the next shades-of-grey map display mode.

13

* **-.*-

Clear circuitry is provided which permits the DVC to be cleared either bythe SKC via MCLRSKC or manually through the MANCLR. There is also memorycycle logic to provide the interface signals between the SKC and theDisplay Memories in the DVC. The DISP/LOAD signal permits the DisplayMemories to be placed on the Display Bus for the display of maps andsymbology or on the Input Bus for the accessing of the Display Memoriesfrom the SKC.

c. Interface to Singer Kearfott Computer (SKC)

The TCPU uses a modified interface which is shown in Figure Al.The control and bus signals use the same type of logic circuitry as the CPUinterface which is described in the main body of the report. The functionof each of the SKC-DVC interface signals is described below. Throughoutthe description, SKC will refer to the SKC Computer and DVC will refer tothe Digital to Video Converter.

Control Signals

Mnemonic Description

TRIGGER TCPU operational trigger signal from the SKC. When the INIT/SHA signal is in the initialize mode (logic 1), the presenceof a TRIGGER will initiate the initialization process. Whenthe INIT/SHA signal is in the shades mode (logic 0), eachtrigger command will advance the TCPU circuitry to displaymaps in the next shades-of-grey display state as shown inTable Al.

logic 0 to 1 transition performs the trigger operation

INIT/SHA The initialize/shades signal from the SKC. A logic 1 placesthe TCPU in the initialize mode. A logic 0 places the TCPUin mode which determines the shades-of-grey display mode inaccordance with Table Al.

RESOL Resolution select from the SKC

logic 0 selects 256 pixels/linelogic 1 selects 512 pixels/line

SYMBRIT Symbol brightness select from the SKC

logic 0 selects black symbolslogic 1 selects white symbols

MCLRSKC Master Clear from the SKC, clears all circuitry in the DVC

logic 1 performs a master clearlogic 0 indicates no master clear

14

No

MCRSKC Memory Cycle Request from the SKC, indicates the SKC isrequesting an access of the DVC Display Memory

logic 1 indicates a cycle requestlogic 0 indicates no cycle request

MCACK Memory Cycle Acknowledge from the DVC, indicates to the SKCthat a requested access of the Display Memory is in progress

logic I indicates a cycle acknowledgelogic 0 indicates no cycle acknowledge

TheMCACK goes to a 1 upon the beginning of the memory cyclerequest service and is terminated by MCC

MCC Memory Cycle Complete from the DVC, indicates to the SKCthat a requested access of the Display Memory is complete

logic I indicates completion of the memory cycle

logic 0 indicates the memory cycle is in progress

The MCC is a pulse of approximately 200 ns in length

DPSKC Data Processed from the SKC, indicates to the DVC that thedata from the DVC has been accepted by the SKC after a VDisplay Memory read cycle is complete

logic I indicates the data has been accepted by the SKC

logic 0 indicates the data is being processed

The DPSKC is a pulse of approximately 500 ns in length

WRITSKC Memory Write Command from the SKC, determines if the DisplayMemory cycle requested is in the read or write mode

logic 1 indicates a memory write cyclelogic 0 indicates a memory read cycle

DISP/LOAD Display/Load control signal from the SKC

logic 1 places all Display Memories in the display modelogic 0 places all Display Memories in a load mode in which

the SKC can access these memories

Data Bus

DBUSSKC/ A 32 line bidirectional bus used for the transfer of databetween the SKC and the DVC. The polarity of data on the busis negative true.

15

I

Address Bus

ABUSSKC/ A 16 line unidirectional b-s from the SKC to the DVC which isused specify the Display Memory location for an access request.The polarity of the address is negative true.

d. Digital to Video Converter Operation with the TCPU Board

The following sequence is to be used for the operation of the DVCfrom the SKC Computer when the TCPU board is used in place of the micro-processor based CPU board. The referenced mnemonics refer to the interfaceof section c above.

1. Prior to the turn-on of power to the DVC, the TRIGGER andMCREQSKC lines from the SKC should be set to logic 0. Thisis to prevent any inadvertent operation of the DVC after thereset is complete.

2. Turn primary power on to the DVC, 28 VDC and 120 VAC 400 Hz.

3. Clear the DVC Circuitry by setting MCLRSKC to a logic I andreturn to a logic 0, or by pushing the MANCLR button on the DVCfront panel.

4. Set DISP/LOAD to a logic 0. This makes all 5 DVC DisplayMemories available to the SKC for the loading of display data.

5. Load data into the DVC Display Memories from the SKC Computer.

6. Set DISP/LOAD to a logic 1. This places all 5 DVC DisplayMemories in the display mode.

7. Set RESOL to determine the map display resolution:

logic 1 for 512 pixels/linelogic 0 for 256 pixels/line

8. Set INIT/SHA to a logic 1. This places the DVC in theinitialization mode.

9. Give the TRIGGER a logic 0 to 1 transition and return to alogic 0. This initiates the initialization routine internalto the DVC.

10. Set INIT/SHA to a logic 0. This places the DVC in a mode todetermine the map shades-of-grey (SOG) display presentation.To set the SOG mode, a counter internal to the DVC is advancedone state for each logic 0 to 1 transition of the TRIGGER line.The TRIGGER line should be returned to a logic 0 after eachadvancement of the counter. At least one TRIGGER command isrequired to turn the map display on. The state table for the

16

SOG operation is given in Table Al. An explanation of themap display modes and video truth table is given in Appendix B.If it is desired to change the SOG display mode while thedisplay is in progress, the required number of TRIGGER commandscan be given by the SKC to advance the SOG counter in the DVCto the desired map display state.

11. If the display does not come on in a satisfactory manner, clearthe DVC with a MCLRSKC command or by pushing the MANCLR button,and repeat this operating routine starting at ftep 8.

12. To stop the display, give the DVC a MCLRSKC command or pushthe MANCLR button. This will halt the display but will notalter the contents of the Display Memories in the DVC.

17

APPENDIX B

MAP VIDEO PROGRAMMABLE READ ONLY MEMORY (PROM)

The Map Video PROM (Figure B1) performs a digital mapping functionbetween the four lines of input data and a four line video output. Themapping mode is determined by the state of the four control lines which areset by the CPU within the DVC. Various map display modes are available tothe system operator who can select under software control the desired modefrom the host SKC Computer. There are three basic modes of map displaywhich are described in paragraphs a-c below. A truth table which describeseach logic function is given in Table B1. Note that each operating modecontains the video output mapping function for all 16 states of the input fdata. Addresses AO - A3 (data inputs) are connected to the data outputsfrom Display Memories 2 - 5 respectively. Addresses A4 - A7 (control lines)are the output bits 1 - 4 of the CPU Digital Display Register and are usedto specify the mapping mode. The PROM outputs 00 - 03 drive the videodigital to analog (D/A) converter within the DVC which provides the analogvideo output. 00 is the least significant converter bit and 03 is the mostsignificant bit. A logic 1 on any of the four converter input lines corres-ponds to increasing the video output brightness.

a. Eight (8) Shades-of-Grey (SOG) Video

The mapping function for the eight SOG mode is defined by addressesO - 15 Table B1 and is repeated in addresses 16 - 111. The data fromDisplay Memories 3 - 5 is directly transmitted to PROM outputs 01 - 03 toprovide 8 video output states. The data from Display Memory 2 has no effecton the PROM output. A logic 0000 output is the darkest video state and alogic 1110 is the brightest -state.

b. Sixteen (16) Shades-of-Grey (SOG) Video

The 16 SOG mode is defined by addresses 112 through 127 of Table B1.There is a direct correspondence between the address inputs AG - A3 andoutputs 00 - 03 to provide 16 video output states,

c. Eight (8) Shades-of-Grey (SOG) Sliding Grey Scale Video

The 8 SOG sliding grey scale is defined by addresses 128 to 255 ofTable B1. Under the sliding grey scale operation, there are 8 modes eachof which provides a distinct mapping correspondence between the 16 statesdefined by the four data address lines, AG - A3, and an 8 SOG video outputon lines 01 - 03. This mode of operation is used to provide increasedcontrast range over portions of a displayed map which would normally bedisplayed in the 16 SOG mode. In this mode of operation, the display modewould first be selected by the CPU over address lines A4 - A7. If mode 0was selected (addresses 128 - 143), the lower 8 states of a 16 SOG displayformat which constitute approximately 1/2 the brightness dynamic range are

18

mapped to 8 new SOGs which comprise the full dynamic range of videobrightness output for expanded contrast range. The seven other slidinggrey scale modes of operation each performs a similar furction on an 8successive state segment of a 16 SOG map.

19

...... , ,,I .

APPENDIX C

CONTROL WORDS - FUNCTIONAL DESCRIPTION

This appendix gives a complete description, in paragraph a-c below,of the Control Words used to direct the operation of the DVC from the hostSKC Computer. A total of four words are used to perform the controlfunction, and tkeir mode of entry and storage in the DVC is described inthe main body of the report.

a. Control Words 0, 1 Display Mode

These two words set the operational status of the DVC when operatingin the display mode.

Definition of Control Word Elements for Control Word 0, (Figure CI)

Byte 0

Bits 0-3 Control Function Select must be 0000 to indicate first ControlWord for Display function.

Bit 4 Synchronization Select

0 = External Synchronization1 = Internal Synchronization

Bit 5 Resolution Select

0 = 256 pixels/line1 = 512 pixels/line

Bit 6 Symbol Brightness

0 = Black symbols/alphanumerics1 = White symbols/alphanumerics

Bit 7 Not used

Byte I

Bit 0 Determines if Monitor 1 External Video Mixer Sources are to beleft on when map is turned off.

0 = External Video Mixer Sources to be turned off1 = External Video Mixer Sources to be left on

Bits 1 - 6 Monitor I Display Memory Select for B/w Mode

20

Displa X Memory Select Display Status

(Bit No)

654321

o 0 0 0 0 0 No Memories Displayed (blank screen)

0 0 0 0 0 1 Display Memory 1

00 0 0 10 Display Memory 2

0 0 0 1 0 0 Display Memory 3

0 0 1 0 0 0 Display Memory 4

0 1 0 0 0 0 Display Memory 5

1 0 0 0 0 0 Display Alphanumeric Page

The Display Memories may be selected in any combination, for example:

0 1 0 0 1 0 Displays the contents of Memories2&5

Bit 7 Not used

Byte 2 - External Video Mixer Select

Video Mixer Select Video Mixer Status

Bit No

321 0 (bit number, for Monitor 1)

76 5 4 (bit number, for Monitor 2)

0 0 0 0 No External Video

0 0 01 External Source 1

0 0 10 External Source 2

010 0 External Source 3

1 0 0 0 External Source 4

External Sources can be selected in any combination, for example:

1 0 01 selects sources l and 4

21

MEMELZ-

Byte 3

Bit 0 Determines if Monitor 2 External Video iixer Sources are to be lefton when map is turned off

0 = External Video Sources to be turned off1 = External Video Sources to be left on

Bits I - 6 Monitor 2 Display Memory Select for B/W Mode

Use the same truth table as Monitor 1 Display Memory Select forB/W Mode.

Definition of Control Word Elements for Control Word 1, (Figure C2)

Byte 0

Bits 0 - 3 Control Function Select

Must be 0001 to indicate second Control Word for Display Function

Bits 4 - 7 Not Used

Byte 1

Bit 0 Not Used

Bits 1 - 4 Shades of Grey Select Code for map presentation

Bit No Shades of Grey Mode

4 3 2 1

0 X X X 3 Shades of Grey

1 0 0 0 4 Shades of Grey Mode 0

1 0 0 1 Shades of Grey Mode l

1 0 1 0 Shades of Grey Mode 2

1 0 1 1 Shades of Grey Mode 3

1 1 0 0 Shades of Grey Mode 4

1101 Shades of Grey Mode 5

1 1 1 0 Shades of Grey Mode 6

111 iShades of Grey Mode 7

See Map PROM Truth Table for more detail on each map mode

22

Bit 5 Display Map on Monitor I

0 = NO1 = YES

Bit 6 Display Map on Monitor 2

0 = NO1 = YES

Bit 7 Determines the display status of the Alphanumeric Page forMonitor 1 when the map is turned off

0 = turn off Alphanumeric PageI = turn on Alphanumeric Page

Byte 2

Bit 0 Determines the display status of the Alphanumeric Page forMonitor 2 when the map is turned off

O = turn off Alphanumeric PageI = turn on Alphanumeric Page V

Bit 1 Update Alphanumeric Page

0 = NO1 = YES

NOTE: Alphanumeric Page is updated prior to display of map.

Bit 2 Message select for updating Alphanumeric Page

0 = lower Display Memory Message1 = upper Display Memory Message

Bit 3 - 7 Update Source Display Memory for Alphanumeric Page Update

Bit No Display Memory Select

7 6 5 4 3

0 0 0 0 1 Display Memory I

0 0 0 1 0 Display Memory 2

0 0 1 0 0 Display Memory 3

0 1 0 0 0 Display Memory 4

1 0 0 0 0 Display Memory 5

23

Byte 3

Bit 0 Clear Alphanumeric Page

0 = NO1 = YES

NOTE: Alphanumeric Page is cleared upon map display turn-off

Bit 1 Preset Display Memory

O =NO1 = YES

NOTE: Display Memories are preset upon map display turn-off

Bit 2 Display Memory Preset Data

0 will write Os into selected Display Memories1 will write ls into selected Display Memories

Bits 3 - 7 Display Memory select for preset

Bit No Display Memory Select

76543

00001 1

00010 2

00100 3

01000 4

10000 5

Display Memories can be selected in any combination for preset,for example 1 0 0 0 1 selects Display Memories I and 5 for preset.

b. Control Word 2, Memory Preset/Clear

This control word presets/clears selected memories within the DVC.

Definition of Control Word Elements (Figure C3)

Byte 0 and Byte 1

Bits 0 - 3 Control Function SelectMust be 0010 to indicate memory preset/clear function

24

Bit 4 Clear Alphanumeric Page

0 = NO1 = YES

Bit 5 Resolution Select for presetting of Display Memories. In the256 pixels/line mode only the section of the Display Memoryrelevant to 256 pixel/line storage is preset. In the 512pixels/line mode the entire Display Memory is preset.

0 = 256 pixels/lineI = 512 pixels/line

Byte 0 Bits 6, 7) Preset Data for Display MemoriesByte 1 Bits 0-2)

Byte 1 Byte 0 Display Memory No21067

2 1

2

3

4

5

0 will place logical Os in the Display Memory

1 will place logical ls in the Display Memory

Byte I Bits 3 -7 Display Memory Select for preset

Bit No Display Memory Select76543

ft - 1

2

4

5

0 Display Memory will not be selected for preset1 Display Memory will be selected for preset

25

Byte 2

Bits 0 - 2 Not Used

Bits 3 - 7 Clears Lower Alphanumeric Message of Selected DisplayMemories

Bit No Display Memory Select76543

3

---- 4

5

0 Lower Alphanumeric Message of Display Memory will notbe selected for clearing.

1 Lower Alphanumeric Message of Display Memory will beselected for clearing.

Byte 3

Bits 0 - 2 Not Used

Bits 3 - 7 Clears Upper Alphanumeric Message of selected DisplayMemories

Bit No Display Memory Select

76543

2

3

4

5

0 Lower Alphanumeric Message of Display Memory will not beselected for clearing.

I Lower Alphanumeric Message of Display Memory will beselected for clearing.

26

c. Control Word 3, Modify Alphanumeric Data

This word modifies or clears contents of Alphanumeric PageMemory.

Definition of Control Word Elements (Figure C4)

Byte

Bits 0 - 3 Control Function SelectMust be 0011 to indicate Modify Alphanumeric Data Function

Bits 4, 5 Not Used

Bits 6 Displays contents of Alphanumeric Page Memory on Monitor 1after Alphanumeric Page update.

0 = NO1 = YES

Bit 7 Displays contents of Alphanumeric Page Memory on Monitor 2after Alphanumeric Page update.

0 = NO1 = YES

Byte 1

Bit 0 Update Alphanumeric Page Memory

0 = NOI = YES

Bit 1 Not Used

Bit 2 Message select from selected Display Memory

0 = Lower Message1 = Upper Message

27

...

Bits 3 - 7 Display Memory source for updating of Alphanumeric PageMemory

Bit No Display Memory Selected

76543I

2

3

4

5

Byte 2

Bit 0 Clear Alphanumeric Page

0 = NO1 = YES

Bits 1, 2 Not Used

Bits 3 - 7 Display Memory select for clearing of Alphanumeric messages.Both Lower and Upper Messages are cleared in each selectedDisplay Memory.

Bit No Display Memory Select76 5 4 3

1 1I! 2

3

4

5

Byte 3 Not Used

28

':GITAL TO I:DE3 CNIVERTER "'E>ORY ORGANIZATION

2DO ESS Data Field

rdr -". . -. -)a] "Aegory ,r oidth

* 31 3 1 i i: ! 1 "7

3 1 I 1 0 0 a 0 3 0 3 5 33 CPU RAM 8 Bit

* 31 13'9 li!i1i 13115F

& 1 0 1 1 1 0 1 0 0 3 0 0 3 5 2 3 ALPHANUMERIC PAGE RAM 3 Bit

& 131i 1111111 11i" 32-C-

2 1 1 j 0 0 0 0 0 0 0 0 0 0 0 5 2 ' .SPLAV 'AEYORY ! ,RAM 32 Sit

* 1 ! 1 1! I{ 11ii 11:: " -

3 1 3 3 3 0 3 3 1 3 33 1 - "E IORY 2 P M 32 Bit

F :.3 1 111 I 1i 131F

i 0 1 0 0 33 0 0 3 0 9 0 3 3 A 3 DISPLAY MEMORY 3 3RAM) 32 Bit

I 1 j 0 3 1 1 0 0 3 1 0 a 3 C 0 3 0 DISPLAY MEMOR 4 'RAM) 32 Bit

I 01 1 i I i I I I I 1 F FF

I 1 0 3 0 32 3 3 3 C3 E C 3 DISPLAY MEMORY 5 ,RAW, 32 Bit

1 1 I 1 " ' ! 1 1 F F '

NOTES:

1. CPU EPROM Memory - 22K of EPRCM is availab,a for use by the DVC. This memory storesthe DVC system operating orogram. it is accessible only from the CPU and not from theSKC Computer. This memory utilizes 2716 CPROM integrated circuits.

2. CPU RAM Memory - IK of RAM is available for use by the DVC CPU. The emory is onlyavailable to the DVC CPU for temporary storage of operational data and computations.The memory utilizes 2114 static RAM integrated circuits.

3. Alphanumeric PAge RAM Memory - 1K of PAM is 'itilized n the Alphanumeric Page Memory.It is only accessible from the DVC CPU and is used to store the alphanumeric datapresently being displayed. This memory utilizes 2114 static RAM integrated circuits.

4. Display Memories 1-5 - Each display memory consists of EK of dynamic RAM memory. Thesememories are used to store both symbolic and shades-of-grey display data. They areaccessible from both the CPU and the KC comouter. These memories utilize 2108 dynamicRAM integrated circuits.

29

T-BLE 2

)!SPLA ', ME ORY AL CA T:3'N, -1EL , 2 1 - , /L :NE E SESOL. T ,N

ADDRESS 1, 2

Disola/ Line No. *ord 'No. 3inary it No. -exadecimal

15 14 13 02 11 0 7 5 5 4 3 2 3 2

S S S J 0 0 02 0 1 M O

15 S S S 0 0 0 0 00 0 1 1 11 Y 0 1 F

0 S S S 0 0 0 00 0010 2003 002

15 S S22 0 2010 I 1 1 1 MO 2F

0 S S S 222221222000 124

15 2 S r 0122 012 1 i I 4

478 0 S S 1 1 i 0 1 1 10 0 0 0 N E

15 S S S 1 1 i01 1 i 10 1 i 1 N DEF

1. Binary address bits 13-15 (labeled SSS) form the Display Memory Select Code. TheMemory Select Codes are:

Address Bit No. Csplav Memory Selected

15 14 130 ! 11 0 2 2I '] 1

i I i5

2. The Display Memory selection is reflected in the thid digit Df the address when specifiedin a hexadecimal format. In addition, the twelfth address bit whch is part of this diitis used in the data address field. Thus to comoute the value of M or N in the tables,both the desired memory selecct code and data address must ne utilized.

30

_____________________ ~ <. ~.~ ~ -. ,

JISPL'Y "E'!ORY ALLCAT:CN, TIELD 1, 5-12 P:XELS/L:NE RESOLUTION

A,0RESS

Display Line No. .-orc N1o. 3inary Bit No. Hexadecimal15 14 1", 12 11 10 9 8 7 6 5 4 3 2 1 2 3 2 1 0

i 3 S S S 2)2)3 3 .31

15~~~~~~~ S 0' 3]]' 3 !F

SE~~ 1 5 F 2 O :1: M- F

S S " .- D1 222i 0 >1 M3552

479 1...............................'0)2! N2F K

,.;79* -... . . ... ..... '3 . NO DFF0

1. Pefer to tne footnotes cf ue 2.

31

,i

DISPLAY MEM0R QL2' 5 1 2 7 ES:LJT:DN

ADDRESS 1

:isolay Line '30. ..Ord "0. eaeln

3 2

S -I 4

D2

3 33 1' s I22 DDI D

7 S S~ ih 22 1 1 D 22E

s 2 12 E1' J

7 S SS 9 32 2 .

3 2 S 2S 2

1-39

efrto the footnotes of 273ble 2.

32

L;E: 'AEBAGE

Lir,e No. Characters E4 -. 7irary it %o. Hexadecimal

E2 14 3 72 77 70 S 3 7 6 3 3 2 7 2 3 2 3 0

,lap ata Storage', 77I '4323

5:2 Pixels/Line),Odd + Even iei9)

a-. 4_E02 - :""."i

63-50 IB i )C202 i i7 N E 0 F

1 3-0 S S S 1 D 1 0 1 010 NEBO

63-60 S S S 73 70001311: EF

I1 1 1 I 2 E F F

The 2er 4onanuweric ',essage is addressed b chancing iexadeciJal Address No. 2from an E to 3n F.

2. Refer -o tne footnotes of ALle 9.

33

~[

:2U/AL?-.AJMEL :3'r' 'z t :';::A

-RE SS

Binary Bit No. c',uela. yeior/ 'ype Availability

15 E 13 12 :110 9 3 7 65 4 3 2 2

& 3 3 3 3 3 .3 3 : 3 ~ '7:6 .r Soar:.,

-~~-r - --g a e -ec:

.3 1 0 1 3. tatic RAM n Board,-and Mired

311 1 0 3 0 33 0 3 3 :>anuneric In 7Soard,Piqne, Static In Sockets

*~ 2112

* o'n ased - Oh oard,cnner Pert -f SocketsAlonarumeric

3101z 111 111'11age

TABLE 7

EXADDALPHANUMERIC PGE7 "-EMORIY ALLO'CATIO)N

LineNo. harcterNo.ADDRESSLin N. Carcte N. irarZ Sit '%o. Hexatecivral

15 li 13 12 13:10 3 3 76 513 2 1 0 3 2 1 0

00 0 5r0 0

5001

63 50FF

34

.. . . .. . . ......

-. ~V V- * :: 33::

.... ... . .... . ....... .

TABLE 8. MCM 6571AL Display Pattern Table Shifted ASCII Charactersand Greek.

.. .. .. . .. .9 .... ... ..... . . ., , .. . . . ... ..... .... .

.I.. ......... .... ..... ..... .

TABLE 9. MCM6574L Display Pattern Table Math Symbols and Pictures.

35

TABLE Al

MAP DISPLAY MODE STATE TABLE

Trigger Commands Map Display Mode

1 8 SOG Sliding Grey Scale Mode 02 8 SOG Sliding Grey Scale Mode 13 8 SOG Sliding Grey Scale Mode 24 8 SOG Sliding Grey Scale Mode 35 8 SOG Sliding Grey Scale Mode 4

6 8 SOG Sliding Grey Scale Mode 57 8 SOG Sliding Grey Scale Mode 68 8 SOG Sliding Grey Scale Mode 7

9 8 SOG Non-Sliding Grey Scale10 16 SOG11 16 SOG12 16 SOG13 16 SOG14 16 SOG15 16 SOG16 16 SOG17 Repeat table starting with Trigger

Command 1.

36

A 1)[-1-,

mAP VIDFD PROM TRUJTH TABLE

IIA I I,( "

('I~ ~ - ~ L ftI 1111.11 11 Il' '11'Ilf-) I A1(11 A

11-1II 'It I 19IA')~~~~ APATA V011 0 I 11

Al flA IA l fi I rIIIv VIllIII t l0Il 1

/ll - 'AlA IIrI':; 0 ~ 111)1))'IAl - ) AIS C)1 11 1 0'1 lI 'l'I(A. (I)1 lf l

AS - Fl~IAPA~~ PINIlIII A rlI.1lP 'I ~IllllrlA&, M AP CIINIII S3 1 11"l MlAP I: I ITI A, I:, Il;I 0 0 1A' M.lAP CoriI7V I) F1) FI '1, , 1 Ay Ill 1I p~l I

('91 / 1,1

Atfn I I At) rI AO')'0 7! I ' Ill)I IF IIC ' ''I1

A I il 1 01 1IO f AA I 1 1 ; i l Y1 I 1 1 I I1 1 ' C I P I C I

II 03 0(11)1 1111 0 11)1( fl~' ir

D 15 f1:01( (1:0 II I'l

I P OC 001) ( 11 1 1 11 )111

(7 I) I111 P, 1'0l1

211 15 (lli I F1

22 I 1111 . C)100 II II I, 11111'

01 c7 P(11 " , 11 i ' I'l') IP4 0I 0111, 11,(1 l'~ lI5 I 9 Or10 I'' I Il'' II l

I4 It )11 IA'll 17P1 I)II

''I 1F l lt W A II ' I ' ll' It It'

1 37

R

TABLE BI - CONTINUED

An In iIFv AmIr , ml ; , I r'It r11i,,' J ,

34 21 (Fo1lS ('F0 (,,'? lrIFFlr

33 33((1 (02 ('FS FFI'(

1/ 24P ('( 0 FF,0 00I 1F FF P 'rFlF

I21 n -, (PhtO 01no ) In2FF ?l21F'(FF

-17 '7 00 0 0111 (Fl IF' to ? 'IFI

40 21 02 0 l |() TrFpIFF'F'1 F 27 OOFI 0 1 1

4.1 22 OOF( l ((t I I nI F I' '?tFr4't 20 0() ](11 I C 10 In'INT-rIr42 22 00F 2 n;0') ?.FII'IJ(

25 ;,1 0 0FF [of PrI' r1F

4" 20 0010 1 12 1 I2?1' I fIF'Fllf

49 30 00? i 00 O (FO,10 PTh F :1 VA I A I Illf11 11 t, (FA 2 F rl(

41 31 fF(12 I 0(000? (:'0,(FI1(0 '2 0021 002, 0 1,01 (r(Ilr?'tf

52 37 0,111 002? (F1 F FFF'I, 34 FF022I 0|001) 0 ?"; I 1F(P?'?l

5, 35 (FOI 0(1 olOl 4FrFlrw

5'1 36 0022 021' o120 [ilpIrr

51/, 10 ('('2 2 000 2P (F'F' U1(FFFF5? 3'? 002? 20 00) Pf l"O 2irl"57 I (002 1 0F 10F on t ?l1,"51 :3 0022 1 F010 toIF 1'"l2I

59 37 -FF:1 I I)Fl I ",tFFF tF'lFFFr60 10 oF? I I 2110 [r,(r2 -

,1 3JD 001 1 1 I I I Ut

64 4? 012010 I VI 'A IFI I1FnI)

6-5 4 I ' ~ l 0 tl nol 'I ~ r

4,F 43 1+110 (FIF FF ''''1FF 1(1(1t'? II)I ll +l lf , l",rA

I'll 41 1F o 0? (in' F.. 0I(n Ill016 41 110FF 0?(': (F In''' IFI"Ilr".

b2 4F 0 02?? Ol I n'70 47 (l' f I0 If t 1rFFTFFJI

74 41 ('110 n'1 ' 1 l I" IFIFI II"

75 47 (F P(;F? I F'F 11 ::F

-h fF FF0F1 1 I' I I",

3if

TABLE B1 - CONTINUED

AI7' 77 A | t l A llt ) , ''t I' I' a t

: !-0 o( 17"n( pt 'A'$'111 1 A I A I I t

05 5, 1 7 1-11, 77 rtt777nI 1 1 01 )1 11 II 1 01 ') ti r

(I 9 5 9 1'10 11 t 0 1l

911 51 9,',l o t I 10 7 1 n SIll+PIiI

07p 57c 0101 It'tl) It',") p1trit I07 59 (71(1 O l Oll tO ]~77 l17'lIllll It

9?0 56 (1101 1011 I1 11 illlil9 1 5Z (0101 I(71 ItlO I~l'li'PIlf

'72 5t0 0 101 1100 I Il)t Pllll-

71 IF 7101 II60 0 Ito Il l'l99; :t 0101 I lull PI'I'7 Ill IP

91, 60 - ! 1711 0000l liftt77 nIltlfi'7 l 17616^ I 100r 17 £Ill l ll 71 11,7'

97 6 1 01 10 0 (7O ''(('7' DOIM 1717tt~l 60 f 10 (010 (1 1() 11P1 I'M1"

'77 63 (7110 0( 11 1t', IP l7fl1f'IF

tOo A,4 0110 01170 (717'') tlltlll

I(It 65 11 in 0ot o 77177 l1ln'1N;

I , ,6 011; 0 0 t to In IIP ' l

10 1 67 0110 011 (110 II'I . '7 711

1174 Ill 7110 I00 I''1 t t7- +IIli!"

Ill S7 0 1 0 1.10, lo7t€' l1lll r

106 6A 0 10 1011 I n7l t II'i7l1'7

l1

1717 1,7 0 1 10 lol n"17, 1, , " IlOll AtC I l1'0 117)0 071(1 flpPIl

I 10 60 011 0(00 0t1 II IVl77l 40 1F1

1 1 7 1 0 1 1 1 0 00 1 1, 1'0 1 "ll:l I ,

114 70 011 t 0010 0 10 ll'll'tIt

115 7 3 0111 0( ('111 1 1 7irrr7 Iy

I IA 7 4 111 1 o"" (7i 0,1, Ill0llt1 47 79 0111 01 1000 )(1 PIIII('f l

I I9 77 0 11 (711 (I II n ll't'1,P1120 7n 0111 1000 110 I11l17Illl

1 79 01 111(11 101 I 0I1ItmI

I:1 7 AI II lo I 7t1 1717t1''lp r

1;1- 77 71 11 111i1 717 nlItf 'Pf

1.14 7t r 0It I 00 I 1w, ( I ' t"11-

I1 5 i n I t, l ::r:,n :,,I+I7 Ph O1Il 1 :{lI IllllI104 7it 011 1100 I11' Il7 llllti!

19 70 7) l11 I 11O1 1 ifir'lt '1!

39

_ -- ... , ... - ----. .: . . -*-'--- .1

TABLE BI CONTINUED

u,77 1)~ *7770 I I'l l(I' I'll7 I, 'I7((7( (7777

I:7 In 7 fl:,''' 1 ' 110 V Ifi 7'I I. "I 7)7* 777( 11h ( 1 771

III~~ 87 ''7, (((77 I II Ir It7 7(( (7

1n3 85 (on00 017) 1 7 r17' p5777 IIII'] @A, 0(00 OIIV 7(7 1(771115 1] 7 1000 Oil[ I 10o ill tit IF(CIA 871 10,10 10070 11177 VIA Fill1717 119 10700 100771 1It0 1171p'l'7

117 1FI7 I 100 linll I to17 7I IIF I

t42 11- 10700 110I o 11111 1 11(7 ''J

141 Rr I(0070 I I I I 17 I I (I itriFli

144 70 tool1 0000 07(7 1177(7777 4 77*1* I lilt In 17(70(77 "(IF , 77*145 91 t0ot 00701 W in(4 Pill lilt Il141, 72 100(71 00710 07(777 ti(7(7(7r f'1IF I !77 p1(7 7177 71-17 71 tool poll11lo0( IR7 1 (171(1411 94 100n1 07100 0 17 or) (7177(7149 9!) loo0t 0101 O7(( 7(7 I71(l7r1!70 96 10W71 0110 1(7( r-o 1'7(((7(P

151 77 1007101 11 Into7 M11'1111153 97 1ont001 1 17o (7(77771

113' 97 1 On71 1011 1 (7 (7 (777 77(

1 56 97' (7(00 1 It() I I 'l (((' I Fri1 -7 70 tool1 1101 1 11 (77nI1 ('lirI57 I'l 1E I1001 1110 1 1 1o 17r1(7t7t

160 AO I IF 10 (0000 0(77 50117(7(7 4 (7*1* I INI 11 717*1(17 ' ' 71 ,A,161 A I(71 0 0 0 (77(7 (7I 77lo (77itIt 7'1125 A;. 1(710 Onto 0 0,7 (7(7 l1 77 7777(77'Fi Fim in If77 m7*rIA] A I710 )11 7(7(77 V(I7I(I7II7I7164 A i 10710 0 100 nIi III7( (71777(r163) A') I(1 rI 71(71 F ' Pl (I.7 lilt(7I11h AA Winl '( o1 777 71'7 Pill7 I7(167 A'77 11)0 1 '17 1( (,7777 (1711 ii1608 A4 111 077 I I.77 571 77fti16-7 A') 17777 '777 17 'I

1 71 A7 'It'7'I 777 77771 72 AC (((777 I(7( I77 7 II I777r

1 4 1A (((17) 1 71 ll7 I 71 (7

1 75' A 1) 1",7 71 1 (( 7 7 1(

40

TABLE BI - CONTINUED

I ;4, 1 444 0 ''4'o '' , 44 !t'rltl4fr 444144144 4) 44444444, 4(44I 4444

I~~~~~~ All, 1] I 1 11 (100 tlllf04 441 4I4( 0 0 01' 1 1444A44444

Inl 1 ,1 11 0 10) i ( lll'4n1 44, I411 1 0 4.41 444 n1411414

4442 44, 4444 O4 1 0 " li 14 I4t0144F

1 "4 74 4441 4(44444 4 444444444I

1116 IA 01 ,, I' tl

I117 lt~ 101 1 I 11hi4 Il

I(44 70 1 I4 1 410 11 1(0 Pil 4 '4Il

z11 r[ 11 1. I1 I l

Ill riI*I44(0 Zr 44444 I I I I I M440r,'0

vI I 1 1 11I010 1::; I: ;r I I ' I'I I 1' I I -A

1 ?1 C I . " " ' t

, I v(II Irllll

1"1?4 (2 1ion 0folo po1) Itlltl lfr ri I W: 11 '1' 1lll rAt F44 71 74 4 O(44 4444 44444 44444444

477 C 4(441 " 0( 44 4 vI44i 4 Ill F4 74 CON 44I 4444 04444 044444 lo4' 4 44444

I 0:4 4(4 44444 0?4444 4444444444n

I C* I I Ion VilOll Ili til47( CA 014 1 0') 014 () 1) 0 0 s U -fir

()1~~ I t', 1 " fO I I (lO FI ~tI4741i CA 4400 044(4 (44444 4444444444[

403 07 14(0 44444 444 o o4444

704 I I I I 4400444440 CD 4I4 I o( I il 444444

I ) . 4440 : 11440 4 4 10 nnI'4444l

A07 C.r Xol I I I4 17 I4 4 (:fi Ii440)44f Nl! Af44444 A I 4411(4(47(44) 444.4 444 4:444440444 4'444444'r4l4'

P01 C)(4 I104 0440( (I4444 4444444(44 4 44A IA I I4 4i 11 l44T4r 4 444 y 44440

210 M,' I 1O 0 1 { n;li' 11lltfl 041i:: 1 , 1 1111. f A' I"

244 j I I40 0( 4 4444444 0 4141 44(444

044 04, 44I I 0 401 0ilt(Il 44444444444;, 2 V 1 f 9 1 ,1 if IO111 1 ri i 1i tl

:,I I D I 1 0 44 04(4,44 :i4444404(

217 D94I 444 40444 4 . 44444 444(4

!11-H DAII ! {1 l( lit 1l411l117 97 4101 I, 11) (44 4 I4't4 4 4f4

;, o r I o 1(l

ifi -I -t.7 4)7 44041 4044 44l4(4 i4444444

41

TABLE BI - CONTINUED

P;'4 FO :A I/ In Or n

,w( lllil I N f It !:IIAIIVq 1; l~ v i ar I

5 El ( 1II IIHI fWHtIMIF

P76, F, 11 00111 ("In0 MO~lllr 1lPF 1, 4zI11) 111 ',C AtF0011 FP 4 111 "0q'100 01)1 11 lr

2 7 rE I 110 111111 W lf

0:10 i4 l ,111 0110 (010) 111)I1 norF

7- 111 0 0111 (lll'l fl00llllt

P3 E 1i& 0l00 0('00 0l)l0ll001)P'3 I r I I t0 0111 ('I l) ll'' Ill')

p 1 CRt I I I0 I€O no i il ll

r, EA I I10 10 I1 ) il')

1"; FA I I0 10 I o I 11(: IlIl (i

P-1 I C. I 1 1 10 100 Il'llo Ill III fir

137 ED "Iln0 1101 I II')) 1119'pt

l:111 F rI I1n Ir IO I~IN

;'40 F 0 1 1 000 ()111 l111lll', r 4 11010 I I II' .IIAIIf'; Ipy flA'1

Pl l 1 1)001 0000 lll lOClW

0 10 10 1 0010 01-00 I1I0ICIIII 1111- ':I ID II'M 01 11 r

041 r3 11 01 1 0001 [11),,11r

If

014 F4 111. 0100 0000 iliiIIIIF

4 F5 1 1)101 0000 I1i1ll

046 r6 I I 0 11 0000 111)l71111.17 F7 In- 0 0.r1 ilIll0f0l IP48 rAI :11 Ow ,~) (1 0 1' ltltllIr

:747 F9! III mot o)i I lo/n l' t il

2 To A ;"II I It)1to 0 10,'0 Dl1l1, t it

P51 rz I!1 l0l 0110 11 r'rllr;151 FC I 1,(, I0 1! pr lll

:151 r!oIi I iloil () iiti>l7 4 r F Iil l l I O lll tt

r,') CC I I I I I I111I1 Illl ":;o

42

.

44-1

dipi

a - 0

43a

6 - 0MN0

U-,,

CZ, Ma-

0

U-

dw0

.a) 0D

44.

a CU

---. ------------

00 0 =

-1L

0 I I45

SINGER KEARFOTT DIGITAL TO VIDEOCOMPUTER (SKC) CONVERTER (DVC)

MCLRSKC CMCRSKC X

MCC TO

DPSKC CPU

WRITSKC BOARD

OMREQ CC

OMATO

BUS

28VDC 120 VACAT 5A 40 0 Hz

PRIME POWER

Figure 4. Singer Kearfott Computer - tblqit,l tO VI(J00 Converter Interface,for Operation with CPU'I.

46

Bit Bit 31

LINE WORD ' WORD I1- - - - - O D 1

LIN I

LINE 2

LINE 27

L I 47 WO D 0W R I- - - - - - - - - - O D 1

Fiur 5. MpDslyFra,52Pxl/ieRslto

£ I47

Bit 0 I~it ~

LINE ~ WORD WORD ______ ~I_ WORD 7

LINE ~

LINE2a I

a I a* I

I I1 a I

I II II I

a aI I I a

a I* £ II I

a aI Ia a

* II I II I II II I II I aa I I* I a* II I~ aa i I aa a* a aI I I IS I a I'a I IS I IS I I

I a

LINE 238

LINE 239 ~~(ORD % WORD 1----------------------------WORD 7

Figure 6. Map Display Format, 256 Pixels/Line Resolution

48

- 4

S. .- - I

-CHARACTER NUMBER

LINE 0 0 1 2- --------------------- 163

LINE 1

LINE 14 0 1 2 63--- --- --

Figure 7. Alphanumeric Page Display Format, 64 Characters/Line, 15 Lines

flYTE NO. YTE 3 RYTE 2 BYTE 1 BYTE 07 6543 21 7 6 543 21 76 5 43 21 7 65 43 21

WnRf) SIT 31 30 29 28 27 ?6 25 24 23 22 21 20 19 15 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Dfl.

HIGHEST ORDER LOWEST ORDERCHARACTER CHARACTER

Figure 8. Alphanumeric Message Data Word Format as Stored in Display Memory

49

DATA BUS BIT NO 7 6 5 4 3 2 1 0(1 BYTE)

CHARACTER GENERATOR .' AROM ADDRESS o

DATA BIT 7 (S) is ROM1 SELECT .7'E

0 = MC 6571 AL SHIFTED ASCII CHARACTERS AND GREEK

1 = MC 6574 L MATH SYMBOLS AND PICTURES

Figure 9. Alphanumeric Character Data Format

bxxxxxxx

bxxxxxxxbxxxxxxx

bxxxxxxx

b x x x x x x x .

bxxxxxxxbxxxxxxxibx x x x x x x

16 LINES b x x x x x x xb x x x x x x x L

b x x x x x x xb-xxxxxxx

bxxxxxxx

bbbbb ,bbI

b = BLANK

x = DOT LOCATION

Figure 10. Alphanumeric Character Dot Matrix Display Fomat

50

-, X X #xxX

SINGER KEARFOTT DIGITAL TO VIDEOCOMPUTER (SKC) CONVERTER (DVC)

TRIGGER "

INIT! SHA C:RESOL DDSYMBRIT D(

MCLRSKC DK:TOMCRSKCTEMPORARY

MCACK XCCPUMCC :x~xBOARD

DPSKC C:

WRITSKC X

DISP/ LOAD-DBUS'SKC/ 32TO I4

ABUSSKC/- I6/ INUBUS

28 VDC 120 VACAT 5A 40 0 H

PRIME POWER

Figure Al. Singer Kearfott Computer - Digital to Video Converter Interface,for Operation with Temporary CPU.

51

0O 00

cr

E 0r

In-CL a,

W

0

tzi

Z U-

0 LA0

w~-

z.

C., cow

0 > C52

A0()

DATA 0INPUT I MA P

A 3 VEOVIDEO

AP ROCM OUTPUTS

CONTROLLINES

A 7

Figure B.. Map Video PROM Block Diagram

53

k ~f yIN.iiyr I1 I RYTfo.L 6 5 4 3 MONITOR?1 1 6o1~ ? 47 65 4 31 -MONITOR 2MnN ITO0RI

WORD FITT 31 30 29 28 i f) 2r 24 23 '7 21 ?0 111 1I 17 Ih I .14 13 1? 11 10 -9 7 6 5 4 3 2 1 S

M I ' M SSMEMORY 0 EXTERNAL EXTERNAL MEMORY 0 Y E Y CONTROLDISPLAY N VIDEO VIDOn DISPIAY N M S N FUNCTIONB/W MODE I MIXER MIAIR 11/W MODF I B 0 C SELECT

T T () L H

0 0 1 1 RR R R 0

2 ! R I N1 0 1

E IE F N ZX A AT T T TE I IR R N 0N N F NA SL L SV VI I

D DE E0 0

0 0N N

WITHOUT MAP WITHOUT MAP

Figure Cl. Control Word 0, Display

RYTE NO. BYTE 3 BYTE 2 BYTE I BYTE 0

7 6 5 4 3 2 1 017 6 5 4 3 2 1 01 6 5 4 3 2 1 7 54 3 2 1UPPER ALPHANUMERIC LOWER ALPIIANUMFRICMSSAGE CLEAR MESSAGF CLEAR DISPLAY MEMORY PRESET -7;

WORD BIT 310221272254 23 22? 1 20, 1() IR 11 16 kI5 14 13 1? 11 10 9 8 765 4 3 210NO. ~

DISPLAY DISPLAY DISPLAY PRESET E L CONTROLMEMORY MEMORY MEMORY DATA S E FUNCTIONSELECT SELECT SELECT 0 R SELECTL R SLC

U AT

I L0 P

NHA

S NE UL ME EC RT I

C

PAG

Figure C2. Control Word 1, Display

54

. . .. . . .. .

BYTE NO. BYTE 3 BYTE? BYTF 1 BYTE 0

7 6 5 4 3 2 1 765432 6 5 4 3 2 1 0 7 6 5 4 3 2 1CLEAR ALPHANUMERIC UPDATE PAGE MEMORY DISPLAY AFTER UPDAT

WORD BIT 31 30 29 28 27 26 25 24 23 22 ISf~1 17 16 15 14 13 12 11 10 9 B 7 6 5 4 3 2 1 0

NO. SC M U M

DISPLAY L SOURCE I P 0 0 CONTROL

MEMORY E DISPLAY S D N N FUNCTION

EL[CT A MEMORY S A I I SELECT

R A T TIG E 0 0

LA E R R

P 5 L 2 1H E PA L HN E AU C NM T UE HR EI RC I

CPA PG AE G

E

Figure C3. Control Word 2, Memory Preset/Clear

BYTE NO. BYTE 3 BYTE 2 BYTE 1 BYTE 0

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1

wORD BIT 31 30 29 28 27 26 ?5 24 j23 22 21 20 lq 1B 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0.-- I I I. I --F ,P PC U U D DDD ,

DISPLAY R R L UPDATE PSOG CONTROLMEMORY E E E SOURCE D D S S S S CODE FUNCTIONSELECT S S A MEMORY A A P P p P SELECTFOR E E R T T L L L L

PRESET T T A E E A A A A

D D L M A Y Y Y Y

A I P E L A A M MT S 1I S P L L A AA P A A II P p P P

L N G A 1t t M MA U N A A D 0Y M E U N N N N

N RM U I IE E I M M T TE R R E E 0 0

S IR R R RD P I IRP C C C 2 1

Y A T PG A P PF G A A

F G G* F F

M M0 0N N

2 1

Figure C4. Control Word 3, Modify Alphanumeric Data

55 HISA-FM-308-81

... ~~~~~~~~... .,.. .%-............... ...........

ILMEI