analytical modeling and design of capacitor bank

Aalborg Universitet

Analytical Modeling and Design of Capacitor Bank Considering Thermal CouplingEffect

Wang, Haoran; Wang, Huai

Published in:IEEE Transactions on Power Electronics

DOI (link to publication from Publisher):10.1109/TPEL.2020.3014913

Publication date:2021

Document VersionAccepted author manuscript, peer reviewed version

Link to publication from Aalborg University

Citation for published version (APA):Wang, H., & Wang, H. (2021). Analytical Modeling and Design of Capacitor Bank Considering Thermal CouplingEffect. IEEE Transactions on Power Electronics , 36(3), 2629-2640. [9162531].https://doi.org/10.1109/TPEL.2020.3014913

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1

Analytical Modeling and Design of Capacitor BankConsidering Thermal Coupling Effect

Haoran Wang, Member, IEEE, and Huai Wang, Senior Member, IEEE

Abstract—The inevitable electro-thermal coupling among ca-pacitors in a bank will lead to non-negligible errors to thetemperature as well as the lifetime prediction of the individualcapacitor. In this paper, the analytical thermal models withthe corresponding design for capacitor banks are proposedconsidering the thermal coupling effect. Firstly, a measurementbased lump thermal model and a physical model-based analyticalthermal model are proposed. Then, with the help of the proposedthermal models, the design method for the thermal matching ofcapacitors in a bank is proposed by optimizing the parametersof individual capacitors, such as the rated parameters and actualloading. To validate the accuracy of the proposed design, casestudies based on a capacitor bank with nine capacitors arepresented.

I. INTRODUCTION

Capacitors are widely used in power electronic convertersto buffer the pulsating power, filter the harmonics, and supportvoltage for stable operation [1–3]. In some applications, theyare also used to provide sufficient energy during the hold-uptime [4, 5]. For these applications where a single capacitorcan not fulfill the voltage rating or capacitance requirements,the capacitor bank is always used as the energy buffer byconnecting several capacitors in parallel for larger capacitanceor in series for higher voltage rating [6–8].

The design criteria of a capacitor bank depend on theapplications and the user’s requirements. For example, inthe Photovoltaic (PV) applications, the minimum capacitance,maximum losses, and maximum volume are the essentialfactors should be considered [9, 10]. In power supply ap-plication, except for the factors mentioned above, the energystorage, differential-mode electromagnetic-interference level,and weight that should be considered [11, 12]. With morestringent constraints brought by automotive, aerospace, andenergy industries, the design of capacitor bank encounters thereliability aspect challenges: a) capacitors are one kind of thestand-out components in terms of failure rate in field operationof power electronic systems [13–17]; b) constraints on volumeand thermal dissipation of capacitors with the trends for highpower density and high reliability capacitor banks [18–21]; c)

Partial results of this manuscript have been presented at the IEEE EnergyConversion Congress and Exposition (ECCE), 2018 sponsored by powerelectronics society and 29th European Symposium on Reliability of ElectronDevices, Failure Physics, and Analysis (ESREF), 2018. This work wassupported by the Innovation Fund Denmark through the Advanced PowerElectronic Technology and Tools Project.

H. Wang and H. Wang are with the Department of Energy Technol-ogy, Aalborg University, 9220 Aalborg, Denmark (e-mail:[email protected] [email protected]).

cost reduction pressure from the global competition dictatesthe minimum design margin of capacitors without undue risk[22, 23].

In recent years, researchers and capacitor manufactureshave devoted much effort to design for the reliability ofcapacitors in high-performance applications. From the researchaspect, thermal modeling and lifetime prediction methods areproposed to obtain the health status of capacitors. For example,the physical structure of the capacitor is built to acquirethe thermal model of capacitors [24–29]. Mission profilebased evaluation method is proposed for lifetime prediction byaccumulating damage from long-term loading profile [13, 30].For reliability performance improvement, researchers proposethe reliability-oriented capacitor sizing and derating designmethods to release the electro-thermal stresses of the capaci-tors and fulfill different lifetime requirements [31, 32]. Fromthe capacitor manufacturers aspect, different series productsof capacitors (e.g. long lifetime series, downsize series, andcooling series) are provided by developing advanced materialor packaging technologies [33]. By using the lower EquivalentSeries Resistance (ESR), lower thermal resistance, or longerrated lifetime products, the thermal stress, as well as the failurerate, can be reduced.

All of these methods discussed above are effective andproposed for the single capacitor. But for capacitor bank, thedirect application of the current methods can not bring thesame benefit in the single capacitor, due to:

a) the capacitor bank is a system with multiple components,where the interactions among capacitors are existing. The ther-mal modeling methods in the literature assume the individualcapacitor is standalone, so the temperature distribution is evenin a symmetrical capacitor bank. It ignores the inevitableelectro-thermal coupling effect among capacitors, which re-sults in the estimation error on temperature and lifetime. In areal case, the electro-thermal interactions among capacitorswill accelerate the degradation of partial capacitors in themiddle and lead to more severe aging [25]. A few literatureidentified the uneven temperature distribution issue by usingFinite Element Method (FEM) simulation and experimentaltesting [25, 29], but it is time-consuming. If the capacitorsor layout of the capacitor bank are changed, the FEM modeland testing setup need to be rebuilt, which consume morethan tens of hours. In [34], the authors propose a thermalmodeling method considering the thermal coupling effect,but the thermal model has to be implemented in the circuitsimulator (e.g., PLECS, Simulink) to solve the nonlinearequations. It can not be integrated as a function into themodel-based design and optimization. Therefore, the analytical

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2

thermal modeling method based on mathematical models isimperative;

b) In a typical capacitor bank implemented with the samecapacitors and symmetrical layout, the uneven temperature dis-tribution, as well as uneven lifetime distribution, is identified,due to partial capacitors in the middle have limited surfacearea to dissipate the heat. For these applications with partialcapacitors aging severe, if all the capacitors in a bank applythe same derating design for longer lifetime, over-design willbe seen from the other capacitors with less thermal stress. Itwould result in more material waste and higher costs. Differentfrom a single capacitor, the capacitor bank has more than onedesign dimensions, such as the component rating, the stressesof individual capacitor, the layout of the capacitor bank, and soon. If these design dimensions can be utilized for optimization,it is possible to achieve higher reliability on the system-levelwith minimum extra cost.

Considering the electro-thermal coupling effect among ca-pacitors, a lumped thermal model based on the measurementand a time-efficient analytical thermal model based on physicalcharacteristics are proposed in this paper. Then, the designapproach to achieve even temperature distribution is proposedby optimizing the rated parameters and the actual loadingof the individual capacitor. Even though the part of resultshave already been presented in conference paper [35], itis worthwhile to have a comprehensive discussion on themodeling and optimization of the capacitor bank. Besides, newresults are added including 1) a lumped thermal model forcapacitor bank; 2) a circuit simulator based thermal modeland its implementation for both string layout and rectanglelayout; 3) a time-efficient analytical state-space thermal modelfor capacitor bank without the help of FEM simulation; and4) thermal matching design case studies and benchmarking.

The rest of this paper is as follows: Section II discusses theexisting evaluation and design method for capacitor banks andtheir challenges; Section III discusses the proposed thermalmodeling method considering the thermal coupling effect;Based on the proposed thermal modeling method, SectionIV proposes a thermal matching design for even temperaturedistribution; Section V validates the accuracy of the proposedmodeling and design methods, followed by the discussions andconclusions.

II. EVALUATION AND DESIGN CHALLENGES OFCAPACITOR BANK

This section presents the typical design and evaluationmethods for capacitor bank. The design challenges and op-portunities are discussed as follows.

A. Evaluation of Capacitor Bank

For a single capacitor, the hot-spot temperature is given as[13]

Th = Ta + Ploss(Rhc +Rca) (1)

where Th is the hot-spot temperature, Ta is the ambienttemperature, and Rhc and Rca are the thermal resistances fromhot-spot to case and from case to ambient, respectively. The

Ploss,i

Th,i

Rhc,i

Tc,i

Ploss,j

Th,j

Rhc,j

Tc,j

Ta

Rca,i Rca,j

Fig. 1. Thermal model of a capacitor bank with two capacitors withoutconsideration of thermal coupling effect.

ambient temperature Ta is measured at the initial conditionbefore power injection to the capacitors, which depends onthe global ambient temperature and heat transfer from othercomponents around the capacitor bank. Ploss is the power lossof individual capacitor, which is estimated from ESR and ca-pacitor current. Assuming there are two capacitors connectedin parallel, the thermal model based on the extension of thesingle capacitor thermal model is shown in Fig. 1. Ploss,i andPloss,j, Th,i and Th,j, and Tc,i and Tc,j are the power loss, hot-spot temperature, and case temperature of capacitor i and j,respectively. Rhc,i and Rhc,j, Rca,i and Rca,j are the thermalresistances of capacitor i and j from the hot-spot to caseand from case to ambient, respectively. Due to the thermalmodel of the individual capacitor in the existing literature isconsidered standalone, there is no heat transfer between thetwo capacitors. For the capacitor bank with the same capacitorsconnected in parallel, the temperature distribution is even fromthe existing evaluation method.

The lifetime of capacitors can be derived from the followingsimplified model, which is popularly applied for electrolyticand film capacitors [13]:

L = L0 × (V

V0)−n × 2

T0−T

10 (2)

where L and L0 are the lifetime under the using conditionand testing condition, respectively. V and V0 are the voltageat using condition and testing condition, respectively. T and T0

are the temperature in Kelvin at using condition and testingcondition, respectively. For electrolytic capacitors, the valueof n typically varies from 3 to 5. For film capacitors, n isfrom around 7 to 9.4, which is used by leading capacitormanufacturers [1]. The application of the lifetime modelresults in fixed accumulated damage. It is far from realitysince the capacitor parameter variations and the statisticalproperties of the lifetime model are not considered. In the fieldoperations, the end-of-life of capacitors could vary within arange due to component parameter tolerances and differencesin the experienced stresses. Therefore, a statistical approachbased on Monte Carlo simulations is applied [13]. Finally, thedistribution of the end-of-life of the capacitors can be obtained,allowing a lifetime analysis with a specified confidence level.




3

Ploss,i

Th,i

Rhc,i

Tc,i

Ta

Rca,i

Ploss,j

Th,j

Rhc,j

Tc,j

Rca,j

Rth,ji Rth,ij

Ploss,iPloss,j

Ploss,i

Th,i

Rhc,i

Tc,i

Ta

Rca,i

Ploss,j

Th,j

Rhc,j

Tc,j

Rca,j

Rth,ji Rth,ij

Ploss,iPloss,j

Fig. 2. The proposed lumped thermal model for a capacitor bank consideringthermal coupling effect.

B. Challenges and Oppotunities

From the evaluation method presented above, it can be seenthat the lifetime of the individual capacitor in a bank dependson the stresses of the capacitor itself, which ignores the heattransfer among the capacitors. When multiple capacitors arepackaged in a bank, there will have heat flowing path amongcapacitors, which results in higher hot-spot temperature Th,i

and Th,j as well as more severely aging. This phenomenonconflicts with the result obtained from the existing evaluationmethod in Section II.A., which should be modeled in a time-efficient way and considered in the design stage.

From the design aspect, all the rated parameters (e.g., L0,T0 and V0) and actual stresses (e.g., T and V ) in the lifetimemodel shown in (2) could be the design variables for thereliability of capacitor. It is possible to optimize these ratedparameters or actual stresses of the individual component toachieve the even temperature in a bank, so that the lifetime ofpartial aging capacitors can be extended and better reliabilityperformance on the system level can be obtained with theminimum extra cost.

III. PROPOSED THERMAL MODELING METHODCONSIDERING THERMAL COUPLING EFFECT

To acquire the even temperature distribution in a capacitorbank, two thermal models are proposed in this section consid-ering the heat transfer among the capacitors: a lumped thermalmodel based on coefficients measurement, and an analyticalthermal model based on the physical structure modeling.

A. A Lumped Thermal Model Based on Measurement

Based on the superposition theory, a lumped thermal modelconsidering both the self-heating and thermal coupling effectin a capacitor bank is provided. Two capacitors i and j in abank are taken as an example, which is shown in Fig. 2. Thethermal coupling effects are represented by controlled voltagesources, which are added to the self-heating sources. Thethermal coefficients of the lumped thermal model are extractedfrom the measurement in FEM simulation or experiment setup.Rhc,i and Rhc,j are the thermal resistances from hot-spot to

case. Rca,i and Rca,j are the equivalent thermal resistancesfrom case to ambient temperature. Rthij and Rthji are theequivalent thermal coupling resistances between capacitor i toj. Considering the self-heating and thermal coupling effects,the general lumped thermal model of the capacitor bank canbe written in the matrix form asTh,1

Th,2

...

Th,m

=

Rth11 Rth12 ... Rth1n

Rth21 Rth22 ... Rth2n

...

Rthm1 Rthm2 ... Rthmn

Ploss,1

Ploss,2

...

Ploss,n

+

Ta,1

Ta,2

...

Ta,m

(3)

where Th,m, Ta,m, Ploss,n are the hot-spot temperature, localambient temperature, and power loss injection of individualcapacitor, respectively. Rthmn are the coupling thermal re-sistance between capacitors obtained from the measurement.In particular, Rthmn

(m = n) is the self-heating thermalresistance from hot-spot to ambient. To extract these equivalentthermal resistances, a step power loss input is applied to eachcapacitor individually, and the temperature responses from theintended monitoring points are extracted. The methodology tofind the thermal response of the capacitor bank is detailed inthe following:

a) The geometry and material information of the capacitorbank are imported to or drawn in a FEM simulation tool;

b) A step response analysis is performed for all the capaci-tors, by applying the step current as well as the power loss toindividual capacitor, respectively;

c) Measure the node temperature of interest, such as casetemperature and hot-spot temperature. Identify the self-heatingresponse of the individual capacitor and its thermal couplingeffect to other capacitors;

d) The extracted temperature response is divided by thepower loss of individual capacitor to calculate the thermalresistance or thermal impedance between two nodes. Thethermal resistance and thermal impedance are given by

Rthab=Ta − Tb

Ploss,i(4)

Zthab(t) =

Ta(t)− Tb(t)

Ploss,i(5)

where Ta and Tb are the temperatures in two adjacent pointsand Ploss,i is the power loss of capacitor under testing.

B. An Analytical Thermal Model Based on Physical Modeling

To obtain the temperature distribution more time-efficient,an analytical model based on the physical structure modelingof the capacitor bank is provided. In this section, the basicdiagram of the analytical thermal model is introduced atthe beginning. Then, two solutions to obtain the steady-statetemperature of the capacitor bank are provided, which are thecircuit simulator-based method and state-space model-basedmethod.




4

Ploss,i

Th,i

Rhc,i

Tc,i

Ta

Rconv,i

Ploss,j

Th,j

Rhc,j

Tc,j

Rr,i Rconv,j Rr,j

Rcond,ij

Rr,ij

Fig. 3. The proposed analytical thermal model for capacitor bank consideringthermal coupling effect.

Effective surface areaTc,i

Th,i

ridij rj

θ

Fig. 4. Description of effective surface area for heat transfer betweencapacitors.

1) Structure Diagram of the Analytical Model: The dia-gram of the proposed analytical thermal model is shown in Fig.3. For the individual capacitor, Rhc,i and Rhc,j are the thermalresistances from hot-spot to case, which are determined bythe physical structure of capacitor and assumed constant indifferent operating conditions (e.g., electrical loading andthermal loading) and locations. Rconv,i and Rconv,j are thethermal resistances from case to ambient for convection heattransfer, which are loading conditions dependent. The thermalresistance of convection heat transfer can be written as

Rconv =1

hconvAeffect(6)

hconv is usually given as a function of ∆T , hconv =

1.42(

∆TH

)1/4, where ∆T is the temperature difference be-

tween two hot points Ta and Tb; H is the height of the capac-itor. Aeffect is the effective surface area for heat dissipation,which is a key parameter to estimate the transfer heat in acapacitor bank. For a single capacitor, all the surfaces areexposed in the ambient air, so that the effective surface areafor heat convection is the whole surface. For the capacitor iin a bank with two capacitors, only a part of the surface isexposed in ambient air, while the other parts are faced to thecapacitor j. The effective surface area is defined in Fig. 4,which can be written as

Aeffect = 2πr2i + 2πriH − kθriH (7)

where k is the number of surrounding capacitors with heatexchange. A view factor θ is considered as a ratio to obtainthe effective surface area from the lateral area, which can bewritten as

θ = 2 arcsin

(rj

ri + dij + rj

)(8)

where ri and rj are the radius of the capacitor i and j,respectively. dij is the distance between capacitors.

Beside the convection heat transfer, radiation heat transferis also considered as shown in Fig. 3. Rr,i and Rr,j are thethermal resistances for radiation heat transfer from case toambient. The radiant energy exchange between a hot bodywith the absolute temperature Ta and an enclosing body withthe absolute temperature Tb is proportional to the differencein the absolute temperatures to the fourth power

q = εσAeffect(T4a − T 4

b ) (9)

ε is the emissivity of the surface material. σ is the Stephan-Boltzman constant.

To represent the heat transfer among capacitors, a new pathfor heat transfer, which contains heat conduction and radiationthermal resistances connected in parallel from capacitor i tocapacitor j, is considered in this thermal structure. Rcond,ij

and Rr,ij are the thermal coupling resistances for conductionand radiation heat transfer through the air. The heat conductioncan be described as

Rcond =1

hcondAcoupling(10)

hcond is the conduction heat transfer coefficient of the air.Acoupling is the coupling surface area between capacitors,which is

Acoupling = θriH (11)

The radiation heat transfer between capacitors can be obtainedfrom (9) with coupling surface area Acoupling.

From the above discussion, it can be seen that the thermalcoefficients of the proposed thermal model are the node tem-perature and power loss dependent. Therefore, the fixed linearthermal resistances can not be used anymore. In order to solvethe nonlinear model and obtain the steady-state temperaturedistribution, the circuit based method and state-space model-based method are proposed and discussed in the following twosections.

2) Circuit Based Method: Building the thermal model incircuit simulation (e.g., Simulink and PLECS) is an effi-cient way to represent the nonlinear thermal impedance andsolve the nonlinear thermal model to obtain the steady-statetemperature distribution. Due to the thermal coefficients forheat conduction, convection, and radiation in the proposedthermal model are nonlinear and temperature-dependent, thecommonly used constant thermal resistor in the circuit simu-lation can not be used anymore. The proposed circuit basedthermal model is shown in Fig. 5, which can be representedin two forms depending on the implementation of nonlinearthermal resistances. In Fig. 5(a), a current control voltagesource is used to represent Rca,i and Rca,j. Based on thepower loss flowing through the nonlinear resistors, the casetemperature can be calculated from the nonlinear equationsin (6) and (9). The thermal coupling resistance Rthij

(i 6= j)is also temperature and power loss dependent, which shouldbe a nonlinear resistor. The possible choices to represent thenonlinear resistors in the circuit simulation are the voltagecontrol current source and current control voltage source.Due to Tc,i and Tc,j have already been represented by the




5

Ploss,i

Th,i

Rhc,i

Tc,i (Ploss,ca,i)

Ta

Ploss,j

Th,j

Rhc,j

Ploss,ij (Tc,i ,Tc,j)

Ploss,ca,i Ploss,ca,j

Tc,j (Ploss,ca,j)

(a) Circuit based thermal model type I.

Ploss,i

Th,i

Rhc,i

Tc,i

Ta

Ploss,j

Th,j

Rhc,j

Ploss,ca,i (Tc,i )

Tc,ij (Ploss,ca,i)

Tc,j

Ploss,ca,j (Tc,j )

(b) Circuit based thermal model type II.

Fig. 5. Circuit based thermal models for capacitor bank by using control-lable voltage source and current source to represent the nonlinear thermalresistances.

Ploss,i

Terminal I:

Th,i Rhc,i

Terminal II:

Tc,i (Ploss,ca,i)

Terminal III:

Ta

Ploss,ij (Tc,i ,Tc,j)

Ploss,ca,i

Terminal I:

Tc,i (Ploss,ca,i)

Terminal II:

Tc,j (Ploss,ca,j)

(a) Three-terminal thermal model for

single capacitor.

(b) Two-terminal thermal model for thermal

coupling connection.

Fig. 6. Basic modules of capacitors and connection to implement the circuitbased thermal model in circuit simulation.

voltage source, the terminal temperatures of Rthij are clamped.Therefore, Rthij

could only be a voltage control current sourceas shown in Fig. 5(a). On the other way, if the thermalresistances from case to ambient are represented by voltagecontrol current sources as shown in Fig. 5(b), the transferheat for self-heating of the individual capacitor, and thetransfer heat among capacitors are determined. At this time,the thermal coupling resistances Rthij

could only be a currentcontrol voltage source, as shown in Fig. 5(b). In the followingdiscussion, the structure in Fig. 5(a) is taken as an example tostudy the implementation of a thermal model for the differentlayout of capacitor bank.

In circuit simulation, the thermal model of a single capacitoris packaged as a three-terminal module as shown in Fig.

Type I

(a) Types of cell in thermal model for string layout.

(b) Circuit based thermal model for string layout.

Ta Type II

Connection

Type II

Type I

Fig. 7. Scalable circuit based thermal model for string layout capacitor bank.

(a) Types of cell in thermal model for rectangle layout.

(b) Circuit based thermal model for rectangle layout.

Type I

Type II

Type III

Type I Type II Type III Connection

Fig. 8. Scalable circuit based thermal model for rectangle layout capacitorbank.

6(a). It can extend for a capacitor bank by using multiplemodules connected through a two-terminal thermal couplingresistor module as shown in Fig. 6(b). In different physicalimplementations, the basic simulation modules have differentthermal coefficients depending on the locations and layout.For the string layout capacitor bank as shown in Fig. 7, threebasic modules are packaged for the scalable implementation.The first two, Type I and Type II, are the thermal models ofcapacitors for the corner and middle locations as shown in Fig.7(a). They have the same structure as the one in Fig. 5(a),but the effective surface area and the coupling surface areaare different. The corner capacitor has one side faced to theneighbor capacitor, and the middle capacitor has two sides.The corresponding Aeffective and Acoupling can be acquiredfrom (7) and (11). The other basic module is the connection torepresent the thermal coupling effect between capacitors from




6

case to case. By using these three basic modules, the thermalmodel of the string layout capacitor bank with differentnumbers of capacitors can be built as shown in Fig. 7(b).For the rectangle layout capacitor bank, four basic simulationmodules to represent the thermal models are implemented asshown in Fig. 8(a). The corner capacitor, border capacitor, andmiddle capacitor have one side, three sides, and four sidesfaced to the neighbor capacitors, respectively, therefore, thecoupling surface area should be updated accordingly. By usingthese capacitor modules and connection module, the thermalmodel of the rectangle layout capacitor bank with scalablenumbers of capacitors can be built as shown in Fig. 8(b). Afterrunning the circuit simulation, the temperature distribution canbe obtained.

3) State-space Model-based Method: The temperature dis-tribution can also be described in the state-space thermalmodel and acquired from iterative computations, becausethe nonlinear thermal resistances need to be updated withinstantaneous temperature. In this section, firstly, the state-space model for thermal dynamics is proposed. Then, theflowchart for iterations is provided to derive the steady-statetemperature distribution.

For capacitor j, an energy balance equation can be built atthe case temperature node, which is shown as

Cth,jdTca,j

dt=

n∑i=1,i6=j

1

Rthi,j

(Tca,i − Tca,j) + Ploss,j (12)

(j = 1, ...,m)

where Ploss,j represents the heat injection related to the node.Tca,j represents the case temperature. Rthi,j

represents the ther-mal resistance between cases. Cth,j represents the equivalentheat capacity of the node, which is ignored for the steady-state temperature estimation. For the capacitor bank with morder differential equations, the thermal dynamics of the casetemperature can be expressed with a matrix representation,

dT

dt= AT +BU (13)

where T represents the node temperatures from case to ambi-ent. U represents the power loss injection. A and B representthe system matrices.

T =

Tca,1

Tca,2

...

Tca,m

U =

Ploss,1

Ploss,2

...

Ploss,n

B =

1 0 ... 0

0 1 ... 0

...

0 0 ... 1

(14)

A =

− 1

Rca1,10 ... 0

0 − 1Rca2,2

... 0

... ... ... ...

0 0 ... − 1Rcam,n

︸︷︷︸

A1:Self−heating

(15)

+

−∑n

j=1

1Rca1,j

− 1Rca1,2

... 1Rca1,n

− 1Rca2,1

−∑n

j=1

1Rca2,j

... 1Rca2,n

... ... ... ...

− 1Rcam,1

− 1Rcam,2

... −∑n

j=1

1Rcam,n

︸︷︷︸

A2:Thermal−coupling

...

1 m

C1 C2 C3 Ci

Fig. 9. Diagram of thermal coupling capacitors in string layout.

...

...

...

...

...

...

......

C1

C2

C3

Ci

Ci+1

Ci+2

Ci+3

C2i

C2i+1

C2i+2

C2i+3

C3i

1

i

1 j

Ci(j-1)+1

Ci(j-1)+2

Ci(j-1)+3

Ci(j-1)+i

Fig. 10. Diagram of thermal coupling capacitors in rectangle layout.

where Rcam,n is the coupling thermal resistance betweencapacitors. In particular, Rcam,n (m = n) is the self-heatingthermal resistance from the case to ambient. The temperaturedistribution of the capacitor bank can be derived as

Th,1

Th,2

...

Th,m

=

Tca,1

Tca,2

...

Tca,m

+

Rhc1 0 ... 0

0 Rhc2 ... 0

...

0 0 ... Rhcm

Ploss,1

Ploss,2

...

Ploss,n

(16)

where Rhcm is the thermal resistance from the hot-spot tocase. Th,m is the hot-spot temperature of the capacitor. Thekey challenge in the state-space thermal model is to identifythe thermal matrix A in (13) for different layouts.

For the string layout of the capacitor bank as shown in Fig.9, C1 and Cm are the corner capacitors, which have the sameeffective surface area (one side faced to neighbor capacitor)and the same self-heating thermal resistance for Rca1,1

andRcam,m

. Ci (1 < i < m) are the middle capacitors with thesame effective surface area (two sides faced to neighbor capac-itor) and the same thermal resistance for Rcai,i (1 < i < m).Then, the self-heating thermal matrix A1 can be obtainedby inserting corner capacitor thermal coefficients to A1(1, 1)and A1(m,m), and middle capacitor thermal coefficients toA1(i, i). From the string layout as shown in Fig. 9, it can beseen that Ci has heat transfer with Ci−1 and Ci+1. Therefore,by inserting the thermal coupling coefficient to A2(i, i−1) andA2(i, i+ 1), the thermal coupling matrix A2 can be obtained,which is shown in Appendix. For the rectangle layout asshown in Fig. 10, three types of capacitor thermal modelsneed to be identified for the thermal matrix according to theeffective surface area. The capacitor located at (i,j) in Fig. 10is the capacitor Ci(j−1)+i. The corner capacitors located in(1, 1), (1, j), (i, 1) and (i, j) have two sides faced to neighborcapacitors, the border capacitors located in (1, :), (j, :), (:, 1)and (:, j) have three sides faced to neighbor capacitors, and themiddle capacitors at the other locations have four sides facedto neighbor capacitors. Then, the self-heating thermal matrixA1 can be obtained depending on the corresponding locations.According to Fig. 10, it can be seen that capacitor C(j−1)+i




7

Physical configuration selection

Single capacitor String layout Rectangle layout

Rth

calculation

Initialize or update the thermal coefficients considering the physical structure

Type I:

Corner cell

Type II:

Middle cellType I:

Corner cell

Type II:

Border cell

Type III:

Middle cellConnection Connection

Rth

calculation

Rth

calculation

Self-heating thermal

resistance matrix A1

Coupling

matrix A2

Thermal resistance matrix A

Rth

calculation

Rth

calculation

Rth

calculation

Self-heating thermal resistance matrix A1

Coupling

matrix A2

Thermal resistance matrix A

Solve linear system: 0 = AT+BU

If T reach steady state?

Derive the hot-spot temperature of individual capacitor

Inp

ut

con

strain

tsL

ayo

ut co

nfig

ura

tion

Th

ermal m

od

eling

Inputs the initial status and physical structure of the capacitor:

Initial case temperature, dimention, numbers, and layout of the capacitor bank

Output temperature distribution

No

Yes

Fig. 11. Flowchart for iterations of the state-space thermal model to obtain the steady-state temperature distribution of capacitor bank.

has four surrounding capacitors for heat transfer, which arethe capacitors Ci(j−1)+i−1, Ci(j−1)+i+1, Ci(j−1)+i−j andCi(j−1)+i+j . Therefore, by inserting the thermal couplingresistances to the interact locations, the thermal couplingmatrix A2 can be obtained and shown in the Appendix.

The state-space model discussed above describes the instan-taneous temperature distribution of the capacitor bank. To de-rive the steady-state temperature distribution, a flowchart basedon the state-space thermal model for iterations is provided asshown in Fig. 11. The input of the flowchart is the physicalcharacteristics of the individual capacitor, the layout of thecapacitor bank, and the initial temperature of the system. Byloading the system parameters, the state-space thermal modelcan be constructed for a specific layout. Through a number ofiterations, the case temperature and hot-spot temperature willbe stabilized, and then the steady-state temperature distributioncan be obtained.

IV. DESIGN FOR THERMAL MATCHING CONSIDERING THETHERMAL COUPLING EFFECT

Thermal modeling of the capacitor bank describes theuneven temperature distribution in the capacitor bank, whichwill result in partial capacitors aging earlier. From the lifetimemodel shown in (2), it can be seen that the rated parameters(e.g, rated lifetime, rated voltage, rated testing temperature)and the actual stresses (e.g., voltage stress and thermal stress)are the key factors to the lifetime. By optimizing the ratedparameters or actual stresses of the individual capacitor, it ispossible to balance the temperature as well as the lifetime ina bank.

For a capacitor bank with specified rated voltage V0, ratedtesting temperature T0, rated lifetime L0, and actual voltageV , the thermal loading Th is the only design variable to thelifetime, which is determined by the current spectrum and theESR of the capacitor. The current flowing through individual




8

capacitor depends on the capacitance (or impedance at thespecified frequency) of each, because of the current sharingamong capacitors. The current of capacitor i is written as

ICi= IAB

Ci

C1 + C2 + ...Cm(17)

where m is the number of capacitors in a bank, Ci is thecapacitance, and IAB is the total current of the capacitor bank.ESR can be written as a function of capacitance, which is givenas

ESRi =1

Cistan δi (18)

where tan δi is the Dissipation Factor (DF) and δi is the lossangle. Based on above equations, the power loss of individualcapacitor can be derived as

Ploss,i = I2CiESRi = Ci

tan δi × I2AB

(C1 + C2 + ...Cm)2s(19)

It can be seen that the power loss of capacitor is linear withCi. By changing the capacitance of the individual capacitor,the corresponding heat injection will change accordingly aswell as the temperature distribution. Worth to be noticed,in the same series of products, the size of capacitor isnormally changed with the capacitance, which will affectthe thermal impedance because of the heat dissipation areavariation. Therefore, the thermal matching method shouldhybrid different downsize series products, which can providevarious capacitance products with the same size. At this time,power loss is the only design variable corresponding to thehot-spot temperature of the individual capacitor. From abovediscussion, the thermal matching optimization model and thedesign constraints can be defined as

min.{X}

X =[Tca,1(C1, C2...Cm)− T̄ ]2 + [Tca,2(C1, C2...Cm)− T̄ ]2

m+...[Tca,m(C1, C2...Cm)− T̄ ]2

m

T̄ =Tca,1(C1, C2...Cm) + Tca,2(C1, C2...Cm)

m+...Tca,m(C1, C2...Cm)

m

Ploss,i =

(IAB ×

Ci

C1 + C2 + ...Cm

)2

ESRi (i = 1, 2...m)

Ploss = Ploss,1 + Ploss,2 + ...Ploss,m

(20)

where X is the temperature variances of the capacitors. T̄is the average temperature. The optimization variables are thecapacitance of the individual capacitor. The optimization targetis to minimize the temperature difference among capacitors.The constraint is to keep the same total power loss, whichcan also be to keep the same capacitance depending on appli-cations. When the temperature difference among capacitors iszero, the capacitance for the individual capacitor in a bank canbe acquired for even temperature distribution as well as evenlifetime. Worth to notice, the voltage-dependent characteristicsof the capacitor have an impact on the component sizing ofthe proposed design method. Therefore, the capacitance usedin this method should be based on a specified voltage, whichneeds to be calibrated first and then taken into the model.

39.2 degree

37.8 degree

36.6 degree

(a) FEM simulation results of temperature distribution.

(b) Experimental results of temperature distribution.

37 degree

36 degree35 degree

Fig. 12. Temperature distribution of a capacitor from experiment andsimulation testing.

32

33

34

35

36

37

38

39

40

Type I Type II Type III

Experiment

FEM sim

Proposed model

-15

-10

-5

0

5

10

15

Type I Type II Type III

ExperimentFEM simProposed model

(a) Comparison of temperature.

(b) Comparison of temperature estimation error.

Tem

per

ature

(degre

e)E

stim

ated

err

or

(%)

Fig. 13. Comparison of temperature estimation among experiment, FEMsimulation and proposed analytical thermal model.

V. VALIDATION OF THE PROPOSED THERMAL MODELINGAND DESIGN METHOD FOR THERMAL MATCHING

A. Thermal Model Verification

In order to verify the effectiveness of the proposed thermalmodel considering the thermal coupling effect, a capacitorbank with nine capacitors is investigated as a case study. NCC-KMQ series 450 V/ 470 µF/ 2000 hours electrolytic capacitorsfrom Nippon Chemi-Con are used to implement the capacitor




9

0 5 10 15

x 104

0

0.01

0.02

0.03

0.04

0.05

Cum

ula

tive d

istr

ibuti

on

functi

on

Number of hours to failure

4.7 yrs

5.3 yrs

5.7 yrs

Capacitors in bank

Capacitor at the middle

Capacitor at the corner

Capacitor at the border

5 years

Fig. 14. Lifetime estimation results of the capacitor bank with nine capacitors(NCC-KMQ series 450 V/ 470 µF/ 2000 hours) based on the method in [13],where n=8.

bank. For the individual capacitor, the diameter is 40 mm andthe height is 45 mm. The distance between the two capacitorsis 2 mm. Chroma 11800 capacitor ripple current tester isused to inject 100 Hz ripple current to the capacitor bank.The current is shared among the nine capacitors connected inparallel, and the power dissipation for the individual capacitoris 0.96 W. The ambient temperature during the test is 25 ◦C.

The proposed analytical thermal model is implementedin Matlab R2018a. The temperature distribution from theanalytical model can be obtained in 5 seconds, while the FEMsimulation takes 12 minutes. The results from the experimentand FEM simulation are shown in Fig. 12. The capacitorsin the middle have the highest temperature in both cases,and the temperature difference between the middle and cornercapacitors is around 2.5 degrees. The comparison between theproposed analytical model and the testing results are shownin Fig. 13 (a). Type I, II, and III are the corner, border, andmiddle capacitors in the capacitor bank. It can be seen that theestimated temperature from the proposed model is compatiblewith the simulation and experimental results. The deviationcomparison among the three cases are shown in Fig. 13 (b),where the errors are within 10 %. The reason for the estimatederror could be that the heat conduction from the pins of thecapacitor to PCB board is ignored in simulation and analyticalmodel, which could result in higher thermal resistance as wellas higher temperature.

B. Verification of Design Method for Thermal Matching

Applying the same ripple current to the capacitor bank,the temperature distribution of the capacitor bank with asymmetrical layout and the same capacitors are shown in Fig.12, where the difference between the highest and the lowesttemperature is 2.5 degree, which leads to 17.5 % lifetime dif-ference as shown in Fig. 14. By applying the proposed thermalmatching design, the capacitance for the individual capacitoris able to be optimized for even temperature distribution, whilethe total power loss still keeps on the same level. Fig. 15 showsthe capacitance of the individual capacitor in conventionaldesign and proposed thermal matching design. The “Optimizedsolution” in Fig. 15 is the ideal capacitance used for theindividual capacitor, and the “Practical solution” is based on

0

100

200

300

400

500

600

700

800

Conventional

solution

Optimized

solution

Practical

solution

Capac

itan

ce o

f in

div

idual cap

acit

or

(uF

)

(a) Capacitance for each solution.

(b) Estimated hot-spot temperature for each solution.

35

36

37

38

39

40

Conventional

solution

Optimized

solution

Practical

solution

Hot-

spot

tem

pera

ture

(degre

e)

Corner cap

Border cap

Middle cap

Corner cap

Border cap

Middle cap

Fig. 15. Capacitance and hot-spot temperature of individual capacitor inconventional symmetrical design and the proposed thermal matching design.

38.4 degree 38.4 degree

Fig. 16. Simulation results of a capacitor bank with proposed thermalmatching design.

the available product in the market which can also fulfill theideal optimization results. The capacitor bank with NCC-KMZ(EKMZ451VSN681MR50S) 450 V/ 680 µF×4, NCC-KMW(EKMW451VSN561MR50S) 450 V/ 560 µF×4 and NCC-KMQ (EKMQ451VSN391MR50S) 450 V/390 µF×1 capac-itors are implemented for simulation and experiment, wherethe results are shown in Fig. 16 and Fig. 17, respectively. Itshows that the temperature distribution among capacitors iseven and the physical characteristics of the capacitor bank areon the same level.

VI. DISCUSSIONS

The thermal modeling method based on measurement inSection III. A is a generic method, which can be applied todifferent power electronic components and systems to acquirethe temperature distribution, due to the measurement-basedmethod to extract the thermal coefficients is independent with




10

36 degree

36 degree

Fig. 17. Experimental results of a capacitor bank with the proposed thermalmatching design.

the system structures, cooling system, and component param-eters. Different from that, the analytical thermal modelingmethod proposed in Section III.B is effective for the capacitorbank with a cylinder capacitor and nature cooling only. Itcan be extended to other package capacitors, but the thermalresistances need to be updated based on the shape, surfacearea, surface material, and so on. For the forced air cooling orother cooling solutions, the model needs to be rebuild basedon the cooling mechanisms and system structure.

In order to balance the temperature as well as the lifetimedistribution, the design method is proposed in Section IV anddemonstrated in a capacitor bank with natural cooling. Butthis method is not limited in the natural cooling condition.For example, in the capacitor bank with forced air cooling,the capacitors far away from the fans are stressed with highertemperatures and vice versa. By optimizing the parametersof the individual capacitor in a bank, it is able to reducethe temperature as well as the failure rate of the capacitorswhich are far away from the cooling source, to achieveeven temperature and lifetime distribution. Future researchefforts are expected, in terms of modeling and design for thereliability of capacitor bank with different cooling solutions.

VII. CONCLUSIONS

This paper proposes the modeling and design methods forthe capacitor bank considering the thermal coupling effect.A lumped thermal model based on the measurement is pro-posed firstly, which is independent with the system structures,cooling system, and component parameters. For more time-efficient thermal modeling, an analytical model is proposedwith programmable capability. Moreover, the design methodfor thermal matching is provided by optimizing the ratedparameters or the actual stresses of individual capacitor. Fromthe case study, the following conclusions can be drawn:

1) The proposed thermal model can be used to estimatethe temperature distribution in a capacitor bank with naturalcooling. It takes 5 seconds only, which is more time-efficientcompared with FEM simulation with tens of minutes. Mean-while, the estimation error is lower than 10 % with acceptableaccuracy;

2) The thermal matching design is able to balance thethermal stresses as well as the lifetime among capacitors in abank by optimizing the capacitance of individual capacitors,while still keep the total power loss on the same level.

APPENDIX ATHERMAL MATRIX

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11

A2 =

−∑n

j=11

Rca1,j− 1

Rca1,20 ... 0

− 1Rca2,1

−∑n

j=11

Rca2,j− 1

Rca2,3... 0

0 − 1Rca3,2

−∑n

j=11

Rca3,j... 0

... ... ... ... ...

0 0 0 ... −∑n

j=11

Rcam,j

(A.1)

A2 =

−∑n

j=11

Rca1,j− 1

Rca1,2... − 1

Rca1,i+10 ... 0

− 1Rca2,1

−∑n

j=11

Rca2,j... 0 − 1

Rca2,i+2... 0

... ... ... ... ... ... ...

− 1Rcai+1,1

0 ... −∑n

j=11

Rcai+1,j− 1

Rcai+1,i+2... 0

0 − 1Rcai+2,2

... − 1Rcai+2,i+1

−∑n

j=11

Rcai+2,j... 0

... ... ... ... ... ... ...

0 0 ... 0 0 ... −∑n

j=11

Rcam,j

(A.2)

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Haoran Wang (S’15-M’18) received the B.S. andM.S. degrees in control science and engineeringfrom Wuhan University of Technology, Wuhan,China, in 2012 and 2015, respectively, and the Ph.D.degree in power electronics from Center of ReliablePower Electronics (CORPE), Aalborg University,Aalborg, Denmark, in 2018, where he is currentlyan Assistant Professor.

From Jul. 2013 to Sep. 2014, he was researchassistant with the Department of Electrical Engineer-ing, Tsinghua University, Beijing, China. He was a

Visiting Scientist with the ETH Zurich, Switzerland, from Dec. 2017 to Apr.2018. His research interests include capacitors in power electronics, reliabil-ity of power electronic systems, and multi-objective life-cycle performanceoptimization of power electronic systems.

Huai Wang (M’12-SM’17) received the B.E. degreein electrical engineering, from Huazhong Universityof Science and Technology, Wuhan, China, in 2007and the Ph.D. degree in power electronics, from theCity University of Hong Kong, Hong Kong, in 2012.

He is currently a Professor at the Center of Reli-able Power Electronics (CORPE), Aalborg Univer-sity, Aalborg, Denmark. He was a Visiting Scientistwith the ETH Zurich, Switzerland, from Aug. toSep. 2014, and with the Massachusetts Institute ofTechnology (MIT), USA, from Sep. to Nov. 2013.

He was with the ABB Corporate Research Center, Switzerland, in 2009. Hisresearch addresses the fundamental challenges in modelling and validationof power electronic component failure mechanisms, and application issuesin system-level predictability, condition monitoring, circuit architecture, androbustness design.

Dr. Wang received the Richard M. Bass Outstanding Young Power Elec-tronics Engineer Award from the IEEE Power Electronics Society in 2016, andthe Green Talents Award from the German Federal Ministry of Education andResearch in 2014. He is currently the Award Chair of the Technical Committeeof the High Performance and Emerging Technologies, IEEE Power ElectronicsSociety, and the Chair of IEEE PELS/IAS/IE Chapter in Denmark. He servesas an Associate Editor of IET POWER ELECTRONICS, IEEE JOURNALOF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS,and IEEE TRANSACTIONS ON POWER ELECTRONICS.


analytical modeling and design of capacitor bank

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