analysis and optimization of thermal issues in high ... · ispd 2001ispd 2001 k. banerjee, m....

ISPD 2001ISPD 2001 K. Banerjee, M. Pedram and A. H. Ajami

Analysis and Optimization ofThermal Issues in High

Performance VLSI

Analysis and Optimization ofThermal Issues in High

Performance VLSI

Kaustav BanerjeeStanford University

Massoud Pedram and Amir H. AjamiUniversity of Southern California


Presentation OutlinePresentation Outline

� Introduction� Thermal Effects and Reliability� Interconnect Performance Optimization� High-Current Effects: ESD� Analysis of Non-uniform Chip Temperature� Non- Uniform Temperature Dependent Delay� Circuit Optimization: Clock Skew� Summary


IntroductionIntroduction

� Sources of chip power dissipation� Chip temperature model� Thermal effects in interconnects� Scaling trends and implications


Sources of Chip Power DissipationSources of Chip Power Dissipation

� Dynamic Power: ∝∝∝∝ CV2f most significant

� Leakage Power: increasing with scaling

� C dominated by interconnects

� Affects interconnect temperature

� Dynamic Power: ∝∝∝∝ CV2f most significant

� Leakage Power: increasing with scaling

� C dominated by interconnects

� Affects interconnect temperature

Devices: Close to Heat SinkDevices: Close to Heat Sink

Interconnects: Away from Heat SinkInterconnects: Away from Heat Sink� Joule Heating: I2R� Joule Heating: I2R


Chip Temperature ModelChip Temperature Model

● 1-D Heat Conduction

Heat SinkPackage

Si Substrate

Rn

TDie

TO = 25 °C

P/A

● TDie = 120 °C (180 nm Node)● Rn = 4.75 cm2 °C/W

��

��

��++++====APRTT nODie

● Assuming same Packagingand Cooling Technologies

(Same Rn) TDie at Other Technology Nodes Calculated


Thermal Effects in InterconnectsThermal Effects in Interconnects

� An inseparable aspect of electrical powerdistribution and signal transmissionthrough the interconnects

� Arise due to self-heating (or Jouleheating) of interconnects caused bycurrent flow

� Thermal effects impact interconnectelectromigration reliability and design


� ∆∆∆∆T increases with increasing tox

Self Heating under DC Stress (IRPS 96)

Thermal impedance θθθθj,defined by ∆∆∆∆T = P x θθθθj

0

100

200

300

400

500

600

0 1 2 3 4Power [W]

∆∆ ∆∆T

[0 C]

M1M3

M2

M4

M1: Metal1M2: Metal2M3: Metal3M4: Metal4

increasingtox

Thickness of AlCu inM4 is doubled

LW

====1000 µµµµµµµµ

m3 m

TiN

Silicon

θθθθj tox

AlCu

Oxide

Cross section



Impact of Scaling Using Low-k (IEDM 96)

Metal

SiO2 SiO2

Low-K(Gap Fill)

Metal

DC Conditions

� As W decreases SH increases. � Low-k increases SH by 10-15%

0

100

200

300

400

500

0 1 2 3

Power [W]

∆∆ ∆∆T [0 C

]

Metal 1StandardDielectric

0.75 µm 1.5 µm 3 µm

Standard Dielectric

0

100

200

300

400

500

0 1 2 3

Power [W]

∆∆ ∆∆T [0 C

]

Metal 1Low-kDielectric

0.75 µm 1.5 µm 3 µmLow-K Dielectric



� Scaling Effects (ITRS ’99)

� As Temperature Increases

� Chip Power and Area increases� Negligible Change in Power Density� Current Density in Metal Lines Increases� Number of Metal Levels Increases

� Electromigration (EM) Time to Failure Decreases� Increased ρρρρ (T) Wire Delay Increases

Scaling Trends and ImplicationsScaling Trends and Implications

Chip Temperature Distribution ?


1.0 1.5 2.0 2.5 3.0 3.5 4.0

0.0

0.2

0.4

0.6

0.8

1.0

1.2

Dielectric Constant (εεεε)

Ther

mal

Con

duct

ivity

[W

/m·K

]

1.0 1.5 2.0 2.5 3.0 3.5 4.0

0.0

0.2

0.4

0.6

0.8

1.0

1.2

Dielectric Constant (εεεε)

Ther

mal

Con

duct

ivity

[W

/m·K

]

Scaling Effects (1) :Thermal Conductivity of DielectricsScaling Effects (1) :Thermal Conductivity of Dielectrics

( ITRS ’99 )Air

HSQ

SiO2

Polyimide

180 nm100 nm 100-130 nm 130 nm

70 nm<50 nm


Full Chip Thermal AnalysisFull Chip Thermal Analysis

● Three Dimensional HeatConduction● Steady State, Uniform Heat

Generation (q’’’), ConstantProperties (k)

,02 ====′′′′′′′′′′′′

++++∇∇∇∇kqT

( Interconnect )

02 ====∇∇∇∇ T( Others )

● Worst Case Simulation– Uniform jrms for all Metal

Lines ( ITRS ’99 )

Si SubstrateSi Substrate

ILDILD

Cu IMD

ILDILD

InterconnectInterconnect

x

z

yTDie

q ′′′′′′′′′′′′

P/A


● NegligibleChange inPower Density

( ITRS ’99 )

● TDie = 133±15°C

● Increase in TmaxDue to JouleHeating ofInterconnects

( FEM Simulation )

Scaling Effects (2) :Maximum Chip TemperatureScaling Effects (2) :Maximum Chip Temperature

0

50

100

150

200

250

180130100705035

Technology Node [nm]

Tem

pera

ture

[°C

]

0.0

0.2

0.4

0.6

0.8

1.0 Power D

ensity [W/m

m2]

Tmax

TDie

0

50

100

150

200

250

0

50

100

150

200

250

180130100705035 180130100705035


Tem

pera

ture

[°C

]

0.0

0.2

0.4

0.6

0.8

1.0

0.0

0.2

0.4

0.6

0.8

1.0 Power D

ensity [W/m

m2]

Tmax

TDie

(IEDM 2000)


Scaling Effects (3) :Temperature DistributionScaling Effects (3) :Temperature Distribution

Tem

pera

ture

[°C

]

100 nm

130 nm

180 nm

35 nm

70 nm

0 1 2 3 4 5 6 7 8 9 100 1 2 3 4 5 6 7 8 9 100 1 2 3 4 5 6 7 8 9 10

120

140

160

180

200

220

120

140

160

180

200

220

Distance from Substrate [µµµµm]

50 nm

50 nm Node

209 °C

126 °C

Global WiresGlobal Wires

(IEDM 2000)


Scaling Effects (4) : Effects onReliability & PerformanceScaling Effects (4) : Effects onReliability & Performance

0

20

40

60

80

100

70 1801301005035

% D

ecre

ase

in T

TF


0

20

40

60

80

100

0

20

40

60

80

100

70 1801301005035 70 1801301005035

% D

ecre

ase

in T

TF


100)()(1% max ××××��

��

�� −−−−====DieTTTF

TTTFTTFinD

0

10

20

30

40

50

180130100705035

% In

crea

se in

RC

Del

ayTechnology Node [nm]

0

10

20

30

40

50

0

10

20

30

40

50

180130100705035 180130100705035

% In

crea

se in

RC

Del

ayTechnology Node [nm]

1001)()(% max ××××��

��

��

�� −−−−====DieT

TDelayRCinIρρρρρρρρ

(IEDM 2000)


Scaling Trends and Implications(Summary)

Scaling Trends and Implications(Summary)

� Scaling trends that cause increasing thermaleffects:

� increasing interconnect levels� increasing current density� low-k dielectrics� increasing thermal coupling



� Introduction� Thermal Effects and Reliability� Interconnect Performance Optimization� High-Current Effects: ESD� Analysis of Non-uniform Chip Temperature� Temperature Dependent Performance� Circuit Optimization: Clock Skew� Summary


Electromigration (EM)� Transport of mass in metal interconnects under

an applied current density� EM lifetime reliability modeled using Black’s

equation given by,��

��

��==== −−−−

mB

nTk

QexpjATTFTTF is the time-to-fail

A is a constant that depends on line geometry andmicrostructure

j is the DC or average current density

Q is the activation energy for EM ( ~ 0.7 eV for AlCu)

Tm is the metal temperature

Reliability ImplicationsReliability Implications


� Accelerated EM stress data yields A, Q, and n inBlack’s equation, and a value of log-normal σσσσLN

� Typical goal: achieve a 10 year lifetime� EM stress data + Black’s equation gives a

technology limit to the maximum allowed currentdensity ( javg ) for the required failure rate and adesired lifetime at a reference temperatureTref ( ~ 100 0C)

� The javg limit does not comprehend self heating

Typical EM AnalysisReliability ImplicationsReliability Implications


Current Density Definitions (DAC 99)

� Peak, Average, and RMS current densities:

� For an unipolar waveform:

� EM is determined by javg, and self-heating by jrms

AI

j peakpeak ==== (((( ))))dttj

Tj

Tavg ��====

0

1 (((( ))))��====T

rms dttjT

j0

21

A is the cross sectional area of interconnect, T is the time period of thecurrent waveform.

T

ton

Ipeak

IrmsIavg = I DC

r = ton/T

peakrms jrj ====peakavg jrj ====

r is the duty factor



� EM lifetime given by:

� Due to self-heating: Tm = Tref + ∆Tself-heating

Impact of Self-Heating on EM (DAC 99)

��

��

��==== −−−−

mB

nTk

QexpjATTF

(((( )))) θθθθRRITTT rmsrefmheatingself2====−−−−====∆∆∆∆ −−−−

Rθθθθ is the effective thermal impedancegiven by,

effinsins

WLKtR ====θθθθ

Weff is the effective metal width to account for quasi-2D heat conduction.


L

Silicon

tins

Metal

insulator

Wm

Kins

Tm

Tref

q

tm


� Typically, design rules specify javg from EM and jrmsfrom self-heating separately.

� Self-consistent approach: comprehends EM andself-heating simultaneously.

� The lifetime at any javg and metal temperature Tm,should be equal to or greater than the lifetimevalue (e.g., 10 year) under the design rule currentdensity (j0).

Self-Consistent Design (Hunter 97)

20

refB2avg

mB

j

TkQexp

jTk

Qexp ��

��

��

��

��

��

≥≥≥≥��

��

��



� Using the relationship between javg, jrms, jpeakand r for an unipolar waveform describedearlier, it can be shown that,

� Incorporating the j2rms and j2avg values fromyields the self-consistent equation,

Self-Consistent Equation

rj

j2rms

2avg ====

(((( ))))(((( )))) effinsrefm

mmmmins

refB

mB20 WKTT

TWtt

TkQexp

TkQexp

jr−−−−

��

��

��

��

��

��

====ρρρρ

This is a single equation in the single unknown temperature Tm




1.0E+05

1.0E+06

1.0E+07

1.0E+08

1.0E+09

0.0001 0.001 0.01 0.1 1

Duty Cycle r

Max

imum

j rm

s [A

/cm

2 ]

1.0E+05

1.0E+06

1.0E+07

1.0E+08

1.0E+09

Max

imum

j pea

k [A/

cm2 ]

Kins

X 10-6 W/m0K

1.15 (SiO2)0.60 (HSQ)0.25 (Polyimide k)0.024 (Air)

Low-k/Cu: Implications for Current Density Limits

● Self-consistent jrms and jpeak decrease significantly as low-kmaterials are introduced.


Reliability ImplicationsReliability ImplicationsImplications for Interconnect Technology

● As r decreases, material changes (increasing j0) will becomeineffective in increasing jpeak.

100

200

300

400

500

600

700

800

0.0001 0.001 0.01 0.1 1

Duty Cycle r

Self-

Con

sist

ent M

etal

Tem

pera

ture

T m

[0 C]

1.0E+04

1.0E+05

1.0E+06

1.0E+07

1.0E+08

1.0E+09

Max

imum

j pea

k [A

/cm

2 ]

Air

j0

X 105 A/cm2

6.0

9.0

13.5

20.3

SiO2

SiO2


Reliability ImplicationsReliability ImplicationsImplications for Current Density Limits

� Comparison with AlCu

0

1

2

3

4

5

6

7

Oxide HSQ Polyimide AirDielectric

Max

imum

Allo

wed

jpe

ak

(MA/

cm2 )

Cu: javg = 1.8 MA/cm2

Cu: javg = 0.6 MA/cm2

AlCu: javg = 0.6 MA/cm2

0.1-µm/Metal 8r = 0.1

● Thermal effects reduce the advantage of Cu as low-kmaterials are introduced


� Thermal effects predominant in semi-global andglobal interconnects which are:� Away from the Si substrate� Long� Typically split into buffered segments

� Long interconnects can be optimally buffered.

Semi-Global and Global Wires

sopt slopt

Performance OptimizationPerformance Optimization


Performance Based Current Density(Signal Lines)

● jrms (max) occurs close to the repeater output due to thedistributed nature of the interconnect.

� 0.25 µµµµm and 0.1 µµµµm technology� Full 3-D Interconnect capacitance extracted� Accurate lopt and sopt values determined by SPICE

simulations

jrms (max)

sopt sopt

lopt

Performance OptimizationPerformance Optimization


� Effect of Thermal coupling Included (NTRS Based)

00.5

11.5

22.5

33.5

44.5

5

Oxide HSQ Polyimide Air

Dielectric

j avg

[x10

5 A/c

m2 ]

PerformanceReliabilityReliability-Multilevel

0.1-µm/Metal 8

● For point-to-point interconnects reliability design limits satisfiedeven after considering thermal coupling

Performance vs ReliabilityPerformance vs Reliability

Gets Worsefor ITRS Data


� Electrostatic Discharge (ESD)

� A short duration (< 200 ns), high current (> 1 A)event

� Can cause open circuit failure of metals andlatent damage that impact EM reliability

High-Current EffectsHigh-Current Effects

Non Steady-State ScenariosNon Steady-State Scenarios


� Failure current densities are much higher than under normalcircuit conditions

0

1

2

3

4

0 2 4 6 8

Current Density, J [x107 A/cm2]

Res

ista

nce

Ris

e,

∆Rm

ax/R

0

0

200

400

600

800

1000

1200

Tem

pera

ture

Ris

e, ∆

T max

[0 C]

Metal 1Metal 2Metal 3Metal 4

∆t = 200 ns

γcrit

Melt Threshold

� Self-heating characteristics of AlCu lines under short-pulse stress conditions (Electron Device Letters 97)

● Metal 1, 2, & 3 showidentical SH

● Higher SH in Metal 4 isdue to smaller surfacearea to volume ratio

● Interconnect failuretemperature is ~ 1000 0C

Non Steady-State Self-HeatingNon Steady-State Self-Heating


Open Circuit Failure (IRPS 2000)

● Passivation fracture due to the expansion of critical volumeof molten AlCu. (@ 1000 0C)

● Independent of overlying dielectric thickness.

Metal 4

~ 12 µµµµm

Metal 1

~ 12 µµµµm



Significant Electromigration PerformanceDegradation

1 µµµµm 0.15 µµµµm

Unstressed AlCu Stressed AlCu

Latent Interconnect Damage (IRPS 2000)



Summary (1)Summary (1)� Thermal Analysis including Interconnect Joule

Heating based on ITRS ’99

� Peak Temperatures in ICs Increase with TechnologyScaling in Spite of Constant Power Density

� Significant Implications for Performance and Reliability� Advanced Chip Cooling Techniques may be Necessary

� Thermal Effects and Reliability� Thermal Effects Strongly Impacts EM� Self-Consistent Analysis: Thermal + EM� Point-to-Point Interconnects Optimized for Performance

Meets Reliability Based Current Density Limits� High-Current Design Rules Must be Followed for I/O

and ESD Protection Circuit Interconnects


Interconnect TemperatureInterconnect TemperatureL

tox

tmInterconnect

OxideVia

Via

Substrate(Tref )

(Tline )

Heat equation in Interconnect (DAC 2001)

2

2line

m

d T Qdx k

= −2

2 22

( ) ( ) ( )lineline ref

d T x T x T xdx

λ λ θ= − −

λλλλ and θθθθ are constants


Solution to Heat EquationSolution to Heat Equation

0 200 400 600 800 1000 1200 1400 1600 1800 2000

108

109

110

111

112

113

114

115

116

117

Position x (micron)

Thermal profile for different technology nodes

T(x) (c)

Tech. node 0.1 micron

Tech. node 0.25 micron

d

d

Tref = 100 °C

T(x=0) = 100 °C T(x=2000) = 100 °CL=2000 µµµµm


Non-Uniform Substrate TemperatureNon-Uniform Substrate Temperature� Due to different switching activities,

substrate temperature is generally non-uniform.� DPM, Functional block clock gating� Thermal time constant is much higher that

signal propagation constant



� Introduction� Thermal Effects and Reliability� Interconnect Performance Optimization� High-Current Effects: ESD� Analysis of Non-uniform Chip Temperature� Temperature Dependent Performance� Circuit Optimization : Clock Skew� Summary


Non-uniform InterconnectThermal Profile

Non-uniform InterconnectThermal Profile

�Long global interconnects span largearea� Experience substrate thermal non-

uniformity with high probability

� Assuming a uniform substrate thermalprofile results in delay estimation errors� Introduces error in wire-planning and

optimization steps


Temperature Dependence ofResistance

Temperature Dependence ofResistance

� Resistance is dependent on Temeprature

�ρρρρ0 is the resistance per unit length atreference temperature

�ββββ is the temperature coefficient ofresistance (1/°C)

� Non-Uniform line temperature �� non-uniform resistance profile� Unit length capacitance is not affected

0( ) (1 ( ))r x T xρ β= + ⋅


Non-Uniform TemperatureDependent Delay

Non-Uniform TemperatureDependent Delay

� Distributed RC delay model (DAC 2001)

∆∆∆∆xrd

CL

L

0 0 00 0( ( ) ) ( )( ( ) )

L L L

d L LxD R C c x dx r x c d C dxτ τ= + + +� � �

0 0 0 0 00 0( ) ( ) ( )

L L

LD D c L C T x dx c xT x dxρ β ρ β= + + −� �

D0 is the Elmore delay model at 0 °°°°C


Delay Degradation withUniform Tref(x)

Delay Degradation withUniform Tref(x)

� With uniform thermal profile (0.25 µµµµm):

� 5-6% increase for each 20-degree increase in longglobal lines

0

5

10

15

20

25

30

35

40

45

50

30 50 70 90 110 130 150Temperature ( C )

Del

ay In

crea

se (%

)L=100L=400L=700L=1000L=2000


� Effect of exponential thermal profiles:

0 200 400 600 800 10001200 14001600 1800 20000

20

40

60

80

100

120

140

160

180

200

Position (X)

T(x)

Exponential Thermal Profile

TH

TL 81012141618202224

30 50 70 90 110 130P e a k T e m p e ra t u re ( C )

L=2000,T1L=1000,T1L=2000,T2L=1000,T2

TL=30 °C

Delay Degradation with Non-uniformTref(x)

Delay Degradation with Non-uniformTref(x)

� Direction of Thermal Gradient is Important


Directional Thermal ProfileDirectional Thermal Profile� Increasing (decreasing) thermal profile is

equivalent to decreasing (increasing)sizing profile for uniform resistance wire

� Increasing thermal profile has betterperformance than that of decreasingthermal profile (optimal wire sizing)

T(x)T(x) T(x)T(x)

xx xx



� Introduction� Thermal Effects and Reliability� Interconnect Performance Optimization� High-Current Effects: ESD� Analysis of Non-uniform Chip Temperature� Temperature Dependent Performance� Circuit Optimization : Clock Skew� Summary


Clock Net RoutingClock Net Routing

� Clock is the most vulnerable signal to theunderlying thermal non-uniformity� Have long global segments in the highest

metal layers� delay variations affect skew

� Clock nets must have near-zero skewamong their sinks to guarantee correctfunctionality of the circuits


H-Tree’sH-Tree’s� H-Tree or bottom-up merging techniques

� Balancing loads seen at merging point inH-Tree to have zero-skew at two sides ofeach branch

1

2

23

3

3

3


Branching Point (CICC 2001)Branching Point (CICC 2001)

� Equal load at each sink: middle pointis the branching point (l)

�With non-uniform thermal profile,branching point dependent on theprofile

l L-l

p qx

1

2 2


Branching Point cont’dBranching Point cont’d� Using thermally dependent delay, optimal

branching location (l*) is:

� With symmetric non-uniform thermalprofile, the branching point is still at l*=L/2

*

*

0

( ) 0l

T x dx l Aβ + − =�A is constant


Movement of Branching PointMovement of Branching Point� In gradually decreasing (increasing)

thermal profile, optimal length l* hasto be less than (greater than) L/2.

T(x)T(x) T(x)T(x)

xx xxL/2L/2 L/2L/2


Thermally Dependent MergingThermally Dependent Merging� Thermal non-uniformity can

introduce a significant skew in theclock tree

�Thermally-dependent bottom-upmerging must be used to minimizethe skew


Results (CICC 2001)Results (CICC 2001)

9.57911µµµµ=300, σσσσ=700

0.01000µµµµ=1000, σσσσ=400

2.40979.5TH=170, TL=1303.63968.66TH=170, TL=110

2.651021TH=170, TL=130

3.981032TH=170, TL=110

5.421042TH=170, TL=90

7.781210µµµµ=2000, σσσσ=1000

5.24957.5TH=170, TL=90

( )T x ax b= +

H LT TaL−= Lb T=

( ) bxT x a e−= ⋅

Ha T=1 ln( )H

L

TbL T

=

2

2( )2

max( )x

T x T eµ

σ− −−

= ⋅

l=L/2skew%

l=l*paramsTline(x)


Effects of Non-UniformTemeprature on EDA Flow

Effects of Non-UniformTemeprature on EDA Flow

� Interconnect non-uniform thermalprofile can affect many EDA flowsteps� Optimal layer assignment� Buffer insertion� Wire sizing� Gate sizing


Summary (2)Summary (2)

� Impact of Non-Uniform Substrate Temperature

� Different switching activities in thesubstrate cause thermal gradients

� Interconnect temperature is stronglydependent on substrate thermal profile

� As technology scales, effect of substratetemperature becomes more important


Summary (2)Summary (2)� Performance dependency

� Delay model for non-uniform line temperaturepresented

� Delay based on uniform worst case line temperatureis not sufficient

� Direction of thermal gradients is important

� Signal Integrity : Clock Skew� Non-uniform substrate temperature introduces skew

in the clock tree� Bottom-up merging techniques must consider non-

uniform interconnect thermal profile� Skew can be minimized by suitable merging

analysis and optimization of thermal issues in high ... · ispd 2001ispd 2001 k. banerjee, m....

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