Analog to Digital, A/D, Digital to Analog, D/A Converters An electronic circuit to convert the analog voltage to a digital computer value Best understood by understanding Digital to Analog first. A fundamental circuit device used is the operational amplifier, or op-amp. Operational Amplifier – A high gain electronic amplifier designed for use with feedback circuits to perform stable, predictable operations (there by its name) which are determined by the external components … Transducer Interfacing Handbook, by Daniel H. Sheingold, Analog Devices, 1980.

Differential Operational Amplifier

Electrical Properties:

• Very high gain 105 to 106 at low frequencies • Very high input impedance, resistance • 0.0 volts between – and +

Wiring external components determines terminal characteristics

ini

f

fi

iinout V

RR

VoutRR

RVAV

+=

+−= 1

-

+

-

+

RfRi

Vin Vout

0 V. A

IfIi

Σ+

-

Summing Junction

Common Mode Rejection Ratio Common-mode- rejection (CMR), a quantity expressed logarithmically in decibels. The amplifier has a balanced differential input. This means that the output voltage is proportional to the difference between the input voltages; and the input terminals, which present high impedance to the input source, are electrically similar. High common-mode rejection means that the amplifier is sensitive only to the difference between the input voltages, even if they are swinging over a wide range, and the difference is quite small. (Analog Devices, Analogic)

∆

=oute

CMVCMRR 10log20

Usually quite high 140dB. Normal-Mode Rejection – Applies to any analog circuit. Normal-Mode Rejection Ratio (NMRR) is the ratio of the transfer function of the circuit or device for the signal component of interest to the transfer function of the unwanted signal component (noise)

=

)()(log20 0

10 fKfKNMRR

K is the transfer function at a given frequency.

Weighted Current Source Digital to Analog, D/A, Converter

p-n-p transistors, diode used to switch the current through the transistor, current summed at the – terminal, through Rf. Requires precision resistors range of R to 2nR. Expensive to manufacture.

Vout

-

+

Rf

A

R 2R 4R 8R

Vref

Bit 1 Bit 2 Bit 4 Bit 8

1.2 V.

TTL Digital Input Data

I out

D/A needs to supply output current to a 4 to 20 mA device. Example: A Current to Pneumatic I/P Converter. This circuit will supply the correct output current, with load resistance, RL variation.

Small circuit forms programmable 4- to 20-mA transmitter p.92 edn | April 17, 2003 www.edn.com

R-2R D/A Converter

I = 2*I1 I1 = 2*I2 I2 = 2*I3 I3 = 2*I4 I = 2*2*2*2*I4 Ladder of only 2 resistor values R and 2*R. Cheaper to manufacture.

[ ]nrefn

refOUT R

VR

VI −−=

⋅⋅⋅+++= 21

21

81

41

21

Vout

-

+

Rf

A

Vref

Bit 8 Bit 4 Bit 2 Bit 1I out

R

2R

R

2R

R

2R

2R

2R

II1

I1

I2

I2

I3

I3

I4

I4

Analog to Digital Flash Converter 2n-1 comparators directly measure signal. Comparators compare the signal against a unique weight. The comparator’s outputs are decoded to a binary signal.

Very fast, but requires many precision components, 16 bit 65,535 comparators.

Successive Approximation Architecture, SAR, A/D Converter Feedback type A/D converters; a D/A converter is in the feedback loop of a digital control circuit that changes its output until it equals the analog input. Completes a conversion in just n-steps, where n is the resolution of the converter in bits. The operation of this converter is analogous to weighing an unknown on a laboratory balance scale using standard weights in-a binary sequence such as 1, 1/2, 1/4, 1/8 ...... 1/n kilograms. Largest standard weight first and down to the smallest one. The largest weight is placed on the balance pan first. If it does not tip, the weight is left on and the next largest weight is added. If the balance does tip, the weight is removed and the next one added. The same procedure is used for the next largest weight and so on down to the smallest. (Datel-Intersil)

Aliasing can be a problem. Use filtering ahead of A/D to remove noise.

Sigma Delta A/D Integrating type, uses an comparator and a single bit DAC.The output of the DAC is subtracted from the input signal. The resulting signal is then integrated, and the integrator output voltage is converted to a single-bit digital output (1 or 0) by the comparator. The resulting bit becomes the input to the DAC, and the DAC’s output is subtracted from the ADC input signal, etc. This closed-loop process is carried out at a very high “oversampled” rate. The digital data coming from the ADC is a stream of “ones” and “zeros,” and the value of the signal is proportional to the density of digital “ones” coming from the comparator. This bit stream data is then digitally filtered and decimated to result in a binary-format output. http://www.analog.com/Analog_Root/static/techSupport/designTools/interactiveTools/sdtutorial/sdtutorial.html Sigma-Delta Modulator Operation The input voltage VIN is first summed with the output of a feedback DAC. This summing can be accomplished by means of a switched capacitor circuit which accumulates charge onto a capacitor summing node. An integrator then adds the output of this summing node to a value it has stored from the previous integration step. A comparator outputs a logic 1 if the integrator output is greater than or equal to zero volts and a logic 0 otherwise. A 1-bit DAC feeds the output of the comparator back to the summing node: +VREF for logic 1 and -VREF for logic 0. This feedback tries to keep the integrator output at zero by making the ones and zeros output of the comparator equal to the analog input. (Analog Devices)

Excellent “Normal Mode” Noise rejection. Theoretically, therefore, any integration interval which is an integral number of cycles of any normal mode noise will reject that noise completely. Thus, if the ramp-up time is a multiple of 1/60 second (say, 0.05, or 0.10 seconds), then 60 Hz pick-up will be attenuated by infinity. Moreover, if it is 0.10 seconds, then both 50 and 60 Hz noise components will be rejected; a convenient and useful consideration for implementing industrial systems in both 50 Hz and 60 Hz environments. (Analogic)

Analog Multiplexer Analog multiplexers are the circuits that time-share an A/D converter among a number of different analog channels. Since the A/D converter in many cases is the most expensive component in a data acquisition system, multiplexing analog inputs to the A/D is an economical approach. Usually the analog multiplexer operates into a sample-hold circuit, which holds the required analog voltage long enough for A/D conversion. (Datel-Intersil) Older technology. These devices are not generally used in process control instrumentation. However, the temperature transmitters used in our lab use this technology.

Quantization Error Resolution is the number output states in bits, example 12 bit resolution. 2n-1 decision points. Smallest signal that can be resolved: Q = (Full Scale) / 2n Example 12 bit A/D 10 volts full scale; Q= 10/4096 = 2.44 mV.

Input Quantization Noise

Uniform Density Function

The mean of this function, mx 212 XX +

=

The variance of the function is [ ] ( )12

212222 XXmxE xx

−=−=σ

Random noise is uniformly distributed in the interval

∆∆−

2,

2 where ∆ is the

quantization level, Q.

The quantization variance is ( )12

22 ∆

=eσ

Assume full scale of 1 volt, the ∆2 is 2-2n

The signal to noise ratio 22

2

2

212 xn

e

xSNR σσσ

∗== The Signal to

Noise Ratio is usually expressed in decibels, dB.

= 2

2

10log10e

xSNRσσ

Therefore each bit of an A/D converter adds 6 dB signal to noise ratio improvement.

0

X1 X2

f(X)

12

1XX −

Monotonicity: In a D/A converter, as the digital input to the converter increases from zero to the maximum, the analog input never exhibits a decrease in output from one conversion to the next. Linearity: The maximum deviation from a straight line drawn through the end points, expressed in percentage of full scale. (Analogic) Frequently one of the bits is assigned as a sign bit. Therefore for a 12 bit A/D the quantization error is 0.05%.

Analog Filter Single Pole Low Pass, RC, used to remove electrical noise form the signal. Specification is usually expressed as – 3dB at some frequency.

Excessive filtering can cause delays in the control response, which is why control engineers should carefully consider the effects of filtering. Electrical noise should be removed by:

1) Using the proper type of wire/cable 2) Shielding, EMI suppression 3) Use proper grounding techniques 4) Filtering, The process control equipment manufacture provides

electrical filtering, that should be sufficient to remove electrical noise.

Anti Aliasing Filters: Aliasing occurs as a result of improper information or signal sample data processing that causes distortion. The definition of proper sampled data signal processing is contained in Shannon's Sampling Theorem. This theorem is defined in the frequency domain and states that to recover without distortion any information, signal or disturbances which contain no frequency component higher than Fc, the signal must be sampled at a rate at least equal to 2*Fc. There are two ways of describing this theorem, one in the time domain and the other in the frequency domain. There is a direct relationship between these domains. Any signal defined in one domain can be defined in the other. If a sin wave is sampled at a rate almost equal to the sample frequency, the resultant frequency is very low and equal to the absolute value of the difference between the input and sample frequencies. It the frequencies are equal, the resultant waveform will have a steady state value. To gain a better understanding of the aliasing effect in terms of industrial control, the analysis must be shifted from the time domain to the frequency domain. Electronic controllers have an input filter, usually a single pole, low pass passive, fixed RC filter. It is used to filter electrical noise and limit the input rate of change. In the frequency domain, the filter defines a spectrum or "window" to the process and transmitter, allowing low frequencies or disturbances to pass while attenuating higher frequencies. The selection of the filter time constant is based on the dynamics of the process as well as the noise present. The corner frequency of most digital controller's filter is around 10 Hz. In a digital controller with a sample rate of Fs, this "window" and its mirror images are shifted and centered around the sample frequency, Fs, and its harmonics. Should the sample frequency be too low, a portion of the sampled frequencies will be folded over into the spectrum of the original frequencies. During reconstruction of the processed signals, distortion will occur. In the ideal case to eliminate distortion from a signal that contains no frequency component higher than Fc, the filter would have to pass all signals or disturbances unattenuated up to Fc, completely suppress all those above Fc and have a sample rate equal to or greater than 2Fc. This is another way of stating Shannon's Sampling Theorem. Bessel function filters are frequently used to suppress this distortion.

Digital Filter Used to filter hydraulic, process induced noise. Should not be used to filter electrical noise! The filter is an exponentially weighted moving average EWMA, of the current

variable, PVcurrent, and the past filtered signal, PVf:

fcurrentf PVPVPV *)1(* λλ −+=

Lambda is the weighting factor. In the digital domain, there is a sample interval Ts. This is the internal execution time of the filter/control algorithm. Lambda, 0.0 < λ < 1.0 is calculated based of the filter time Tf by:

f

sTT

e−

−= 1λ Avoid using a large number, high filter time constants result in poor control performance. Avoid exceeding 1.5 seconds filter time if possible.

Never use the Controller Reset as a filter! Remember the reset term

integrates the error, not filtering the PV; even though the results may

appear to be the same.