Design of Two-Stage Operational Amplifier

Made by :-

Namit Ohri(12213010)

Himaanshu Gauba(12116019)

Abstract— This paper presents a design of Two Stage CMOS operational amplifier as per the given specifications. The OP-AMP is

designed to exhibit a gain bandwidth product of 60MHz and exhibits a gain of 65dB with a 60 phase margin. Design and simulations

are done in Cadence.

Index Terms—2 stage op-amp, simulations, design.

I. INTRODUCTION

A two stage OPAmp is an integral part of any electronic system, the real world all the applications are analog and thus for

filtering and amplification of anolg signals need OpAmp. Also to convert to digital domain one needs an ADC and to get back a

viable signal we need a DAC. Both ADC and DAC have an OpAmp as an integral part of them. In this paper we describe the

basic design procedure for a two stage operational amplifier.

The design starts with the conception of a problem with a given specifications, then we go ahead with our implementation and

compare our theoretical results with the given specifications. The remaining part of this paper is arranged as follow: in the

section II we describe our procedure, approach and calculations to achieve the given specifications, in section-III, we specify our

design challenges and practical issues with our design, in section-IV we present the simulation results for our design to verify

our theoretical values with practical simulations, and finally in section-V we discuss our simulation results and design of two

stage operational amplifier.

II. TWO STAGE OP-AMP DESIGN PROCEDURE

Given specifications are as follows:

1. Gain > 65 dB

2. Slew Rate =0.1 V/ns

3. Supply voltage=1.8 V

4. Load capacitance= 1 pF

5. Input Common Mode Range= 0.9 V to 1.7 V

6. CMRR=80 dB

7. Gain bandwidth Product=60 MHz

8. Phase margin=60°

A. Device Characterization

Before starting with any design using NMOS and PMOS we need to know important design parameters of them, i.e., we have

to characterize the device for our calculation, these device parameters depend on ‘L’ and not on ‘W’, thus we simulate as described

in section IV-A, we calculate Vth from gm Vs. Vgs plot by extrapolating the linear part of the

curve to Vgs axis, the point of intersection gives Vth, for λ we have to plot Id Vs Vds, the slope of this curve in the saturation

region gives m = Gds = 1/( λ *Id), thus we can find λ as λ= m/Id. After finding λ we can find UnCox, from the slope of gm Vs Vds

plot. Similar procedure is repeated for PMOS and the results have been tabulated in Table.1.

B. Designing the Tail transistor and the differential pair

We have slew rate = IT/CL where, It is tail current and Cl is the load capacitance so we have that IT = 22uA, but using this

current the specs of OpAmp could not be met and thus we take IT = 45uA.

From the given minimum ICMR value Vcmin =Vdsattail+Vgs1 = 2∆Vgs+Vth. Assuming a ∆Vgs=0.17V we have

(W/L)tail = 2*IT/K’(∆VGS)2 = 7.37

Where K’ = UnCox = 421 uA/V

Now (W/L)diff = 0.5(W/L)tail = 3.685

This gives voltage gain of first stage as Gm(Ron||Rop) = 45.396 dB .

C. Designing the Mirror pair

For the mirror transistor, we have VCmax = VDD - |VGSP| + VTH

|VGSP| = 0.806 which gives |∆VGSP| = 0.36

(W/L)mirror = 2*ID/K’(∆VGSP)2 = 5.8338

D. Designing the second stage

For the M6 transistor, we have Vsg4 = Vsg6

Gm4 = 2*ID/|∆VGSP| = 1.1102 * 10-4

(W/L)4 = 5.8338, Gm2 = 2*ID/|∆Vgsn| = 40u/0.18 = 235.29 uA/V

Gm6 = 10Gm2 = 2352.9 uA/V

(W/L)6 = (Gm6/Gm4)*(W/L)4 = 123.63

I6 = Gm62/2*K’*(W/L)6 = 53uA

III. DESIGN CHALLENGES AND TRADE-OFFS

Current value (tail) has to be modified from trial and error to reach the specified gain value since the outer stage was not

providing much gain. Also the L for the transistor 7 has to be taken different from that of transistor 6 because the W/L ratio was

quite high of transistor 6 and maximum allowable value of W is only 50um in the simulation. So this was chosen after doing

several iterations and observing the gain value.

IV. SIMULATION RESULTS

All simulation results, figure and tables and discussion will be here. Every figure and table should have discussion.

Fig. 1 Phase vs Frequency

Fig. 2 Gain vs Frequency

The Unity Gain Bandwidth was calculated to be 59.8 MHz.

CMRR was calculated directly through simulation = 84.8 dB.

Fig. 3 STEP INPUT OF 1UV AND SLEW RATE CALCULATED IS 0.3737V/NS

Fig. 4 STEP INPUT OF 1MV AND SLEW RATE CALCULATED IS 0.341V/NS

Fig. 5 STEP INPUT OF 1V AND SLEW RATE CALCULATED AS 0.084V/NS

V. CONCLUSIONS

A two stage operational amplifier was designed meeting the required specifications but with a trade-off between GBW and the

phase margin. Simulation were successfully carried out for finding the phase margin and the gain. However the phase margin

was found to be 3.2 degrees less than the required as per the specifications.

REFERENCES

1. B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, Inc., 2001Fig. 2 Gain vs Frequency