Analog Offi ce®

Analog Offi ce provides a unifi ed, easy-to-use, and

fully integrated RFIC design suite…and enables

us to successfully tape-out on a short schedule.

Cindy Yuen, Epic Communications

The Analog Office® RFIC design environment is a unique user experience as it

combines ease-of-use, fl exibility and accuracy with all the tools essential for RFIC

design in a single desktop solution. It also lets you control and seamlessly integrate

best-in-class third-party tools to capture, synthesize, simulate, optimize, layout,

extract, and verify designs from system to fi nal tape-out. Built upon AWR’s Unifi ed

Data Model™, Analog Offi ce software gives you the power to streamline your design

process, increase productivity, and shorten time-to-market.

PRODUCTIVITY-FOCUSED DESIGN FLOW

Windows UI: simply an elegant interface Since the company was founded in

1994, AWR’s mission has been simple: To provide a superior “high-frequency

design fl ow,” whether you’re learning a new capability or preparing a fi nal design

for the foundry. Every element of the Analog Offi ce software

environment is so well integrated it’s easy to forget that working

behind the scenes is exceptionally powerful design software.

Unifi ed Data Model: schematic and layout The cornerstone

of AWR’s design fl ow, our single, object-oriented database is

synchronized at its core, in the database, not through multiple layers

of software. So whether you’re driving the design from the schematic,

simulation, or layout, the Analog Offi ce design environment lets you

take your ideas from concept through simulation and directly to

physical implementation— all in one platform.

Open, standard-based PDKs: true interoperability Analog Offi ce

software lets you export design layouts to an OpenAccess-based

database using interoperable PDK libraries (IPL) so you can access

the same libraries across all design tools from OpenAccess-based

tool vendors. You’ll save time, achieve optimum performance, and get your product

through development faster.

USER-FLEXIBLE DESIGN ENVIRONMENT

AWR’s Analog Offi ce RFIC design platform is unique in its ability to let you integrate

third-party tools at all stages of the design process.

DRC/LVS: “signed off/approved” links to EDA vendors Analog Offi ce DRC and

LVS features provide synergy with your customers’ “signed off/approved” DRC/

LVS tools, including AWR’s, Mentor Graphics’ Calibre®, Assura™ from Cadence, and

open-source ICED. All are easily managed from within the Analog Offi ce environment.

Advancing the Design of RFICs

Analog Offi ce software handles mixed-signal

designs like this complex PLL in a 0.13um

RFCMOS process.

EM Socket™: seamless integration of

third-party EM point tools AWR’s EM

Socket interface allows you to directly and

seamlessly integrate popular EM solvers into

the Analog Offi ce design environment. Choose general-

purpose EM tools like CST, Sonnet, and Zeland as well as

specialized “silicon-wise” EM tools like OEA International’s NET-AN™.

HSPICE®: direct import of formatted netlists Import HSPICE-formatted encrypted

netlists directly into Analog Offi ce software for ready simulation within the AWR

environment. This makes it possible to bring in legacy designs as well as those

from other groups or companies.

INNOVATIVE TECHNOLOGIES

All of AWR’s software tools are continually enhanced to ensure they always

represent the state-of-the-art in technology while making sure they serve to

increase your productivity. AWR innovations include:

APLAC® Simulation Technology APLAC high-frequency circuit simulator

technology — “battle tested” and foundry-proven by Nokia® mobile phones for more

than a decade — today is a standard component of the Analog Offi ce design suite.

Powerful APLAC engines deliver effi cient simulators tailored for harmonic balance

and time-domain analysis of large-scale and extremely nonlinear RFIC designs.

Intelligent Net (iNet™) Technology iNet delivers “on the fl y” interconnect

extraction, similar in concept to timing-driven or wire-driven digital design, yet

tailored to the needs of RF designers. iNet focuses on accurate RF interconnect

modeling and analysis throughout the entire RFIC design process.

ACE™ Automated Circuit Extraction Technology ACE technology dramatically

reduces the time required to perform initial modeling of complex interconnects by using

layout-based models for circuit extraction - automating identifi cation of transmission

lines from layout and partitioning these structures into pre-existing models.

AXIEM™ 3D Planar EM Technology AXIEM transforms RFIC design by enabling EM

analysis to be accurate and fast enough to serve as an upfront design diagnostic

utility. AXIEM is tailored to 3D high-frequency planar components, delivering

exceptionally accurate EM simulation that is fast, effi cient and capable to handle

extremely large and complex designs.

Analog Offi ce software is a complete

analog and RFIC design environment

that can easily be complemented by

third-party EDA tools.

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the Analog Of

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ANALOG OFFICEDESIGN FLOW

DesignEntry

OpenAccess

Circuit Sim.HB/APLAC

HSPICE

SpiralExtraction

ACE/VeloceRF

RouterPulsic Lyric

DRC/LVSCalibre,

Assura, ICEDDRC & LVS

Circuit Sim.Spectre

EM SimulatorAXIEM, CST, IE3D, Sonnet

NetExtraction

ACE/Net-An

Block/ChipLayout

System Design & Simulation: VSS

Tape-out

Analog Offi ce in the Design Process Linear and nonlinear circuit simulation

Layout with parasitic extraction

EM analysis

Co-simulation with system tools

Statistical design and design centering

Link to back-end DRC/LVS

Features at a Glance High performance harmonic balance and transient solver technologies

• Harmonic balance

• Transient-assisted harmonic balance

• Multi-rate harmonic balance (optional)

• Transient/time-domain

Transient, AC and noise analysis using both HSPICE and APLAC

Intelligent Nets (iNets) interconnect extraction technology

ACE automatic circuit extraction technology

EM Socket interface for integration of third party tools:

• OEA International NET-AN for 3D RLCK extraction

• Helic VeloceRF™ optimized for spiral inductors

AXIEM 3D planar EM analysis (optional) for upfront design diagnostics and post-layout verifi cation

DRC/LVS tools such as Calibre, Assura and ICED

Seamless integration with AWR’s Visual System Simulator™ design suite for system co-simulation

USACorporate Headquarters

AWR Corporation

1960 E. Grand Avenue, Suite 430

El Segundo, CA 90245

+1 310 726 3000

+1 310 726 3005 (fax)

JapanAWR Japan KK

Level 5, 711 Building

7-11-18 Nishi-Shinjuku, Shinjuku-ku

Tokyo 160-0023 Japan

+81 3 5937 4803

UKAWR UK

2 Hunting Gate

Hitchin, Herts

SG4 0TJ, UK

+44 (0) 1462 428 428

FinlandAWR – APLAC

Lars Sonckin kaari 16

FI-02600 Espoo, Finland

+358 10 834 5900

FranceAWR France

140 Avenue Champs Elysees

75008 Paris, France

+33 1 70 36 19 63

Copyright © 2009 AWR Corporation. All rights reserved. AWR and the AWR logo, Analog Offi ce, Microwave Offi ce and APLAC are registered trademarks and Visual System Simulator, AXIEM, ACE, EM Socket, iNet, Unifi ed Data Model are trademarks of AWR Corporation. All others are property of their respective holders.

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