analog circuit testingjonewb/analog.pdf · mixed/analog-signal testing.1 analog circuit testing •...
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![Page 1: Analog Circuit Testingjonewb/analog.pdf · Mixed/analog-signal testing.1 Analog Circuit Testing • Test Problems • Basic Components / Parameters • Test Methods −DSP Based −Design](https://reader030.vdocuments.us/reader030/viewer/2022021800/5e6a25f2ef38950ce32347d7/html5/thumbnails/1.jpg)
Mixed/analog-signal testing.1
Analog Circuit Testing
• Test Problems• Basic Components / Parameters• Test Methods
− DSP Based− Design for Test− Built-in Self-Test− Algorithmic Method
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Mixed/analog-signal testing.2
• Continuous signals in analog circuits• Fault models• Device parameters• Test time• Test effectiveness (fault coverage)• Test cost
Test Problems
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Mixed/analog-signal testing.3
Typical Analog Components
• Operational amplifiers• Integrators• DAC & ADC• Phase lock loops• Filters
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Mixed/analog-signal testing.4
Operational Amplifiers
Ideal op-amp1.voltage-controlled voltage source
2.infinite voltage gain
3.infinite input impedance
4.zero output impedance
5.infinite bandwidth
6.no offset voltage
7.infinite CMRR
Va
VbA(Va-Vb)
ia=0
ib=0
Property
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Mixed/analog-signal testing.5
1.finite gain(practical op-amps A≅≅≅≅ 102~ 104)2.finite linear range(VDD>Vo>GND)3.offset voltage
− input offset voltage Voffset is defined as the differentialinput voltage needed to restore Vo=0
− for MOS op-amps, Voffset is about 5~15mv for BJT op-amps, Voffset is about 1~2mv
Property of real op-amp
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Mixed/analog-signal testing.6
4.Common Mode Rejection Ration(CMRR)
− The CMRR measure how much the op-amp can suppresscommon-mode signals at its input
− Common-mode input voltage Vin.c= Differential-mode input voltage Vin,d=Va-Vb
Differential gain Ad= Vo/ Vin,d
Common-mode gain Ac= Vo/ Vin,c CMRR= (Ad/Ac) or 20 log10 (Ad/Ac) in dB (Typically 60~80dB)
+
Common-mode input Differential-mode input
Vin.c
Va
Vb+
- -
+Vo Vo
Property of real op-amp(con’t)
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Mixed/analog-signal testing.7
5.Frequency Response− Limited bandwidth(typically, 100MHz unity-gain
bandwidth)− Gain decreases at high frequencies , because
a.stray capacitances b.finite carrier mobilities6.Slew Rate(typically,for MOS op-amps,1~50V/µµµµs)
− The maximum rate of output change dVo/dt7.Nonzero Output Resistance
− Typically,0.1~5kΩ− Large Ro will limit frequency response when a
capacitor is connected to its output
Property of real op-amp(con’t)
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Mixed/analog-signal testing.8
Very high(A=102~104)Dominant pole (100MHz unity-gain bandwidth)High(60~80dB)High(>100MΩ)Low(0.1~5kΩ)Low(<0.5µA)Low(<10mV,<0.2nA)
InfiniteInfinite
InfiniteInfiniteZeroZeroZero
Open-loop gainOpen-loop bandwidth
Common-mode rejectionratioInput resistanceOutput resistanceInput current
Practical(typical)idealproperty
Characteristics of Op-Amps
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Mixed/analog-signal testing.9
Operational-amplifier architectures
The two-stage architecture
Differential amp provides:− high input impedance− large CMRR− low offset voltage− high gain
Differential inputamplifier
Level shifting
Differential–to-single-ended
Gain stage
OutputBufferstage
Va
VbVo
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Mixed/analog-signal testing.10
Second block provides:− level shift− added gain− differential-to-single-ended conversion
Output stage provides:− low output impedance− large driving capability
Operational-amplifier architectures(con’t)
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Mixed/analog-signal testing.11
741 OPAMP (BJT)
Bias network Differentialamplifier
CC-CE gainstage
Level shift Output stage
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Mixed/analog-signal testing.12
TWO-STAGE CMOS OPAMP
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Mixed/analog-signal testing.13
Active-RC Integrator
+- -+
vI(t) vo(t)
0V0i1
i1
C
R
∫=
−=
Miller or inverting integrator
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Mixed/analog-signal testing.14
Frequency response of the integrator
-6dB/octave
ω(log scale)
dB
0
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Mixed/analog-signal testing.15
Switched-capacitor Integrator
ϕ1 ϕ2
c1
c2vi Tc
ϕ1
ϕ2
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Mixed/analog-signal testing.16
Switched-capacitor Integrator(con’t)
c1
c2vi
c1
c2
During φ1 During φ2
−Req= Tc/C2
−Time constant=C1 Req= (TcC1)/C2
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Mixed/analog-signal testing.17
Switched-capacitor Integrator(con’t)
ϕ1 ϕ2
c1
c2cs
Advantage:−Time constant=(TcC1)/C2 can be
well controlled in an IC process
(The accuracy of capacitor ratios
In MOS technology can be
controlled to within 0.1%)
Disadvantage:
− it is sensitive to stray capacitances
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Mixed/analog-signal testing.18
Stray-insensitive switched-capacitorIntegrator
ϕ1
ϕ1
ϕ2
ϕ2
C1
C2
ϕ1
ϕ2
ϕ1
ϕ2
C1
C2
Noninverting switched-capacitor integrator
inverting switched-capacitor integrator
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Mixed/analog-signal testing.19
A/D Converters
• Successive approximation• Integrating• Flash• Sigma-delta
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Mixed/analog-signal testing.20
Successive Approximation(I)• Reasonably quick conversion
time• Moderate circuit complexity• Basic ideal: Binary search to
determine the closest digitalword
• Signed Input: within• Output: offset-binary coding
Ex : 2bit offset-binary code
Start
1,0/ == iVV ADin , Sample
ADin VV />
1=ib 0=ib
−→ +
++→
1+→ ii
≥
Stop
Yes
NO
Yes
NO
codeNumber
1110010010-1-2
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Mixed/analog-signal testing.21
Successive Approximation(II)
• DAC-based successive approximation– internal DAC typically determines the accuracy and
sped of the SA ADC.– sample/hold is required so that input does not charge
during the conversion time.V i
nS/H +
-
Successive-approximationregister (SAR) and control
logic
D/A converterV D/A
b1
b2 bN
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Mixed/analog-signal testing.22
Integrating (or Dual-Slope ADC) (I)• high-accuracy data conversion on very slow-
moving signals• Very low offset error, Very low gain error, Highly
linear• Small amount of circuitry required
-Vin S1 R1C1
S2
Controllogic CounterVref
Clockfclk=1/Tclk
bN
b1b2b3
comparator
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Mixed/analog-signal testing.23
Integrating (or Dual-Slope ADC) (II)
Time
Vx
-Vin1
T1
T2 (Three values of three inputs)
-Vin3
-Vin2
Phase I Phase II
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Mixed/analog-signal testing.24
Integrating (or Dual-Slope ADC) (III)
• Basic ideal : Conversion is performed in two phases– Phase I
• fixed time interval of length T1,T1=2NTclk
where Tclk is the period for one clock cycle• S1is connected to -Vin such that Vx ramps up proportional to
the magnitude of Vin
• At the end of phase I,– Phase II
• At the beginning, counter is reset, S1 is connected to Vref,resulting in a constant slope for the decaying voltage at Vx
• The counter simply counts until Vx is less than zero,and get T2
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Mixed/analog-signal testing.25
Flash (I)
• Very-high-speed approach• Large area and power hungry
– 2N comparators– 2N reference voltages, Vr1, Vr2, ….,generated by a
resistor string• The invert gain must be large enough to amplify
(Vin-Vri) to ViH and ViL of its succeeding latches.Usually, gain25100 for 8-bit resolution.
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Mixed/analog-signal testing.26
Flash (II)
(2N-1) toN
encoder
R/2RRRRRRR
R/2
Overrange
Vr1
Vr3Vr4
Vr2
Vr7
Vin
Vr5Vr6
Vref
Comparators
N bit Digital Output
Example: 8-bit A/D
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Mixed/analog-signal testing.27
Flash (III)• Issues in Designing Flash ADC
– Large input capacitive load• large number of comparators connected to Vin, and requires a
strong and power hungry buffer• often limit the speed
– Resistor string bowing• errors are greatest at the center node of the resistor string• considerable improvement obtained forcing the center tap
voltage to be correct. (More voltage references)– Comparator Latch-to-Track delay
• especially when a small input signal of the opposite polarityfrom the previous period is present
• minimized by keeping the time constants of the internal nodesof the latch as small as possible.
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Mixed/analog-signal testing.28
Flash (IV)• Issues in Designing Flash ADC
– Signal and/or clock delay• Even very small differences in the arrival of clock or input
signals at the different comparators can cause errors.• Ex:8bit 250MHz ADC, if clock skew between comparators
greater than 5ps, the converter will have more than 1 LSBerror.
– Substrate and power supply noise• 7.8mV of noise injection would cause a 1LSB error for an 8-bit
convertor with Vref=2V– Bubble error
• error due to comparator metastability, noise, cross talk, limitedbandwidth, …,etc.
– Flashback• caused by latched comparators when they are switched from
track to latch mode.
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Mixed/analog-signal testing.29
Sigma-delta(I)
• Block diagram of a A/D converter
H(Z)
Digial OutSigma-Deltamodulator
Analoginput n-bit
A/D
n-bit D/A
n-bit
Digit decimation filterS/H
Anti-aliasing filter(SC filter)
quantization
Digital Analog
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Mixed/analog-signal testing.30
Sigma-Delta(II)• Block diagram of a D/A converter
RegisterDigital
InterpolationFilter(FIR)
Sigma-DeltaModulator
RelaxedSmoothing
Filter
Analogoutput
Digital AnalogNyquist rate
High speedclock
(muiltiple-feedback modulator & DAC ADC)
N -bit N-bit N+K bit M-bit
PCM(SCF + RC Filter)
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Mixed/analog-signal testing.31
Sigma-Delta(III)
• Oversampling and quantization noise
• Oversampling and Anti-filter
=
fs/2 fs
fs/2 fs
fs/2 fs Nfs-fs/2
Want
No OversamplingAnti-Filter needed
Oversampling andAnti-Filter needed
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Mixed/analog-signal testing.32
Advantages:•Large SNR forlow M•Guaranteedstability•Maximumuseful inputrange
Drawbacks:•Sensitivity tocircuitimperfections•Largercomplexity ofthe digital part
Advantages:•Large SNR forlow M•Smaller noisepattern.
Drawbacks:•Conditionalstability•Useful inputrange smallerthan full-scalerange•need of low-gainintegrators
Advantages:
•Large SNR forvery low M•Betterstability•Smaller noisepatterns
Drawbacks:•More complexdigital andanalogcircuitry•Sensitivity toDAC non-linearity
Advantage:•Stability•Simple circuit•maximumuseful inputrange
Drawbacks:•high value ofM needed•Presence ofnoise patterns
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Mixed/analog-signal testing.33
Sigma-Delta(IV)
• Structure– Single-loop high-order modulators
• Feedforward (FF) modulator• Multiple-feedback (MF) modulator
– Cascade modulators(MASH: Multi-stage noise shaping )• Stability
– High order(> 3 order) : non stable and little input level– Make sure stable:
• Proper selection of scaling coefficient• Taking advantage of the bounded nature of signals at
integrator output, or including limiters• Global resetting of the integrator when an unstable operation
is detected
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Mixed/analog-signal testing.34
D/A Converters
• Weighted resistors• Fixed references• Multiple
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Mixed/analog-signal testing.35
Weighted resistors
• An appropriate set of signals that are all selected in abinary fashion
• The binary array of signals might be voltages,changes, or currents
• DAC– Binary-weighted resistor DAC– Reduced-resistance-ratio ladders– R-2R-based DAC– charge-redistribution switched-capacitor DAC– current-mode DAC
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Mixed/analog-signal testing.36
Binary-Weighted Resistor
• Does not require many resistor or switches• Disadvantages
– Resistor ratio and current ratio are on the order of– monotonicity is not guaranteed– prone to glitches
=
−−−−−=
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Mixed/analog-signal testing.37
Reduced-resistance-ratio ladders• Reduce the large resistor ratios in a binary-weighted array• Introduce a series resistor to scale signals in portions of
the array VA=-1/4 Vref• An additional 4R was added such that resistance seen to
the right of the 3R equals R.• One-forwith the resistance ratio compared to the binary-
weighted case• Current ratio has remained unchanged
=>Switches must be scaled in sizeRf
2R 4R 2R 4R
-Vref
Vout
3R
R
Va=1/4(-Vref)
4R
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Mixed/analog-signal testing.38
R-2R-based DAC
• Smaller size and better accuracy than a binary-sized approach– resistance ratio of only 2
• Current ratio is still large =>large ratio of switch sizes Rf
2R 2R 2R 2R
-Vref
Vout
R
2R
R R
I/8
I I/2 I/4
∑ ∑= =
− ==
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Mixed/analog-signal testing.39
Charge-redistribution Switched-Capacitor DAC
• Replace R into switch and capacitor in previousDAC
• Insensitive to OPAMP input-offset voltage, 1/fnoise, and finite amplifier gain
• An additional sign bit can be realized byinterchanging the clock phases(shown inparentheses)
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Mixed/analog-signal testing.40
Current-Mode DAC
• High-speed• Switch current to output or to ground• The output current is converted to a voltage through
RF• A major limitation during high-speed
operation!!!!Glitches• Glitch disturbance can be reduced by
– limiting the bandwidth (placing a capacitor across RF )• This method slows down the circuit.
– using a sample and hold on the output signal to athermometer code.
– modifying some or all of the digital word from a binary codeto a thermometer code.(most popular method.)
B1 B2 B3 B4
I I/2 I/4 I/8
Rf
Vo
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Mixed/analog-signal testing.41
Fixed references(Decoder-based DAC)
• Most straight forward approach– Create 2N reference signals and pass the appropriate
signal to the output
• Resistor string• Folded resistor-string
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Mixed/analog-signal testing.42
Resistor string
• Example 1: a 3-bitDAC withtransmission-gate,tree-like decoder
• Time-constant ≈3RtrCtr+2•3RtrCtr+……+N • 3RtrCtr=N(N+1)/2 *3 RtrCtr
b3
b3' b2
b3' b2' b1
R
b3
R
R
R
b3
b3' b2
b3' b2' b1'
R
b3
R
R
R
Vref
-
+Vout
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Mixed/analog-signal testing.43
Resistor string
• Example 2: a 3-bitDAC with digitaldecoding
• Time-constant ≈Rtr•2NCtr
R
R
R
R
R
R
R
R
Vref
3 to 1decoder
Vout
b1
b2
b3
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Mixed/analog-signal testing.44
Folded resistor-string
• Reduce the amount ofdigital decoding
• Reduce largecapacitive loading
• Decoding is verysimilar to that for adigital memory
2 to 1 of 4 decoder
2 to
1 o
f 4 d
ecod
er
Vref Word lines
Bit lines
2N resistors(all equal sizes)
Output line
b3 b4
b1
b2
Vout
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Mixed/analog-signal testing.45
Multiple
• Requires only 2*2N/2resistors• Monotonic if OPAMPS have
matched, voltage-insensitiveoffset voltages.
• For high speed, OPAMPS mustbe fast.
• For high resolution, OPAMPSmust be low noise.
• The matching requirements ofthe second resistor string arenot nearly as severe as those forthe first string.– The second resistor string is used
to decode only lower-order bits
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Mixed/analog-signal testing.46
Parameters of ADC &DAC
• Resolution & accuracy• A/D conversion time & D/A settling time• Rise & fall time• Signal to noise ratio• Dynamic Range• Harmonic distortion & Intermodulation distortion
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Mixed/analog-signal testing.47
Parameters of ADC &DAC
• Differential nonlinearity (DNL)• Integral nonlinearity (INL)• Gain and offset errors• Monotoicity• Missing codes• Slew rate• Overshoot
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Mixed/analog-signal testing.48
Resolution & Accuracy• Resolution
– the number of distinct analog levels corresponding to different digitalwords. i.e. N-bit resolution implies distinct analog levels.
– Resolution is not necessarily an indication of the accuracy of theconverter, but instead it usually refers to the number of digital input oroutput bits.
• Accuracy– Absolute accuracy
• the difference between the expected and actual and transferresponses
• Includes offset, gain and linearity errors– Relative accuracy
• the accuracy of offset and gain errors have been removed• a 12-bit accuracy implies that the converter’s error is less than the
(full-scale/212)
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Mixed/analog-signal testing.49
A/D Conversion Time, D/A Settling Time• A/D conversion time & sampling Rate
– The conversion time is the time taken for the converter tocomplete a single measurement including acquisition time for theinput signal.
– the sampling rate is the speed at which sampling can becontinuously converted and is typically the inverse of theconversion time.
• D/A Settling Time– the settling time is defined as the time it takes for the converter to
within some specified amount of final value(usually 0.5LSB).– The sampling rate is the rate at which sample can be
continuously converted and is typically the inverse of the settlingtime.
• Both A/D and D/A converter have limited accuracywhen their sampling instance are ill defined.
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Mixed/analog-signal testing.50
Rise & Fall Time (I)• Cause sampling jitter & glitch
– Sampling jitter• This error is result of the effective
sampling time changing from onesampling instance to the next andbecomes more pronounced forhigh-speed signals.
• When high-speed signals are beingsampled, the input signal changesrapidly, resulting in small amountsof aperture uncertainly causing theheld voltage to be significantlydifferent from the ideal held voltage
Vintideal
tactual
tideal
tactual
Sampling jitter
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Mixed/analog-signal testing.51
Rise & Fall Time (I)
I/4 I/8
Rf
Vout
I1
I2
I1+I2
– Glitch• Glitches are a major limitation during high-speed operation for
converter that have digital logic• Glitches area mainly the result of different delay occurring
when switching different signals.• The glitch disturbance can be reduced by limiting the
bandwidth• In DAC, thermometer-based converter does have advantages
over its binary counterpart, such as low DNL errors,guaranteed monotonicity, and reduced glitching noise
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Mixed/analog-signal testing.52
Signal to Noise Ratio(SNR) (I)
• The signal to noise ratio(SNR) value (in dB) of asignal node in a system is defined as
SNR=10 log[signal power/noise power] =10 log[V2
x(rms) / V2n(rms)]
=20 log[Vx(rms) / Vn(rms)] where Vx(rms) is a normalized signal of a node in a
circuit, Vn(rms) is a normalized noise power
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Mixed/analog-signal testing.53
Signal to Noise Ratio(SNR) (II)
• If Vx is a sawtooth of heght Vref (or a random signaluniformly distributed between 0 and Vref),and noiseonly quantization noise VQ(rms)=VLSB/
SNR=20log [Vx(rms) / VQ(rms)] =20log [(Vref(rms)/ ) / (VLSB(rms)/ )] =20log(2N) = 6.02 N dB
• If Vx is a sinusoidal waveform between 0 and Vref.SNR=20log [Vx(rms) / VQ(rms)] =20log [(Vref(rms)/ )/ (VLSB(rms)/ )] =20log( 2N) = 6.02N + 1.76 dB
12
12 12
122
322
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Mixed/analog-signal testing.54
Dynamic Range(DR) (I)
• Two different definitions:1. The ratio of maximum amplitude input sinusoidal to
minimum amplitude input sinusoidal.• maximum input: input with PSNR or maximum
allowable input.• minimum input : input with SNR=0.
2. Effective number of bit using the equation PSNR=6.02Neff+1.76dB where 1 is commonly used.
DR Vin
PSNR
0dB
SNR
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Mixed/analog-signal testing.55
Dynamic Range(DR) (II)
• DAC analog output measured using spectrum analyzer• ADC digital output analyzer using Fast Fourier
Transform(FFT).• Dynamic Range is function of the frequency of the
sinusoidal input
Full power bandwidth
0.5bit(or 3dB)
fin
Neff (or PSNR)
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Mixed/analog-signal testing.56
Harmonic Distortion & Intermodulation Distortion
• Nonlinear Distortion• For the application of a certain device(amplifier or
mixer ……)– One of the series term provides the desired output– The remaining term produce undesired spurious signals which
correspond to conversion loss & signal distortion• If input vi=Acosw1t """"Single tone test (only HD)
output vo: vo=k1vi+k2vi2+k3vi3+……Then,
++++=
++++=
+++=
+++=
!
!
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Mixed/analog-signal testing.57
Harmonic Distortion & Intermodulation Distortion
If input vi: vi=A(cosw1t +cosw2t) "Two-tone test output vo: vo=k0+k1vi+k2vi2+k3vi3+……
Then,
!!
!
!
+
++++++
−+−+
++
++
++++
±++−+
+=
+++++++=
++++=
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Mixed/analog-signal testing.58
Integral Nonlinearity (INL)
• INL error is defined to be the deviation from astraight line, after both the offset and gain errorhave been removed.– A conservative measure of nonlinearity is to use the
endpoints of the converter’s transfer response todefine the straight.
– An alternate define is to find the best -fit straight linesuch that the maximum difference (or perhaps themean squared error) is minimized.
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Mixed/analog-signal testing.59
Differential Nonlinearity(DNL)
• DNL is defined as the variation in analog stepsizes away from 1LSB (typically, once gain andoffset error have been removed).
• an ideal converter has it’s maximum DNL of 0 forall digital values, where as a converter with amaximum DNL of 0.5 LSB has its step sizevarying from 0.5LSB to 1.5LSB.
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Mixed/analog-signal testing.60
Gain and Offset Errors(I)
• Gain Error:– Gain error is the difference at the full-scale value
between the ideal and actual when the offset error hasbeen reduced to zero.
– DAC• Egain(DAC)=( - )- ( -1)
– ADC• Egain(ADC)=( - ) – (2N – 2)
1…1 0…0
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Mixed/analog-signal testing.61
Gain and Offset Errors(II)
• Offset Error– DAC
• offset error is the output that occurs for the input code thatshould produce zero output .
• Eoff(DAC)=Vout / V LSB|0…..0
– ADC• Offset error is the deviation of V 0…01 from 1/2LSB• Eoff(ADC)= - 1/2LSB
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Mixed/analog-signal testing.62
Monotonicity
• Monotonicity mean the output always increase as theinput increases.
• A monotonic D/A , the slope of the D/A converter’stransfer response is of only one sign.
• If the maximum DNL error is less than 1LSB, then aD/A converter is guaranteed to be monotonic.However, many monotonic converter may have amaximum DNL greater than 1 LSB.
• Similarly,a converter is guaranteed to be monotonic ifthe maximum INL is less than 0.5LSB.
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Mixed/analog-signal testing.63
Missing Codes
• Although monotonicity is appropriate for D/Aconverters, the equation term for A/D converter ismissing codes.
• An Q/D converter is guaranteed not to have anymissing codes if the maximum DNL Error is lessthan 1LSB or if the maximum INL error is lessthan 0.5LSB.
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Mixed/analog-signal testing.64
Slew rate
• The slew rate is the maximum rate at which theoutput changes when input signal are large
• Additional slewing time greatly increase thedistortion and also increase the transient timeduring slew rate limiting(which occurs often foropamps used in switched-capacitor applications).
• In non-oversampled D/A converter the largestdistortion mostly occurs at the high frequency endof the frequency band.This distortion results fromthe finite slew rate of output amplifiers.
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Mixed/analog-signal testing.65
Overshoot
• In some designs, the output voltage of thesample-and-hold can show an overshoot at themoment the slew operation in amplifiers isfinished and the signal level comes within thelinear operation rate.
• This overshoot can be caused by a limited overallsystem stability introduced by a maximization ofthe bandwidth.
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Mixed/analog-signal testing.66
Phase Lock Loop• Used in two ways
– Demodulator-follow phase or frequency modulation– Track a carrier or synchronizing signal
• Narrowband filters to recover signals• Synchronizing digital transmissions in
communications• Frequency synthesizers,multipliers and dividers
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Mixed/analog-signal testing.67
Phase lock loop
• Structure :phase detector,charge pump,filter,VCO
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Mixed/analog-signal testing.68
Demodulator(1)
• frequency demodulation :wo tracks the input frequency wias it varies according to the modulation.
• Vc is proportional to wo,therefore,Vc is demodulated signal
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Mixed/analog-signal testing.69
Demodulator(2)• Phase demodulation:
– In this application, sits at the average of– Vd is the demodulated output
θ
θ
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Mixed/analog-signal testing.70
Track a carrier or synchronizesignal
• Synchronize signal
outputpad
dclk
clock
clock pad
clockroute
dclk+dpad
clockdclk
data out
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Mixed/analog-signal testing.71
Narrowband filters to recoversignals
• A clock signal vo is to be synchronized to a digital datasignal vi
• The clock could have been recovered with a narrow-bandfilter
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Mixed/analog-signal testing.72
Narrowband filters to recoversignals
• The low-pass filter is first or second order• The low-pass filter is to remove the second term
at twice the frequency of the input signal
PD
VCO
−
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Mixed/analog-signal testing.73
Narrowband filters to recoversignals
• When the system is in lock( ),the output of the filter isalso equal to zero
• The increase in the low-pass filter’s output will cause theVCO’s frequency to increase until it is the same as that ofthe input signal ,which will keep the two signals insynchronism
Φ−==
Φ−+Φ=
Φ= , is the input to VCO
=Φ
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Mixed/analog-signal testing.74
Frequency synthesizers,multipliers and dividers
PhaseDetector
Chargepump Filter VCO
U
D
1/n
Ffb
referenceclock(Fin)
n*Fin
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Mixed/analog-signal testing.75
DFT for PLL using IEEE 1149.1
• A DFT strategy to test embedded Charge-PumpPhase Locked Loops in systems incorporatingboundary scan
• DFT allows the verification of the operatingfrequency range of the CP-PLL while the systemis in test mode
• This is achieved with a minimal degradation inPLL performance
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Mixed/analog-signal testing.76
Proposed DFT Circuit
PHASE
DETECTOR
UP
DOWN
Fref
TMS
SinBS CELL
ANALOG
TMS
TMSFILTER
SWITC
HSW
ITCHPref
Nref
Current
source
VOLTAGE
CONTROLLED
OSCILLATOR
R
CHARGE-PUMP
DFT BLOCK
FIG: Charge pump PLL with DFT
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Mixed/analog-signal testing.77
Proposed Test Strategy
• By providing an additional test pin for an analogtest signal, and by the use of an IEEE 1149.1scan register to shift in voltage values anddisable VCO feedback, we can characterize theVCO by sampling its dynamic delay
• This allows us to verify the operating frequencyrange of the PLL without performing anyfrequency measurements
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Mixed/analog-signal testing.78
Test Procedure• 1. When system is in test mode: TMS is high• 2. Set ANALOG to sweep Vc through in specific
steps• 3. Set Vc• 4. Shift in voltage input to Vin through Sin line• 5. Measure delay Tdyn at the output Fout of the
PLL• 6. Repeat steps 3, 4, 5, to sweep frequency
range
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Mixed/analog-signal testing.79
VCO It has a square wave frequency output VCOout which
is a function of a varying input control voltage Vc The VCO can be treated as an open loop circuit with
feedback provided externally The output frequency of VCO is
Delay
DC Transfer block
Vc
Vin
Tdyn=f(Vc)
Vt
VCOout
)2(T1fdyn
=
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Parameters of PLL
• Capture range• Tracking range• Frequency settling time• Frequency overshoot• Frequency rise time• Jitter
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Mixed/analog-signal testing.81
Capture range
• The maximum difference between the inputsignal’s frequency and the oscillator’s free-running frequency where lock can eventuallybe attained is defined as the capture range
• This frequency is on the order of the polefrequency of the low-pass filter
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Mixed/analog-signal testing.82
Tracking range(lock range)
• Once lock is attained,as long as the input signal’s frequencychanges only slowly it will remain in lock over a range that ismuch larger than the capture range
• This range is calculated as follows:
• The PLL will track the input signal as long as the frequency of theinput signal does not exceed this range
==−
±=ω
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Mixed/analog-signal testing.83
Frequency settling time(1)
• When PD change ratio• The output frequency will
change to a targetfrequency
• The output voltage ofVCO output frequencyrises toward to objectivevalue
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Mixed/analog-signal testing.84
Frequency settling time(2)
• Frequency acquisitiontime is the Frequencysettling time
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Mixed/analog-signal testing.85
Frequency overshoot
• Frequency overshoot isshown in the left figure
• Frequency rise time isthe 10%~90% of settlingtime
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Mixed/analog-signal testing.86
Jitter(sampling time uncertainty)
• To quantify this sampling time uncertainty asknown as aperture jitter
Π=
Π=∆
∆
Π=
Π<∆
#An 8-bit full-scale250MHz converter,it’s sampling timeuncertainty under5ps
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Mixed/analog-signal testing.87
Digital signal processing
# Low cost test solution# Flexible# Simplified instrument set# Simplified command set# Advanced CPU/DSP cores# Domain transformation# Statistic method
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Mixed/analog-signal testing.88
DSP based testing
• AWG(Arbitrary WaveformGenerators) is basically a DAC
• Waveform digitizer is a ADC• It can used in many purpose:
spectrum analysis,scope viewing ,voltage measurement etc.
• It is a low cost solution compared toATE and a more flexible design
• It needs pre/post-processing circuit,so speed is reduced-undersamplingthe signal and signal compression isneeded
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Mixed/analog-signal testing.89
DSP based testing(example)
• VXI card-cage generate phase-lock clocking to AWG andHP82000 (good centralclocking)
• HP82000 provides all of thetiming and control signals forthe ADC
• AWG provides a sine-wave forthe analog input of the ADC
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Mixed/analog-signal testing.90
DSP methods• Histogram
– Gain,offset,INL,DNL• Fourier transform
– SNR,SNR+D,peak harmonic,total harmonic, coherence, non-coherence
• Time-frequency domain(modulation)– Capture &tracking range– Frequency rise , fall , overshoot , settling time , jitter
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Mixed/analog-signal testing.91
Histogram methods(1)
• The signal generator is not externallycontrolled
• Digital data recorder:analyze the data andcalculate device errors
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Mixed/analog-signal testing.92
Histogram methods(2)
• Resulting tally count of a converter withlinearity errors
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Mixed/analog-signal testing.93
Fourier transform(FFT testing)
• Similar to histogram test method• Many of the concerns for the histogram test
are also converters for FFT testing
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Mixed/analog-signal testing.94
Fourier transform(2)
• Result of transforming a pure sine wave withan ideal converter
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Mixed/analog-signal testing.95
Fourier transform(3)
• Illustration of quantizationnoise
• Results of transforming apure sine wave with aconverter with nonlinearity
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Mixed/analog-signal testing.96
Testable design approaches
• Design for test• BIST• Algorithmic
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Mixed/analog-signal testing.97
Design for test
• Controllability/ Observability• Isolation• Sample/ hold• COS (Control and Observation Structure)• Analog Scan• IEEE 1149.4
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Mixed/analog-signal testing.98
• Controllability The ability to apply a specific signal value to each
node in a circuit by setting values on the circuitinputs.
• Observability The ability to determine the signal value at any node
in a circuit by controlling the circuit’s inputs andobserving its outputs .
Cotrollability/Observability
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Mixed/analog-signal testing.99
Isolation/Sampling
• For complex of mixed-signal devices, the functionalblocks can be isolated for testability.
• In analog circuit, capacitors form the memory cell. The values of the signal can be sampled and held.
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Mixed/analog-signal testing.100
Isolation
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Mixed/analog-signal testing.101
Sample/Hold
HC
S/H
Aout
Ain 1S+
-
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Mixed/analog-signal testing.102
Control and Observation Structure (COS)
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Mixed/analog-signal testing.103
Examples of COSs
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Mixed/analog-signal testing.104
Examples of COSs
!
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Mixed/analog-signal testing.105
Operations of COSs
No. Data path Operation FunctionAin→→→→Aout1 Normal Normal operation mode
AC signal observationAin→→→→Bus Monitor2
7 Scan-inBus→→→→Sin6 ApplySout→→→→Aout DC signal application
Scan-outSout→→→→Bus5DC signal observation4 Ain→→→→Sin SampleAC signal applicationControlBus→→→→Aout3
No. Operation (Concurrent)
ConScan-in(Normal, Scan-in)10ConScan-out(Normal, Scan-out)11ConApSout(Apply, Scan-out)12
ConSamMon(Sample, Monitor)14ConCntSin(Control, Scan-in)13
8 ConSample(Normal, Sample)9 ConMonitor(Normal, Monitor)
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Mixed/analog-signal testing.106
Scan-in/Scan-out
• A chain of capacitors and voltage-follower buffersform an analog shift register.
• The test input signal can be scanned in frominput pins to the internal nodes and the testresults can be scanned out from the internalnodes to output pins.
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Mixed/analog-signal testing.107
Scan-out
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Mixed/analog-signal testing.108
IEEE std. 1149.4
• Providing a mechanism for interconnect testing of aboard with analog, digital , and mixed-signal chips.
• IC test either in isolated or in surface mounted.
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Mixed/analog-signal testing.109
Structure of an 1149.4 chip
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Mixed/analog-signal testing.110
Test Bus Interface Circuit
+-
VTH V
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Mixed/analog-signal testing.111
BIST
• A/D & D/A pairs• Oscillation-loop based• On chip stimuli generation• Output analysis
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Mixed/analog-signal testing.112
A/D & D/A Pairs
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Mixed/analog-signal testing.113
Requirements
• Only for specific circuit including A/D and D/Aconverters
• DAC resolution must be higher than that of ADC(usually ≥ 2 bits)
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Mixed/analog-signal testing.114
Oscillation-loop Based for OP amp.• A fault in the circuit will either prevent the circuit from
oscillating or alter the oscillation frequency.• Feedback circuitry is added to the CUT in test mode
such that the resulting circuit is an oscillator.• The oscillation frequency is determined by circuit
parameters such as the gain of the op amp and unitygain frequency.
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Mixed/analog-signal testing.115
Oscillation-based Test
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Mixed/analog-signal testing.116
On Chip Stimuli Generation
• Digital frequency Synthesis• Delta-Sigma Oscillators• Fixed-length periodic bit stream
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Mixed/analog-signal testing.117
Digital frequency Synthesis
-1Z+1-bitDAC
LPfilter
DACROM
Counter nf
DSmod
Frequencycontrol word
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Mixed/analog-signal testing.118
Delta-Sigma Oscillators
-1Z
-1Z
DS
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Mixed/analog-signal testing.119
Fixed-length periodic bit stream
-1
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-1 -1 -1 -1
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Mixed/analog-signal testing.120
Output Analysis
• Voltage/Current Comparator
• Frequency Counter
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Mixed/analog-signal testing.121
Voltage Comparator
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Mixed/analog-signal testing.122
Current Comparator#
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Mixed/analog-signal testing.123
Frequency Counter
TDMcomparator
counter 2( flip-flops)
counter 1( flip-flops)
reference voltage 1
reference voltage 2
CUTaφ
clockbφ
7 φφ
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reference voltage 1
reference voltage 2
time
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Mixed/analog-signal testing.124
Algorithmic method
• Based on the state equations of a system• Using the check-sum method• Capable of testing, diagnosis, and error
correction• Apply to various technologies
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Mixed/analog-signal testing.125
µ
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⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅
⋅⋅⋅⋅⋅⋅
=
⋅⋅⋅
State Equation of a Linear System
or µ⋅+⋅=
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Mixed/analog-signal testing.126
Check-sum Method
• Many analog circuits can be expressed as astate-variable system
• Changes in the state can be computed usingmatrix-vector multiplications.
• Multiple checksum vector can be used toincrease the error detection capability , and/or forerror correction.
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Mixed/analog-signal testing.127
µ
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where [ ] [ ]
•⋅⋅⋅=⋅⋅⋅ αααγγγ
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Mixed/analog-signal testing.128
Signal Flow Graph of a Current Detection Scheme
=+−= ∑∑==
βα must hold if no faults exist.
1 / S +1
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β γ
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Mixed/analog-signal testing.129
µ
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It can be show that
αα= if faults directly affect
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Mixed/analog-signal testing.130
Fault Diagnosis and Error Correction Architecture
A/D
STATE VARIABLE SYSTEM
ERROR DET
ERROR DET
DEMUX
DECODE
T1
D
T2
yu
e1
e2
controlinput
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Mixed/analog-signal testing.131
State Equations of an OTA SystemA fifth-order low-pass Chebyshev filter using OTA
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Mixed/analog-signal testing.132
Test Structure of the filter
m n
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