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Analog ApplicationsJournal

Fourth Quarter, 2011

© Copyright 2011 Texas Instruments

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ApplicationsCommunications and Telecom www.ti.com/communicationsComputers and Peripherals www.ti.com/computers Consumer Electronics www.ti.com/consumer-appsEnergy and Lighting www.ti.com/energyIndustrial www.ti.com/industrialMedical www.ti.com/medicalSecurity www.ti.com/security Space, Avionics and Defense www.ti.com/space-avionics-defense Transportation and Automotive www.ti.com/automotive Video and Imaging www.ti.com/video

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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Data AcquisitionHow delta-sigma ADCs work, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

This article continues the exploration of the topology and functionality of delta-sigma ADCs that was begun in Part 1. The modulator described in Part 1 requires a digital/decimation filter to minimize high-frequency noise and reduce the output-data rate. Operation of this filter is discussed, including the conversion of the modulator’s 1-bit data stream to 24-bit words and adjusting the decimation ratio by changing the master-clock and output-data-rate ratio.

Power ManagementSolar charging solution provides narrow-voltage DC/DC system bus for multicell-battery applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Systems powered directly by a solar panel typically do not allow the solar panel to operate at maximum efficiency. This article presents a solution that efficiently charges multicell batteries and provides system bus voltage by operating the solar panel at its maximum power point (MPP). This solution also intelligently connects and disconnects the battery from the system.

Solar lantern with dimming achieves 92% efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Solar lanterns with LEDs have become very popular, and switching regulators are typically used to efficiently drive LEDs from a variety of battery voltages. Analog and PWM dimming techniques provide an easy method of controlling light output and extending operating time between charges. This article presents two 2.8-W solar-lantern solutions, one configured with analog dimming and the other with PWM dimming. The linearity and efficiency of the two techniques are evaluated to determine how various operating conditions affect dimming performance.

Interface (Data Transmission)Extending the SPI bus for long-distance communication . . . . . . . . . . . . . . . . . . . . . . . .16

Communications between integrated circuits typically use a single-ended interface designed for short distances. As the distance increases, interface designs that work in the lab may fail on the factory floor because of added propagation delay and other problems prevalent in the harsh environment. This article describes typical problems and solutions related to clock synchronization, noise immunity, large ground-potential differences, unterminated data lines, and electrical transients.

General InterestAnalog linearization of resistance temperature detectors . . . . . . . . . . . . . . . . . . . . . . .21

Precision temperature measurements often use resistance temperature detectors (RTDs) because they are very stable and useful for temperatures ranging from cryogenic to over 800°C. RTDs have second-order nonlinearity of approximately 0.38% per 100°C measurement range. In applications where digital compensation is not available, an analog technique for RTD linearization can be used. This article describes this technique, which can also be used with bridge sensors and other ratiometric devices.

Index of Articles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

TI Worldwide Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Contents

To view past issues of the Analog Applications Journal, visit the Web site

www.ti.com/aaj

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Analog Applications Journal is a collection of analog application articles designed to give readers a basic understanding of TI products and to provide simple but practical examples for typical applications. Written not only for design engineers but also for engineering managers, technicians, system designers and marketing and sales personnel, the book emphasizes general application concepts over lengthy mathematical analyses.

These applications are not intended as “how-to” instructions for specific circuits but as examples of how devices could be used to solve specific design requirements. Readers will find tutorial information as well as practical engineering solutions on components from the following categories:

• Data Acquisition

• Power Management

• Interface (Data Transmission)

• Amplifiers: Audio

• Amplifiers: Op Amps

• Low-Power RF

• General Interest

Where applicable, readers will also find software routines and program structures. Finally, Analog Applications Journal includes helpful hints and rules of thumb to guide readers in preparing for their design.

Introduction

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How delta-sigma ADCs work, Part 2

A strong addition to the process-control design environ-ment is the delta-sigma (DS) analog-to-digital converter (ADC). This device’s claim to fame is its high 24-bit reso-lution, which provides 224 or about 16 million output codes. Granted, not all of the lower bits are noise-free, but it is not unusual for a DS ADC to have 20 noise-free bits, or about 1 million noise-free output codes. This is at least four times better than the performance of 16-bit converters.

Figure 1 shows a block diagram of a DS ADC. As explained in Part 1 of this article series (see Reference 1), the modulator of a DS converter shapes the data in such a way as to allow high reso lution by reducing low-frequency noise. Part 1 also pointed out that the undesirable charac-teristics of the modulator output are high-frequency noise and a high-speed, 1-bit output rate. Once the signal resides in the digital domain, a low-pass digital-filter function can be used to attenuate the high-frequency noise, and a

Data Acquisition

By Bonnie BakerSignal Integrity Engineer

∆ΣModulator

AnalogInput

DigitalFilter

DecimatorFilter

DigitalOutput

Digital/Decimation Filter

Sample Rate ( )fS

Data Rate ( )fD

f fS D/ Decimation Ratio (DR)=

Figure 1. Block diagram of DS ADC

Input

Σ Σ Σ Output

Delay Delay

b1 bib2 b3

Delay

Figure 2. First-order, low-pass averaging filter

decimator-filter function can be used to slow down the output-data rate. This article, Part 2, will consider each function independently, although real-world designs inter-twine them in the same silicon.

The digital-filter functionThe digital-filter function implements a low-pass filter by first sampling the modulator stream of the 1-bit code. Figure 2 shows a first-order, low-pass averaging filter. An averaging filter is the most common filter technique used in DS converters. As can be seen, the digital filter in Figure 2 is a weighted averaging filter. Almost all DS ADCs incorporate a class of averaging filters called sinc filters, named for their frequency response. Many DS devices, especially audio devices, use other filters in conjunction with sinc filters as part of a process called two-stage deci-mation. Low-speed industrial DS ADCs usually use only the sinc filter.

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Data Acquisition

The output rate of a digital filter is the same as the sampling rate. Figure 3 shows a digital filter’s outputs. In the time domain (Figure 3a), the digital filter is responsible for the high resolution of the DS converter. Notice that the 24-bit code train resembles the original signal. However, in the frequency domain (Figure 3b), the digital filter applies only a low-pass filter to the signal. In so doing, it attenuates the modulator’s quantization noise; but it also reduces the frequency bandwidth, as any good low-pass filter will. With the quantization noise reduced, the sig-nal re-emerges in the time domain.

The signal is now a high-resolution, digital version of the input signal, but it is still too fast to be useful. The designer could have the converter deliver every one of the samples, but it would be pointless to do so because:

• This converter would require a very fast controller or processor.

• While it might appear that there is an abundance of high-quality samples at the high sampling rate of the modulator, most of them don’t provide any useful infor-mation, since a low-pass filter has been applied. In other words, the extra samples are interpolations or interme-diate results.

The decimator-filter functionThe second function of the digital/decimation filter is the decimator. The word “decimate” was originally used by the Roman army to mean the killing of every tenth man of a group that was guilty of mutiny. In the case of the digital/decimation filter, the “decimation” of the digital filter’s samples is much more dramatic. In the decimation circuit, the digital signal’s output rate is reduced by throwing away or “killing” portions of the output data. The way to do this is to discard some of the samples.

800000

7FFFFF

0000000

QuantizationNoise

Signal

fS

Figure 3. Outputs of a digital filter

(a) Time domain (b) Frequency domain

This may seem a bit distressing. Previously, there was a beautiful sine wave that was well-defined with a large number of samples. Throwing away a large number of those samples leaves a skeleton of the original signal; but, remember, most of those samples are not “real.” They can be thought of as the filter’s work-in-process samples. In fact, according to the Nyquist theorem, the new “skeletal” version of the signal has exactly the same informational content as the previous waveform, but now it is at a manageable data rate. Decimating some of the samples has not caused any information to be lost.

Figure 4 conceptually shows the decimation process. The digital filter’s time-domain output in Figure 3a has been brought forward to Figure 4a. Figure 4b shows the decimator-filter function’s output signal.

This completes the description of the digital-filter and decimator-filter functions in a DS converter.

Pulling the DS ADC togetherPart 1 of this series showed the inner workings of the modulator in the time and frequency domains. It also showed how the modulator shaped noise into higher

800000 800000

7FFFFF 7FFFFF

0000000 0000000

f fS D/ Decimation Ratio (DR)=

Figure 4. Digital/decimation filter’s output from decimation process

(a) Input sampling rate (fS) (b) Output-data rate (fD)

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Data Acquisition

frequencies because of an oversampling sys-tem with negative feedback. As previously stated in the present article, the digital/ decimation filter reduces high-frequency noise and passes the input signal to the out-put of the converter at a reduced data rate. The combination of these two components provides a high-resolution ADC.

The meaningful variables in this system are the modulator’s sampling rate (fS) and the digital/decimation filter’s output-data rate (fD). The ratio between these two vari-ables is defined as the decimation ratio (DR). The decimation ratio is equal to the number of modulator samples per data out-put. Decimation ratio values range anywhere from 4 in the Texas Instruments (TI) ADS1605 ADC to a maximum of 32,768 for TI’s ADS1256 ADC.

Consider the output spectrum of the DS modulator in Figure 5. The modulator samples at a fre-quency of fS and, in doing so, shapes the quantization noise into higher frequencies. Many DS converters permit the designer to program the data rate directly by adjusting the decimation ratio. Suppose the data rate is chosen to be some fraction of fS, as shown in Figure 5a. The fre-quencies from 0 to fD, which constitute the output, are in the signal band. Note the noise level in the signal band.

In Figure 5a, the effective number of bits (ENOB) is very high. Since the output-data rate (fD) is determined by the decimator-filter function, it depends on the decima-tion ratio (DR), where DR = fS/fD. Figure 5b shows that the value for fD, which has moved to the right, is now higher. Unfortunately, there is also more noise. Most of the noise is in the higher frequencies, decreasing the signal-to-noise ratio and the ENOB.

There is a way to increase the sampling speed (fS) while keeping the ENOB the same, and that is to increase the master-clock rate. This will also increase fD but will not decrease the decimation ratio. Unfortunately, increasing the master-clock rate will also increase power consump-tion. Additionally, most converters have a practical limit for fS beyond which they will not function properly.

ConclusionA DS ADC fundamentally includes a modulator and a digi-tal/decimation filter. The modulator converts the analog signal directly into the digital domain by using a 1-bit ADC and oversampling. The modulator topology implements a noise-shaping function that drives the lower-frequency quantization noise into higher frequencies. The low-pass digital/decimation filter throws away the high-frequency

noise that was shaped by the modulator stage and reduces the data-output rate of the device to a usable frequency.

There is a strong relationship between the output-data rate and the converter’s resolution. If the sample rate is kept constant, lower data rates provide high effective reso lution, or ENOB, at the output of the converter.DS ADCs have other functions besides the basics in these

two articles, acting as current sources, voltage sources, input buffers, etc. However, examining any DS ADC will always reveal a modulator and a digital/decimation filter. In choosing a DS ADC, it is best to start with the funda-mentals and then see what else the device has to offer.

ReferencesFor more information related to this article, you can down-load an Acrobat® Reader® file at www.ti.com/lit/litnumber and replace “litnumber” with the TI Lit. # for the materials listed below.

Document Title TI Lit. #1. Bonnie Baker, “How delta-sigma ADCs work,

Part 1,” Analog Applications Journal (3Q 2011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLYT423

2. “16-bit, 5MSPS analog-to-digital converter,” ADS1605/6 Datasheet . . . . . . . . . . . . . . . . . . . . SBAS274

3. “Very low noise, 24-bit analog-to-digital converter,” ADS1255/6 Datasheet . . . . . . . . . . SBAS288

Related Web sitesdataconverter.ti.comwww.ti.com/product/ADS1256www.ti.com/product/ADS1605

QuantizationNoise

QuantizationNoise

Signal Signal

fD fD

f fS D/ Decimation Ratio (DR)=

fS fS

Figure 5. Increased DR provides a lower-noise, slower output signal

(a) High DR decreases noise (b) Low DR increases noise

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Power Management

Solar charging solution provides narrow-voltage DC/DC system bus for multicell- battery applications

IntroductionSolar-powered systems typically must operate from a very wide input-voltage range due to the large variations in a solar panel’s output voltage. This wide operating range limits the system’s ability to consume maximum power from the solar cell under all light conditions. The ideal solar charging application operates the solar cell at its max i mum power point (MPP) while simultaneously limit-ing the input-voltage range of the system. This goal is achieved by inte grating a narrow-voltage DC/DC (NVDC) battery-charging architecture with a solar-charger design. The narrow voltage range for the system power bus pro-vides higher system efficiency, minimizing battery charg ing times and extending battery run times.1 This article shows the NVDC charging architecture in a solar charging appli-cation and introduces a circuit that provides acceptable charger operation under several operating conditions, such as battery overtemperature, a discharged battery, a fully charged battery, and a system-current overload.

Conventional charger topologyFigure 1 shows a conventional charger topology used with high-power switching chargers. Notebook charging is a typical application for this topology. One drawback is the system’s wide operating voltage range, which requires more expensive, less efficient power supplies to generate the

By Wang Li, Battery Power Applications Engineer,and Michael Day, Power Applications Manager

InputSource

System Load

C310 µF

Q1 Q2

Q3Power-Path

Selector

Charger

IIN_SNS

IOUT_SNS

VOUT

VSYS

Figure 1. Conventional charger topology

power rails for the downstream circuitry.1 The system volt-age ranges from the highest AC adapter voltage (typically 22 V for a lightly loaded adapter) to the lowest battery voltage, which is 9 V for a 3S2P laptop battery pack. (3S2P is an abbreviation for three batteries in series with two of these series connections in parallel.) When the AC adapter is present, the power-path-selector MOSFETs (Q1 and Q2) turn on, and the battery MOSFET (Q3) turns off. The AC adapter voltage is applied to both the system voltage and the battery charger’s input, delivering power to both circuits simultaneously. If the AC adapter voltage drops due to a brownout, an overcurrent condition, or unplug-ging the adapter, Q1 and Q2 turn off to prevent battery power from flowing backwards into the adapter. Q3 turns on and connects the battery-pack voltage directly to the system. In this way, the system is always supplied with power—either from the adapter or the battery.

Requirements of a solar-powered chargerThe battery-charger architecture in Figure 1 is acceptable for systems that use an AC adapter, but it is not ideal for solar charging applications because there is no way to limit the input current. To keep the solar cell always operating at its MPP, which will minimize battery charge time and the solar cell’s size and cost, the charger needs a current-limiting mechanism. Unlike a conventional AC wall adapter,

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Power Management

a solar cell should be operated with very tight control over its load current. Figure 2 shows the V-I characteristics of a typical solar cell under one light condition and helps explain this concept. The solid line represents the output current of the solar panel as its voltage varies, while the dashed line represents the output power. Because the panel’s voltage drops as the current it delivers increases, an MPP is created at a specific voltage and current. A solar cell’s MPP varies with differ-ent light conditions and temperatures. If very little charging and system current are required, the solar cell may operate at Point A in Figure 2, which is below its MPP. The solar cell delivers less than its maximum power, which is acceptable because the system is getting the power it needs. However, if the battery charge current or system power requirements increase, the charger pulls more current and the solar cell operates at Point B in Figure 2. At Point B, the solar cell’s output current has increased, but the actual delivered power has gone down because of the drop in volt-age. With reduced power from the solar cell, it takes longer to charge the battery. A well-designed solar-cell charger should contain circuitry that separates the solar cell from the system as well as circuitry that con-trols the solar cell’s total current so the cell can be oper-ated at its MPP. This combination of circuitry can fully utilize the solar cell’s available power, resulting in a less expensive system because the designer does not have to oversize the solar cell to meet charging requirements.

Basics of maximum-power-point trackingSolar-cell chargers include special circuitry called maximum-power-point tracking (MPPT) circuitry that prevents the charger from consuming more than the solar cell’s maximum power. This is typically implemented by setting the minimum operating voltage that corresponds with the solar cell’s MPP. A design using the solar cell in Figure 2 allows the charger and system to draw any current from the solar cell as long as the solar cell’s voltage remains above VMPP. When the current increases to the point where the voltage drops to VMPP, a special control loop in the charger takes over and regulates the total current from the solar cell to maintain the solar cell’s voltage at VMPP. At this operating point, the solar cell delivers its maximum power. Any power not required for the system load is used to charge the battery. This voltage-based MPPT circuitry is fairly accurate at provid-ing maximum power, even with varying solar-cell illumination levels. Although reduced light lowers the solar cell’s maxi-mum power and current capability, the

MPP is still achieved at approximately the same voltage.2 Voltage-based MPPT circuitry typically consists of only two resistors external to the battery charg er.3 All other circuitry is integrated into the charger IC itself. A solar cell’s VMPP does vary significantly with temperature. If desired, additional circuitry can be added to track a solar cell’s VMPP change with temperature. Tracking MPP over temperature can reduce charging times by 40%.4

Adding NVDC charging architectureFigure 3 shows how a narrow-voltage DC/DC (NVDC) charging architecture can separate the solar cell from the system. Rather than being connected to the solar cell via

0 2 4 6 8

Solar-Cell Voltage (V)

So

lar-

Cell C

urr

en

t( m

A)

So

lar-

Cell P

ow

er

(mW

)

100

80

60

40

20

0

500

400

300

200

100

0

Solar-Cell Current

Solar-CellPower

Point A

Point BIMPP

VMPP

Figure 2. Solar panel’s V-I curve and output-power curve

InputSource

System Load

C310 µF

Q1 Q2

R1

R2

Charger

IIN_SNS

IOUT_SNS

VOUT

VIN_CHG

MPPT

Reverse PolarityProtection andInrush-Current

Control

Figure 3. NVDC architecture with MPPT circuitry

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Power Management

the power-path-selector FETs, the system is connected directly to the battery. The system voltage is now equal to the battery voltage, regardless of the input voltage of the adapter or solar cell. The narrow operating voltage allows the designer to optimize the system power supplies for size, cost, and efficiency.1 It also eliminates the need for the battery FET. The NVDC architecture is useful for solar charging because it routes all current through the charger. This allows the MPPT circuitry to effectively control the total current from the solar cell and maintain operation at the maximum rated power.

Connecting the system directly to the battery as in Figure 3 has significant advantages, but it also has dis-advantages under certain operating conditions that should be considered. These conditions are as follows:

1. When the battery voltage is lower than the battery’s precharge voltage, the battery current must be limited to the precharge current, which may not be sufficient to operate the system.

2. When the battery temperature is outside the allowable range for charging, the charger must disable charging, which also disables the system’s power.

3. When the battery is fully charged, it should be discon-nected from the charging source to extend battery life, but the system should remain on.

All of these conditions can be addressed with the addi-tion of FETs Q4 and Q5 to the NVDC architecture (see Figure 4). A gas gauge or a host controller monitors volt-ages, current, and battery temperature and uses these inputs to control the FETs, which connect or disconnect the battery to or from the charger depending on the oper-ating conditions. The host can be as complicated as a micro-processor with analog-to-digital converters that continu-ously monitors operating conditions and adjusts charger performance based on the system’s needs, or it can be

simple, discrete circuitry that monitors only battery voltage and temperature.

A deeply discharged battery requires preconditioning prior to being charged. Typical Lithium-Ion (Li-Ion) batter-ies require the charger to apply a precharge current that is 1/10 of the fast-charge current until the battery voltage rises above a specific voltage, typically 3 V/cell. When the host detects a battery voltage that is less than the specified precharge voltage (VBAT < VPRECHG), it turns Q5 on and provides a precharge current through RPRECHG. The value of RPRECHG is chosen to provide the maximum allowable precharge current when the battery voltage is fully dis-charged. In this operating mode, the system is effectively isolated from the battery voltage, which allows the charger to maintain the NVDC regulation voltage even with a dis-charged battery. When the battery voltage increases above the precharge voltage, the host turns Q5 off and Q4 on, effectively shorting the battery and the system together. The battery’s charge current increases to the charger’s maximum output current minus the current into the system. If the system current exceeds the charger’s fast-charge current, the battery enters supplement mode where current flows out of the battery to the system.

If the host detects an over- or undertemperature fault condition, it turns off both Q4 and Q5. This stops the battery charging while still allowing the charger to power the system. The host can also turn Q4 and Q5 off when the battery reaches its full-charge voltage to increase battery life. Detailed information on the battery-disconnect circuitry can be found in Reference 5.

ConclusionThe NVDC charger architecture coupled with MPPT and the battery-disconnect circuitry provides several advan-tages over standard charging architectures. It intelligently connects and disconnects the battery from the system

Off

On

V > VBAT PRECHG V < VBAT PRECHG

Battery Temp.in Normal Range

OnOffQ5

OffOff

Co

ntr

ol

FE

Ts

Q4

Battery FullyCharged or

Temp. isHigh or Low

Q4

Q5

RPRECHG

InputSource

System Load

C310 µF

Q1 Q2

R1

R2

Reverse PolarityProtection andInrush-Current

Control Charger

IIN_SNS

IOUT_SNS

VOUT

VIN_CHG

MPPT

Figure 4. NVDC architecture with battery-disconnect circuitry

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Power Management

under the appropriate operating conditions, allowing the designer to optimize the solar panel’s output power for the system’s needs. The charger also provides a narrow system operating voltage, which optimizes efficiency and extends battery life.

ReferencesFor more information related to this article, you can down-load an Acrobat® Reader® file at www.ti.com/lit/litnumber and replace “litnumber” with the TI Lit. # for the materials listed below.

Document Title TI Lit. #1. Xiaoguo Liang, Gnanavel Jayakanthan, and

Meng Wang, “Design considerations for narrow Vdc based power delivery architecture in mobile computing systems,” in Proc. Applied Power Electronics Conference and Exposition (APEC), Palm Springs, CA, 2010, pp. 794–800 [Online]. Available: http://ieeexplore.ieee.org . . . . . . . . . . . . . . . . . —

Document Title TI Lit. #2. Lokesh Ghulyani, “Simple MPPT-based

lead acid charger using bq2031,” Application Report. . . . . . . . . . . . . . . . . . . . . . . SLVA378

3. “Synchronous switch-mode battery charge controller for solar power with maximum power point tracking,” bq24650 Datasheet . . . SLUSA75

4. Jared Casey, “Maximum power point tracking with the bq24650 charger,” Application Report. . . . . . . . . . . . . . . . . . . . . . . SLUA586

5. Wang Li, “A discrete narrow voltage DC/DC (NVDC) charger solution for multi-cell batteries,” Application Report . . . . . . . . . . . . . SLUA620

Related Web sitespower.ti.comwww.ti.com/product/bq2031www.ti.com/product/bq24650

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Solar lantern with dimming achieves 92% efficiency

Solar lanterns are becoming increasingly popular, especially for decorative nighttime lighting or in areas with unreliable or nonexistent electrical service. These lanterns charge a battery during the day and then use that stored energy during the night to provide light on outdoor paths and side-walks, or for indoor activities such as cooking or reading. Since the lanterns typically are powered by low-cost and robust multicell lead-acid batteries, a common problem encountered is how to efficiently convert this chemical energy to lumens (visible light output). To solve this, LEDs are frequently used because they produce many lumens per watt of energy consumed. A switching regulator is usually employed to efficiently convert the variable battery voltage to a regulated yet changeable (dimmable) current in the LED, which creates light. Efficiency must remain high over the battery voltage and dimming range in order to prolong battery life. A complete, cost-effective solu tion is needed to efficiently convert the 6, 9, 12, or 15 V of a common lead-acid battery pack to light with dimming capabilities.

Single LED versus an LED stringWhen designing a solar-lantern system, designers must choose whether to produce the desired amount of light with multiple smaller, lower-power LEDs or one larger, high-brightness LED. Typically, a single LED driver drives a string of smaller LEDs in a series configuration. The advantages of this approach are that the current in each LED is exactly the same and the LEDs can be positioned to illuminate a wider area than is possible with a single LED. However, even with equal currents, the LEDs cannot each emit exactly the same color of light unless they are tested and binned before assembly. This is more costly.

A single high-brightness LED emits light to a smaller area, but this can be overcome by a diffuser cover placed over the LED. When pick-and-place costs in assembly are considered, a single high-brightness LED is usually more cost-effective overall than several smaller LEDs. A single

By Chris GlaserApplications Engineer

Power Management

LED does not need to be binned, which also reduces costs. This article discusses use of the low-cost, single high-brightness LED. The LED current is set to 800 mA for a dimmable 2.8-W power output, which is typical for solar lanterns.

Easily dimmableThe light output of the solar lantern must be adjustable according to the needs of the user. For instance, more light might be required for reading than for cooking. Dimming the light output draws less energy from the battery and results in a longer battery run time.

Analog dimming and pulse-width-modulator (PWM) dimming are two methods that can be implemented to reduce the LED’s light output. Analog dimming reduces the average current in the LED, while PWM dimming operates the LED at full current but varies the duty cycle at which this full current is applied. Thus, PWM dimming creates an average LED current equivalent to the full cur-rent multiplied by the duty cycle of the applied PWM sig-nal. The PWM dimming frequency should be above the bandwidth detectable by the human eye so that the viewer does not notice any flicker. In general, analog dimming is more efficient, but PWM dimming eliminates the LED color shift that occurs when the LED is driven at different currents (as in analog dimming). So, the LED light color remains the same across the dimming range. Since both dimming methods have advantages and disadvantages, the ideal solar-lantern LED driver should accommodate both dimming methods. A PWM signal from a microcontroller, which typically is present in the solar-lantern system for battery management and other tasks, should be the single dimming interface with the LED driver for both methods. The Texas Instruments TPS62150 supports analog and PWM dimming from a PWM signal, as shown in Figures 1 and 2 (see next page). Detailed design equations are found in References 1 and 2.

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Power Management

The advantage of these circuits is their similarity. Only small schematic changes and a change to the PWM signal’s frequency are needed to implement analog or PWM dim-ming in a given design. This means that the same LED driver circuit can be used for multiple solar-lantern designs. Simply populate the circuit with different components and load a slightly different code to the microcontroller, and the solar lantern is optimized for either highest efficiency or most constant light color through the use of either ana-log or PWM dimming.

TPS62150RGT

PVIN

PVIN

AVIN

EN

SS/TR

11

12

10

13

DE

F

FS

W

PG

ND

PG

ND

8 7

16

15

SW

SW

SW

Vos

FB

PG

AGND

ETPad

1

2

3

14

5

4

6

17

PWM

4 to 17 V

C10.1 µF

4.7 µF 22 µF

R3

12.7 kΩ

LED CurrentSet to 800 mA

3.3 µH

R1

0.1 ΩR2

499 Ω

VIN VOUTVOUT

9

Figure 1. Circuit schematic for analog dimming

TPS62150RGT

PVIN

PVIN

AVIN

EN

SS/TR

11

12

10

13

DE

F

FS

W

PG

ND

PG

ND

8 7

16

15

SW

SW

SW

Vos

FB

PG

AGND

ETPad

1

2

3

14

5

4

6

17

PWM

4 to 17 V

9

4.7 µF 22 µF

LED CurrentSet to 800 mA

3.3 µH

R1

0.1 ΩR2

49.9 kΩ

VIN VOUTVOUT

Figure 2. Circuit schematic for PWM dimming

Another major concern is the dimming linearity. Does the rate of change in the LED current (and thus the light output) across the dimming range correspond to the rate of change of the input signal (in this case, the duty cycle of the PWM signal)? If this is true for the given LED driver, then the code development is quite simple, as a 10% increase in duty cycle results in a 10% increase in light output. If this were not true, then additional testing and code would be needed to correlate a given change in the input signal to the desired change in light output. This

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Power Management

correlation might also vary across the dimming range, resulting in further complications to the dimming algorithm. Fortunately, the circuits in Figures 1 and 2 support very high dimming linearity, as shown in Figures 3 and 4. Each circuit has a coefficient of determination (R2 value) of 1, which indicates perfect linearity. (The R2 value is a statistical measure of the vari a bility in a data set, and a value of 1 indicates zero variability.) This results in a very simple code development for the dim-ming algorithm and provides a pleasant user experience in the smooth dimming behavior of the lantern.

However, for analog dimming, the linear equations modeling this linearity have a y-axis intercept of 94 mA. This shows another limitation of analog dimming—an inability to dim the LED at very low out-put currents. To solve this, PWM dimming is used, with a y-axis intercept of –7 mA. This allows very low LED currents to be achieved at very low PWM duty cycles.

Achieving high efficiencyEfficiency is critical in any battery- powered system, but especially in a solar lantern. Since it cannot be assumed that every day will have sunlight, the batteries have to last for more than one day at a time without a recharge. By an efficient conversion of stored chemical energy to light and a reduction of the light output through dimming, the LED driver increases the battery run time. In addition to sup-porting dimming, an efficient LED driver should (1) operate at a relatively low switching frequency to reduce the switch-ing losses, (2) have a power-save mode to boost the efficiency at low light levels, and (3) have a cost-effective method to reduce the losses in the current-sensing resistor, R1 in Figure 1. The TPS62150 is a good choice because it has these three features and produces the efficiency

0 10 20 30 40 50 60 70 80 90 100

1000

800

600

400

200

0

LE

D C

urr

en

t( m

A)

V = 12 VIN

V =IN 15 V

V =IN 9 V

V =IN 6 V

Duty Cycle (%)

Figure 3. Analog dimming linearity

0 10 20 30 40 50 60 70 80 90 100

1000

800

600

400

200

0

LE

D C

urr

en

t( m

A)

V = 12 VIN

V =IN 15 V

V =IN 9 V

V =IN 6 V

Duty Cycle (%)

Figure 4. PWM dimming linearity

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Power Management

shown in Figures 5 and 6. Due to a higher voltage drop when the LED is driven at its full current, and due to reduced effi-ciency during the turn-on and turn-off of the IC, the efficiency of PWM dimming is lower than that of analog dimming.

ConclusionThis article has presented an efficient 2.8-W solar-lantern solution that drives a single high-brightness LED and provides either analog or PWM dimming from a PWM signal. Analog dimming achieves better efficiency over the entire dimming range, while PWM dimming allows very low LED currents (for very low light levels) at low PWM duty cycles and has the best efficiency at full output power. Both dimming circuits are extremely linear. This design is well-suited for solar lanterns powered from rechargeable lead-acid, nickel, or lithium batteries.

ReferencesFor more information related to this article, you can down-load an Acrobat® Reader® file at www.ti.com/lit/litnumber and replace “litnumber” with the TI Lit. # for the materials listed below.

Document Title TI Lit. #1. “Using the TPS62150 as step-down LED

driver with dimming”. . . . . . . . . . . . . . . . . . . . . SLVA4512. “Design tool for analog dimming using a

PWM signal” . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLVC366

100

90

80

70

60

50

40

Eff

icie

nc

y (

%)

V = 12 VIN

V =IN 15 V

V =IN 9 V

V =IN 6 V

0 100 200 300 400 500 600 700 800 900 1000

LED Current (mA)

Figure 5. Analog dimming efficiency

0 100 200 300 400 500 600 700 800 900 1000

100

90

80

70

60

50

40

Eff

icie

nc

y (

%)

V = 12 VIN

V =IN 15 V

V =IN 9 V

V =IN 6 V

LED Current (mA)

Figure 6. PWM dimming efficiency

Document Title TI Lit. #3. “3-17V 1A step-down converter in 3×3 QFN

package,” TPS62150/1/2/3 Datasheet. . . . . . . . SLVSAL5

Related Web sitespower.ti.comwww.ti.com/product/TPS62150

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Interface (Data Transmission)

Extending the SPI bus for long-distance communication

The serial peripheral interface (SPI) bus is an unbalanced or single-ended serial interface designed for short-distance communication between integrated circuits. Typically, a master device exchanges data with one or multiple slave devices. The data exchange is full-duplex and requires syn-chronization to an interface clock signal. However, recent trends in the design of industrial data-acquisition systems have not taken this synchronization requirement into account, and distances between the microcontroller and the corresponding analog-to-digital and digital-to-analog converters (ADCs and DACs) can reach 100 m or more.

The impact of the added propagation delay on the data-to-clock synchronicity is often ignored, and interface designs that operate perfectly in the lab environment cease operation when implemented on the factory floor. There can be multiple reasons for the interface malfunction. This article tries to shed light on the major ones, including:

• Lack of synchronization due to large propagation delays of the signal path

• Reduced noise immunity due to long-distance, unbalanced signal paths

• Damaged transceivers due to large ground-potential differences (GPDs)

• Data transmission errors due to unterminated data lines

• Transceiver latch-up and network downtime due to large electrical transients

SynchronicityAn SPI primarily uses three interface lines:

• An interface clock initiated by the master device to ensure synchronous data transfers

• A data line for data sent from the master to a slave

• A data line for data sent from a slave to the master

A fourth wire that carries what is known as the slave-select signal is not required for controlling interface flow but is needed for addressing a specific slave out of a range of slave devices. Figure 1a shows a simplified schematic of a microcontroller unit (MCU) operating as the master that controls two data converters representing the slaves.

With byte lengths ranging from 8 to 12 bits and multiples thereof, and data rates ranging from 1 to 20 Mbps, the standard SPI configuration allows for short propagation times and hence only short distances in order to maintain synchronicity between the interface clock and the data transmitted in both directions. Figure 1b shows the inter-face timing of the first three data bits when the SPI is configured to change data at the rising clock edge and to sample data at the falling clock edge.

Over long distances, however, the transmission cable introduces significant propagation delay into the signal path. Assuming a typical signal velocity of 5 ns/m, a 100-m cable will cause a propagation delay of 500 ns. Because the data sent from the master to the slave experiences the same delay as the master-initiated interface clock, both will remain in sync across the entire data link. In the oppo-site direction, however, the slave sends data to the master only when the first clock edge reaches the slave. Further-more, this data will experience a second delay on its way back to the master, so the slave data will be out of sync by twice the cable’s propagation delay.

Of course, communicating across a 100-m cable won’t be possible without appropriate line drivers and receivers. These components will further increase the propagation delay by about another 50 ns, for a total of 550 ns. The slave data will therefore lag behind the first clock edge by a total of 1100 ns, or 11 bits when a data rate of 10 Mbps is assumed.

By Thomas KugelstadtSenior Applications Engineer

CLK

SIMO

SOMIADC1

SCK

MOSI

MISOMCU

CE

CE

CLK

SIMO

SOMIADC2

SS1

SS2

Figure 1. Simplified schematic of an SPI

(a) MCU master controlling two slaves

(b) Timing of first three data bits

MOSI SIMO

SCK

MISO SIMO

Tx2

Rx2

Tx3

Rx3

Tx1

Rx1

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Interface (Data Transmission)

The only possible solution for restoring synchronicity between the slave data and the interface clock while maintaining a high data rate is to feed the clock signal from the slave back to the master. Figure 2 clarifies the benefit of clock feedback. Here t0 represents the first rising clock edge, or the start of a data transmission, and tP is the data-link propagation delay. After tra-versing the data link, both the master clock (SCKM) and the master data (MOSI) remain in sync. Feeding back the master clock signal synchronizes the clock with the slave data so that both arrive equally delayed at the master. The only require-ment is that the master provide two inde-pendent SPI ports, one configured as a master (SPI1) and the other configured as a slave (SPI2). Most modern microcontrol-lers possess two or more SPI ports, so this requirement poses no problem.

Nevertheless, implementing a long-distance, SPI-compatible interface in the real world is not a trivial task. Long-distance data links are always subject to external noise sources, ground-potential differences (GPDs), volt-age and current surges due to inductive load switching, and often even reflections due to wrong or no termination. The flowing schematic in Figure 3 (see next page) tries to cover all of these aspects by showcasing the various trans-ceiver and protection circuits that can counteract the derogating effects.

Increasing noise immunityUnbalanced or single-ended drivers and receivers are inadequate for accomplishing a robust data link over long distances, as they are susceptible to common-mode noise. An excellent method to eliminate common-mode noise in a synchronous, full-duplex interface such as an SPI is the use of RS-422 differential driver and receiver circuits in combination with twisted-pair cable.

Because the conductors of twisted-pair cable are closely electrically coupled, external noise induced equally into both conductors appears as common-mode noise at the receiver input. Although differential receivers are sensitive to signal differences, they are immune to common-mode signals. The receiver therefore rejects common-mode noise, and signal integrity is maintained.

Another benefit of close electric coupling is that the currents in the two conductors create magnetic fields that cancel each other. The initial transversal electromagnetic (TEM) waves of the two conductors are therefore largely reduced to electric fields that cannot radiate into the envi-ronment (see Figure 4). Only the far smaller fringing fields outside the conductor loop can radiate, thus yielding much lower electromagnetic interference (EMI).

Eliminating ground loops and GPDsWhile the RS-485 and RS-422 standards specify that a data link without a ground wire can be operated with a GPD of up to ±7 V, it is advisable not to assume that these values

SCKM

SCKS

CLK

MOSI

SIMO2

SIMO1

DataLink

SOMI

Master

t0

t0

t + 2t0 P

t + t0 P

t + t0 P

t + t0 P

t + t0 P

tP

tP

tP

tP

t + 2t0 P

Slave

SPl1 =Master

SPl2 =Slave

Figure 2. Clock-feedback path restores synchronicity

H

E

t

Figure 4. TEM-wave radiation effects

(a) Relationship of magnetic and electric fields (b) Single conductor (c) Closely coupled conductor pair

LargeFringingFields

LargeFringingFields

SmallFringingFields

CoupledFields

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Interface (Data Transmission)

EN1 EN2

SDI

SDO

CLKIN

GND

ADC

A0

A0

To PE Mains

DE

1D

2D

1R

2R

1Y

1A

2A

2Y

1Z

1B

2B

2Z

VCC

GNDRE

1 kΩ

1 kΩ

100 Ω

100 Ω

UCA0SOMI

UCA0CLK

UCB0SIMO

UCB0CLK

DVCC

DVSS

SPIMaster

SPISlave

MasterNode

To PE Mains

PE

VS1a

VS1b

RF

RF

RF

RF

CF

CF

CF

CF

4700 pF2 kV

MSP430G2X33 SN65C1167

0.1 µF0.1 µF

1 kΩ

VS2

VS2

0.1 µF

0.1 µF

RF

RF

RF

RF

CF

CF

CF

CF

DE

1R

2R

1D

2D

1A

1Y

2Y

2A

1B

1Z

2Z

2B

VCC VCC1 VCC2

VCC

GND GND1 GND2

INA

IN

OUT

OUT

B

C

D

OUTA

OUT

IN

IN

B

C

D

RE

1 kΩ 1 kΩ

1 kΩ

100 Ω

100 Ω

SlaveNode

PE

VS2_ISO

4700 pF2 kV

SN65C1167 ISO7242C

0.1 µF 0.1 µF

Figure 3. SPI extended via RS-422 data link

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Interface (Data Transmission)

represent the maximum GPD. Much higher values are often encountered in industrial plants, sometimes reaching sev-eral hundreds and even thousands of volts. Because GPDs largely depend on factors outside the system designer’s control, such as the electric installation and/or the number of electric motors and generators, the most secure way to prevent transceiver damage from large ground-potential variations is to galvanically isolate any remote network node from the bus. The circuit in Figure 3 demonstrates this by having only the remote transceiver connected to the bus, while the data-converter circuit is galvanically isolated.

Also, to provide the input and output signals of the remote transceiver with a stable ground reference, the transceiver’s ground terminal as well as the digital isola-tor’s ground terminal (GND1) are connected to the master ground potential via a separate ground conductor. This form of grounding is known as a single ground reference.

Avoiding antennas through line terminationThe data link in Figure 3 is terminated with 100-W resis-tors, as suggested by the RS-422 standard, matching the characteristic impedance of the bus cable. A myth exists that bus cables of a few meters in length or data links operating at low data rates don’t need termination. Don’t believe it. Operating the bus without termination can turn the transmission line into a nasty receiver/transmitter antenna. The lack of termination resistors, which usually absorb the incident wave power sent by the driver, causes standing waves to occur; and the entire incident wave is reflected into the bus. The reflected waves mix with other incident waves, thus yielding standing waves for signal fre-quencies whose quarter wavelengths, or multiples thereof, equal the length of the data link.

Depending on their location, the wave nodes (minima) and antinodes (maxima) can have varying effects on the bus transceivers (see Figure 5). A driver close to an anti-node sees a high impedance and therefore transfers insuf-ficient energy to the bus. A driver close to a node sees a very low impedance or a short. The resulting output current can exceed the driver’s maximum drive capability and even trigger its current limit at around 250 mA. Receivers located at antinodes can be damaged by excessively large input signals that exceed the receiver’s common-mode input range. Receivers close to nodes experience insuffi-cient signal strength and are highly susceptible to noise and EMI. Any of the foregoing events will result in data errors from either the transmission or the reception of wrong data.

Protecting the network against damaging transientsElectrical overstress transients caused by electrostatic dis-charge (ESD), switching of inductive loads, or lightning strikes will corrupt data transmission and damage bus transceivers unless effective measures are taken to dimin-ish their impact. Modern transient-voltage suppressors, such as the ones in Figure 3, are the preferred protection components for high-speed data transmission due to their low capacitance, which allows them to be designed into every node of a multinode network without requiring a reduction in data rate.

Depending on the power rating of the transient-voltage suppressor chosen, the maximum clamp voltages can range from 25 to 35 V, which is higher than a standard transceiver’s maximum bus voltage of 14 V. In this case, the internal protection circuit of the transceiver must

Driver sees a lowimpedance (short)

Receiver sees ahigh impedance

L = ¼ × n × λfor n = 1, 3, 5

L

OpenLine

Figure 5. Effects of an unterminated bus

(a) Effects with a quarter-wave line length

(b) Effects of connecting drivers and receivers at nodes and antinodes

Driver at Antinode– Driver sees a

high impedance– Very small supply

current

Receiver at Antinode– Received signal can

exceed maximumcommon-modeinput range

– Receiver can bedamaged

Driver at Node– Driver sees

a short– Very high

supply current

Receiver at Node– Low signal voltage– Highly susceptible

to noise/EMI

OpenLine

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Interface (Data Transmission)

absorb the remaining clamp energy to protect the device from damage.

For ESD and burst transients, the clamp energy is rather low due to the short pulse duration and does not pose a problem to the internal ESD cells. Clamp energy from surge transients, however, can present a serious challenge due to the much longer pulse duration. For transceivers specified with low ESD immunity, series resistors might be necessary to reduce the remaining current flowing into the transceiver. Common resistor values range from 5 to 10 W. Note that these resistors must be surge-rated to provide high pulse robustness.

Although the transient-voltage suppressor’s diodes divert large transient currents to ground, it must be ensured that these currents are further diverted to true earth potential without disturbing the ground reference of the remaining circuitry. Often this is accomplished by implementing a

high-voltage capacitor that has one plate connected to ground and the other plate connected to a protective-earth (PE) island. This island is then connected via a short, low-inductance earthing wire to the PE terminal of the local mains supply.

In addition to the suppressor’s action on the bus side, further protection against signal degradation is required on the transceiver’s single-ended sides. This is accomplished with R-C low-pass filters, which filter transient remnants in the reception path and stop high-frequency noise from entering the transmission path.

Related Web sitesinterface.ti.comwww.ti.com/product/ISO7242Cwww.ti.com/product/SN65C1167

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General Interest

Analog linearization of resistance temperature detectors

Resistance temperature detectors (RTDs) are commonly used in industrial and scien-tific temperature measurements. The most common types are pure platinum (Pt) formed into wire or evaporated in a thin film on a substrate. They rely on the funda-mental temperature-dependent resistance properties of this noble metal. They are very stable and useful at temperatures ranging from cryogenic to over 800°C. A wide range of physical configurations, resist ance ranges and accuracies is avail-able.1 The commonly used notation “Pt100” indicates a 100-W resistance at 0°C. The relationship between the RTD’s resistance and temperature is described by the Callendar-Van Dusen equation,

RRTD = R0[1 + AT + BT2 + C(T – 100)T3],

whose values are defined as follows:

R0 is a 100-W resistance at 0°C (Pt100)A = 3.9083 × 10–3

B = –5.775 × 10–7

C = 0 for T > 0°C, or C = –4.23225 × 10–12 for T < 0°C.

The resistance of a Pt100 RTD increases with tempera-ture at approximately 0.39%/°C. While they are far more linear than thermocouples, RTDs have a significant second-order nonlinearity of approximately 0.38% per 100°C measurement range (see Figure 1). This nonlinearity is often corrected digitally, but there are many applications for purely analog processing and linearization of the RTD.

This article explains an analog technique for linearization of the RTD. The same technique is also used with bridge sensors such as pressure and load cells. The principles can be applied to other ratiometric devices with primarily second-order nonlinearity; i.e., any sensor or system with an output that is proportional to an excita-tion voltage or current.

The exaggerated graph in Figure 2 shows that the temperature coefficient decreases with increasing temperature, producing an upward bow in the middle. Above 0°C, standardized data for the Pt100 has a purely second-order or para-bolic function. Assuming calibration at two end-point temperatures, this produces an error that is greatest at the midpoint temperature.

By Bruce TrumpStaff Technologist

400

350

300

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100

50

0

–100 0 100 200 300 400 500 600 700 800

Temperature (°C)

Re

sis

tan

ce

()

Ω

100 at 0°CΩCurvature due tosecond-ordernonlinearity

Figure 1. Resistance of Pt100 RTD versus temperature

RTD Temperature

RT

D V

olt

ag

e

RTD

VOUTA

RTD voltage isgradually boostedwith increasingexcitation current

RTD resistancewith second-ordernonlinearity(exaggerated)

Figure 2. RTD voltage versus temperature

When the RTD is excited with a current source, the resulting RTD voltage is directly proportional to the resist-ance, yielding the same nonlinearity. If, however, the excita-tion current is gradually increased as the RTD temperature

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General Interest

is increased, the nonlinearity can be greatly reduced. Figure 2 shows an increasing excitation current derived from the output of the amplified RTD voltage. This current is, in effect, a controlled amount of positive feedback. It yields an interesting “chicken-or-egg” dichotomy: The RTD voltage at the input of the amplifier is linearized when the output of the amplifier is linearized—and vice versa. The correct amount of positive feedback results in both.

When positive feedback is optimized, a much smaller s-shaped error remains with nearly equal negative and positive values, reaching maximums at ¼ and ¾ full scale (see Figure 3). This primarily third-order nonlinearity does not come from the RTD but is an artifact of the linearization tech-nique. Its magnitude depends on the tem-perature range chosen for linearization. Figure 3 shows the initial nonlinearity error for a –100°C to +800°C temperature range—a 900°C span. The 3.7% RTD non-linearity at midscale is reduced to approxi-mately ±0.11%, a 33:1 improvement. The improvement is even greater for narrow temperature ranges, approaching 150:1 for a 200°C range.

The use of positive feedback might raise the concern of possible circuit instability. The magnitude of this feedback is small enough, however, to have negligible effect on the stability of commonly used circuits.

Figure 4 shows a practical implementation of an RTD. R1 provides the primary excita-tion current from VREF, a stable voltage reference. R5 provides the temperature- varying component of excitation current from the output of A1. R2, R3, and R4 set the required amplifier gain and offset to produce the desired output-voltage range. The Texas Instruments (TI) OPA188* shown in this example is a new low-noise, chopper-stabilized operational amplifier that contributes negligible error to the circuit. Its very low and stable offset voltage makes it a possible upgrade to TI’s OPA277 precision industrial amplifier.

The resistor values to achieve best correction can be calculated with iterative techniques. Many designers might optimize this type of circuit by using creative calculations or approximations. A closed-form solution is possible by

solving the nodal equation that relates the RTD voltage, RTD resistance, VREF, R1, R5, and VOUT:

RTD RTD

RTD RTDRTD REF OUT

RTD RTD

RTD RTD

R R5 R R1

R R5 R R1V V V

R R5 R R1R1 R5

R R5 R R1

× ×+ +

= × + ×× ×

+ ++ +

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

–0.5

–100 0 100 200 300 400 500 600 700 800

Temperature (°C)

Err

or

( %)

Corrected output withnonlinearity peaksat ¼ and ¾ scale

Nonlinearity of RTDfor 900 C span°

Zero error atmidscale andendpoints

Figure 3. Percentage of RTD error versus temperature

*The OPA188 is expected to be available in early 2012. For general specifica-tions, please refer to the dual version, OPA2188, at www.ti.com/product/OPA2188

0ºC to200ºC

Pt100

100 Ω

R1

4.99 kΩ

R4

1 kΩ

R5

106.18 kΩ

R3

60.44 kΩ

R2

49.13 kΩ

A1OPA188

V

0 V at 0°C

5 V at 200°C

OUT

V

5 VREF

–

+

+

Figure 4. Typical RTD configuration with error compensation

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General Interest

Three conditions must be met to achieve zero error at the calibration endpoint tem-peratures and the midpoint temperature. Three separate variations of the preceding equation are written to describe the three zero-error conditions and are solved simul-taneously for the only unknown variable, R5. The resistance of the RTD at the mid-point temperature is not halfway between the endpoint resistances. This midpoint condition holds the key to the solution for best linearity correction.

The math yields three results for R5; only one is a positive resistance. The expres sion for R5 is very long and impractical to pre-sent here. To download an Excel® work-sheet that provides the calculations, go to http://www.ti.com/lit/zip/SLYT442 and click Open to view the WinZip® directory online (or click Save to download the WinZip file for offline use). Then open the file RTD_Linearization_v7.xls to view the calculation worksheet. This closed-form solution is intellectually satisfying and avoids possible problems with convergence, but the results are no better than those produced with iterative calculations. Practical implemen-tations often require trimming of resistors for calibration because accurate, non-standard values are often required. SPICE simulation can help determine actual perform ance with the nearest standard values. The WinZip file download listed above also includes two RTD simulation examples in TINA-TI™ SPICE files. One file implements an RTD linearization circuit based on an operational amplifier, and the other file is based on an instrumentation amplifier. Please see Reference 2 for more information on an RTD simulator for SPICE.

Figure 5 shows that uncorrected non-linearity of the RTD increases as the cali-brated temperature range is increased, reaching approximately 2% for a 500°C span. The variation in the RTD’s excitation current to compensate for this nonlinearity is approx-imately four times the nonlinearity. Thus, for a 500°C measurement span, the excitation current increases by approximately 8% from low-scale temperature to full scale.

Low-resistance connections to the RTD are crucial in maintaining accuracy with this circuit. For this reason, high-resistance RTDs such as Pt1000 or Pt5000 may be most practical. With a four-wire (or Kelvin) connection to the RTD and an additional operational amplifier, errors induced by wire resistance can be eliminated.

An integrated instrumentation amplifier with a three-wire RTD connection can provide an alternative solution (see

16

14

12

10

8

6

4

2

0

0 100 200 300 400 500 600 700 800

Temperature Measurement Span (°C)

Pe

rce

nt

()

%

UncorrectedRTD error

Required change inexcitation current

Figure 5. Correlation of excitation current to RTD error

0ºC to200ºC

REF

Pt100

100 Ω

R1

4.99 kΩ

R5

106.18 kΩ

R6

4.99 kΩ

R7

99.9 Ω

A1INA826

V

5 VREF

R8801 Ω

–

RG

RG

+

+

Equal resistance createscommon-mode voltage

Resistance createscommon-mode voltage

V

0 V at 0°C

5 V at 200°C

OUT

Figure 6. Amplifier with three-wire RTD connection

Figure 6). In the three-wire connection, two connections are used on the ground side of the RTD. Equal currents flowing in equal line resistances create a common-mode input voltage that is rejected by the instrumentation amplifier. Current flowing in the ground-wire connection also creates a common-mode voltage. Note that the cur-rents in signal connections are not precisely equal. They differ due to the varying linearity correction current from R5. Nevertheless, this configuration removes most of the error that is due to line resistance.

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Analog Applications JournalHigh-Performance Analog Products www.ti.com/aaj 4Q 2011

General Interest

Table 1. Partial listing of TI’s integrated circuits for RTDs and bridge sensors

PRODUCT SENSOR TYPE EXCITATION OUTPUT FEATURES

XTR105 RTD Dual 1-mA current 4 to 20 mA Resistor-programmed range and linearization

XTR106 Pressure bridge Voltage 4 to 20 mA Corrects positive or negative second-order nonlinearity

XTR108 RTD Dual programmable current 4 to 20 mA or voltage Programmable excitation current and linearization

XTR112 High-impedance RTD Dual 100-µA current 4 to 20 mA Excitation for Pt1000 RTD

XTR114 High-impedance RTD Dual 250-µA current 4 to 20 mA Excitation for Pt5000 RTD

PGA309 Pressure bridge Programmable voltage Voltage Digitally controlled analog-signal path with linearization

Other sensor typesBridge sensors such as strain gauges and load cells fre-quently require linearization with similar techniques. Voltage excitation is generally used for these applications, but the concept is the same. Excitation voltage is varied with amplifier output voltage. These sensors can have a downward bowing nonlinearity requiring that the excita-tion voltage decrease as pressure increases. Furthermore, nonlinearity may vary significantly from unit to unit, so individual calibration may be required.

Integrated solutionsTI uses variable excitation for linearization in several inte-grated circuits intended for RTDs and bridge sensors (see Table 1). Some circuits are designed specifically for remote sensors with two-wire, 4- to 20-mA current-loop output. XTR106 and PGA309 provide voltage excitation, which is preferred for many strain-gauge bridge-sensor applications. Though designed for specific sensor types, these devices have been successfully adapted to a variety of sensor applications, with and without variable excitation for linearization.

References1. Resistance thermometer. Wikipedia [Online]. Available:

http://en.wikipedia.org/wiki/Resistance_thermometer2. Thomas Kuehl. (2007, May 28). Developing a precise

Pt100 RTD simulator for SPICE. EN-Genius Network: analogZONE: acquisitionZONE [Online]. Available: http://www.analogzone.com/acqt_052807.pdf

3. Bruce C. Trump. (1994, March 3). Pressure gauge responds linearly to altitude. EDN [Online]. Available: http://www.edn.com/archives/1994/030394/05di5.htm

Related Web siteswww.ti.com/product/partnumberReplace partnumber with INA826, OPA277, OPA2188, PGA309, XTR105, XTR106, XTR108, XTR112, or XTR114

Support files with Excel spreadsheet and TINA-TI™ simulation examples: www.ti.com/ lit/zip/SLYT442

25

Analog Applications Journal

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4Q 2011 www.ti.com/aaj High-Performance Analog Products

Index of Articles

Index of Articles Title Issue Page Lit. No.

Data AcquisitionAspects of data acquisition system design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . . 1 SLYT191Low-power data acquisition sub-system using the TI TLV1572 . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . . 4 SLYT192Evaluating operational amplifiers as input amplifiers for A-to-D converters . . . . . . . . . . . . . . . . .August 1999 . . . . . . 7 SLYT193Precision voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999. . . . 1 SLYT183Techniques for sampling high-speed graphics with lower-speed A/D converters . . . . . . . . . . . . . .November 1999. . . . 5 SLYT184A methodology of interfacing serial A-to-D converters to DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000. . . . . 1 SLYT175The operation of the SAR-ADC based on charge redistribution. . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000. . . . 10 SLYT176The design and performance of a precision voltage reference circuit for 14-bit and

16-bit A-to-D and D-to-A converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . . 1 SLYT168Introduction to phase-locked loop system modeling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . . 5 SLYT169New DSP development environment includes data converter plug-ins . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . . 1 SLYT158Higher data throughput for DSP analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . . 5 SLYT159Efficiently interfacing serial data converters to high-speed DSPs . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 10 SLYT160Smallest DSP-compatible ADC provides simplest DSP interface . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . . 1 SLYT148Hardware auto-identification and software auto-configuration for the

TLV320AIC10 DSP Codec — a “plug-and-play” algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . . 8 SLYT149Using quad and octal ADCs in SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 15 SLYT150Building a simple data acquisition system using the TMS320C31 DSP . . . . . . . . . . . . . . . . . . . . .February 2001. . . . . 1 SLYT136Using SPI synchronous communication with data converters — interfacing the

MSP430F149 and TLV5616 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . . 7 SLYT137A/D and D/A conversion of PC graphics and component video signals, Part 1: Hardware . . . . . .February 2001. . . . 11 SLYT138A/D and D/A conversion of PC graphics and component video signals, Part 2: Software

and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . . 5 SLYT129Intelligent sensor system maximizes battery life: Interfacing the MSP430F123

Flash MCU, ADS7822, and TPS60311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . . 5 SLYT123SHDSL AFE1230 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . . 5 SLYT114Synchronizing non-FIFO variations of the THS1206 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 12 SLYT115Adjusting the A/D voltage reference to provide gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . . 5 SLYT109MSC1210 debugging strategies for high-precision smart sensors . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . . 7 SLYT110Using direct data transfer to maximize data acquisition throughput. . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . 14 SLYT111Interfacing op amps and analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2002 . . . . . . . . . 5 SLYT104ADS82x ADC with non-uniform sampling clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . . 5 SLYT089Calculating noise figure and third-order intercept in ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . 11 SLYT090Evaluation criteria for ADSL analog front end. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . 16 SLYT091Two-channel, 500-kSPS operation of the ADS8361 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . . 5 SLYT082ADS809 analog-to-digital converter with large input pulse signal . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . . 8 SLYT083Streamlining the mixed-signal path with the signal-chain-on-chip MSP430F169. . . . . . . . . . . . . .3Q, 2004 . . . . . . . . . 5 SLYT078Supply voltage measurement and ADC PSRR improvement in MSC12xx devices . . . . . . . . . . . . .1Q, 2005 . . . . . . . . . 5 SLYT07314-bit, 125-MSPS ADS5500 evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . 13 SLYT074Clocking high-speed data converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . 20 SLYT075Implementation of 12-bit delta-sigma DAC with MSC12xx controller . . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . 27 SLYT076Using resistive touch screens for human/machine interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . . 5 SLYT209ASimple DSP interface for ADS784x/834x ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . 10 SLYT210Operating multiple oversampling data converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . . 5 SLYT222Low-power, high-intercept interface to the ADS5424 14-bit, 105-MSPS converter for

undersampling applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . 10 SLYT223Understanding and comparing datasheets for high-speed ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2006 . . . . . . . . . 5 SLYT231Matching the noise performance of the operational amplifier to the ADC . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . . 5 SLYT237Using the ADS8361 with the MSP430™ USI port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . . 5 SLYT244Clamp function of high-speed ADC THS1041 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2006 . . . . . . . . . 5 SLYT253Conversion latency in delta-sigma converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . . 5 SLYT264Calibration in touch-screen systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2007 . . . . . . . . . 5 SLYT277Using a touch-screen controller’s auxiliary inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2007 . . . . . . . . . 5 SLYT283

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Index of Articles

Title Issue Page Lit. No.

Data Acquisition (Continued)Understanding the pen-interrupt (PENIRQ) operation of touch-screen controllers . . . . . . . . . . .2Q, 2008 . . . . . . . . . 5 SLYT292A DAC for all precision occasions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2008 . . . . . . . . . 5 SLYT300Stop-band limitations of the Sallen-Key low-pass filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2008 . . . . . . . . . 5 SLYT306How the voltage reference affects ADC performance, Part 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2009 . . . . . . . . . 5 SLYT331Impact of sampling-clock spurs on ADC performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2009 . . . . . . . . . 5 SLYT338How the voltage reference affects ADC performance, Part 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2009 . . . . . . . . 13 SLYT339How the voltage reference affects ADC performance, Part 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2009 . . . . . . . . . 5 SLYT355How digital filters affect analog audio-signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2010 . . . . . . . . . 5 SLYT375Clock jitter analyzed in the time domain, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2010 . . . . . . . . . 5 SLYT379Clock jitter analyzed in the time domain, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2010 . . . . . . . . . 5 SLYT389The IBIS model: A conduit into signal-integrity analysis, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2010 . . . . . . . . 11 SLYT390The IBIS model, Part 2: Determining the total quality of an IBIS model. . . . . . . . . . . . . . . . . . . . .1Q, 2011 . . . . . . . . . 5 SLYT400The IBIS model, Part 3: Using IBIS models to investigate signal-integrity issues. . . . . . . . . . . . . .2Q, 2011 . . . . . . . . . 5 SLYT413Clock jitter analyzed in the time domain, Part 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2011 . . . . . . . . . 5 SLYT422How delta-sigma ADCs work, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2011 . . . . . . . . 13 SLYT423How delta-sigma ADCs work, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2011 . . . . . . . . . 5 SLYT438

Power ManagementStability analysis of low-dropout linear regulators with a PMOS pass element. . . . . . . . . . . . . . . .August 1999 . . . . . 10 SLYT194Extended output voltage adjustment (0 V to 3.5 V) using the TI TPS5210 . . . . . . . . . . . . . . . . . .August 1999 . . . . . 13 SLYT195Migrating from the TI TL770x to the TI TLC770x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . 14 SLYT196TI TPS5602 for powering TI’s DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999. . . . 8 SLYT185Synchronous buck regulator design using the TI TPS5211 high-frequency

hysteretic controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999. . . 10 SLYT186Understanding the stable range of equivalent series resistance of an LDO regulator . . . . . . . . . .November 1999. . . 14 SLYT187Power supply solutions for TI DSPs using synchronous buck converters . . . . . . . . . . . . . . . . . . . .February 2000. . . . 12 SLYT177Powering Celeron-type microprocessors using TI’s TPS5210 and TPS5211 controllers . . . . . . . .February 2000. . . . 20 SLYT178Simple design of an ultra-low-ripple DC/DC boost converter with TPS60100 charge pump. . . . .May 2000 . . . . . . . . 11 SLYT170Low-cost, minimum-size solution for powering future-generation Celeron™-type

processors with peak currents up to 26 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . 14 SLYT171Advantages of using PMOS-type low-dropout linear regulators in battery applications . . . . . . . .August 2000 . . . . . 16 SLYT161Optimal output filter design for microprocessor or DSP power supply . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 22 SLYT162Understanding the load-transient response of LDOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 19 SLYT151Comparison of different power supplies for portable DSP solutions

working from a single-cell battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 24 SLYT152Optimal design for an interleaved synchronous buck converter under high-slew-rate,

load-current transient conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 15 SLYT139–48-V/+48-V hot-swap applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 20 SLYT140Power supply solution for DDR bus termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . . 9 SLYT130Runtime power control for DSPs using the TPS62000 buck converter . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . 15 SLYT131Power control design key to realizing InfiniBandSM benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . 10 SLYT124Comparing magnetic and piezoelectric transformer approaches in CCFL applications . . . . . . . . .1Q, 2002 . . . . . . . . 12 SLYT125Why use a wall adapter for ac input power? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . 18 SLYT126SWIFT™ Designer power supply design program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 15 SLYT116Optimizing the switching frequency of ADSL power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 23 SLYT117Powering electronics from the USB port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 28 SLYT118Using the UCC3580-1 controller for highly efficient 3.3-V/100-W isolated supply design . . . . . . .4Q, 2002 . . . . . . . . . 8 SLYT105Power conservation options with dynamic voltage scaling in portable DSP designs . . . . . . . . . . .4Q, 2002 . . . . . . . . 12 SLYT106Understanding piezoelectric transformers in CCFL backlight applications. . . . . . . . . . . . . . . . . . .4Q, 2002 . . . . . . . . 18 SLYT107Load-sharing techniques: Paralleling power modules with overcurrent protection . . . . . . . . . . . .1Q, 2003 . . . . . . . . . 5 SLYT100Using the TPS61042 white-light LED driver as a boost converter . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2003 . . . . . . . . . 7 SLYT101Auto-Track™ voltage sequencing simplifies simultaneous power-up and power-down. . . . . . . . .3Q, 2003 . . . . . . . . . 5 SLYT095Soft-start circuits for LDO linear regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . 10 SLYT096UCC28517 100-W PFC power converter with 12-V, 8-W bias supply, Part 1. . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . 13 SLYT097UCC28517 100-W PFC power converter with 12-V, 8-W bias supply, Part 2. . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . 21 SLYT092LED-driver considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . 14 SLYT084Tips for successful power-up of today’s high-performance FPGAs . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2004 . . . . . . . . 11 SLYT079

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Index of Articles

Title Issue Page Lit. No.

Power Management (Continued)A better bootstrap/bias supply circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . 33 SLYT077Understanding noise in linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . . 5 SLYT201Understanding power supply ripple rejection in linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . . 8 SLYT202Miniature solutions for voltage isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . 13 SLYT211New power modules improve surface-mount manufacturability . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . 18 SLYT212Li-ion switching charger integrates power FETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . 19 SLYT224TLC5940 dot correction compensates for variations in LED brightness . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . 21 SLYT225Powering today’s multi-rail FPGAs and DSPs, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2006 . . . . . . . . . 9 SLYT232TPS79918 RF LDO supports migration to StrataFlash® Embedded Memory (P30) . . . . . . . . . . .1Q, 2006 . . . . . . . . 14 SLYT233Practical considerations when designing a power supply with the TPS6211x . . . . . . . . . . . . . . . .1Q, 2006 . . . . . . . . 17 SLYT234TLC5940 PWM dimming provides superior color quality in LED video displays . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . 10 SLYT238Wide-input dc/dc modules offer maximum design flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . 13 SLYT239Powering today’s multi-rail FPGAs and DSPs, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . 18 SLYT240TPS61059 powers white-light LED as photoflash or movie light . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . . 8 SLYT245TPS65552A powers portable photoflash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . 10 SLYT246Single-chip bq2403x power-path manager charges battery while powering system . . . . . . . . . . . .3Q, 2006 . . . . . . . . 12 SLYT247Complete battery-pack design for one- or two-cell portable applications . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . 14 SLYT248A 3-A, 1.2-VOUT linear regulator with 80% efficiency and PLOST < 1 W . . . . . . . . . . . . . . . . . . . . . .4Q, 2006 . . . . . . . . 10 SLYT254bq25012 single-chip, Li-ion charger and dc/dc converter for Bluetooth® headsets . . . . . . . . . . . .4Q, 2006 . . . . . . . . 13 SLYT255Fully integrated TPS6300x buck-boost converter extends Li-ion battery life. . . . . . . . . . . . . . . . .4Q, 2006 . . . . . . . . 15 SLYT256Selecting the correct IC for power-supply applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2007 . . . . . . . . . 5 SLYT259LDO white-LED driver TPS7510x provides incredibly small solution size . . . . . . . . . . . . . . . . . . .1Q, 2007 . . . . . . . . . 9 SLYT260Power management for processor core voltage requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2007 . . . . . . . . 11 SLYT261Enhanced-safety, linear Li-ion battery charger with thermal regulation and

input overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . . 8 SLYT269Current balancing in four-pair, high-power PoE applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . 11 SLYT270Power-management solutions for telecom systems improve performance, cost, and size. . . . . . .3Q, 2007 . . . . . . . . 10 SLYT278TPS6108x: A boost converter with extreme versatility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2007 . . . . . . . . 14 SLYT279Get low-noise, low-ripple, high-PSRR power with the TPS717xx . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2007 . . . . . . . . 17 SLYT280Simultaneous power-down sequencing with the TPS74x01 family of linear regulators . . . . . . . . .3Q, 2007 . . . . . . . . 20 SLYT281Driving a WLED does not always require 4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2007 . . . . . . . . . 9 SLYT284Host-side gas-gauge-system design considerations for single-cell handheld applications . . . . . . .4Q, 2007 . . . . . . . . 12 SLYT285Using a buck converter in an inverting buck-boost topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2007 . . . . . . . . 16 SLYT286Understanding output voltage limitations of DC/DC buck converters . . . . . . . . . . . . . . . . . . . . . . .2Q, 2008 . . . . . . . . 11 SLYT293Battery-charger front-end IC improves charging-system safety. . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2008 . . . . . . . . 14 SLYT294New current-mode PWM controllers support boost, flyback, SEPIC, and

LED-driver applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2008 . . . . . . . . . 9 SLYT302Getting the most battery life from portable systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2008 . . . . . . . . . 8 SLYT307Compensating and measuring the control loop of a high-power LED driver . . . . . . . . . . . . . . . . .4Q, 2008 . . . . . . . . 14 SLYT308Designing DC/DC converters based on SEPIC topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2008 . . . . . . . . 18 SLYT309Paralleling power modules for high-current applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2009 . . . . . . . . . 5 SLYT320Improving battery safety, charging, and fuel gauging in portable media applications . . . . . . . . . .1Q, 2009 . . . . . . . . . 9 SLYT321Cell balancing buys extra run time and battery life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2009 . . . . . . . . 14 SLYT322Using a portable-power boost converter in an isolated flyback application . . . . . . . . . . . . . . . . . .1Q, 2009 . . . . . . . . 19 SLYT323Taming linear-regulator inrush currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2009 . . . . . . . . . 9 SLYT332Designing a linear Li-Ion battery charger with power-path control . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2009 . . . . . . . . 12 SLYT333Selecting the right charge-management solution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2009 . . . . . . . . 18 SLYT334Reducing radiated EMI in WLED drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2009 . . . . . . . . 17 SLYT340Using power solutions to extend battery life in MSP430™ applications . . . . . . . . . . . . . . . . . . . . .4Q, 2009 . . . . . . . . 10 SLYT356Designing a multichemistry battery charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2009 . . . . . . . . 13 SLYT357Efficiency of synchronous versus nonsynchronous buck converters. . . . . . . . . . . . . . . . . . . . . . . .4Q, 2009 . . . . . . . . 15 SLYT358Fuel-gauging considerations in battery backup storage systems . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2010 . . . . . . . . . 5 SLYT364Li-ion battery-charger solutions for JEITA compliance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2010 . . . . . . . . . 8 SLYT365Power-supply design for high-speed ADCs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2010 . . . . . . . . 12 SLYT366Discrete design of a low-cost isolated 3.3- to 5-V DC/DC converter . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2010 . . . . . . . . 12 SLYT371Designing DC/DC converters based on ZETA topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2010 . . . . . . . . 16 SLYT372Coupled inductors broaden DC/DC converter usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2010 . . . . . . . . 10 SLYT380

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Index of Articles

Title Issue Page Lit. No.

Power Management (Continued)Computing power going “Platinum” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2010 . . . . . . . . 13 SLYT382A low-cost, non-isolated AC/DC buck converter with no transformer. . . . . . . . . . . . . . . . . . . . . . .4Q, 2010 . . . . . . . . 16 SLYT391Save power with a soft Zener clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2010 . . . . . . . . 19 SLYT392An introduction to the Wireless Power Consortium standard and TI’s compliant solutions . . . . .1Q, 2011 . . . . . . . . 10 SLYT401Fine-tuning TI’s Impedance Track™ battery fuel gauge with LiFePO4 cells in

shallow-discharge applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2011 . . . . . . . . 13 SLYT402Implementation of microprocessor-controlled, wide-input-voltage, SMBus smart

battery charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2011 . . . . . . . . 11 SLYT410Benefits of a coupled-inductor SEPIC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2011 . . . . . . . . 14 SLYT411IQ: What it is, what it isn’t, and how to use it . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2011 . . . . . . . . 18 SLYT412Backlighting the tablet PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2011 . . . . . . . . 23 SLYT414Challenges of designing high-frequency, high-input-voltage DC/DC converters. . . . . . . . . . . . . . .2Q, 2011 . . . . . . . . 28 SLYT415A boost-topology battery charger powered from a solar panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2011 . . . . . . . . 17 SLYT424Solar charging solution provides narrow-voltage DC/DC system bus for

multicell-battery applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2011 . . . . . . . . . 8 SLYT439Solar lantern with dimming achieves 92% efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2011 . . . . . . . . 12 SLYT440

Interface (Data Transmission)TIA/EIA-568A Category 5 cables in low-voltage differential signaling (LVDS). . . . . . . . . . . . . . . .August 1999 . . . . . 16 SLYT197Keep an eye on the LVDS input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999. . . 17 SLYT188Skew definition and jitter analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000. . . . 29 SLYT179LVDS receivers solve problems in non-LVDS applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000. . . . 33 SLYT180LVDS: The ribbon cable connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . 19 SLYT172Performance of LVDS with different cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 30 SLYT163A statistical survey of common-mode noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 30 SLYT153The Active Fail-Safe feature of the SN65LVDS32A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 35 SLYT154The SN65LVDS33/34 as an ECL-to-LVTTL converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . 19 SLYT132Power consumption of LVPECL and LVDS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . 23 SLYT127Estimating available application power for Power-over-Ethernet applications . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . 18 SLYT085The RS-485 unit load and maximum number of bus connections . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . 21 SLYT086Failsafe in RS-485 data buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2004 . . . . . . . . 16 SLYT080Maximizing signal integrity with M-LVDS backplanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . 11 SLYT203Device spacing on RS-485 buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . 25 SLYT241Improved CAN network security with TI’s SN65HVD1050 transceiver . . . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . 17 SLYT249Detection of RS-485 signal loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2006 . . . . . . . . 18 SLYT257Enabling high-speed USB OTG functionality on TI DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . 18 SLYT271When good grounds turn bad—isolate!. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2008 . . . . . . . . 11 SLYT298Cascading of input serializers boosts channel density for digital inputs . . . . . . . . . . . . . . . . . . . . .3Q, 2008 . . . . . . . . 16 SLYT301RS-485: Passive failsafe for an idle bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2009 . . . . . . . . 22 SLYT324Message priority inversion on a CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2009 . . . . . . . . 25 SLYT325Designing with digital isolators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2009 . . . . . . . . 21 SLYT335Magnetic-field immunity of digital capacitive isolators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2010 . . . . . . . . 19 SLYT381Interfacing high-voltage applications to low-power controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2010 . . . . . . . . 20 SLYT393Designing an isolated I2C Bus® interface by using digital isolators . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2011 . . . . . . . . 17 SLYT403Isolated RS-485 transceivers support DMX512 stage lighting and special-effects applications . .3Q, 2011 . . . . . . . . 21 SLYT425Industrial data-acquisition interfaces with digital isolators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2011 . . . . . . . . 24 SLYT426Extending the SPI bus for long-distance communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2011 . . . . . . . . 16 SLYT441

Amplifiers: AudioReducing the output filter of a Class-D amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . 19 SLYT198Power supply decoupling and audio signal filtering for the Class-D audio power amplifier . . . . .August 1999 . . . . . 24 SLYT199PCB layout for the TPA005D1x and TPA032D0x Class-D APAs. . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000. . . . 39 SLYT182An audio circuit collection, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 39 SLYT1551.6- to 3.6-volt BTL speaker driver reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 23 SLYT141Notebook computer upgrade path for audio power amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 27 SLYT142An audio circuit collection, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 41 SLYT145An audio circuit collection, Part 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . 34 SLYT134

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Index of Articles

Title Issue Page Lit. No.

Amplifiers: Audio (Continued)Audio power amplifier measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . 40 SLYT135Audio power amplifier measurements, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . 26 SLYT128Precautions for connecting APA outputs to other devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2010 . . . . . . . . 22 SLYT373

Amplifiers: Op AmpsSingle-supply op amp design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999. . . 20 SLYT189Reducing crosstalk of an op amp on a PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999. . . 23 SLYT190Matching operational amplifier bandwidth with applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000. . . . 36 SLYT181Sensor to ADC — analog interface design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . 22 SLYT173Using a decompensated op amp for improved performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . 26 SLYT174Design of op amp sine wave oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 33 SLYT164Fully differential amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 38 SLYT165The PCB is a component of op amp design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 42 SLYT166Reducing PCB design costs: From schematic capture to PCB layout . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . 48 SLYT167Thermistor temperature transducer-to-ADC application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 44 SLYT156Analysis of fully differential amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000. . . 48 SLYT157Fully differential amplifiers applications: Line termination, driving high-speed ADCs,

and differential transmission lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 32 SLYT143Pressure transducer-to-ADC application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 38 SLYT144Frequency response errors in voltage feedback op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 48 SLYT146Designing for low distortion with high-speed op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . 25 SLYT133Fully differential amplifier design in high-speed data acquisition systems . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 35 SLYT119Worst-case design of op amp circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 42 SLYT120Using high-speed op amps for high-performance RF design, Part 1 . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 46 SLYT121Using high-speed op amps for high-performance RF design, Part 2 . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . 21 SLYT112FilterPro™ low-pass design tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . 24 SLYT113Active output impedance for ADSL line drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2002 . . . . . . . . 24 SLYT108RF and IF amplifiers with op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2003 . . . . . . . . . 9 SLYT102Analyzing feedback loops containing secondary amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2003 . . . . . . . . 14 SLYT103Video switcher using high-speed op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . 20 SLYT098Expanding the usability of current-feedback amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . 23 SLYT099Calculating noise figure in op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . 31 SLYT094Op amp stability and input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . 24 SLYT087Integrated logarithmic amplifiers for industrial applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . 28 SLYT088Active filters using current-feedback amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2004 . . . . . . . . 21 SLYT081Auto-zero amplifiers ease the design of high-precision circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . 19 SLYT204So many amplifiers to choose from: Matching amplifiers to applications . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . 24 SLYT213Getting the most out of your instrumentation amplifier design . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . 25 SLYT226High-speed notch filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2006 . . . . . . . . 19 SLYT235Low-cost current-shunt monitor IC revives moving-coil meter design . . . . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . 27 SLYT242Accurately measuring ADC driving-circuit settling time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2007 . . . . . . . . 14 SLYT262New zero-drift amplifier has an IQ of 17 µA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . 22 SLYT272A new filter topology for analog high-pass filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2008 . . . . . . . . 18 SLYT299Input impedance matching with fully differential amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2008 . . . . . . . . 24 SLYT310A dual-polarity, bidirectional current-shunt monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2008 . . . . . . . . 29 SLYT311Output impedance matching with fully differential operational amplifiers . . . . . . . . . . . . . . . . . . .1Q, 2009 . . . . . . . . 29 SLYT326Using fully differential op amps as attenuators, Part 1: Differential bipolar input signals . . . . . . .2Q, 2009 . . . . . . . . 33 SLYT336Using fully differential op amps as attenuators, Part 2: Single-ended bipolar input signals . . . . .3Q, 2009 . . . . . . . . 21 SLYT341Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs . . . . . . . . . . . . . . . . . . . .3Q, 2009 . . . . . . . . 24 SLYT342Using the infinite-gain, MFB filter topology in fully differential active filters . . . . . . . . . . . . . . . . .3Q, 2009 . . . . . . . . 33 SLYT343Using fully differential op amps as attenuators, Part 3: Single-ended unipolar input signals . . . .4Q, 2009 . . . . . . . . 19 SLYT359Interfacing op amps to high-speed DACs, Part 2: Current-sourcing DACs . . . . . . . . . . . . . . . . . . .4Q, 2009 . . . . . . . . 23 SLYT360Operational amplifier gain stability, Part 1: General system analysis. . . . . . . . . . . . . . . . . . . . . . . .1Q, 2010 . . . . . . . . 20 SLYT367Signal conditioning for piezoelectric sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2010 . . . . . . . . 24 SLYT369Interfacing op amps to high-speed DACs, Part 3: Current-sourcing DACs simplified . . . . . . . . . .1Q, 2010 . . . . . . . . 32 SLYT368Operational amplifier gain stability, Part 2: DC gain-error analysis . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2010 . . . . . . . . 24 SLYT374Operational amplifier gain stability, Part 3: AC gain-error analysis . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2010 . . . . . . . . 23 SLYT383

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Index of Articles

Title Issue Page Lit. No.

Amplifiers: Op Amps (Continued)Using single-supply fully differential amplifiers with negative input voltages to drive ADCs . . . .4Q, 2010 . . . . . . . . 26 SLYT394Converting single-ended video to differential video in single-supply systems . . . . . . . . . . . . . . . .3Q, 2011 . . . . . . . . 29 SLYT427

Low-Power RFUsing the CC2430 and TIMAC for low-power wireless sensor applications: A power-

consumption study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2008 . . . . . . . . 17 SLYT295Selecting antennas for low-power wireless applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2008 . . . . . . . . 20 SLYT296

General InterestSynthesis and characterization of nickel manganite from different carboxylate

precursors for thermistor sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001. . . . 52 SLYT147Analog design tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . 50 SLYT122Spreadsheet modeling tool helps analyze power- and ground-plane voltage drops

to keep core voltages within tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . 29 SLYT273Analog linearization of resistance temperature detectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2011 . . . . . . . . 21 SLYT442

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SLYT437© 2011 Texas Instruments Incorporated

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