analog %26 digital communicationa lab

7/31/2019 Analog %26 Digital Communicationa Lab

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011

This is a one type educational service to the third year ECE students for having their Analog and Digital

Communication lab experiments using only discrete components. We congratulate our esteemed

Professor S. Saravanan, Erode for providing all experiments details given here from his industrial experience.

This will facilitate the students knowledge in building the circuits by their own without firing the hand.

Expt No. 1

AMPLITUDE MODULATION AND DEMODULATION

Date:

AIM: To construct an amplitude modulation circuit and measure the Modulation Index. To recover the

modulating signal from the AM wave by using a Diode Detector circuit.

TEST RIGS:

S.NO. NAME RANGE QNTY

1 DSO 0 30 MHZ 1

2 FUNCTION GENERATORS 0 2 MHZ 2

3 VARIABLE POWER SUPPLY 0 30 V ( DUAL ) 1

COMPONENTS:

S.NO. NAME PART NUMBER QNTY

1 RESISTORS 33K, 39K, 47K, 68E, 68E, 100K, 1K 1 each

2 CAPACITORS 10uF, 0.01uF, 0.1uF 1, 2, 1 each

3 DIODE OA79 1

4 BREAD BOARD 1

5 POTENTIOMETERS 100K 1

6 IC CA3080 1


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THEORY:

Amplitude modulation (AM) is a method of impressing a message signal onto an alternating-current (AC)

carrier waveform. The highest frequency of the modulating data is normally less than 10 percent of thecarrier frequency. The instantaneous amplitude (overall signal power) varies depending on the

instantaneous amplitude of the modulating signal.

In AM, the carrier itself does not fluctuate in amplitude. Instead, the modulating signal appears in the form

of signal components at frequencies slightly higher and lower than that of the carrier. These components

are called sidebands. The lower sideband (LSB) appears at frequencies below the carrier frequency; the

upper sideband (USB) appears at frequencies above the carrier frequency. The LSB and USB are

essentially "mirror images" of each other in a graph of signal amplitude versus frequency. The sideband

power accounts for the variations in the overall amplitude of the signal.

An Amplitude Modulated Signal is represented as follows.

Vam(t) = [ Ec + EmSin(2fmt) ] [ Sin(2fct) ]

Where Ec + EmSin(2fmt) is the Amplitude Modulated WaveEm is the peak change in the amplitude of the Envelope ( volts )fm is the frequency of the modulating signal.

PURPOSE:

This experiment demonstrates the principle of Multiplier operation using the CA3080 OperationalTransconductance Amplifier. A simple demodulator demonstrates one method of recovering an amplitudemodulated signal using a diode detector known as envelope detector. The modulation index m is

calculated that indicates by how much the modulated variable varies around its unmodulated level. Itrelates to the variations in the amplitude of the carrier signal. The value of m is within the range of 1.

PINOUT DIAGRAM OF CA3080:


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PINOUT DIAGRAM OF OA79 (germanium diode)

MODULATOR:

-9V

R7

100K Off set Null

R247K

+9V

-

+

U1

CA30803

26

7

4 5

R1

33K

R368E

-9V

R468E

CarrierSignal

AM Out

+9V

R539K

Modulating Signal

R6100K

0

DEMODULATOR:

R8

1K

0

D1

OA79

Message OutC3

0.1uF

AM In

C1

0.01uF

C2

0.01uF

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MODULATION GRAPH:

PROCEDURE:

1. Connections are made for the AM Modulator and Demodulator as shown in the circuit diagrams.2. Frequency of the input carrier is fixed at constant amplitude of 1 volt and 150 KHz.3. A message signal of 1 KHz at 0.5 volt amplitude is applied at the modulating signal input.

4. The Vmax and Vmin are measured and tabulated to calculate the Modulation Index m5. The amplitude of the message signal is varied in steps till the Vmin reaches the minimum.6. The same set of amplitude values are used for two or three modulating frequencies and values

tabulated.

7. The maximum value of mis observed to be1.8. The demodulated message signal is observed from the output of the Envelope Detector and

tabulated in the demodulator side of the tabulation..9. A selection of RC network is important for a faithful recovery of the message signal.10. All optimum parameters like Vcc are noted down.

TABULAR COLUMN:

Vc = 150 KHz @ 1 Volt Amplitude

S.No.

Modulator Side Demod Side

Fm Vm Vmax Vmin m Fo Vo

1 1 KHz

0.5

1

1.5

2


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2 2 KHz

0.5

1

1.5

2

3 3 KHz

0.5

1

1.5

2

REFERENCES:

1. CA3080/CA3080A DATASHEET.2. OA79 DATASHEET.3. Understanding and Using OTA Op-Amp Ics ( Nuts and Volts Magazine )4. Electronic Communications Systems V Edition by Wayne Tomasi Pearson Education.5. Communication Lab Manual ECE Department SSIT, Tumkur6. Communication Lab Manual ECE Department Easwari Engg College, Chennai.

RESULT: Thus the modulation Index of an Amplitude Modulation Circuit was calculated and themessage signal was recovered using an Envelope Detector.

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Expt No. 2

FREQUENCY MODULATION AND FSK GENERATION

Date:

AIM: To construct a Frequency Modulation circuit using a sinusoidal input waveform and to measure the

Modulation Index. To use the same circuit for FSK generation with a square waveform.

TEST RIGS:


1 DSO 0 30 MHZ 1

2 FUNCTION GENERATOR 0 2 MHZ 1


COMPONENTS:


1 RESISTORS 1.5K, 5.6K, 10K 1 EACH

2 CAPACITORS 1 nF 2

3 INTEGRATED CIRCUIT NE/SE566D 1

4 BREAD BOARD 1

THEORY:

FREQUENCY MODULATION:

Frequency modulation (FM) is a method of impressing data onto an alternating-current (AC) waveby varying the instantaneous frequency of the wave. This scheme can be used with analog or digital data.

In analog FM, the frequency of the AC signal wave, also called the carrier, varies in a continuous

manner. Thus, there are infinitely many possible carrier frequencies. In narrowband FM, commonly usedin two-way wireless communications, the instantaneous carrier frequency varies by up to 5 kilohertz (kHz,where 1 kHz = 1000 hertz or alternating cycles per second) above and below the frequency of the carrierwith no modulation.

In wideband FM, used in wireless broadcasting, the instantaneous frequency varies by up toseveral megahertz (MHz, where 1 MHz = 1,000,000 Hz). When the instantaneous input wave has positivepolarity, the carrier frequency shifts in one direction and when the instantaneous input wave has negativepolarity, the carrier frequency shifts in the opposite direction. At every instant in time, the extent of carrier-frequency shift (the deviation) is directly proportional to the extent to which the signal amplitude is positiveor negative.


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In digital FM, the carrier frequency shifts abruptly, rather than varying continuously. The numberof possible carrier frequency states is usually a power of 2. If there are only two possible frequencystates, the mode is called frequency-shift keying (FSK). In more complex modes, there can be four, eight,

or more different frequency states. Each specific carrier frequency represents a specific digital input datastate. Frequency Modulation is widely used in communication systems. The most well known use is inFM broadcasting. Digital FM is used in modems and multi tone selective signaling systems.

The general definition of frequency modulated signal SFM(t) is given by the formula:

)d)(mK2tf2cos(A))t(tf2cos(A)t(S

t

fCCCCFM

+=+=

where,

)(m is the modulating signal.

CA is the amplitude of the carrier.

Cf is the carrier frequency.

fK is the frequency deviation constant measured in Hz/V.

FREQUENCY SHIFT KEYING:

Frequency-shift keying (FSK) is a frequency modulation scheme in which digital information istransmitted through discrete frequency changes of a carrier wave. The simplest FSK is binary FSK(BFSK). BFSK literally implies using a pair of discrete frequencies to transmit binary (0s and 1s)

information. With this scheme, the "1" is called the mark frequency and the "0" is called the spacefrequency. The time domain of an FSK modulated carrier is illustrated in the waveforms.

PURPOSE:

This experiment demonstrates some of the principles of VCO operation using the NE566

integrated circuit by implementing a Frequency Modulation Circuit. The modulation index h is calculated

that indicates by how much the modulated variable varies around its unmodulated level. It relates to the

variations in the frequency of the carrier signal.

h = f/Fm where f is the frequency deviation and Fm is the modulating frequency.

An FSK signal is generated by replacing the sine wave input with a square wave. The MARK andSPACE frequencies are observed for 2 KHz signal.

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PINOUT DIAGRAM OF NE566:

Figure 1

CIRCUIT DIAGRAMS:

FM & FSK MODULATOR:

VCC

C2

0.01UF

C1?

12 V+

R1?

0

R3

10K

U1A

NE5563

5

1

6

7

4

8

SQ OUT

OUT

GND

R1

C1

TRI OUT

V+

R21.5K

MODULATING SIGNAL INPUTC3

0.001UF

SQUARE WAVE OUTPUT

TRIANGLE WAVE OUTPUT

Figure 2

The NE/SE566 Function Generator is a general purpose voltage-controlled oscillator designed for

highly linear frequency modulation. The circuit provides simultaneous square wave and triangle wave

outputs at frequencies up to 1MHz. A typical connection diagram is shown in Figure 2. The controlterminal (Pin 5) must be biased externally with a voltage (Vc) in the range

V+ Vc V+

where VCC is the total supply voltage. In Figure 2, the control voltage is set by the voltage divider

formed with R2 and R3. The modulating signal is then AC coupled with the capacitor C2. The modulating

signal can be direct coupled as well, if the appropriate DC bias voltage is applied to the control terminal.

The frequency is given approximately by

fo =


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and R1 should be in the range 2k< R1


10/38


TABULATION FOR FM:

S.No.

Modulating

Signal Fm

Frequency

Modulation fFM

Frequency

deviation =Fc ~fFM

Modulation

Index h=/Fm

BW =

2 ( Fm + )

1 1 KHz

2 2 KHz

3 3 KHz

4 4 KHz

5 5 KHz

TABULATION FOR FSK:

Signal Amplitude(V) Time period(sec)

Modulating signal

Carrier signal

Mark Frequency

Space Frequency

Result: Thus an FM and FSK modulation signal were generated and the properties were tabulated.

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Expt No. 3

BALANCED MODULATOR

Date:

AIM: To construct a Balanced Modulator and note down its working principle.

TEST RIGS:


1 DSO 0 25 MHZ 1



COMPONENTS:


1 RESISTORS 100K 2

2 CAPACITOR 220pF 1

3 DIODES IN4148 4

4 BREAD BOARD 1

5 INDUCTOR Decade InductanceBox

1

THEORY:

A Balanced Modulator generates a DSB signal. The inputs to a balanced modulator are the carrier and a

modulating signal. The output is the upper and lower sidebands. A balanced modulator suppresses the

carrier, leaving only the sum and the difference frequencies at the output. The output of a balanced

modulator can be further processed by filters or phase-shifting circuitry to eliminate one of the sidebands,

thereby resulting in an SSB signal. One of the most popular and widely used balanced modulator is the

diode ring or lattice modulator illustrated in figure 1. Figure 1.

Modulating

Signal

V1

Carrier Signal

DSB Output

T2

TRANSFORMER CT

15

6

48

D4

D1N4148

D1

D1N4148

D2

D1N4148

T1

TRANSFORMER CT

1 5

6

4 8

D3

D1N4148


12/38


It consists of an input transformer T1, an output transformer T2, and four diodes connected in a

bridge configuration. The carrier signal is applied to the center taps of the input and output transformers.

The modulating signal is applied to the input transformer T1. The output appears across the secondary of

the output transformer T2.

The carrier sine wave, which is usually considerably higher frequency and amplitude than the

modulating signal is used as a source of forward and reverse bias for the diodes. The carrier turns the

diodes off and on at a high rate of speed. The diodes act like switches which connect the modulating

signal at the secondary of T1 to the primary of T2.

The greatest carrier suppression will occur when the diode characteristics are perfectly matched.

A carrier suppression of 40 dB is achievable with well-balanced components.

CIRCUIT DIAGRAM:

Figure 2.

PROCEDURE:

1. Connections aremade as shown infigure 2.

2. A carrier wave of200KHz at 1 voltpp amplitude and amessage signal of

3. 1 KHz at less than 1 Volt pp are applied as shown in the circuit diagram.

4. The output waveform is noted to have a suppressed carrier.5. The output frequency of the carrier is noted and tabulated as shown.6. The carrier frequency is varied and the inductance value is tuned to have maximum amplitude.7. All the parameters are tabulated for fc = 150 KHz and 100 KHz.

TABULATION:

S.No.Carrier

Frequency fc

Modulating

Frequency fm

Amplitude of

fm

Output Carrier

Frequency FoVo

1 200 KHz 1 KHz 0.5 V

2 150 KHz 1 KHz 0.5 V

3 100 Khz 1 KHz 0.5 V

RESULT: Thus a simple balanced modulator is built to understand its working principle.

REFERENCE:

1. COMMUNICATION LABORATORY MANUAL, UNIVERSITY OF FLORIDA2. DIGITAL AND ANALOG COMMUNICATION SYSTEMS, Leon W. Couch

V1

Carrier Signal

D3

D1N4148

D2

D1N4148

D4

D1N4148

DSB Output

R2

100k

L12.2mH

C1

220pF

D1

D1N4148V1

Modulating Signal

R1

100k


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Expt No. 4

PRE-EMPHASIS & DE-EMPHASIS

Date:

AIM: To design a Pre-Emphasis and De-Emphasis circuit for a desired roll-over frequency and compare

the practical output with theoritical calculations.

TEST RIGS:


1 DSO 0 30 MHZ 1



COMPONENTS:


1 RESISTORS 100E, 820E, 2.2K, 15K 1 each

2 CAPACITORS 100nF 1

3 INTEGRATED CIRCUIT LM741 1

4 BREAD BOARD 1

THEORY:

When an FM system is compared to an AM system with a modulation index of 1 operating under

similar noise conditions, then it can be shown that the FM signal has a signal to noise ratio which is 3 m2

better than the AM system. mhere is the modulation index or deviation ratio for the FM signal.

In an FM system the

higher frequencies contributemore to the noise than the lower

frequencies. Because of this all

FM systems adopt a system of

pre-emphasis where the higher

frequencies are increased in

amplitude before being used to

modulate the carrier.

The transfer function

sketched above is used for a pre-


14/38


emphasis circuit for FM signals in the FM band. The Time T = 75s. For FM systems in the FM band m~

5 resulting in a S/N improvement of 19dB. With pre-emphasis this can be increased by 4dB for a total of

23dB.

At the receiver the higher frequencies must be de-

emphasized in order to get back the original baseband signal.

The transfer function of the de-emphasis circuit is shown

above.

PURPOSE:

This experiment demonstrates the use of Pre-Emphasis and De-Emphasis circuits in FMTransmitters and Receivers respectively as discussed in the Theory part of this experiment. A separatecircuit and its design are used to build the circuits and to observe their performances.

The Frequencies F1 and F2 are selected according to the desired levels of frequency response atthe source and the destination. Usually the values of 100 Hz and 20 KHz are selected as the Audiospectrum and the boost and cut frequencies are used in the design.

PINOUT DIAGRAM OF LM741:

CIRCUIT DIAGRAMS: PRE-EMPHASIS:

Figure 1 DESIGN:

Given: F1 = 2.1 KHz and F2 = 15 KHz

F1 = 1/(2rC) and F2 = 1/(2RC)

Choose C = 100nF, then r = 820E and R = 100E

Also r/R = Rf/R1, then R1 = 2.2K and Rf = 15K

r

Rf

0

Vi1Vac

0Vdc

Vo

0

-Vcc

R1

C

U1

LM7413

2

7

4

6

1

5

+

- V+

V-

OUT

OS1

$PIN6

+Vcc

0

R


15/38


TABULAR COLUMN:

Input Vi = 500 mV

S.No. Frequency

Output

Vo Gain = 20 Log V0/Vi

1 100

2 250

3 500

4 1k

5 2.5k

DE-EMPHASIS:

Figure 2 DESIGN:

Fc = 1/(2RdCd)

Choose Cd = 100nF and Fc = F1 = 2.1 KHz

Then Rd = 820E

Also r/R = Rf/R1, then R1 = 2.2K and Rf =

15K

TABULAR COLUMN:

Input Vi = 500 mV

S.No. Frequency Output Vo Gain = 20 Log V0/Vi

1 100

2 250

3 500

4 1k

5 2.5k

0

R1

C

U1

LM741

3

2

7

4

6

1

5

+

- V+

V-

OUT

OS1

$PIN6

Vi

1Vac0Vdc

0

Rd

+Vcc

Rf

-Vcc0

Vo

0


16/38


PROCEDURE:

1. The values of the Resistors and the Capacitors are calculated using the design formulas for lower

cut-off frequency F1 and Upper cut-off frequency F2 for Pre-Emphasis circuit.2. Similarly the cut-off frequency F1 for De-Emphasis circuit is used to arrive at the values of thepassive components.

3. Connections are made as shown in the figures of Pre-Emphasis and De-Emphasis circuits.4. A minimum of 500 mV is applied as Vi to the inputs.5. The frequency is varied in steps throughout the audio range and the corresponding readings are

tabulated.6. The gain is calculated as shown in the Tabular Columns.7. A graph of Frequency versus Output Voltage is drawn on a Semi-Log Graph Sheet.

GRAPHS:

The Graphs for both the circuits will resemble as shown in the theory part.

REFERENCES:

1. LM741 DATASHEET2. Electronic Communications Systems V Edition by Wayne Tomasi Pearson Education.3. Communication Lab Manual ECE Department SSIT, Tumkur4. Communication Lab Manual ECE Department Easwari Engg College, Chennai.

RESULT: Thus a circuit to improve the frequency response of FM receivers was studied using Pre-

Emphasis and De-Emphasis.

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17/38


Expt No. 5

PHASE LOCKED LOOP AND APPLICATIONS

Date:

AIM: To construct a Phase Locked Loop and to observe the locking frequency range.

TEST RIGS:


1 DSO 0 30 MHZ 1



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18/38


Expt No. 6

PWM GENERATION AND DETECTION

Date:

AIM: To generate a Pulse Width Modulation signal for a sinusoidal message signal and to compare the

detected message signal with the input signal.

TEST RIGS:


1 DSO 20 MSPS 1



COMPONENTS:


1 RESISTORS 1.5K, 10K,1K 2,1,1

2 CAPACITORS 100nF, 10nF, 1.5uF 1,1,2

3 BREAD BOARD 1

4 IC LM741 1

5 POTENTIOMETER 100K 1

THEORY:

Pulse-width modulation (PWM) is a digital modulation technique, which converts an analog signal

into a digital signal for transmission. The modulator converts an audio signal (the amplitude-varying

signal) into a sequence of pulses having a constant frequency and amplitude, but the width of each

pulse is proportional to the Amplitude of the audio signal.

In this experiment, a square-wave generator or a monostable multivibrator can be used to generate the

PWM signal, whose output pulse width is determined by the values of R4, C3, and Vin(+). The LM741

operational amplifier acts as a voltage comparator.

The reference voltage at Vin(+) input (pin 3) is determined by the resistor values of R3 and R5. The

combination of R4 and C3 provides the path for charging and discharging. When no audio signal is

applied, the dc reference voltage at Vin(+) input can be changed by adjusting the R5 value.

If dc level of R5 is fixed and an audio signal is applied to the audio input, the audio signal is added to the

fixed dc level and the reference voltage will be changed with the change of audio amplitude. The resulting

PWM signal presents at the output of the comparator.


19/38


PIN DIAGRAM OF LM741:

CIRCUIT DIAGRAMS:

PULSE WIDTH MODULATION CIRCUIT:

R3

1k

+12V

R4

10k

-12V

C3

10nF

R5100K

C4

100nF

1KHz Sine Wave

PWM Output

0

U1

LM741

3

2

7

4

6

1

5+

-

V+

V-

OUT

OS1

OS2

Figure 1

DEMODULATION CIRCUIT:

PWM InputC1

1uFModulatingSignal

C2

1uF

R1

1.5k

R2

1.5k

0

Figure 2

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MODULATION GRAPH:

PROCEDURE:

1. The Circuit of Figure 1 and 2 are connected and cascaded to form a PWM Modulator and

Demodulator.

2. A 1 KHz Sine Wave with an amplitude of 1 Volt is applied to the input. The non-inverting input is

adjusted to have a zero DC bias by varying the 100K potentiometer R5 to have a 50% duty cycle.

3. The output PWM is noted for its ON time and OFF time and tabulated.

4. If the amplitude of the input signal generates a fairly good PWM, then the amplitude is fixed and

the values are tabulated for different frequency inputs.

5. The corresponding demodulated sine wave is verified.

TABULAR COLUMN:

S.No. INPUT FREQUENCY ( KHz ) AMPLITUDE (Vin)PWM

T ON T OFF

1 1 KHz

2 2 KHz

3 3 KHz

4 4 KHz

5 5 KHz

6 6 KHz

RESULT:

Thus a Pulse Width Modulation signal for a sinusoidal message signal was generated and the detected

message signal was compared with the input signal.


21/38


Expt No. 7

AGC CHARACTERISTICS

Date:

AIM: To study the principle of an Automatic Gain Control circuit and its performance characteristics.

TEST RIGS:


1 DSO 100 MSPS 1



COMPONENTS:


1 RESISTORS 470E, 1K, 10K, 33K, 120K, 240K, 100K 1 each, 240K 2

2 CAPACITORS 10uF 3

3 TRANSISTOR J176, 2N3904 1 each

4 BREAD BOARD 1


6 INTEGRATED CIRCUIT LM358 1

THEORY:

Automatic gain control (AGC) is an adaptive system found in many electronic devices. The

average output signal level is fed back to adjust the gain to an appropriate level for a range of input signal

levels. For example, without AGC the sound emitted from an AM radio receiver would vary to an extreme

extent from a weak to a strong signal; the AGC effectively reduces the volume if the signal is strong and

raises it when it is weaker.

AGC algorithms often use a PID controller where the P term is driven by the error between

expected and actual output amplitude. Automatic Gain Control or AGC is a circuit design which maintains

the same level of amplification for sound or radio frequency. If the signal is too low the AGC circuit will

increase (amplify) the level and if it is too high, will lower it to maintain a constant level as possible.

The Automatic Gain Control principle is widely used in AM receivers and sometimes AGC is

called a compressor-expander.


22/38


HOW IT WORKS?:

Using the circuit presented here, we can construct a very inexpensive AGC amplifier with the

following features: a dynamic range greater than 50 dB; negligible distortion to the output waveform; fast

attack and slow decay; an adjustable output level from 0 to 1.2 V p-p; operation from a single 5-V supply;

less than 1-mA current drain; and low cost.

Referring to the circuit diagram, J1 (a Pchannel JFET), coupled with R2 and the equivalent

resistance of R3 and R4, form a voltage divider to the input signal source. With input levels below 40 mV

p-p, the input is evenly divided between R2 (120k) and R3 R4 (120k). The output amplitude of U1A isnt

large enough to turn on J1, which acts as a positive peak detector. The gate of the JFET is pulled to +5 V,

pinching its channel off and creating a very high resistance from drain to source. This essentially removes

it from the circuit.

At input levels above 40 mV p-p, Q1 is turned on at the positive peaks of the output of U1A,

lowering the JFETs gate to source voltage. The channel resistance decreases and attenuates the input

signal to maintain the output of U1A at approximately 1.2 V p-p.

The circuit, as shown, was tested with a sine-wave input ranging from 300 Hz to 30 kHz at 40 mV

to 20 V p-p, a 54-dB range. It maintained the output level at 1.2 V p-p, 0.5 dB, with no visible distortion

when comparing it with the input waveform. With a 40 mV to 20 V p-p input signals, the amplitude of the

signal across the JFET (VDS) measured less than 20 mV p-p.

Other JFETs with VGS(OFF) of 5V or under, such as the 2N5019 or 2N5116, should work equally

well in this circuit, although they havent been tried. To use JFETs with higher V GS(OFF), such as the2N3993 (it was tried and worked equally well), increase the supply voltage to 12 V.

PURPOSE:

The use of AGC circuits in radio receivers have now being integrated into the monolithic receiver

ICs. Hence this simple to implement design technique is studied which can be used in any other circuit

where constant amplitude output is necessary.

PIN DIAGRAM OF LM358:


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PIN DIAGRAM OF J176:

PIN DIAGRAM OF 2N3904:

CIRCUIT DIAGRAM:

R2

120k

C2

10uF

0

0-1.2v

Q12N3904

R6

33k

Audio Input

R11k

R4240k

Audio Output

5v

P110k

R710k

0

C410uF

0

C1

10uF

R3240k

C310uF

5v

U1ALM358

3

2

8

4

1

+

-

V+

V-

OUT

0

D 0

0

0-20v @ 1KHz

S

5v

R5

470

G

R8

100k

J1J176

PROCEDURE:

1. Connections are made for the AGC circuit as shown in the circuit diagram.

2. The frequency of audio input signal is fixed at constant frequency of 1 KHz.

3. The Amplitude of the input is made to vary in steps from 1 Volt.

4. The output is noted to be constant at 1.2 Volts irrespective of the input amplitude increment in steps

5. The input versus the output amplitude is tabulated as given below.

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TABULATION:

Input Frequency = 1 KHz

S.No.

Input

Amplitude

Vi

Output

Amplitude

Vo

1 1Less than

1.2V

2 2 1.2

3 3 1.2

4 4 1.2

5 5 1.2

6 6 1.2

7 7 1.2

8 8 1.2

9 9 1.2

10 10 1.2

REFERENCES:

1. DATASHEETS OF LM358, J176, 2N3904.2. Electronic Communications Systems V Edition by Wayne Tomasi Pearson Education.3. ECE1352 Analog Integrated Circuits I, University of Toronto.4. http://electronicdesign.com/article/analog-and-mixed-signal/effective-agc-amplifier-can-be-built-at-

a-nominal-.aspx

RESULT: Thus an automatic gain control circuit was rigged up and its performance characteristics was

studied.


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Expt No. 8

FM DETECTOR

Date:

AIM: To demodulate an FM signal using a PLL FM Demodulator.

TEST RIGS:


1 DSO 0 25 MHZ 1

2 DUAL DIGITAL SYNTHESIZER FUNCTION GENERATOR 0 2 MHZ 1


COMPONENTS:


1 RESISTORS 680E, 2.2K 1 each

2 CAPACITORS 1uF, 1nF, 10nF, 750pF 1 each

3 INTEGRATED CIRCUITS NE565 1 each

4 BREAD BOARD 1


THEORY:

There are a number of circuits that can be used to demodulate FM. Each type has its own

advantages and disadvantages, some being used when receivers used discrete components and others

now that ICs are widely used.

Below is a list of some of the main types of FM demodulator or FM detector. In view of the

widespread use of FM, even with the competition from digital modes that are widely used today, FMdemodulators are needed in many new designs of electronics equipment.

Slope FM detector

Foster-Seeley FM detector

Ratio detector

PLL, Phase locked loop FM demodulator

Quadrature FM demodulator

Coincidence FM demodulator

Each of these different types of FM detector or demodulator has its own advantages and

disadvantages.


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Phase locked loop, PLL FM demodulator or detector is a form of FM demodulator that has gainedwidespread acceptance in recent years. PLL FM detectors can easily be made from the variety of phaselocked loop integrated circuits that are available, and as a result, PLL FM demodulators are found in

many types of radio equipment ranging from broadcast receivers to high performance communicationsequipments.

The way in which a PLL FM demodulator operates is quite straightforward. The loop consists of aphase detector into which the incoming signal is passed, along with the output from the voltage controlledoscillator (VCO) contained within the phase locked loop. The output from the phase detector is passedinto a loop filter and then used as the control voltage for the VCO.

Phase locked loop (PLL) FM demodulator

With no modulation applied and the carrier in the centre position of the pass-band the voltage onthe tune line to the VCO is set to the mid position. However if the carrier deviates in frequency, the loopwill try to keep the loop in lock. For this to happen, the VCO frequency must follow the incoming signal,and in turn for this to occur the tune line voltage must vary. Monitoring the tune line shows that thevariation in voltage corresponds to the modulation applied to the signal. By amplifying the variations involtage on the tune line it is possible to generate the demodulated signal.

PLL FM demodulator performance

The PLL FM demodulator is normally considered a relatively high performance form of FM demodulator ordetector. Accordingly they are used in many FM receiver applications.

The PLL FM demodulator has a number of key advantages:

Linearity: The linearity of the PLL FM demodulator is governed by the voltage to frequencycharacteristic of the VCO within the PLL. As the frequency deviation of the incoming signalnormally only swings over a small portion of the PLL bandwidth, and the characteristic of the VCOcan be made relatively linear, the distortion levels from phase locked loop demodulators arenormally very low. Distortion levels are typically a tenth of a percent.

Manufacturing costs: The PLL FM demodulator lends itself to integrated circuit technology.Only a few external components are required, and in some instances it may not be necessary touse an inductor as part of the resonant circuit for the VCO. These facts make the PLL FMdemodulator particularly attractive for modern applications.

PLL FM demodulator design considerations

When designing a PLL system for use as an FM demodulator, one of the key considerations is the loopfilter. This must be chosen to be sufficiently wide that it is able to follow the anticipated variations of thefrequency modulated signal. Accordingly the loop response time should be short when compared to theanticipated shortest time scale of the variations of the signal being demodulated.


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A further design consideration is the linearity of the VCO. This should be designed for the voltage tofrequency curve to be as linear as possible over the signal range that will be encountered, i.e. the centrefrequency plus and minus the maximum deviation anticipated.

In general the PLL VCO linearity is not a major problem for average systems, but some attention may berequired to ensure the linearity is sufficiently good for hi-fi systems.

DEMODULATOR using NE/SE565 :

Pin Description of NE565:

Figure 1.

NE565 as FM Detector:

The 565 Phase-Locked Loop is a general purpose circuit

designed for highly linear FM demodulation. During Lock,the average DC level of the phase comparator output signal

is directly proportional to the frequency of the input signal.

As the input frequency shifts, it is this output which causes

the VCO to shift its frequency to match that of the input.

Consequently, the linearity of the phase comparator output with frequency is determined by the voltage-

to-frequency transfer function of the VCO. Because of its unique and highly linear VCO, the 565 PLL can

lock to and track an input signal over a very wide bandwidth with high linearity. A typical connection is

shown in figure 4. The VCO free-running frequency is given approximately by

and should be adjusted to be at the center of the input signal frequency

range. C1 can be any value from 220pF to 750pF, but R1 should be within the range of 2000 to 20000

ohms with an optimum value of the order of 4000 ohms. A small capacitance should be connected to Pin

7 and 8 to eliminate possible oscillation in the control current source.

MODEL GRAPH:

Modulating Signal

Carrier Signal

FM Signal

Demodulated Signal Figure 2.


28/38


CIRCUIT DIAGRAM:

C1

1uF

U1

LM565

2

3

5

1

10

46

8

9

7

IN

IN2

VIN

-VCC

+VCC

VOUTREF

TRES

TCAP

VCON

-Vcc

R3

10K

C2

1n

R1

2.2k

+Vcc

R2680E

C310n

Message Out

C4

750pF

FM Input

0

Figure 3.

PROCEDURE:

1. Connections are made as shown in figure 3 using the PLL IC NE565.2. With the absence of the input FM signal, the output at pin 4-5 should be a square wave.3. Adjust the square wave to have an output frequency of 100 KHz by adjusting the 10K POT.4. An FM signal is generated with the following settings Fo=100KHz, Fm=1KHz, Fd=10KHz or

more and less than 30 KHz, Wave=Sine and Amplitude=500mV using a Dual DigitalSynthesizer Function Generator. This is the input signal to the demodulator.

5. The output is a demodulated waveform of 1KHz.6. Decreasing or increasing the frequency deviation results in a distorted output.7. The frequency of FM carrier signal is varied and tabulated.

TABULATION:

S.No. Fo KHz Fm KHz Fd KHz VFM Vo in KHz

1 75 1 20 100 mV

2 100 1 20 101 mV

3 125 1 20 102 mV

RESULT: Thus an FM detector circuit was rigged up to extract a message signal from an FM signal. An

undistorted message signal was captured at an optimum frequency deviation setting of 20 KHz.

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Expt No. 9

PAM AND VERIFICATION OF SAMPLING THEOREM

Date:

AIM: To rig up a circuit to generate a Pulse Amplitude Modulation Signal and to verify the sampling

theorm for appropriate message signal to avoid Aliasing.

TEST RIGS:


1 DSO 100 MSPS 1


COMPONENTS:


1 RESISTORS 3.3K, 4.7K, 22K 1 each

2 CAPACITORS 100nF 1

3 TRANSISTOR SL100 1

4 BREAD BOARD 1

THEORY:

Pulse-amplitude modulation, acronym PAM, is a form of signal modulation where the messageinformation is encoded in the amplitude of a series of signal pulses.

Example: A two bit modulator (PAM-4) will take two bits at a time and will map the signal amplitude to oneof four possible levels, for example 3 volts, 1 volt, 1 volt, and 3 volts.

Demodulation is performed by detecting the amplitude level of the carrier at every symbol period.

Pulse-amplitude modulation is widely used in baseband transmission of digital data. Some versions of thewidely popular Ethernet communication standard are a good example of PAM usage. In particular, theFast Ethernet 100BASE-T2 medium (now defunct), running at 100 Mbit/s, utilizes 5 level PAM modulation

(PAM-5) running at 25 mega pulses/sec over two wire pairs.

Pulse Amplitude Modulation has also been developed for the control of Light Emitting Diodes especiallyfor lighting applications. LED drivers based on the PAM technique offer improved energy efficiency oversystems based upon other common driver modulation techniques such as Pulse Width Modulation as theforward current passing through an LED is relative to the intensity of the light output and the LEDefficiency increases as the forward current is reduced.


30/38


Figure: 1 Pulse Amplitude Modulation

PURPOSE:

Pulse Amplitude Modulation is the most simplest of all Digital Modulation Techniques currently

available. A simple circuit around a single driver transistor is implemented and the aliasing effect is noted.

CIRCUIT DIAGRAM:

PAM

V2

R2

22K

R3

3.3KV1

FREQ = 100HzVAMPL = 3VVOFF = 3 V DC

5KHz @ 5V

C1

100nF

Message

R1

4.7K

Modulating Signal

CarrierPulse

Q1

SL100

0 Figure: 2 Circuit Diagram

FILTER DESIGN:

1. Let the Cut off frequency of the filter fo >> fm2. Choose Fo = 500 Hz = 1/( 2R3C1)3. Choose C1 = 100nF, therefore R3 = 3.3K4. Rc = 4.7K, Rb = 22K

PROCEDURE:

1. The circuit of figure 2 is rigged up with modulating frequency connected to the collector of SL100with amplitude of 3 volts and at 100 Hz sine wave.

2. An offset of 1 to 3 Volts DC bias is adjusted in the function generator which supplies themodulating signal of 100 Hz.3. A Carrier signal of 1 to 5 KHz with minimum amplitude of 1 V is applied as shown in the circuit.4. The output PAM is available at the collector of Q1.5. Adjust the amplitude of both the carrier and the modulating signal to get a pure PAM signal.6. The low-pass filter comprising of R3 and C1 demodulates the PAM signal.7. All the signals are tabulated.8. To verify the Sampling Theorem, the frequency of the carrier and the modulating signals are

altered asa. Fc < 2Fmb. Fc = 2Fmc. Fc > 2Fm

And the output PAM signals is verified with sampling theorem as shown in figure 3.


31/38


TABULATION:

S.No.Vc

(pp)

Volts

Fc in

Hz

Vm(pp)

Volts

Reconstructed

Signal

Vo

Volts

Fo in

Hz

1

2

3

4

5

6

PINOUT DIAGRAM OF SL100:

VERIFICATION OF SAMPLING THEOREM:

Figure 3. Verification of Sampling Theorem

REFERENCES:

1. Datasheet of SL1002. Electronic Communications Systems V Edition by Wayne Tomasi Pearson Education.3. Communications Lab Manual, ECE Department, S.S.I.T., Tumkur 5721054. Communications Lab Manual, ECE Department, Easwari Engg College, Chennai 89.

RESULT: Thus a PAM circuit was built and sampling theorem was verified under three conditions of Fm

& Fc.


32/38


Expt No. 10

PULSE CODE MODULATION ENCODER AND DECODER

Date

AIM: To rig up a Pulse Code Modulation Circuit and to observe the message pulses at the output of the

Detector. This is to be carried out with the help of trainer kit.

TEST RIGS:


1 DSO 0 30 MHZ 1



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34/38


The input signal is compared to the integrated output pulses and the delta (difference) signal is

applied to the quantizer. The quantizer generates a positive pulse when the difference signal is negative,

and a negative pulse when the difference signal is positive.

This difference signal moves the integrator step by step closer to the present value input, tracking

the derivative of the input signal.

For example if we consider 1.5 kHz sinusoidal input signal with maximum amplitude 1 and delta ischosen to be 0.125 which is equivalent to 4 bit quantization i.e. 16 quantization levels.

To achieve a resolution equivalent to 4 bit quantization with 4 kHz sampling rate an oversamplingratio of 16 is needed i.e. (4^2)/(1^2)*4kHz=64 kHz. In Figure 2, 32 times oversampling is used and theoutput of the integrator tracks nicely the input signal.

Figure 2. 32 times oversampled DM signal

A delta modulation decoder has to integrate

the modulated signal and low pass filter the output of

the integrator as shown in figure 3.

Figure 3. DM Decoder

PURPOSE:

This experiment demonstrates the principle of Delta Modulation from its first principles as

described in the theory section. An active Integrator circuit can be built using an Op-Amp followed by a

Low Pass Filter to decode the message signal usually voice.

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35/38


CIRCUIT DIAGRAM:

C210n

-Vcc = - 5V

U2A

40135

3

12

14

67

4

8910111213

D

CLK

QQ

VDD

SGND

R

S2D2R2

CLK2!Q2Q2

Note: Vcc = 5V

mr(t)

U1

LM741

3

2

7

4

6

1

5

Clock In 10 KHzSquare Wave

0

Message In250 Hz

C1

100n

0 -Vcc

X1

1

1

U3

CD4016

14

7

13

1

5

4

6

8

12

11

2

3

9

10-Vcc

Out

R4

100k

-VccR3

150k

+Vcc

+Vcc

R2100k+Vcc

-Vcc

R1100k

Figure 4. Delta Modulator

DESCRIPTION OF THE COMPONENTS USED:

LM741:

The amplifiers offer many features which make their application

nearly foolproof: overload protection on the input and output, no

latch-up when the common mode range is exceeded, as wellas freedom from oscillations.

CD4013:

The CD4013B dual D-type flip-flop is a monolithic

complementary MOS (CMOS) integrated circuit constructed

with N- and P-channel enhancement mode transistors. Each

flip-flop has independent data, set, reset, and clock inputs and

Q and Q outputs.

These devices can be used for shift register

applications, and by connecting Q output to the data input,

for counter and toggle applications. The logic level present at

the D input is transferred to the Q output during the positive-

going transition of the clock pulse. Setting or resetting is

independent of the clock and is accomplished by a high level

on the set or reset line respectively.


36/38


TRUTH TABLE:

CD4016:

The CD1016 Series Types are Quad Bilateral Switches

intended for the Transmission or Multiplexing of Analog or

Digital Signals. Each of the four independent bilateral switches

has a single control signal input which simultaneously biases

both the P and N device in a given switch ON or OFF.

Applications include

Analog Signal switching / multiplexing / Signal gating /

Squelch Control / Chopper Modulator / Demodulator

Digital Signal Switching / Multiplexing

CMOS logic implementation

A to D & D to A Conversion

Digital Control of Frequency, Impedance, Phase, and Analog-Signal Gain

PURPOSE:

This experiment demonstrates the principle of Delta Modulation and how the various building

blocks are implemented from the block diagram representations. The demodulation part is left to the

student to design and test its functionality.

PRECAUTIONS:

Clock input should be between 0 and +Vdd for CD4013.

The ICs should be populated on to the Bread Board in location where they have the best fit.


37/38


HOW IT WORKS:

The LM741 is operated open loop as a comparator between the input signal m(t) and the

feedback error signal mr(t). The function of CD4013 is to hold the value of the quantized error signal constant at + or Vcc

during the sampling period.

Both the ICs CD4013 and CD4016 are enabled by the same clock input.

A DC integrator is used in the feedback loop.

The propagation delay in the Flip-flop is considered negligible.

TABULATION:

S.No.

Carrier Input ( Square Wave ) Message Input ( Sine Wave )

Frequency in KHz Amplitude in V Frequency in Hz Amplitude in V

1 10 5 250 1

2 10 5 1000 1

PROCEDURE:

1. The circuit of figure 3 is rigged up with all precautionary measures.

2. The clock signal input is a square wave of 10 KHz with an amplitude of 5V.

3. The message signal input is a sine wave at 250Hz with amplitude of 1V.

4. The DSO is used to observe the message signal and the output DM signal.5. The amplitude of the carrier and the message signal are adjusted to produce a distortion less DM.

6. Observe the error signal at pin 3 of U1.

7. Tabulate the observation.

PS:

Students are advised to design a Demodulator circuit for the block diagram of figure 3.

from the knowledge acquired from the theory of Linear Integrated Circuits

REFERENCES:

1. DATASHEETS of LM741, CD4013, CD4016.

2. DIGITAL COMMUNICATIONS LAB, UNIVERSITY OF CENTRAL FLORIDA.

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38/38

Expt No. 12

DIGITAL MODULATION TECHNIQUES USING TRAINERS

Date

AIM: To study the various Digital Modulation Techniques and to observe the waveforms using Advanced

Digital Communication Trainer Kit.

TEST RIGS:


1 DSO 0 30 MHZ 1

2 Advanced Digital Communication Trainer 10 Experiments 1

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