an94: si2401 modem designer’s guide...packages, this solution includes a dsp data pump, modem...

Rev. 0.31 8/16 Copyright © 2016 by Silicon Laboratories AN94

AN94

Si2401 MODEM DESIGNER’S GUIDE

1. Introduction

This application note is intended to supplement theSi2401 data sheet and is divided into two sections: The"Functional Description" on page 4 and the "SoftwareDesign Reference" on page 15. The Hardware DesignReference provides functional descriptions andinformation necessary to design ISOmodem hardware.Chipset specifications can be found in the data sheet.The Software Design Reference includes information onhow to control the functionality of the modem with ATcommands and register settings. Particular topics ofinterest in either design reference can be easily locatedthrough the Table of Contents or the comprehensiveindex located at the back of this document.

The Hardware Design Reference is divided into threesections. The first section describes the modulationsand protocols supported by the chipset. Next, themodem and DAA chip operation are described, and areference design including a suggested bill of materialsis presented. Silicon Laboratories also has printedcircuit board layout files available separately. Theseinclude double-sided and single-sided layouts withoptions for through-hole isolation components.

Additionally, evaluation boards, useful for evaluating themodem chipset or for initial prototyping work, areavailable. Check with your Silicon Laboratoriessalesperson or distributor for more details.

The Software Design Reference consists of sectionsfocused on the modem controller, memory, and digitalinterface. The modem controller section includes acomplete description of AT commands, “fast connect”options, transparent HDLC/synchronous access mode,escape methods, and default settings. The memorysection describes the S-Registers used to configureboth the modem chip and the line-side DAA chip. Thedigital interface chapter provides details about the serialinterface capability of the modem. Additionally, there areseveral programming examples, a section on testing,and a comprehensive section with configuration settingsfor most countries. Several appendices containinformation on PCB layout, a prototype bring-up guide,and suggestions for transitioning a Si2400 design to aSi2401 design.

Figure 1. Functional Block Diagram

Si3010

IsolationInterface

Hybridand dc

Termination

Ring Detect

Off-Hook

TIP

RING

ExternalCircuitry

Isolation Barrier

UA

RT Controller

(AT Decoder,Call Progress)

Iso

latio

n I

nte

rfa

ce

ControlInterface

ClockInterface

DSP(Data Pump)

RXD

TXD

RESET

EOFR/GPIO1

XOUT

XTALI

Si2401

CTS

RI/GPIO5

INT/GPIO4

ESC/GPIO3

CD/GPIO2

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TABLE OF CONTENTS

Section Page

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43. Hardware Design Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.1. Modulations and Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53.2. Modem and DAA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63.3. Modem (System-Side) Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63.4. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63.5. Power Supply and Bias Circuitry (Si2401) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63.6. Isolation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.7. System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.8. DAA (Line-Side) Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.9. Power Supply and Bias Circuitry (Si3010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.10. Ringer Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.11. DAA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.12. Emissions/Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.13. DC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.14. AC Termination (Si3010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.15. Ring Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.16. Ringer Impedance and Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.17. Pulse Dialing and Spark Quenching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.18. Billing Tone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.19. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.20. Bill of Materials: Si2401/3010 Chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4. Software Design Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154.1. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.2. Configurations and Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.3. Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.4. AT Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.5. S-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254.6. Fast Connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604.7. Low Level DSP Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654.8. Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5. Si2401 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875.1. CTR-21 Test Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875.2. FCC68 Test Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885.3. In-Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895.4. Board Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

6. UL1950 3rd Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Appendix A—ISOmodem® Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Appendix B—Prototype Bring-Up Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Appendix C—Transitioning from the Si2400 to the Si2401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106Appendix D—Si3008 Supplement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112Appendix E—Si3006 Supplement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127Appendix F—Si2401/Si3008 Prototype Bring-Up Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

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2. Functional Description

The Si2401 is a complete modem chipset with integrated direct access arrangement (DAA) that provides aprogrammable line interface to meet global telephone line requirements. Available in two 16-pin small-outlinepackages, this solution includes a DSP data pump, modem controller, codec, and DAA.

The modem accepts simple modem AT commands and provides connect rates up to 2400 bps full-duplex over thePublic Switched Telephone Network (PSTN) with V.42 hardware support through HDLC framing. To minimizehandshake times, the Si2401 can implement a V.22-based fast connect. The modem also supports the V.23reversing protocol and standard alarm formats including SIA.

This device is ideal for embedded modem applications due to its small board space, low power consumption, andglobal compliance. The Si2401 solution integrates a silicon DAA using Silicon Laboratories’ proprietary third-generation isolation technology. This highly-integrated DAA can be programmed to meet worldwide PTTspecifications for ac termination, dc termination, ringer impedance, and ringer threshold. The DAA can also monitorline status for parallel handset detection and overcurrent conditions.

The Si2401 is designed for rapid assimilation into existing modem applications. The device interfaces directlythrough a UART to a microcontroller. The Si2401URT-EVB evaluation board connects directly to a standard RS-232 interface. This allows for evaluation of the modem immediately upon powerup via HyperTerminal or anystandard terminal software.

The chipset can be fully programmed to meet international telephone line interface requirements with fullcompliance to FCC, TBR-21, JATE, and other country-specific PTT specifications. In addition, the Si2401 has beendesigned to meet the most stringent worldwide requirements for out-of-band energy, billing-tone immunity, high-voltage surges, and safety requirements.

Table 1. Selectable Configurations

Configuration ModulationCarrier

Frequency (Hz)Data Rate

(bps)Standard

Compliance

V.21 FSK 1080/1750 300 Full

V.22* DPSK 1200/2400 1200 Full

V.22bis* QAM 1200/2400 2400 No retrain

V.23 FSK

1300/2100 1200/75 Full; plus reversing (Europe)V.23 1300/1700 600/75

Bell 103 FSK 1170/2125 300 Full

Bell 212A DPSK 1200/2400 1200 Full

Security DTMF — 40 Full

SIA—Pulse Pulse — Low Full

SIA Format FSK 1170/2125 300 half-duplex 300 bps only

*Note: The Si2401 only adjusts its DCE rate from 2400 bps to 1200 bps if it is connecting to a V.22-only (1200 bps only) modem. Because the V.22bis specification does not outline a fallback procedure, the host should implement a fallback mechanism consisting of hanging up and connecting at a lower baud rate. Retraining to accommodate changes in line conditions that occur during a call must be implemented by terminating the call and redialing.

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3. Hardware Design Reference

The Si2401 chipset consists of a 16-pin SOIC low-voltage modem chip (Si2401) and a 16-pin SOIC line-side DAA chip (Si3010) connecting directly with thetelephone local loop (TIP and RING). This modemsolution is a complete hardware (controller-based)modem that connects to a host processor through aserial interface. Isolation is provided by SiliconLaboratories’ isolation technology, which uses high-voltage capacitors instead of a transformer. Thisisolation technology complies with globaltelecommunications standards including FCC, CTR-21,JATE, and all known country-specific requirements.Country, EMI/EMC, and safety test reports areavailable. Check with your Silicon Laboratoriessalesperson or distributor for more details.

Additional features include programmable ac/dctermination and ring impedance, on-hook and off-hookintrusion detection, caller ID, loop voltage/loop currentmonitoring, overcurrent detection, ring detection, andthe switch-hook function.

All required program and data memory is included in themodem chip. When the modem receives a software orhardware reset, all register settings revert to the defaultvalues stored in the on-chip program memory. The hostprocessor interacts with the modem controller throughAT commands used to change register settings andcontrol modem operation. Changing register settingsand controlling the modem is described in the SoftwareDesign Reference.

3.1. Modulations and ProtocolsTables 1 and 2 list the modulations and protocols andcarriers and tones supported by the Si2401 modem.The Si2401 supports all modulations and protocols fromBell 103 through V.22bis but does not include errorcorrection or compression.

Table 2. Carriers and Tones

Specification Transmit Carrier (Hz)

Receive Carrier (Hz)

Answer Tone (Hz)

Carrier Detect (Acquire/Release)

V.22bis, V.22OriginateAnswer

12002400

24001200

2100–43 dBm/–48 dBm–43 dBm/–48 dBm

V.23 fwd rev 1300/2100390/450

——

——

–43 dBm/–48 dBm–43 dBm/–48 dBm

V.21Originate (M/S)Answer (M/S)

1180/9801850/1650

1850/16501180/980

2100–43 dBm/–48 dBm–43 dBm/–48 dBm

Bell212AOriginateAnswer

12002400

24001200

2225–43 dBm/–48 dBm–43 dBm/–48 dBm

Bell103Originate (M/S)Answer (M/S)

1270/10702225/2025

2225/20251270/1070

2225–43 dBm/–48 dBm–43 dBm/–48 dBm

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3.2. Modem and DAA OperationThis section describes hardware design requirementsfor optimum Si2401 modem chipset implementation.There are three important considerations for anyhardware design. First, the reference design andcomponents listed in the associated bill-of-materialsshould be followed exactly. These designs reflect fieldexperience with millions of deployed units throughoutthe world and are optimized for cost and performance.Any deviation from the reference design schematic andcomponents will likely have an adverse affect onperformance. Secondly, circuit board layouts mustrigorously follow "Appendix A—ISOmodem® LayoutGuidelines" on page 92. Deviations from these layouttechniques will likely impact modem performance andregulatory compliance. Finally, all reference designs usea standard component numbering scheme. Thissimplifies documentation references andcommunication with the Silicon Laboratories technicalsupport team. It is strongly recommended that thesesame component reference designators be used in allISOmodem® designs.

The following sections describe the operation anddesign considerations of the modem chip, DAA chip,and associated circuitry.

3.3. Modem (System-Side) ChipThe Si2401 modem chip contains a controller, a DSP,program memory (ROM), data memory (RAM), a serialinterface, a crystal oscillator, and an isolation interface.The "Typical Application Schematic" on page 13 clearlyshows that in spite of the significant internal complexityof the chip, the external support circuitry is very simple.The following section describes the function and use ofthe pins and some important considerations for theselection and placement of components.

3.4. Crystal OscillatorThe Si2401 contains an on-chip clock generator. Usinga single master clock input, the Si2401 can generate allmodem sample rates necessary to support V.22bis,V.22/Bell212A, and V.21/Bell103 standards and a9.6 kHz rate for audio playback. Either a 27 MHz or4.9152 MHz clock on XTALI or a 4.9152 MHz crystalacross XTALI and XTALO form the master clock for theSi2401. This clock source is sent to an internal phaselocked loop (PLL), which generates all necessaryinternal system clocks. The PLL has a settling time of~1 ms. Data on RXD should not be sent to the deviceprior to settling of the PLL.

The crystal oscillator circuit requires a 4.9152 MHzfundamental mode parallel-resonant crystal. Typicalcrystals require a 20 pF load capacitance. This load iscalculated as the series combination of the capacitancefrom each crystal terminal to ground including parasiticcapacitance due to package pins and PCB traces. Theparasitic capacitance is estimated as 7 pF per terminal.This in combination with the 33 pF capacitor provides40 pF per terminal, which, in series, yields the proper20 pF load for the crystal.

Frequency stability and accuracy are critically importantto the performance of the modem. ITU-T specificationsrequire less than 200 ppm difference in the carrierfrequency of two modems. This value, split between thetwo modems, requires the oscillator frequency of eachmodem to be accurate and stable over all operatingconditions to within ±100 ppm. This tolerance includesthe initial accuracy of the crystal, frequency drift overthe temperature range the crystal will experience, andfive year aging of the crystal. Other factors affecting theoscillator frequency include the tolerance andtemperature drift of the load capacitor values.

The CLKIN/XTALI pin (pin 1) can accept a 3.3 Vexternal 4.9152 MHz clock signal meeting the accuracyand stability requirements described above. This is theonly input pin on the modem that is not 5 V tolerant. TheSi2401 will accept a 27 MHz clock that meets thevoltage and stability requirements described above if a<10 k resistor is connected between Pin 11 (GPIO4)and Pin 12 (Gnd) and the Si2401 is reset.

3.5. Power Supply and Bias Circuitry (Si2401)

Power supply bypassing is important for the properoperation of the Si2401, the suppression of unwantedradiation and prevention of interfering signals and noisefrom being coupled into the modem via the powersupply. C50 provides filtering of the 3.3 V system powerand must be located as close to the Si2401 chip aspossible to minimize lead lengths. The best practice isto use surface mount components connected between apower plane and a ground plane. This techniqueminimizes the inductive effects of component leads andPCB traces and provides bypassing over the widestpossible frequency range.

Two bias voltages used inside the modem chip requireexternal bypassing and/or clamping. VA (pin 13) isbypassed by C51. R12 and R13 are optional resistorsthat can, in some cases, reduce radiated emissions dueto signals associated with the isolation interface. Thesecomponents must be located as close to the Si2401chip as possible to minimize lead lengths.

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3.6. Isolation InterfaceThe interface connecting the modem chip and the DAAchip through a high-voltage isolation barrier provided bycapacitors C1 and C2 serves three purposes. First, ittransfers control signals and transmit data from themodem chip to the DAA chip. Secondly, it transfersreceive and status data from the DAA chip to themodem chip. Finally, it provides power from the modemchip to the DAA chip while the modem is in the on-hookcondition. The signaling on this interface is intended forcommunication between the modem and the DAA chipsand cannot be used for any other purpose. It isimportant to keep the length of the C1 and C2 traces asshort and direct as possible. The layout guidelines forthe pins and components associated with this interfaceare described in "Appendix A—ISOmodem® LayoutGuidelines" on page 92 and must be carefully followedto ensure proper operation and avoid unwantedemissions.

3.7. System InterfaceThe serial interface allows the host processor tocommunicate with the modem controller through aUART driver. In this mode, the modem is analogous toan external “box” modem. The interface pins are 5 Vtolerant, and communicate with TTL compatible low-voltage CMOS levels. RS232 interface chips, such asthose used on the Si2401URT-EVB evaluation board,can be used to make the serial interface directlycompatible with a PC or terminal serial port. Theoperation of these pins is described in the section,"Software Design Reference" on page 15.

3.8. DAA (Line-Side) ChipThe Si3010, DAA or line-side chip, contains an ADC, aDAC, control circuitry, and an isolation interface. TheSi3010 and surrounding circuitry provide all functionalityfor telephone line interface requirement complianceincluding a full-wave bridge, hookswitch, dc termination,ac termination, ring detect, loop voltage/currentmonitoring, and call progress monitoring. A schematicof the Si3010 circuitry is shown in Figure 2 with thecomponent functions identified. Additionally, the Si3010external circuitry is largely responsible for EMI, EMC,safety, and surge performance.

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3.9. Power Supply and Bias Circuitry(Si3010)

The Si3010 is powered by a small current passedacross the isolation barrier in the on-hook mode and bythe loop current in the off-hook mode. Since there is nosystem ground reference for the line-side chip due toisolation requirements, a virtual ground, IGND, is usedas a reference point for the Si3010. Several biasvoltages and signal reference points used inside theDAA chip require external bypassing, filtering, and/orclamping. VREG2 (pin 10) is bypassed by C6. VREG(pin 7) is bypassed by C5. These components must belocated as close to the Si3010 chip as possible tominimize lead lengths. The best practice is to usesurface mount components and very short PCB tracelengths to minimize the inductive effects of componentleads and PCB traces thereby bypassing over thewidest possible frequency range and minimizing loopareas that can radiate radio-frequency energy.

3.10. Ringer NetworkR7 and R8 comprise the ringer network. Thesecomponents determine the modem’s on-hookimpedance at TIP and RING. These components areselected to present a high impedance to the line, andcare must be taken to ensure the circuit board areaaround these components is clean and free ofcontaminants, such as solder flux and solder flakes.Leakage on RNG1 (Si3010, pin 8) and RNG2 (Si3010,pin 9) can impair modem performance.

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3.11. DAA OperationThis section describes the detailed functionality of theintegrated DAA included in the Si2401 chipset. Thisfunctionality is generally transparent to the user whenusing the on-chip controller in the Si2401 modem.When bypassing the on-chip controller, the low-levelDAA functions of the Si3010 described in this sectioncan be controlled through S registers.

3.12. Emissions/ImmunityThe Si2401 chipset and recommended DAA schematicis fully-compliant with and passes all internationalelectromagnetic emissions and conducted immunitytests (includes FCC part 15,68; EN50082-1). Carefulattention to the Si2401 "Bill of Materials: Si2401/3010Chipset" on page 14, "Typical Application Schematic"on page 13, and the layout guidelines included in"Appendix A—ISOmodem® Layout Guidelines" on page92 will ensure compliance with these internationalstandards.

3.13. DC TerminationThe Si2401 has programmable settings for the dcimpedance, current limiting, minimum operational loopcurrent, and TIP/RING voltage, which are selected withSF5, SF6, and SF8. The dc impedance of the Si2401 isnormally represented with a 50 slope as shown inFigure 3 but can be changed to an 800 slope bysetting SF8[1] (DCR). This higher dc terminationpresents a higher resistance to the line as loop currentincreases.

Figure 3. FCC Mode I/V Characteristics, DCV[1:0] = 11, MINI[1:0] = 00

For applications requiring current limiting per the legacyTBR-21 standard, SF5[3] (ILIM) may be set to selectthis mode. In this mode, the dc I/V curve is changed to a2000 slope above 40 mA, as shown in Figure 4. Thisallows the Si2401 to operate with a 50 V, 230 feed,which is the maximum linefeed specified in the TBR-21standard.

Figure 4. TBR-21 Mode I/V Characteristics, DCV[1:0] = 11, MINI[1:0] = 00

The SF6[7:6] (MINI[1:0]) selects the minimumoperational loop current for the Si2401, and SF6[5:4](DCV[1:0]) adjusts the DCT pin voltage, which affectsthe TIP/RING voltage of the DAA. These bits allowimportant trade-offs. Increasing TIP/RING voltageincreases signal headroom, whereas decreasing theTIP/RING voltage allows compliance to PTT standardsin low-voltage countries, such as Japan. Increasing theminimum operational loop current above 10 mA alsoincreases signal headroom and prevents degradation ofthe signal level in low voltage countries.

3.14. AC Termination (Si3010)The Si2401 has four ac termination impedancesselected with SF6[3:0] (ACT), which are listed inTable 3. If an ACT setting other than the four listed inTable 3 is selected, the ac termination is forced to 600 (ACT[3:0] = 0000).

The most widely-used ac terminations are available asregister options to satisfy various global PTTrequirements. The real 600 impedance satisfies therequirements of FCC Part 68, JATE, and other countryrequirements. Setting ACT[3:0] = 0011 satisfies therequirements of TBR-21, and most countries requiring acomplex impedance except New Zealand.ACT[3:0] = 0100 is used for New Zealand.

ACT[3:0] = 1111, is designed to satisfy minimum returnloss requirements for every country that requires a

12

11

10

9

8

7

6.01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11

Loop Current (A)

FCC DCT Mode

Vol

tage

Acr

oss

DA

A (

V)

45

40

35

30

25

20

15

10

5.015 .02 .025 .03 .035 .04 .045 .05 .055 .06

Loop Current (A)

CTR21 DCT Mode

Vo

lta

ge

Ac

ros

s D

AA

(V

)

AN94

Rev. 0.31 11

complex termination. Selecting this setting ensuresmeeting minimum PTT requirements.

3.15. Ring ValidationRing validation prevents false triggering of a ringdetection by validating the ring frequency. Invalidsignals, such as a loop current change when a parallelhandset goes off-hook, pulse dialing, or a high-voltageline test, are ignored.

The ring validation circuit operates by calculating thetime between alternating crossings of positive andnegative ring thresholds to validate that the ringfrequency is within tolerance. High- and low-frequencytolerances are programmable in registers SED[5:0](RAS[5:0]) and SEE[3:0] (RMX[3:0]). Register SEC[3:1](RCC[2:0]) defines how long the ring signal must bewithin tolerance.

Once the duration of the ring frequency is validated bythe RCC bits, the circuitry stops checking for frequencytolerance and begins checking for the end of the ringsignal, which is defined by a lack of additional thresholdcrossings for a period of time configured by registerSEE[7:4] (RTO[3:0]). When the ring frequency is firstvalidated, a timer defined by SEC[6:4] (RDLY[2:0]) isstarted. If the RDLY[2:0] timer expires before the ringtimeout, the ring is validated, and a valid ring isindicated. If the ring timeout expires before theRDLY[2:0] timer, a valid ring is not indicated.

Ring validation requires the following five parameters:

Timeout parameter to place a lower limit on the frequency of the ring signal (the RAS[5:0] bits. This is measured by calculating the time between crossings of positive and negative ring thresholds.

Minimum count to place an upper limit on the frequency (the RMX[5:0] bits).

Time interval over which the ring signal must be the correct frequency (the RCC[2:0] bits).

Timeout period that defines when the ring pulse has ended based on the most recent ring threshold crossing (the RTO[3:0] bits).

Delay period between when the ring signal is validated and when a valid ring signal is indicated to help accommodate distinctive rings (the RDLY[2:0] bits).

There is also a ring validation enable bit, SEC[7](RNGVE), which enables or disables the ring validationfeature in both normal operating mode and low-powersleep mode.

3.16. Ringer Impedance and ThresholdThe ring detector in a typical DAA is ac-coupled to theline with a large, 1 µF, 250 V decoupling capacitor. Thering detector on the Si3010 is resistively-coupled to theline. Inherently, this network produces a very high ringerimpedance of approximately 20 M to the line. Thisvalue is acceptable for the majority of countries,including FCC and TBR-21.

Several countries including Poland, South Africa, andSlovenia, require a maximum ringer impedance that canbe met with an internally-synthesized impedance bysetting SF5[2] (RZ) = 1. Certain countries also specifyringer thresholds differently. SF5[1] (RT) selectsbetween two different ringer thresholds: 15 V ±10% and21 V ±10%. This setting enables satisfaction ofworldwide ringer threshold requirements. Thresholdsare set so that a ring signal is guaranteed to not bedetected below the minimum, and a ring signal isguaranteed to be detected above the maximum.

3.17. Pulse Dialing and Spark QuenchingPulse dialing is accomplished by going off- and on-hookto generate make and break pulses. The nominal rate is10 pulses per second. Some countries have strictspecifications for pulse fidelity, including make andbreak times, make resistance, and rise and fall times. Ina traditional solid-state dc holding circuit, there are anumber of issues in meeting these requirements.

The Si2401 dc holding circuit has active control of theon- and off-hook transients to maintain pulse dialingfidelity.

Spark quenching requirements in countries, such asItaly, the Netherlands, South Africa, and Australia, dealwith the on-hook transition during pulse dialing. Thesetests provide an inductive dc feed resulting in a largevoltage spike. This spike is caused by the lineinductance and the sudden decrease in current throughthe loop when going on-hook. The traditional way ofdealing with this problem is to put a parallel RC shuntacross the hookswitch relay. The capacitor is large(~1 F, 250 V) and relatively expensive. By settingSF5[5:4] (OHS[1:0]), the Si2401 loop current can becontrolled to achieve three distinct on-hook speeds topass spark quenching tests without additional BOMcomponents.

Table 3. AC Termination Settings

ACT[3:0] AC Termination

0000 600 0011 220 + (820 || 120 nF) and 220 +

(820 || 115 nF)

0100 370 + (620 || 310 nF)

1111 Global complex impedance

AN94

12 Rev. 0.31

3.18. Billing Tone“Billing tones” or “metering pulses” generated by thecentral office can cause modem connection difficulties.The billing tone is typically either a 12 or 16 kHz signaland is sometimes used in Germany, Switzerland, andSouth Africa. Depending on line conditions, the billingtone may be large enough to cause major modemerrors.

Although the DAA remains off-hook during a billing toneevent, the received data from the line is corrupted (or amodem disconnect or retrain may occur) in the presenceof large billing tones. If the user wishes to receive datathrough a billing tone, an external LC filter must beadded. A modem manufacturer can provide this filter tousers in the form of a dongle that connects on the phoneline before the DAA. This keeps the manufacturer fromhaving to include a costly LC filter internal to the modemwhen it may only be necessary for a few countries/customers.

To operate without degradation during billing tones inGermany, Switzerland, and South Africa, an external LCnotch filter is required. (The Si3010 can remain off-hookduring a billing tone event, but modem data will be lost[or a modem disconnect or retrain may occur] in thepresence of large billing tone signals.) The notch filterdesign requires two notches: One at 12 kHz and one at16 kHz. Because these components are fairlyexpensive and few countries supply billing tone support,this filter is typically placed in an external dongle oradded as a population option for these countries.Figure 5 shows an example billing tone filter. Figure 6shows the billing tone filter and the ringer impedancenetwork for the Czech Republic. Both of these circuitsmay be combined into a single external dongle.

L3 must carry the entire loop current. The seriesresistance of the inductors is important to achieve anarrow and deep notch. This design has more than25 dB of attenuation at both 12 and 16 kHz.‘

Figure 5. Billing Tone Filter

Figure 6. Dongle Applications Circuit

The billing tone filter affects the ac termination andreturn loss. The current complex ac termination passesworldwide return loss specifications both with andwithout the billing tone filter by at least 3 dB. The actermination is optimized for frequency response andhybrid cancellation while having greater than 4 dB ofmargin with or without the dongle for South Africa,Australia, TBR-21, Germany, and Swiss country-specific specifications.

Table 4. Component Values—Optional Billing Tone Filters

Symbol Value

C1,C2 0.027 F, 50 V, ±10%

C3 0.01 F, 250 V, ±10%

L3 3.3 mH, >120 mA, <10 , ±10%

L4 10 mH, >40 mA, <10 , ±10%

L4

C3

RING

TIP

FROMLINE

ToDAA

C1

C2

L3

TIP

RING

L33.3mH, 120 mA

C10.027F, 50 V

C20.027F, 50 V

FromLine

ToSi3010

L43.3mH, 40 mA

C30.01F, 250 V

AN94

Rev. 0.31 13

3.19. Typical Application Schematic

GP

IO1

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FR

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NT

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CL

KG

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GND12

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DC

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IB4

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B5

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8

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C2

D1

R1

2

Q2

R1

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Y1

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C1

0

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R1

3

Q4

R11

C8R

15

Z1

Q3

C5

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C4

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6

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pic

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chem

atic

AN94

14 Rev. 0.31

3.20. Bill of Materials: Si2401/3010 Chipset

Component Value Supplier(s)

C1, C2 33 pF, Y2, X7R, ±20% Panasonic, Murata, Vishay

C3 10 nF, 250 V, X7R, ±20% Venkel, SMEC

C4 1.0 µF, 50 V, X7R, ±20% Venkel, SMEC

C5, C6, C50 0.1 µF, 16 V, X7R, ±20% Venkel, SMEC

C7 2.7 nF, 50 V, X7R, ±20% Venkel, SMEC

C8, C9 680 pF, Y2, X7R, ±10% Panasonic, Murata, Vishay


C40, C411 33 pF, 16 V, NPO, ±5% Venkel, SMEC


D1, D22 Dual Diode, 225 mA, 300 V, CMPD2004S Central Semiconductor

FB1, FB2 Ferrite Bead, BLM21AG601SN1 Murata

Q1, Q3 NPN, 300 V, MMBTA42 OnSemi, Fairchild

Q2 PNP, 300 V, MMBTA92 OnSemi, Fairchild

Q4, Q5 NPN, 80 V, 330 mW, MMBTA06 OnSemi, Fairchild

RV1 Sidactor, 275 V, 100 A Teccor, Protek, ST Micro

R1 1.07 k, 1/2 W, 1% Venkel, SMEC, Panasonic

R2 150 , 1/16 W, 5% Venkel, SMEC, Panasonic



R5, R6 100 k, 1/16 W, 5% Venkel, SMEC, Panasonic

R7, R8 20 M, 1/16 W, 5% Venkel, SMEC, Panasonic

R9 1 M, 1/16 W, 1% Venkel, SMEC, Panasonic

R10 536 , 1/4 W, 1% Venkel, SMEC, Panasonic

R11 73.2 , 1/2 W, 1% Venkel, SMEC, Panasonic

R12, R13 56 , 1/16 W, 1% Venkel, SMEC, Panasonic

R15, R163 0 , 1/16 W Venkel, SMEC, Panasonic

U1 Si2401 Silicon Labs

U2 Si3010 Silicon Labs

Y11,4 4.9152 MHz, 20 pF, 100 ppm, 150 ESR ECS Inc., Siward

Z1 Zener Diode, 43 V, 1/2 W, BZT52C43 On Semi

Notes:1. In STB applications, C40, C41, and Y1 can be removed when using the 27 MHz clock input feature.2. Several diode bridge configurations are acceptable. For example, a single DF04S or four 1N4004 diodes may be

used.3. Murata BLM21AG601SN1 may be substituted for R15–R16 (0 ) to decrease emissions.4. To ensure compliance with ITU specifications, frequency tolerance must be less than 100 ppm including initial

accuracy, 5-year aging, 0 to 70 °C, and capacitive loading. 50 ppm initial accuracy crystals typically satisfy this requirement.

AN94

Rev. 0.31 15

4. Software Design Reference

The Si2401 modem chipset is controller-based. Nomodem drivers are required to run on the systemprocessor. This makes the Si2401 ideal for embeddedsystems because a wide variety of processors andoperating systems can interface with the Si2401through a simple UART (universal asynchronousreceiver transmitter) driver.

The Si2401 can be programmed to comply with FCC,JATE, CTR-21, and other country-specific PTTrequirements. “Fast connect” and “transparent HDLC”modes are also supported.

The Si2401 is highly integrated. The basic Si2401functional blocks are shown in Figure 8. The Si2401includes a controller, data pump (DSP), ROM, RAM, anoscillator, phase-locked loop (PLL), timer, serialinterface, UART, and a DAA interface. The modemsoftware is permanently stored in the on-chip ROM.Only modem setup information (other than defaults) andother software updates must be stored on the host anddownloaded to the on-chip RAM during initialization.There is no non-volatile on-chip memory other thanProgram ROM. The default user interface for the Si2401is the serial interface including the UART.

This section provides information about the architectureof the modem, the functional blocks, registers, and theirinteraction. The AT command set is presented andoptions are explained. The accessible memorylocations (S-Registers) are described. Instructions forwriting to and reading from them are discussed alongwith any limitations or special considerations. A largenumber of configuration and programming examplesare offered as illustrations of actual testableapplications. These examples can be used alone or incombination to create the desired modem operation.

This section is organized into seven major sections:Serial Interface, Controller, AT Command S-Registers,Fast Connect, DSP Control, and ProgrammingExamples. The “Controller” section contains informationabout using controller functions and features, such asthe AT command set, result codes, escape methods,power control, and system reset information. The “DSP”section is brief because the programmer has littlecontrol over the operation of the DSP. The use offeatures that modify DSP behavior is described in othersections. The “Memory” section describes the use of S-Registers to control the operation, features, andconfiguration of the modem.

Finally, the “Programming Examples” section illustratesthe implementation of modem functions and featureswith the required AT commands and register values.Configuration data is provided for most countries. Theseexamples can be used both to test modem operationand as a programming aid.

Figure 8. Si2401 Functional Block Diagram

SerialInterface/

UART DS

P DAAInterface

ROM

PLLClocking

XTI XTO

INT

RESET

C1

To PhoneLine

AOUT

Data Bus

Con

trol

ler

Si3

010

RXDTXDCTSCD

ESCRI

Pro

gram

Bus

RAM

C2

Timer

AN94

16 Rev. 0.31

4.1. Serial InterfaceThe Si2401 has a universal asynchronous receiver/transmitter (UART) serial interface compatible withstandard microcontroller serial interfaces. After powerupor reset, the speed of the serial (Data TerminalEquipment—DTE) interface is set by default to2400 bps with the 8-bit, no parity, and one-stop bit (8N1)format described below.

The serial interface DTE rate can be modified by writingSE0[2:0] (SD) with the value corresponding to thedesired DTE rate. (See Table 5.) This is accomplishedwith the command, ATSE0=xx, where xx is thehexadecimal value of the SE0 register.

Immediately after the ATSE0=xx string is sent, the hostUART must be reprogrammed to the new DTE rate inorder to communicate with the Si2401.

The carriage return character following the ATSE0=xxstring must be sent at the new DTE rate to observe the“O” response code. See Table 7 on page 18 for theresponse code summary.

4.2. Configurations and Data RatesThe Si2401 can be configured to any of the Bell andCCITT operation modes listed in Table 6. Whenconfigured for V.22bis, the modem connects at1200 bps if the far end modem is configured for V.22.This device also supports SIA and other protocols forthe security industry. Table 1 on page 4 provides themodulation method, carrier frequencies, data rate, baudrate, and notes on standard compliance for eachmodem configuration of the Si2401. Table 6 showsexample register settings (S07) for some of the modemconfigurations.

As shown in Figure 9, 8-bit and 9-bit data modes refer tothe DTE format over the UART. Line data formats areconfigured through registers S07 (MF1) and S15 (MLC).If the number of bits specified by the format differs fromthe number of bits specified by the DCE datacommunications equipment or line (DTE) format, theMSBs are either dropped or bit-stuffed, as appropriate.For example, if the DTE format is 9 data bits (9N1), andthe line data format is 8 data bits (8N1), the MSB fromthe DTE is dropped as the 9-bit word is passed from theDTE side to the DCE (line) side. In this case, thedropped ninth bit can then be used as an escapemechanism. However, if the DTE format is 8N1, and theline data format is 9N1, an MSB equal to 0 is added tothe 8-bit word as it is passed from the DTE side to theDCE side.

The Si2401 UART does not continuously check for stopbits on the incoming digital data. Therefore, if the TXDpin is not high, the RXD pin may echo meaninglesscharacters to the host UART. This requires the hostUART to flush its receiver FIFO upon initialization.

Figure 9. Link and Line Data Formats

Table 5. DTE Rates

DTE Rate (bps) SE0[2:0] (SD)

300 000

1200 001

2400 010

9600 011

19200 100

38400 101

115200 110

307200 111

Table 6. Modem Configuration Examples (S07[7] (HDEN) = 0, S07[6] (BD) = 0)

Modem Protocol Register S07 Values

V.22bis 0x06

V.22 0x02

V.21 0x03

Bell 212A 0x00

Bell 103 0x01

V.23 (1200 tx, 75 rx) 0x16

V.23 (75 tx, 1200 rx) 0x26

V.23 (600 tx, 75 rx) 0x10

V.23 (75 tx, 600 rx) 0x20

DTE InterfaceData Rate: SE0[2:0] (SD)Data Format: SE0[3] (ND)

DCE (Line) InterfaceData Rate: S07 (MF1)

Data Format: S15 (MLC)

Si3010Si2401

RJ11TXD

RXD

AN94

Rev. 0.31 17

4.2.1. 8-Bit Data Mode (8N1)

The 8-bit data mode is the default mode after powerupor reset and is set by SE0[3] (ND) = 0b. It isasynchronous, full duplex, and uses a total of 10 bitsincluding a start bit (logic 0), eight data bits, and a stopbit (logic 1). Data received from the remote modem istransferred from the Si2401 to the host on the RXD pin.Data transfer to the host begins when the Si2401asserts a logic 0 start bit on RXD. Data is shifted out ofthe Si2401 LSB first at the DTE rate determined by theSE0[2:0] (SD) setting and terminates with a stop bit.Data from the host for transmission to the remotemodem is shifted to the Si2401 on TXD beginning with astart bit, LSB first at the DTE rate determined by theSE0[2:0] setting and terminates with a stop bit. After themiddle of the stop bit time, the Si2401 begins looking fora logic 1 to logic 0 transition signaling the start of thenext character on TXD to be sent to the line (remotemodem).

4.2.2. 9-Bit Data Mode (9N1)

The 9-bit data mode is set by SE0[3] (ND) = 1. It isasynchronous, full duplex, and uses a total of 11 bitsincluding a start bit (logic 0), 9 data bits, and a stop bit(logic 1). Data received from the line (remote modem) istransferred from the Si2401 to the host on the RXD pin.Data transfer to the host begins when the Si2401asserts a logic 0 start bit on RXD. Data is shifted out ofthe Si2401 LSB first at the DTE rate determined by theSE0[2:0] (SD) setting and terminates with a stop bit.Data from the host for transmission to the line (remotemodem) is shifted to the Si2401 on TXD beginning witha start bit, LSB first at the DTE rate determined by theS-Register SE0[2:0] (SD) setting, and terminates with astop bit. After the middle of the stop bit time, the Si2401begins looking for a logic 1 to logic 0 transition signalingthe start of the next character on TXD to be sent to theline (remote modem).

The ninth data bit may be used to indicate an escape bysetting S15[0] (NBE) = 1. In this mode, the ninth data bitis normally set to 0 when the modem is online. Whenthe ninth data bit is set to 1, the modem goes offline intocommand mode, and the next frame is interpreted as anAT command. Data mode can be reentered using theATO command.

4.2.3. Flow Control

No flow control is needed if the DTE rate and DCE rateare the same. If the serial link (DTE) data rate is sethigher than the line (DCE) rate of the modem, flowcontrol is required to prevent loss of data to thetransmitter.

To control data flow, the clear-to-send (CTS) pin is used.When CTS is asserted, the Si2401 is ready to accept a

character. While CTS is negated, no data should besent to the Si2401 on TXD. To simplify flow control, theSi2401 has an integrated ten character transmit FIFOand allows for two different CTS reporting methods. Bydefault, the CTS pin is negated as soon as a start bit isdetected on the TXD pin and remains negated until themodem is ready to accept another character (seeFigure 2 on page 9.) By setting SFC[7] = 1 (CTSM),CTS is negated when the FIFO is 70% full and isreasserted when the FIFO is 30% full.

4.3. ControllerThe controller provides several vital functions includingAT command parsing, DAA control, connect sequencecontrol, DCE protocol control, intrusion detection,parallel phone off-hook detection, escape control, callerID control, ring detect, DTMF control, call progressmonitoring, and HDLC framing. The controller alsowrites to the control registers that configure the modem.Virtually all interaction between the host and the modemis done via the controller. The controller uses AT(ATtention) commands and S-Registers to configureand control the modem.

The modem has two modes of operation: commandmode and data mode. The Si2401 is asynchronous inboth command mode and data mode. The modem is incommand mode at powerup, after a reset, before aconnection is made, after a connection is dropped, andduring a connection after successfully “Escaping” fromthe data mode back to the command mode using one ofthe methods previously described. The following sectiondescribes the AT command set available in commandmode.

Upon reset, the modem is in command mode andaccepts AT-style commands. An outgoing modem callcan be made using the “ATDT#” (tone dial) or “ATDP#”(pulse dial) command after the device is configured. Ifthe handshake is successful, the modem responds withthe “c”, “d”, or “v” string and enter data mode. (The bytefollowing the “c”, “d”, or “v” is the first data byte.) At thispoint, AT-style commands are not accepted. There arethree methods that may be used to return the Si2401 tocommand mode:

Use the ESC pin—To program the GPIO3 pin to function as an ESCAPE input, set GPIO3 SE2[5:4] = 11. In this setting, a positive edge detected on this pin returns the modem to command mode. The “ATO” string can be used to re-enter data mode.

Use 9-bit data mode—If 9-bit data format with escape is programmed, a 1 detected on bit 9 returns the modem to command mode. (See Figure 2 on page 9.) This is enabled by setting SE0[3] (ND) = 1

AN94

18 Rev. 0.31

and S15[0] (NBE) = 1. The ATO string can be used to reenter data mode. Ninth bit escape does not work in the security modes.

Use “+++”—The escape sequence is a sequence of three escape characters that are set in S-register

S0F (“+” characters by default). If the ISOmodem® chipset detects the “+++” sequence and detects no activity on the UART before or after the “+++” sequence for a time period set by S-register S10, it returns to command mode. To disable this escape sequence, set S-register S10=FF. To remove the time-dependent behavior, set S-register S10=00.

Whether using an escape method or not, when thecarrier is lost, the modem automatically returns tocommand mode and reports “N”.

4.4. AT Command SetThe Si2401 supports a subset of the typical modem ATcommand set since it is intended for use with adedicated microcontroller instead of general terminalapplications. AT commands begin with the letters ATand are followed directly (no space) by the command.All AT commands must be entered in upper case orlower case (not mixed) except w##, r#, m#, q#, and z(wakeup-on-ring).

AT commands can be divided into two groups: controlcommands and configuration commands. Controlcommands, such as ATD, cause the modem to performan action (going off-hook and dialing). The value of thistype of command is changed at a particular time toperform a particular action. For example, theATDT1234<CR> command causes the modem to gooff-hook and dial the number, 1234, via DTMF. Thisaction exists only during a connection attempt. Noenduring change in the modem configuration existsafter the connection or connection attempt has ended.

Configuration commands change modemcharacteristics until they are modified or reversed by asubsequent configuration command or the modem isreset. Modem configuration status can be determinedwith the use of “ATSR?<CR>” Where R is the twocharacter hexadecimal address of an S-register.

A command line is defined as a string of charactersstarting with AT and ending with an end-of-linecharacter, <CR> (13 decimal). Command lines maycontain several commands one after the other. If thereare no characters between AT and <CR>, the modemresponds with “O” after the carriage return.

4.4.1. Command Line Execution

The characters in a command line are executed one ata time. Unexpected command characters are ignored,but unexpected data characters may be interpreted

incorrectly.

After the modem has executed a command line, theresult code corresponding to the last commandexecuted is returned to the terminal or host. In additionto the “ATH” and “ATZ” commands, the commands thatwarrant a response (e.g., “ATSR?” or “ATI”) must be thelast in the string and followed by a <CR>. All othercommands may be concatenated on a single line. Toecho command line characters, set the Si2401 to echomode using the E1 command.

All numeric arguments, including the address and valueof an S-register, are in hexidecimal format, and twodigits must always be entered.

4.4.2. <CR> End-Of-Line Character

This character is typed to end a command line. Thevalue of the <CR> character is 13 in decimal, the ASCIIcarriage return character. When the <CR> character isentered, the modem executes the commands in thecommand line.

Note: Commands that do not require a response are exe-cuted immediately and do not need a <CR>.

4.4.3. AT Command Set Description

A Answer

The “A” command makes the modem go off-hook andrespond to an incoming call. This command is to beexecuted after the Si2401 has indicated a ring hasoccurred. (The Si2401 indicates an incoming ring byechoing an “R”.)

Table 7. AT Command Set Summary

Command FunctionA Answer line immediately with modem

DT# Tone dial numberDP# Pulse dial number

E Local echo on/offH0 Go on-hook (hang up modem)H1 Go off-hookI Chip revision:I Interrupt read and clearM Speaker control optionsO Return online

RO V.23 reverseS Read/write S-Registers

w## Write S-Register in binaryr# Read S-Register in binarym# Monitor S-Register in binaryq# Read S-Register in binaryV0 Result code with no carriage returnV1 Result code with added carriage returnsZ Software resetz Wakeup on ring

AN94

Rev. 0.31 19

This command is aborted if any other character istransmitted to the Si2401 before the answer process iscompleted.

Auto answer mode is entered by setting S00 (NR) to anon-zero value. NR indicates the number of rings beforeanswering the line.

Upon answering, the modem communicates bywhatever protocol has been determined via the modemcontrol registers in S07 (MF1).

If no transmit carrier signal is received from the callingmodem within the time specified in S39 (CDT), themodem hangs up and enters the idle state.

D Dial

DT# Tone Dial Number.

DP# Pulse Dial Number.

The D commands make the modem dial a telephonecall according to the digits and dial modifiers in the dialstring following the command. A maximum of 64 digits isallowed. A DT command performs tone dialing, and aDP command performs pulse dialing.

The ATH1 command can be used to go off-hook withoutdetecting a dial tone or dialing.

The dial string must contain only the digits “0–9”, “*”, “#”,“A”, “B”, “C”, “D”, or the modifiers “;”, “/”, or “,”. Othercharacters are interpreted incorrectly. The modifier “,”causes a two second delay (added to the spacing valuein S04) in dialing. The modifier “/” causes a 125 msdelay (added to the spacing value in S04) in dialing. Themodifier “;” returns the device to command mode afterdialing and must be the last character.

If any character is received by the Si2401 between theATDT#<CR> (or ATDP#<CR>) command and when theconnection is made (“c” or “d” is echoed), the extracharacter is interpreted as an abort, and the Si2401returns to command mode ready to accept ATcommands. A line feed character immediately followingthe <CR> is treated as an “extra character” and abortsthe call.

If the modem does not have to dial (i.e., “ATDT<CR>” or“ATDP<CR>” with no dial string), the Si2401 assumesthe call was manually established and attempts to makea connection.

Automatic Tone/Pulse Dialing

The Si2401 can be configured to attempt DTMF dialingand automatically revert to pulse dialing if it determinesthat the line is not DTMF-capable. This feature is bestexplained by the following example:

If it is desired that the telephone number, 12345, bedialed, it is normally accomplished through either theATDT12345 or the ATDP12345 command. In the force

pulse dialing mode of operation, the following stringshould be issued instead:

ATDT1,p12345

If the result code returned is “t,” this indicates that thedialing was accomplished using DTMF dialing. If theresult code returned is “tt,”, it indicates that the dialingwas accomplished using pulse dialing.

In the above example, the Si2401 dials the first digit “1”using DTMF dialing. The “,” is used to pause in order toensure that the central office has had time to accept theDTMF digit “1”. When the Si2401 processes the “p”command, it attempts to detect a dial tone. If a dial toneis detected, the DTMF digit “1” was not effective, hence,the line does not support DTMF dialing. Conversely, ifthe dial tone is not detected, the DTMF digit “1” waseffective, and the line supports DTMF dialing. Thecharacter after the “p” may or may not be dialeddepending on whether the DTMF digit “1” was effectiveor not. If the “1” was effective (DTMF mode), thecharacter after the “p” is skipped. The next DTMF digitto be dialed is “2”. Subsequent digits are all DTMF. If the“1” was not effective, the first character after the “p” (the“1”) is pulse dialed, and subsequent digits are all pulsedialed. When using the character “p”, there need to beat least two digits following it for proper operation.

E Command Mode Echo

Tells the Si2401 whether or not to echo characters sentfrom the terminal.

EO

Does not echo characters sent from the terminal.

E1

Echoes characters sent from the terminal.

H0 Hangup

Hang up and go into command mode (go offline).

H1 Off-hook

Go off-hook and remain in command mode. (BeforeATH1, set register SAA = 00 for proper operation.)

I Chip Identification

This command causes the modem to echo the chiprevision for the Si2401 device.

A = Revision A

B = Revision B

C = Revision C, etc.

I6

Display the ISOmodem model number.

“2401” = Si2401.

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:I Interrupt Read

This command causes the ISOmodem chipset to reportthe contents of the interrupt status register (S09). TheWOR, PPD, NLD, RI, OCD, and REV bits are alsocleared, and the INT is deactivated on this read.

M Speaker On/Off Options

These options are used to control AOUT for use with acall progress monitor speaker. Register SF4[3:0] andSE4 and SE2 need to be programmed properly prior tothe ATMx command.

M0

Speaker always off.

M1

Speaker on until carrier established. The modem setsSF4[3:2] (ARL) = 11b and SF4[1:0] (ATL) = 11b after aconnection is established.

M2

Speaker always on.

M3

Speaker on after last digit dialed, off at carrier detect.

O Return to Online Mode

This command returns the modem to the online mode. Itis frequently used after an escape sequence to resumecommunication with the remote modem.

RO Turn-Around

This command initiates a V.23 “direct turnaround”sequence and returns online.

S S Register Control

SR=N

Write an S register. This command writes the value “N”to the S-register specified by “R”. “R” is a hexidecimalnumber, and “N” must also be a hexadecimal numberfrom 00–FF. This command does not wait for a carriagereturn <CR> before taking effect.

Note: Two digits must always be entered for both “R” and “N”.

SR?

Read an S register. This command causes the Si2401to echo the value of the S-register specified by R in hexformat. R must be a hexidecimal number.

Note: Two digits must always be entered for R.

w## Write S Register in BinaryThis command writes a register in binary format. Thefirst byte following the “w” is the address in binaryformat and the second byte is the data in binary format.This is a more rapid method to write registers than the“SR=N” command and is recommended for use by ahost microcontroller.

r# Read S Register in Binary

This command reads a register in binary format. Thebyte following the “r” is the address in binary format.The modem echoes the contents of this register inbinary format. This is a more rapid method to readregisters than the “SR?” command and isrecommended for use by a host microcontroller.

Notes:

1. w## and r# are not required to be on separate lines (i.e., no <CR> between them). Also, the result of an r# is returned immediately without waiting for a <CR> at the end of the AT command line.

2. Once a <CR> is encountered, “AT” is again required to begin the next “AT” command.

3. Modem result codes should be disabled to avoid confusion with data being read. This can be done by setting S62 = 40.

m# Monitor S Register in Binary

This command monitors a register in binary format. Thebyte following the “m” is the address in binary format.The Si2401 constantly transmits the contents of theregister at the set baud rate until a new byte istransmitted to the device. The new byte is ignored andviewed as a stop command. The modem result codesshould be disabled (as described above in r#) beforeusing this command. q# Read S Register in BinaryThis command is exactly the same as the r# command;however, the response from the Si2401 is formatted as0x55 followed by the contents of the register in binary.This guarantees that the register contents are alwayspreceded by 0x55 and allows the result codes to remainenabled.V Result Code Options

V0

Result codes reported according to Table 9.

V1

Result codes reported with an additional carriage returnand line feed (default).

Z Software Reset

The “Z” command initiates a software reset causing allregisters, with the exception of E0, which controls theDTE settings, to default to their powerup value.

The hardware reset pin, RESET (Si2401, pin 8), is usedto reset the Si2401 to factory default settings.

z Wakeup on Ring (lower-case z)

The Si2401 enters a low-power mode in which the DSPand microcontroller are powered down. In this mode,only the line-side device (Si3010) and the C1/C2communication link are functional. An incoming ringsignal or line transient causes the Si2401 to power upand echo an “R”. Any character received on the RXD

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Rev. 0.31 21

pin also causes the Si2401 to exit the wakeup-on-ringstate. Return from wake-on-ring can also be set totrigger the INT pin by setting S08[6] (WORM) = 1b.

4.4.4. Alarm Industry AT Commands

The Si2401 supports a complete set of commandsnecessary for making connections in security industrysystems. The Si2401 is configurable in two modes forthese applications. The first mode uses DTMFmessaging and is selected with the “!1” command. Thesecond mode uses FSK transmit with a toneacknowledgement and is selected with “!2”.

The following are a few general comments about theuse of “!” commands. Specific details for each commandare given below. The first instance of the “!” must be onthe same line as the ATDT or ATDP command. DRTmust be set to data mode (SE4[5:4] (DRT) = 0b) beforeattempting to send tones after a “!” command. The threedata-mode escape sequences (“+++”, “escape” pin and“ninth-bit”) function in “!2” mode. However, using the“+++” or “ninth-bit” is not recommended becausecharacters could be sent to and misinterpreted by theremote modem. Only the “escape pin” (Si2401, pin 14)is recommended for use in the “!2” mode. The “!1” modehas a special escape provision described below. The ATcommands for Alarm Industry applications aredescribed in Table 8.

4.4.4.1. !1

Dial number and follow the DTMF security protocol.

The format for this command is as follows:

ATDT<phone number>!1<message 1><CR>

K

!<message 2><CR>

K

!<message 3><CR>

K

K

!<message n><CR>

The modem dials the phone number and echoes “r”(ring), “b” (busy), and “c” (connect) as appropriate. “c”echoes only after the Si2401 detects the HandshakeTone. After a 250 ms delay, the modem sends theDTMF tones containing the first message (messagemust contain digits 0–9, B–F only as shown in column 3of Table 11), then listens for a Kissoff Tone. If a KissoffTone shorter than or equal to the value stored inS36(KTL) (default = 480 ms) is detected, the Si2401echoes a “K”. A “k” is echoed if the length of the KissoffTone is longer than the S36(KTL) value. The controllercan then send the next message. All messages must bepreceded by a “!” and followed by a <CR> and receivedby the Si2401 within 250 ms after the “K” is echoed.Setting S0C[0] (MCH) = 1b causes a “.” to be echoedwhen the DTMF tone is turned on and a “/” character tobe echoed when the DTMF tone is turned off. This helpsthe host monitor the status of the message being sent.The previous message can be resent if the hostresponds with a “~” after the Si2401 echoes a “K”. Anycharacter other than a “!” or a “~” sent to the modemimmediately after the “K” causes the modem to escapeto the command mode and remain off-hook. Anycharacter except “!” and “~” sent during the transmissionof a message causes the message to be aborted andthe modem to return to the command mode.

If the Kissoff Tone is not received within 1.25 seconds,the modem echoes a “^”. A “~” from the host causes thelast message to be resent. Any character other than a“!” or a “~” sent to the modem immediately after the “^”causes the modem to escape to the command modeand remain off-hook.

4.4.4.2. !2

Dial the number and follow the “SIA Format” protocol forAlarm System Communications.

The modem dials the phone number and echoes “r”(ring), “b” (busy), and “c” (connect) as appropriate. “c”echoes only after the Si2401 detects the HandshakeTone and the speed synchronization signal is sent. Thesignaling is at 300 bps, half-duplex FSK. The host cansend the first SIA block after the “c” is received. Oncethe block is transmitted, the modem can monitor for theacknowledge tone by completing the followingsequence:

1. Place the Si2401 in the command mode by pulsing the ESCAPE pin (Si2401 pin 14). The “+++” and “ninth-bit” escape modes operate in the “!2” mode but are not recommended because they can send unwanted characters to the remote modem.

2. Issue the “ATX1” command to turn the modem transmitter off and begin monitoring for the acknowledgment tones.

Table 8. AT Command Set Extensionsfor the Alarm Industry

Command Function

!1 Dial and switch to DTMF security mode

!2 Dial and switch to “SIA Format”

X1 SIA half-duplex mode search

X2 SIA half-duplex return online as transmitter

X3 SIA half-duplex return online as receiver

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22 Rev. 0.31

3. Monitor for a positive (negative) acknowledgment “P” (“N”) after the tone has been detected for at least 400 ms.

4. The modem, still in command mode, can be placed online as a transmitter by issuing the “ATX2” command or a receiver by issuing the “ATX3” command. If tonal acknowledgement is not used, the host can toggle the ESCAPE pin to place the Si2401 in the command mode and issue an “ATX2” or an “ATX3” command to reverse data direction.

This sequence can be repeated for long messages.

4.4.5. Modem Result Codes and Call Progress

Table 9 shows the modem result codes that can beused in call progress monitoring. All result codes are asingle character to speed up communication and easehost processing.

4.4.5.1. Automatic Call Progress Detection

The Si2401 has the ability to detect dial, busy, andringback tones automatically. The following is adescription of the algorithms that have beenimplemented for these three tones.

Dial Tone. The dial tone detector looks for a dial tone after going off-hook and before dialing is initiated. This can be bypassed by enabling blind dialing (set S07[6] (BD) = 1b). After going off-hook, the Si2401 waits the number of seconds in S01 (DW) before searching for the dial tone. In order for a dial tone to be detected, it must be present for the length of time programmed in S1C (DTT). Once the dial tone is detected, dialing commences. If a dial tone is not detected within the time programmed in S02 (CW), the Si2401 hangs up and echoes an “n” to the user.

Busy/Ringback Tone. After dialing has completed, the Si2401 monitors for Busy/Ringback and modem answer tones. The busy and ringback tone detectors both use the call progress energy detector. The registers that set the cadence for busy and ringback are listed in Table 10.Si2401 register settings for global cadences for busy and ringback tones are listed in Table 22 on page 86.

Table 9. Modem Result Codes

Command Function

a British Telecom Caller ID Idle Tone Alert Detected

b Busy Tone Detected

c Connect

d Connect 1200 bps (when pro-grammed as V.22bis modem)

f Hookswitch Flash or Battery Reversal Detected

H Modem Automatically Hanging Up in !2, !1

I Intrusion Completed (parallel phone back on-hook)

i Intrusion Detected (parallel phone off-hook on the line)

K Kissoff Tone Detected

k Contact ID Kissoff Tone too long (!1)

L Phone Line Detected

l No Phone Line Detected

m Caller ID Mark Signal Detected

N No Carrier Detected

n No Dial tone (time-out set by CW [S02])

O Modem OK Response

R Incoming Ring Signal Detected

r Ringback Tone Detected

t Dial Tone

v Connect 75 bps TX (V.23 originate only)

x Overcurrent State Detected After an Off-Hook Event

^ Kissoff tone detection required

, Dialing Complete

Table 10. Busy and Ringback Cadence Registers

Register Name Function Units

S16 BTON Busy tone on time 10 ms

S17 BTOF Busy tone off time 10 ms

S18 BTOD Busy tone delta time 10 ms

S19 RTON Ringback tone on time 53.333 ms

S1A RTOF Ringback tone off time 53.333 ms

S1B RTOD Ringback tone delta time 53.333 ms

Table 9. Modem Result Codes (Continued)

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4.4.5.2. Manual Call Progress Detection

Because other call progress tones beyond thosedescribed above may exist, the Si2401 supports manualcall progress. This requires the host to read and writethe low-level DSP registers and may require realtimecontrol by the host. Manual call progress may berequired for detection of application-specific ringback,dial tone, and busy signals. The section on DSP low-level control should be read before attempting manualcall progress detection.

The call progress biquad filters can be programmed tohave a custom frequency response and detection level(as described in "S-Registers" on page 25).

Four dedicated user-defined frequency detectors canbe programmed to search for individual tones. The fourdetectors have center frequencies that can be set byregisters UDFD1–4 (see Table 15 on page 66).SE5[6] [TDET] [SE8 = 0x02] Read Only Definition canbe monitored, along with TONE, to detect energy atthese user-defined frequencies. The default trip-threshold for UDFD1–4 is –43 dBm but can be modifiedwith the DSP register, UDFSL.

By issuing the “ATDT;” command, the modem goes off-hook, checks for dial tone, and if it exists, returns tocommand mode. The blind dialing bit S07[6] can be setto suppress dial tone detection. The user can then putthe DSP into call progress monitoring by first settingSE8 = 0x02. Next, set SE5 (DSP2) = 0x00 so no tonesare transmitted, and set SE6 (DSP3) to the appropriatecode, depending on which types of tones are to bedetected.

The tone is detected while present. Use ATmE5 tocreate a stream of data to parse for the toneinformation.

At this point, users may program their own algorithm tomonitor the detected tones. If the host wishes to dial, itshould do so by blind dialing, setting the dial timeoutS01 (DW) to 0 seconds and issuing an“ATDT<Phone Number>;<CR>” command. Thisimmediately causes the ISOmodem chipset to dial andreturn to command mode.

Once the host has detected an answer tone usingmanual call progress, the host should immediatelyexecute the “ATDT” command in order to make aconnection. This causes the Si2401 to search for themodem answer tone and begin the correct connectsequence.

In manual call progress, the DSP can be programmedto detect specific tones. The result of the detection isreported in SE5 (SE8 = 0x2) as explained above. Theoutput is priority-encoded such that if multiple tones aredetected, the one with the highest priority whosedetection is also enabled is reported (see SE5 [SE8=02]Read Only.)

In manual call progress, the DSP can be programmedto generate specific tones (see SE5[2:0] (TONC)(SE8 = 02) Write Only). For example, settingSE5[2:0] (TONC) = 110b generates the user-definedtone (as indicated by UFRQ in Table 15 on page 66)with an amplitude of TGNL.

Table 11 shows the mappings of Si2401 DTMF values,keyboard equivalents, and the related dual tones.

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Table 11. DTMF Values

DTMFCode

Keyboard Equivalent

Contact ID

Digit

Tones

Low High

0 0 0 941 1336

1 1 1 697 1209

2 2 2 697 1336

3 3 3 697 1477

4 4 4 770 1209

5 5 5 770 1336

6 6 6 770 1477

7 7 7 852 1209

8 8 8 852 1336

9 9 9 852 1477

10 D – 941 1633

11 * B 941 1209

12 # C 941 1477

13 A D 697 1633

14 B E 770 1633

15 C F 852 1633

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4.5. S-RegistersAny register not documented here is reserved and should not be written. Bold selection in bit-mapped registersindicates default values.

Table 12. S-Register Summary

“S” Register

Register Address

(hex)

Name Function Reset

S00 0x00 NR Number of rings before answer; 0 suppresses auto answer. 0x00

S01 0x01 DW Number of seconds modem waits before dialing after going off-hook (maximum of 109 seconds).

0x02

S02 0x02 CW Number of seconds modem waits for a dial tone before hang-up added to time specified by DW (maximum of 109 seconds).

0x03

S03 0x03 CLW Duration that the modem waits (53.33 ms units) after loss ofcarrier before hanging up.

0x0E

S04 0x04 TD Both duration and spacing (5/3 ms units) of DTMF dialed tones. 0x30

S05 0x05 OFFPD Duration of off-hook time (5/3 ms units) for pulse dialing. 0x18

S06 0x06 ONPD Duration of on-hook time (5/3 ms units) for pulse dialing. 0x24

S07 0x07 MF1 This is a bit-mapped register.* 0x06

S08 0x08 INTM This is a bit-mapped register.* 0x00

S09 0x09 INTS This is a bit-mapped register.* 0x00

S0C 0x0C MF2 This is a bit-mapped register.* 0x00

S0D 0x0D MF3 This is a bit-mapped register.* 0x00

S0E 0x0E DIT Pulse dialing Interdigit time (10 ms units added to a minimum time of 64 ms).

0x46

S0F 0x0F TEC TIES escape character. Default = +. 0x2B

S10 0x10 TDT TIES delay time (53.33 ms units). 0x13

S11 0x11 OFHI This is a bit-mapped register.* 0x04

S12 0x12 ACL Absolute Current Level. When S13[4] (OFHD) = 0b, ACL represents the absolute current threshold used by the off-hook intrusion algorithm (1.1 mA units).

0x00

S13 0x13 MF4 This is a bit-mapped register.* 0x10

S15 0x15 MLC This is a bit-mapped register.* 0x04

S16 0x16 BTON Busy tone on. Time that the busy tone must be on (10 ms units) for busy tone detector.

0x32

S17 0x17 BTOF Busy tone off. Time that the busy tone must be off (10 ms units) for busy tone detector.

0x32

S18 0x18 BTOD Busy tone delta time (10 ms units). A busy tone is detected to be valid if (BTON – BTOD < on time < BTON + BTOD) and (BTOF – BTOD < off time < BTOF + BTOD).

0x0F

*Note: These registers are explained in detail in the following section.

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26 Rev. 0.31

S19 0x19 RTON Ringback tone on. Time that the ringback tone must be on (53.333 ms units) for ringback tone detector.

0x26

S1A 0x1A RTOF Ringback tone off. Time that the ringback tone must be off (53.333 ms units) for ringback tone detector.

0x4B

S1B 0x1B RTOD Detector time delta (53.333 ms units). A ringback tone is deter-mined to be valid if (RTON – RTOD < on time < RTON + RTOD) and (RTOF – RTOD < off time < RTOF + RTOD).

0x07

S1C 0x1C DTT Dial tone detect time. The time that the dial tone must be valid before being detected (10 ms units).

0x0A

S1E 0x1E TATL Transmit answer tone length. Answer tone length in seconds when answering a call (1 s units).

0x03

S1F 0x1F ARM3 Answer tone to transmit delay. Delay between answer tone end and transmit data start (5/3 ms units).

0x2D

S20 0x20 UNL Unscrambled ones length. Minimum length of time required for detection of unscrambled binary ones during V.22 handshaking by a calling modem (5/3 ms units).

0x5D

S21 0x21 TSOD Transmit scrambled ones delay. Time between unscrambled binary one detection and scrambled binary one transmission by a call mode V.22 modem (53.3 ms units).

0x09

S22 0x22 TSOL Transmit scrambled ones length. Length of time scrambled ones are sent by a call mode V.22 modem (5/3 ms units).

0xA2

S23 0x23 VDDL V.22X data delay low. Delay between handshake complete and data connection for a V.22X call mode modem (5/3 ms units added to the time specified by VDDH).

0xCB

S24 0x24 VDDH V.22X data delay high. Delay between handshake complete and data connection for a V.22X call mode modem (256 x 5/3 ms units added to the time specified by VDDL).

0x08

S25 0x25 SPTL S1 pattern time length. Amount of time the unscrambled S1 pat-tern is sent by a call mode V.22bis modem (5/3 ms units).

0x3C

S26 0x26 VTSO V.22bis 1200 bps scrambled ones length. Minimum length of time for transmission of 1200 bps scrambled binary ones by a call mode V.22bis modem after the end of pattern S1 detection (53.3 ms).

0x0C

S27 0x27 VTSOL V.22bis 2400 bps scrambled ones length low. Minimum length of time for transmission of 2400 bps scrambled binary ones by a call mode V.22bis modem (5/3 ms units).

0x78

S28 0x28 VTSOH V.22bis 2400 bps scrambled ones length high. Minimum length of time for transmission of 2400 bps scrambled binary ones by a call mode V.22bis modem (256 x 5/3 ms units added to the time specified by VTSOL).

0x08

Table 12. S-Register Summary (Continued)

“S” Register

Register Address

(hex)

Name Function Reset

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Rev. 0.31 27

S29 0x29 IS Intrusion suspend. When S82[2:1] (IB) = 10b, this register sets the length of time from when dialing begins that the off-hook intrusion algorithm is blocked (suspended) (500 ms units).

0x00

S2A 0x2A RSO Receive scrambled ones V.22bis (2400 bps) length.Minimum length of time required for detection of scrambled binary ones during V.22bis handshaking by the answering modem after S1 pattern conclusion (5/3 ms units).

0xD2

S2B 0x2B DTL V.23 direct turnaround carrier length. Minimum length of time that a master mode V.23 modem must detect carrier when searching for a direct turnaround sequence (5/3 ms units).

0x18

S2C 0x2C DTTO V.23 direct turnaround timeout. Length of time that the modem searches for a direct turnaround carrier (5/3 ms units added to a minimum time of 426.66 ms).

0x08

S2D 0x2D SDL V.23 slave carrier detect loss. Minimum length of time that a slave mode V.23 modem must lose carrier before searching for a reverse turnaround sequence (5/3 ms units).

0x0C

S2E 0x2E RTCT V.23 reverse turnaround carrier timeout. Amount of time a slave mode V.23 modem searches for carriers during potential reverse turnaround sequences (5/3 ms units).

0xF0

S2F 0x2F FCD FSK connection delay low. Amount of time delay added between end of answer tone handshake and actual modem connection for FSK modem connections (5/3 ms units).

0x3C

S30 0x30 FCDH FSK connection delay high. Amount of time delay added between end of answer tone handshake and actual modem con-nection for FSK modem connections (256 x 5/3 ms units).

0x00

S31 0x31 RATL Receive answer tone length. Minimum length of time required for detection of a CCITT answer tone (5/3 ms units).

0x3C

S32 0x32 OCDT The time after going off-hook when the loop current sense bits are checked for overcurrent status (5/3 ms units).

0x0C

S34 0x34 TASL Answer tone length when answering a call (5/3 ms units). This register is only used if TATL (1E) has a value of zero.

0x5A

S35 0x35 RSOL Receive scrambled ones V.22 length (5/3 ms units). Minimum length of time that an originating V.22 (1200 bps) modem must detect 1200 bps scrambled ones during a V.22 handshake.

0xA2

S36 0x36 ARM1 Second kissoff tone detector length. The security modes, A1 and !1, echo a “k” if a kissoff tone longer than the value stored in SKDTL is detected (10 ms units).

0x30

S37 0x37 CDR Carrier detect return. Minimum length of time that a carrier must return and be detected in order to be recognized after a carrier loss is detected (5/3 ms units).

0x20


“S” Register

Register Address

(hex)

Name Function Reset


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28 Rev. 0.31

S39 0x39 CDT Carrier detect timeout. Amount of time modem waits for carrier detect before aborting call (1 second units).

0x3C

S3A 0x3A ATD Delay between going off-hook and answer tone generation when in answer mode (53.33 ms units).

0x29

S3C 0x3C CIDG This is a bit mapped register.* 0x01

S62 0x62 RC This is a bit mapped register.* 0x41

S82 0x82 IST This is a bit mapped register.* 0x08

SAA 0xAA OPC Overload protect counter. Set SAA = 00 when used with ATH1. 0x04

SC0 0xC0 V80C This is a bit mapped register.* 0x00

SC1 0xC1 ITF1 Transmit flow control off threshold. Threshold, in bytes, above which the modem will generate a flow off signal (maximum threshold value of 20).

0x14

SC2 0xC2 ITF2 Transmit flow control on threshold. Threshold, in bytes, below which the modem will generate a flow on signal. This value must be less than ITF1.

0x04

SC3 0xC3 V80M This is a bit mapped register.* 0x00

SDB 0xDB LVS Line Voltage Status. Eight bit signed, 2s complement number representing the tip-ring voltage. Each bit represents 1 volt. Polarity of the voltage is represented by the MSB (sign bit).0000_0000 = Measured voltage is < 3 V.

SDF 0xDF DGSR This is a bit mapped register.* 0x0C

SE0 0xE0 CF1 This is a bit mapped register.* 0x22

SE1 0xE1 GPIO1 This is a bit mapped register.* 0x0E

SE2 0xE2 GPIO2 This is a bit mapped register.* 0x00

SE3 0xE3 GPD This is a bit mapped register.*

SE4 0xE4 CF5 This is a bit mapped register.* 0x00

SE5 0xE5 DADL (SE8 = 0x00) Write only definition. DSP register address lower bits [7:0].*

SE5 0xE5 DDL (SE8 = 0x01) Write only definition. DSP data word lower bits [7:0].*

SE5 0xE5 DSP1 (SE8 = 0x02) Read only definition. This is a bit mapped register.1

SE5 0xE5 DSP2 (SE8 = 0x02) Write only definition. This is a bit mapped register.1

SE6 0xE6 DADH (SE8 = 0x00) Write only definition. DSP register address upper bits [15:8].

SE6 0xE6 DDH (SE8 = 0x01) Write only definition. DSP data word upper bits [13:8]


“S” Register

Register Address

(hex)

Name Function Reset

AN94

Rev. 0.31 29

SE6 0xE6 DSP3 (SE8 = 0x02) Write only definition. This is a bit mapped register.1

SE8 0xE8 DSPR4 Set the mode to define E5 and E6 for low level DSP control.

SEB 0xEB TPD This is a bit mapped register.* 0x00

SEC 0xEC RV1 This is a bit mapped register.* 0x88

SED 0xED RV2 This is a bit mapped register.* 0x19

SEE 0xEE RV3 This is a bit mapped register.* 0x16

SF0 0xF0 DAA0 This is a bit mapped register.* 0x40

SF1 0xF1 DAA1 This is a bit mapped register.* 0x0C

SF2 0xF2 DAA2 This is a bit mapped register.*

SF3 0xF3 DAA3 Line Current Status. Eight-bit value returning the loop current. Each bit represents 1.1 mA of loop current.

0000_0000 = Loop current is less than required for normal oper-ation.

0x00

SF4 0xF4 DAA4 This is a bit mapped register.* 0x0F


SF6 0xF6 DAA6 This is a bit mapped register.* 0xF0


SF8 0xF8 DAA8 This is a bit mapped register.* —



“S” Register

Register Address

(hex)

Name Function Reset


AN94

30 Rev. 0.31

Table 13. Bit-Mapped Register Summary

“S” Register

Register Address

(hex)

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Binary

S07 0x07 MF1 BD V23R V23T BAUD CCITT FSK 0000_0110

S08 0x08 INTM CDM WORM PPDM NVDM RIM CIDM OCDM REVM 0000_0000

S09 0x09 INTS CD WOR PPD NVD RI CID OCD REV 0000_0000

S0C 0x0C MF2 CDE CIDM[1:0] 9BF BDL MLB 0000_0000

S0D 0x0D MF3 RI INTP RBTS EHR EHB EHI EHE 0000_0000

S11 0x11 OFHI DCL[3:0] 0000_0100

S13 0x13 MF3 BTID OFHD CIDB HDEN 0001_0000

S15 0x15 MLC ATPRE VCTE FHGE EHGE STB BDA[1:0] NBE 0000_0100

S3C 0x3C CIDG CIDG[2:0] 0000_0001

S62 0x62 RC OCR IR NLR RR 0100_0001

S82 0x82 IST IST[3:0] LCLD IB[1:0] 0000_1000

SC0 0xC0 V80C ITC[1:0] ESA1 ESA2 ESOM[1:0] ESAM[1:0] 0000_0000

SC3 0xC3 V80M TRANSP[1:0] 0000_0000

SDF 0xDF DGSR DGSR[6:0] 0000_1100

SE0 0xE0 CF1 ICTS ND SD[2:0] 0010_0010

SE1 0xE1 GPIO1 GPD5 GPIO5 0000_1110

SE2 0xE2 GPIO2 GPIO4[1:0] GPIO3[1:0] GPIO2[1:0] GPIO1[1:0] 0000_0000

SE3 0xE3 GPD GPD4 GPD3 GPD2 GPD1 0000_0000

SE4 0xE4 CF5 NBCK SBCK DRT GPE 0000_0000

SE5 0xE5 DSP1 DDAV TDET TONE[4:0] 0000_0000

SE5 0xE5 DSP2 DTM[3:0] TONC[2:0] 0000_0000

SE6 0xE6 DSP3 CPSQ CPCD USEN2 USEN1 V23E ANSE DTMFE 0000_0000

SEB 0xEB TPD PDDE 0000_0000

SEC 0xEC RVC1 RNGV RDLY[2:0] RCC[2:0] 1000_1000

SED 0xED RVC2 RAS[5:0] 0001_1001

SEE 0xEE RVC3 RTO[3:0] RMX[3:0] 0001_0110

SF0 0xF0 DAA0 FOH[1:0] LM[1:0] 0100_0000

SF1 0xF1 DAA1 BTE PDN PDL LVFD HBE 0000_1100

SF2 0xF2 DAA2 FDT 0000_1000

SF4 0xF4 DAA4 ARL[1:0] ATL[1:0] 0000_1111

SF5 0xF5 DAA5 OHS[1:0] ILIM RZ RT 0000_0000

SF6 0xF6 DAA6 MINI[1:0] DCV[1:0] ACT[3:0] 1111_0000

SF8 0xF8 DAA8 LRV[3:0] DCR —

SF9 0xF9 DAA9 BTD OVL ROV 0010_0000

SFC 0xFC DAAFC CTSM 0000_0000

AN94

Rev. 0.31 31

Reset settings = 0000_0110 (0x06)

S07 (MF1). Modem Functions 1

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name BD V23R V23T BAUD CCITT FSK

Type R/W R/W R/W R/W R/W R/W

Bit Name Function

7 Reserved Read returns zero.

6 BD Blind Dialing.

0 = Disable.1 = Enable (Blind dialing occurs immediately after “ATDT#” command).

5 V23R V.23 Receive.*

V.23 75 bps send/600 (BAUD = 0) or 1200 (BAUD = 1) bps receive.0 = Disable.1 = Enable.

4 V23T V.23 Transmit.*

V.23 600 (BAUD = 0) or 1200 (BAUD = 1) bps send/75 bps receive.0 = Disable.1 = Enable.


2 BAUD 2400/1200 Baud Select.*

2400/1200 baud select (V23R = 0 and V23T = 0).0 = 12001 = 2400600/1200 baud select (V23R = 1 and V23T = 1).0 = 6001 = 1200

1 CCITT CCITT/Bell Mode.*

0 = Bell.1 = CCITT.

0 FSK 300 bps FSK.*

0 = Disable.1 = Enable.

*Note: See Table 6 on page 16 for proper setting of modem protocols.

AN94

32 Rev. 0.31


S08 (INTM). Interrupt Mask


Name CDM WORM PPDM NVDM RIM CIDM OCDM REVM

Type R/W R/W R/W R/W R/W R/W R/W R/W

Bit Name Function

7 CDM Carrier Detect Mask.0 = Change in CD does not affect INT.1 = A high to low transition in CD (S09, bit 7), which indicates loss of carrier, activates INT.

6 WORM Wake-on-Ring Mask.0 = Change in CD does not affect INT.1 = A low to high transition in WOR (S09, bit 6) activatesINT.

5 PPDM Parallel Phone Detect Mask.0 = Change in PPD does not affect INT.1 = A low to high transition in PPD (S09, bit 5) activates INT.

4 NVDM No Phone Line Detect Mask.0 = Change in NLD does not affect INT.1 = A low to high transition in NLD (S09, bit 4) activates INT.

3 RIM Ring Indicator Mask.0 = Change in RI does not affect INT.1 = A low to high transition in RI (S09, bit 3) activates INT.

2 CIDM Caller ID Mask.0 = Change in CID does not affect INT.1 = A low to high transition in CID (S09, bit 2) activates INT.

1 OCDM Overcurrent Detect Mask.0 = Change in OCD does not affect INT.1 = A low to high transition in OCD (S09, bit 1) activates INT.

0 REVM V.23 Reversal Detect Mask.0 = Change in REV does not affect INT.1 = A low to high transition in REV (S09, bit 0) activates INT.

AN94

Rev. 0.31 33


S09 (INTS). Interrupt Status


Name CD WOR PPD NVD RI CID OCD REV

Type R/W R/W R/W R/W R/W R/W R/W R/W

Bit Name Function

7 CD Carrier Detect (sticky).Active high bit indicates carrier detected (equivalent to inverse of CD pin). Clears on :1 read.

6 WOR Wake-on-Ring (sticky).Wake-on-ring has occurred. Clears on :I read.

5 PPD Parallel Phone Detect (sticky).Parallel phone detected since last off-hook event. Clears on :I read.

4 NVD No Phone Line Detect (sticky).No line phone detected. Clears on :I read.

3 RI Ring Indicator (sticky).Active high bit when the Si2403 is on-hook, indicates ring event has occurred. Clears on :I read.

2 CID Caller ID (sticky).Caller ID preamble has been detected; data soon follows. Clears on :I read.

1 OCD Overcurrent Detect (sticky).Overcurrent condition has occurred. Clears on :I read.

0 REV V.23 Reversal Detect (sticky).V.23 reversal condition has occurred. Clears on :I read.

AN94

34 Rev. 0.31


S0C (MF2). Modem Functions 2


Name CDE CIDM[1:0] 9BF BDL MLB

Type R/W R/W R/W R/W R/W

Bit Name Function

7 CDE Carrier Detect Enable.

0 = Disable.1 = Enable GPI02 as an active low carrier detect pin (must also set SE2[3:2] [GPIO2] = 01).

6:5 CIDM[1:0] Caller ID Monitor.

00 = Caller ID monitor disabled.01 = Caller ID monitor enabled. Si2401 must detect channel seizure signal followed by marks in order to report caller ID data. (Normal Bellcore caller ID)10 = Reserved.11 = Caller ID monitor enabled. Si2401 must only detect marks in order to report caller ID data.


3 9BF Ninth Bit Function.

Only valid if the ninth bit escape is set S15[0] (NBE).0 = Ninth bit equivalent to ALERT.1 = Ninth bit equivalent to HDLC EOFR.

2 BDL Blind Dialing.

0 = Blind dialing disabled.1 = Enables blind dialing after dial timeout register S02 (CW) expires.

1 MLB Modem Loopback.

0 = Not swapped.1 = Swaps frequency bands in modem algorithm to do a loopback in a test mode.


AN94

Rev. 0.31 35


SOD (MF3). Modem Functions 3


Name RI INTP RBTS EHR EHB EHI EHE

Type R/W R/W R/W R/W R/W R/W R/W

Bit Name Function


6 RI Ring Indicator.

Specifies the functionality of pin3.0 = Pin 3 functions as GPIO5 controlled by register SE1.1 = Pin 3 functions as RI. RI asserts during a ring and negates when no ring is present.

5 INTP INT Polarity.

Specifies the polarity of the INT function on pin 11.0 = An interrupt forces pin 11 low.1 = An interrupt forces pin 11 high.

4 RBTS Ringback Tone Selector.

Controls the unit step size for registers S19, S1A and S1B.0 = 53.33 ms units. Necessary for detecting a ringback tone.1 = 10 ms units. Necessary for detecting a reorder tone.

3 EHR Enable Hangup on Reorder.

Modem is placed on-hook if a ringback or reorder tone is detected. See S0D[4].0 = Disable.1 = Enable.

2 EHB Enable Hangup on Busy.

Modem is placed on-hook if a busy signal is detected.0 = Disable.1 = Enable.

1 EHI Enable Hangup on Intrusion.

Modem is placed on-hook if parallel intrusion is detected.0 = Disable.1 = Enable.

0 EHE Enable Hangup on Escape.

Modem is placed on-hook if a ESC signal is detected.0 = Disable.1 = Enable.

AN94

36 Rev. 0.31



S11 (OFHI). Off-Hook Intrusion


Name DCL[3:0]

Type R/W

Bit Name Function

7:4 Reserved Read returns zero.

3:0 DCL[3:0] Differential Current Level.

Differential current level to detect intrusion event (1 mA units).

S13 (MF3). Modem Function 3


Name BTID OFHD CIDB HDEN


Bit Name Function


6 BTID BT Caller ID Wetting Pulse.

0 = Enable.1 = Disable.


4 OFHD Off-Hook Intrusion Detect Method.

0 = Absolute.1 = Differential.


2 CIDB British Telecom Caller ID Decode.

0 = Disable.1 = Enable.When set, SOC[6:5] is overwritten by the modem, as needed.

1 HDEN HDLC Framing.



AN94

Rev. 0.31 37


S15 (MLC). Modem Link Control


Name ATPRE VCTE FHGE EHGE STB BDA[1:0] NBE

Type R/W R/W R/W R/W R/W R/W R/W

Bit Name Function

7 ATPRE Answer Tone Phase Reversal.

0 = Disable.1 = Enable answer tone phase reversal.

6 VCTE V.25 Calling Tone.

0 = Disable.1 = Enable V.25 calling tone.

5 FHGE 550 Hz Guardtone.

0 = Disable.1 = Enable 550 Hz guardtone.

4 EHGE 1800 Hz Guardtone.

0 = Disable.1 = Enable 1800 Hz guardtone.

3 STB Stop Bits.

0 = 1 stop bit.1 = 2 stop bits.

2:1 BDA[1:0] Bit Data.

00 = 6 bit data.01 = 7 bit data.10 = 8 bit data.11 = 9 bit data.

0 NBE Ninth Bit Enable.

0 = Disable.1 = Enable ninth bit as Escape and ninth bit function (register C).

AN94

38 Rev. 0.31


S3C (CIDG). Caller ID Gain


Name CIDG[2:0]

Type R/W

Bit Name Function

7:3 Reserved Read returns 0.

2:0 CIDG[2:0] Caller ID Gain.

The Si2400 dynamically sets the On-Hook Analog Receive Gain SF4[6:4] (ARG) to CIDG during a caller ID event (or continuously if S0C[6:5] (CIDM = 11b). This field should be set prior to caller ID operation.000 = 0 dB001 = 3 dB010 = 6 dB011 = 9 dB100 = 12 dB

AN94

Rev. 0.31 39


S62 (RC). Result Codes Override


Name OCR IR NLR RR

Type R/W R/W R/W R/W

Bit Name Function


6 OCR Overcurrent Result Code (“x”).

0 = Enable.1 = Disable.


2 IR Intrusion Result Code (“I” and “i”).


1 NLR No Phone Line Result Code (“L” and “l”).


0 RR Ring Result Code (“R”).


AN94

40 Rev. 0.31


S82 (IST). Intrusion


Name IST[3:0] LCLD IB[1:0]

Type R/W R/W R/W

Bit Name Function

7:4 IST[3:0] Intrusion Settling Time.

0000 = IST equals 1 second.Delay between when the ISOmodem chipset goes off-hook and the off-hook intrusion algorithm begins (250 ms units).

3 LCLD Loop Current Loss Detect.

0 = Disable.1 = Enables the reporting of “I” and “L” result codes while off-hook. Asserts INT if GPIO4 (SE2[7:6]) is enabled as INT.

2:1 IB[1:0] Intrusion Blocking.

This feature only works when SDF 0x00. Defines the method used to block the off-hook intrusion algorithm from operating after dialing has begun.00 = No intrusion blocking.01 = Intrusion disabled from start of dial to end of dial.10 = Intrusion disabled from start of dial to register S29 time out.11 = Intrusion disabled from start of dial to carrier detect or to “N” or “n” result code.


AN94

Rev. 0.31 41


SC0 (V80C). V80 Commands


Name ITC[1:0] ESA1 ESA2 ESOM[1:0] ESAM[1:0]


Bit Name Function

7:6 ITC[1:0] Transmit Flow Control.

Specifies the flow control to be implemented.00 = No flow control/CTS only*01 = Partial XON/XOFF flow control (modem -> host only)10 = Hardware flow control (CTS and RTS*)01 = Full XON/XOFF flow control

5 ESA1 Synchronous Access Mode control parameter 1.

Specifies the actions taken if a transmit data buffer underrun or overrun condition occurs immediately after a non-flag octet, while operating in framed sub-mode.0 = In framed sub-mode, abort on underrun in middle of frame1 = In framed sub-mode, transmit a flag on underrun in middle of frame and notify host of underrun or overrun

4 ESA2 Synchronous Access Mode control parameter 2.

Specifies the CRC polynomial used while operating in framed sub-mode.0 = CRC generation and checking disable1 = In framed sub-mode, a 16-bit CRC is generated by the modem in the transmit direc-tion and checked by the DCE in the receive direction

3:2 ESOM[1:0] Enable Synchronous Originate Mode.

00 = Direct01 = Initiate synchronous access mode when connection is completed and data state is entered (See Table 1 on page 4 for the V.80 commands supported)10 = Reserved11 = Reserved

1:0 ESAM[1:0] Enable Synchronous Answer Mode.

00 = Direct01 = Initiate synchronous access mode when connection is completed and data state is entered (See Table 1 on page 4 for the V.80 commands supported)10 = Reserved11 = Reserved

*Note: CTS can be ignored, thereby implementing ‘no flow control’; GPIO1 is used as RTS.

AN94

42 Rev. 0.31


Reset settings = 0000_1100 (0x0C)

SC3 (V80M). V80 Options


Name TRANSP[1:0]

Type R/W

Bit Name Function


0 TRANSP[1:0] Chooses which Submode is entered upon connection.

0 = Framed submode1 = Transparent submode

SDF (DGSR). Intrusion Deglitch


Name DGSR[6:0]

Type R/W

Bit Name Function


6:0 DGSR[6:0] Deglitch Sample Rate.

Sets the sample rate for the deglitch algorithm and the off-hook intrusion algorithm (40 ms units).0000000 = Disables the deglitch algorithm, and sets the off-hook intrusion sample rate to 200 ms and delay between compared samples to 800 ms.

AN94

Rev. 0.31 43


SE0 (CF1). Chip Functions 1


Name ICTS ND SD[2:0]

Type R/W R/W R/W

Bit Name Function


5 ITCS Invert CTS Pin.

0 = Inverted (CTS).1 = Normal (CTS).


3 ND 0 = 8N1.1 = 9N1 (hardware UART only).

2:0 SD[2:0] Serial Dividers.

000 = 300 bps serial link.001 = 1200 bps serial link.010 = 2400 bps serial link.011 = 9600 bps serial link.100 = 19200 bps serial link.101 = 38400 bps serial link110 = 115200 bps serial link.111 = 307200 bps serial link.

AN94

44 Rev. 0.31

Reset settings = 0000_1110 (0x0E)


SE1 (GPIO1). General Purpose Input/Output 1


Name GPD5 GPIO5

Type R/W R/W

Bit Name Function


1 GPD5 GPIO5 Data.Data = 0.Data = 1.

0 GPIO5 GPIO5.0 = Digital input.1 = Digital output (relay drive).

SE2 (GPIO2). General Purpose Input/Output 2


Name GPIO4[1:0] GPIO3[1:0] GPIO2[1:0] GPIO1[1:0]


Bit Name Function

7:6 GPIO4[1:0] GPIO4.

00 = Digital input.01 = Digital output (relay drive).10 = AOUT.11 = INT function defined by S08.

5:4 GPIO3[1:0] GPIO3.

00 = Digital input.01 = Digital output (relay drive).10 = Reserved.11 = ESC function (digital input).

3:2 GPIO2[1:0] GPIO2.

00 = Digital input.01 = Digital output (relay drive; also used for CD function).10 = Reserved.11 = Digital input.

1:0 GPIO1[1:0] GPIO1*.

00 = Digital input.01 = Digital output (relay drive).10 = Reserved.11 = Reserved.

*Note: To be used as a GPIO pin; SE4[3] (GPE) must equal zero.

AN94

Rev. 0.31 45



SE3 (GPD). GPIO Data


Name GPD4 GPD3 GPD2 GPD1


Bit Name Function


3 GPD4 GPIO4 Data.

Data = 0Data = 1

2 GPD3 GPIO3 Data.

Data = 0Data = 1

1 GPD2 GPIO2 Data. Data = 0Data = 1

0 GPD1 GPIO1 Data.

Data = 0Data = 1

SE4 (CF5). Chip Functions 5


Name NBCK SBCK DRT GPE

Type R R R/W R/W

Bit Name Function

7 NBCK 9600 Baud Clock (Read Only).

6 SBCK 600 Baud Clock (Read Only).

5 DRT Data Routing.

0 = Data mode, DSP output transmitted to line, line received by DSP input.1 = Loopback mode, TXD through microcontroller (DSP) to RXD. AIN looped to AOUT.


3 GPE GPIO1 Enable.

0 = Disable.1 = Enable GPIO1 to be HDLC end-of-frame flag.


AN94

46 Rev. 0.31


SE5 (DSP1). (SE8 = 0x02) Read Only Definition


Name DDAV TDET TONE[4:0]

Type R R R

Bit Name Function

7 DDAV DSP Data Available.

6 TDET Tone Detected.

Indicates a TONE (any of type 0–25 below) has been detected.0 = Not detected.1 = Detected.


4:0 TONE[4:0] Tone Type Detected.

When TDET goes high, TONE indicates which tone has been detected from the following:TONE Tone Type Priority00000–01111 DTMF 0–15 (DTMFE = 1)1 See Table 11 on page 24. 110000 Answer tone detected 2100 Hz (ANSE = 1)2 210001 Bell 103 answer tone detected 2225 Hz (ANSE = 1) 210010 V.23 forward channel mark 1300 Hz (V23E = 1)3 310011 V.23 backward channel mark 390 Hz (V23E = 1) 310100 User defined frequency 1 (USEN1 = 1)4 410101 User defined frequency 2 (USEN1 = 1) 410110 Call progress filter A detected 610111 User defined frequency 3 (USEN2 = 1)5 511000 User defined frequency 4 (USEN2 = 1) 511001 Call progress filter B detected 6

Notes:1. SE6[0] (DTMFE) SE8 = 0x02.2. SE6[1] (ANSE) SE8 = 0x02.3. SE6[2] (V23E) SE8 = 0x02.4. SE6[3] (USEN1) SE8 = 0x02.5. SE6[4] (USEN2) SE8 = 0x02.

AN94

Rev. 0.31 47


SE5 (DSP2). (SE8 = 0x02) Write Only Definition


Name DTM[3:0] TONC[2:0]

Type W W

Bit Name Function

7 Reserved Always write zero.

6:3 DTM[3:0] Tone Type Generated.DTMF tone (0–15) to transmit when selected by TONC = 001. See Table 11 on page 24.

2:0 TONC[2:0] DTMF Tone Selector.

ToneTone Type

000 Mute 001 DTMF010 2225 Hz Bell mode answer tone with phase reversal 011 2100 Hz CCITT mode answer tone with phase reversal100 2225 Hz Bell mode answer tone without phase reversal 101 2100 Hz CCITT mode answer tone without phase reversal 110 User-defined programmable frequency tone (UFRQ)

(see Table 15 on page 66, default = 1700 Hz) 111 1300 Hz V.25 calling tone

AN94

48 Rev. 0.31


SE6 (DSP3). (SE8 = 0x02) Write Only Definition


Name CPSQ CPCD USEN2 USEN1 V23E ANSE DTMFE

Type W W W W W W W

Bit Name Function

7 CPSQ Call Progress Squaring Filter.0 = Disable.1 = Enables a squaring function on the output of filter B before the input to A (cascade only).

6 CPCD Call Progress Cascade Disable.0 = Call progress filter B output is input into call progress filter A. Output from fil-ter A is used in the detector.1 = Cascade disabled. Two independent fourth order filters available (A and B). The largest output of the two is used in the detector.

5 Reserved

4 USEN2 User Tone Reporting Enable 2.0 = Disable.1 = Enable the reporting of user defined frequency tones 3 and 4 through TONE.

3 USEN1 User Tone Reporting Enable 1.0 = Disable.1 = Enable the reporting of user defined frequency tones 1 and 2.

2 V23E V.23 Tone Reporting Enable.0 = Disable.1 = Enable the reporting of V.23 tones, 390 Hz and 1300 Hz.

1 ANSE Answering Tone Reporting Enable.0 = Disable.1 = Enable the reporting of answer tones.

0 DTMFE DTMF Tone Reporting Enable.0 = Disable.1 = Enable the reporting of DTMF tones.

AN94

Rev. 0.31 49


SEB (TPD). Timer and Powerdown


Name PDDE

Type R/W

Bit Name Function


3 PDDE Powerdown DSP Engine.

0 = Power on.1 = Powerdown.


AN94

50 Rev. 0.31


SEC (RVC1). Ring Validation Control 1


Name RNGV RDLY[2:0] RCC[2:0]

Type R/W R/W R/W

Bit Name Function

7 RNGV Ring Validation Enable.

0 = Ring validation feature is disabled.1 = Ring validation feature is enabled in both normal operating mode and low-power mode.

6:4 RDLY[2:0] Ring Delay.These bits set the amount of time between when a ring signal is validated and when a valid ring signal is indicated. RDLY[2:0] Delay000 0 ms001 256 ms010 512 ms...111 1792 ms

3:1 RCC[2:0] Ring Confirmation Count.

These bits set the amount of time that the ring frequency must be within the tolerances set by the RAS[5:0] bits and the RMX[3:0] bits to be classified as a valid ring signal.RCC[2:0] Ring Confirmation Count Time000 100 ms001 150 ms010 200 ms011 256 ms100 384 ms101 512 ms110 640 ms111 1024 ms

0 Reserved This bit must always be written to zero.

AN94

Rev. 0.31 51


SED (RVC2). Ring Validation Control 2


Name RAS[5:0]

Type R/W

Bit Name Function


5:0 RAS[5:0] Ring Assertion Time.These bits set the minimum ring frequency for a valid ring signal. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a regular rate. If a second or subsequent TIP/RING event occurs after the timer has timed out, the frequency of the ring is too low, and the ring is invalidated. The difference between RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qual-ify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every 1/(2 x 20 Hz) = 25 ms. To calculate the correct RAS[5:0] value for a frequency range [f_min, f_max], the following equation should be used: RAS[5:0] = 1 / (2 x f_min).

AN94

52 Rev. 0.31


SEE (RVC3). Ring Validation Control 3


Name RTO[3:0] RMX[3:0]

Type R/W R/W

Bit Name Function

7:4 RTO[3:0] Ring Timeout.

These bits set when a ring signal is determined to be over after the most recent ring threshold crossing.RTO[3:0] Ring Timeout0000 80 ms0001 128 ms0010 256 ms...1111 1920 ms

3:0 RMX[3:0] Ring Assertion Maximum Count.These bits set the maximum ring frequency for a valid ring signal. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a reg-ular rate. When a subsequent TIP/RING event occurs, the timer value is compared to the RMX[3:0] field, and if it exceeds the value in RMX[3:0], the frequency of the ring is too high, and the ring is invalidated. The difference between RAS[5:0] and RMX[3:0] identifies the minimum duration between TIP/RING events to qualify as a ring, in binary-coded incre-ments of 2.0 ms (nominal). A TIP/RING event typically occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every 1/(2 x 20 Hz) = 25 ms. To calculate the cor-rect RMX[3:0] value for a frequency range [f_min, f_max], the following equation should be used: RMX[3:0] x 2 ms = RAS[5:0] – 2 ms – (1/(2 x f_max)).

AN94

Rev. 0.31 53


SF0 (DAA0). DAA Low Level Functions 0


Name FOH[1:0] LM[1:0]

Type R/W R/W R/W

Bit Name Function

7:6 FOH[1:0] Fast Off-Hook Selection.

These bits determine the length of the off-hook counter. The default setting is 128 ms.00 = 512 ms01 = 128 ms10 = 64 ms11 = 8 ms


1:0 LM[1:0] Line Mode.

These bits determine the line status of the Si2401.* 00 = On-hook01 = Off-hook10 = On-hook line monitor mode11 = Reserved

*Note: Under normal operation, the Si2401 internal microcontroller automatically sets these bits appropriately.

AN94

54 Rev. 0.31

Reset settings = 0000_1100 (0x0C)



Name BTE PDN PDL LVFD HBE


Bit Name Function

7 BTE Billing Tone Enable.

When the line-side device detects a billing tone, SF9[3] (BTD) is set.0 = Disable.1 = Enable.

6 PDN Powerdown.

0 = Normal operation.1 = Powers down the Si2401.

5 PDL Powerdown Line-Side Chip (typically only used for board level debug.)

0 = Normal operation. Program the clock generator before clearing this bit.1 = Places the line-side device in lower power mode.

4 LVFD Line Voltage Force Disable.0 = Normal operation.1 = The circuitry that forces the LVS register to all 0s at 3 V or less is disabled. This reg-ister may display unpredictable values at voltages between 0 to 2 V. All 0s are displayed if the line voltage is 0 V.

3 Reserved Do not modify.

2 HBE Hybrid Transmit Path Connect.


1:0 Reserved Do not modify.

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Rev. 0.31 55


Reset settings = 0000_1111 (0x0F)



Name FDT

Type R

Bit Name Function

7:4 Reserved Read only.

3 FDT Frame Detect (Typically only used for board-level debug).

1 = Indicates frame lock has been established.0 = Indicates frame lock has not been established.

2:0 Reserved Reserved



Name ARL[1:0] ATL[1:0]

Type R/W R/W

Bit Name Function


3:2 ARL[1:0] AOUT Receive—Path Level.

DAA receive path signal AOUT gain.00 = 0 dB01 = –6 dB10 = –12 dB11 = Mute

1:0 ATL[1:0] AOUT Transmit—Path Level.

DAA transmit path signal AOUT gain.00 = –18 dB01 = –24 dB10 = –30 dB11 = Mute

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56 Rev. 0.31




Name OHS[1:0] ILIM RZ RT


Bit Name Function


5:4 OHS[1:0] On-Hook Speed.

These bits set the amount of time for the line-side device to go on-hook. The on-hook speeds specified are measured from the time the register is written until loop current equals zero.OHS[1:0] Mean On-Hook Speed

00 Less than 0.5 ms01 3 ms ±10% (Meets ETSI standard)1X 20 ms ±10% (Meets Australian spark quenching spec)

3 ILIM Current Limiting Enable.0 = Current limiting mode disabled.1 = Current limiting mode enabled. This mode limits loop current to a maximum of 60 mA per the TBR-21 standard.

2 RZ Ringer Impedance.

0 = Maximum (high) ringer impedance.1 = Synthesized ringer impedance used to satisfy a maximum ringer impedance specifi-cation in countries, such as Poland, South Africa, and Slovenia.


0 RT Ringer Threshold Select.Used to satisfy country requirements on ring detection. Signals below the lower level do not generate a ring detection; Signals above the upper level are guaranteed to generated a ring detection.0 = 13.5 to 16.5 VRMS1 = 19.35 to 23.65 VRMS

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Rev. 0.31 57

Reset settings = 1111_0000 (0xF0)



Name MINI[1:0] DCV[1:0] ACT[3:0]

Type R/W R/W R/W

Bit Name Function

7:6 MINI[1:0] Minimum Operational Loop Current.Adjusts the minimum loop current at which the DAA can operate. Increasing the mini-mum operational loop current can improve signal headroom at a lower TIP/RING volt-age.MINI[1:0] Min Loop Current

00 10 mA01 12 mA10 14 mA11 16 mA

5:4 DCV[1:0] TIP/RING Voltage Adjust.These bits adjust the voltage on the DCT pin of the line-side device, which affects the TIP/RING voltage on the line. Low voltage countries should use a lower TIP/RING volt-age. Raising the TIP/RING voltage can improve signal headroom.DCV[1:0] DCT Pin Voltage

00 3.1 V01 3.2 V10 3.35 V11 3.5 V

3:0 ACT[3:0] AC Termination Select.ACT[3:0] AC Termination

0000 Real 600 termination that satisfies the impedance requirements of FCC part 68, JATE, and other countries.

0011 Global complex impedance. Complex impedance that satisfies global impedance requirements EXCEPT New Zealand. May achieve higher return loss for countries requiring complex ac termination.[220 + (820 || 120 nF) and 220 + (820 || 115 nF)].

0100 Complex impedance for use in New Zealand.[370 + (620 || 310 nF)]

1111 Complex impedance that satisfies global impedance requirements.

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58 Rev. 0.31

Reset settings vary with line-side vision.




Name LRV[3:0] DCR

Type R R/W

Bit Name Function

7:4 LRV[3:0] Line-Side Device Revision Number.

0011 = Si3010 Rev C0100 = Si3010 Rev D0101 = Si3010 Rev E0110 = Si3010 Rev F

3:2 Reserved Read returns an indeterministic value.

1 DCR DC Impedance Selection.0 = 50 dc termination is selected. This mode should be used for all standard applications.1 = 800 dc termination is selected.


SF9 (DAA9). DAA Low Level Functions 9 Read Only


Name BTD OVL ROV

Type R/W R R/W

Bit Name Function

7:4 Reserved Do not modify.

3 BTD Billing Tone Detect (sticky).

0 = No billing tone detected.1 = Billing tone detected.

2 OVL Receive overload. Same as ROV, except not sticky.

1 ROV Receive Overload (sticky).

0 = No excessive level detected.1 = Excessive input level detected.


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Rev. 0.31 59


SFC (DAAFC). DAA Low Level Functions


Name CTSM

Type R/W

Bit Name Function

7 CTSM Clear-to-Send (CTS) Mode.

0 = CTS pin is negated as soon as a start bit is detected and reasserted when the transmit FIFO is empty.1 = CTS pin is negated when the FIFO is > 70% full and reasserted when the FIFO is < 30% full.

6:0 Reserved Read value indeterminate.

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60 Rev. 0.31

4.6. Fast ConnectIn modem applications that require fast connectiontimes, it is possible to reduce the length of thehandshake.

Additional modem handshaking control can be adjustedthrough the registers shown in Table 15. These

registers are most useful if the user has control of boththe originating and answering modems.

When the fast connect settings are used, there may beunintended data received initially.The host must toleratethese bytes. Figures 10, 14, 15 and illustrate theconnect sequence for V.22 and V.22b.

4.6.1. Internal Connect Sequence

V.22 and Bell212 modes use the same state machines.They do not deviate much. Assuming NAT = 0...

After dialing, these are the events that occur, assumingthat S07=02

Check answer tone length for S31 time units(Checking of answer tone is totally skipped ifS31=0)

Wait until the end of answer tone

Wait an additional S1F time units

Begin detection of unscrambled ones pattern (S20time units minimum)

If successful,

Wait S21 time units

Transmit scrambled ones for S22 time units

Transmit scrambled ones while detectingscrambled ones (S35 time units minimum)

If successful,

Transmit scrambled ones for S23+S24 time units

send 'c' result code

data connection (includes HDLC handling)

For S07=00, these are the events that occur:


Wait S1F time units then


Begin detection of unscrambled ones pattern (S20time units minimum)

If successful,

Wait S21 time units

Transmit scrambled ones for S22 time units

Transmit scrambled ones while detectingscrambled ones (S35 time units minimum)

If successful,

Transmit scrambled ones for S23+S24 time units



For S07=01, Bell103, these are the events that occur:


Wait S1F time units then


Begin transmitting mark

Table 14. V.22/Bell212 Handshaking Control Registers

Register Name Function Units Default Fast Connect

S1E TATL Transmit Answer Tone Length 1 s 0x03 00

S1F ATTD Answer Tone to Transmit Delay 5/3 ms 0x2D 00

S20 UNL Unscrambled Ones Length—V.22 5/3 ms 0x5D 00

S21 TSOD Transmit Scrambled Ones Delay—V.22 53.3 ms 0x09 00

S22 TSOL Transmit Scrambled Ones Length—V.22 5/3 ms 0xA2 00

S23 VDDL V.22/22b Data Delay Low 5/3 ms 0xCB 00

S24 VDDH V.22/22b Data Delay High (256) 5/3 ms 0x08 00

S34 TASL Answer Tone Length(only used in S1E[TATL] = 0x00)

5/3 ms 0x5A F0

S35 RSOL Receive V.22 Scrambled Ones Length 5/3 ms 0xA2 00

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Rev. 0.31 61

Wait S2F+S30 time units



Assuming that the NAT bit is set...

Case #1:If the answer tone length is non-zero.

The modem will need to detect a "short answer tone".

"Short" being defined as detection of one singleinstance of an answer tone.

Once the "short answer tone" is detected, the Si2400goes directly into the S1F delay loop.

Case #2: If the answer tone length is zero

NAT bit is a don't care.

Figure 10. V.22

Originate

Transmitter

Receiver

Scrambled binary 1 @ 1200 bps Data

S21

480 ms

S22

270 ms

S23 + S24

765 ± 10 ms3752 ms

S31

100 ms

S1FS20

155 ms

Detect unscrambledbinary ‘1’s

S35

270 ± 40 ms270 ms


S3A

2.187s

S20

155 ms

Unscrambled binary 1 @ 1200 bpsAns tone

Answer

S1E

3s75 ms

Tx

Rx

B212

Look for end of ans tonefor bell 212A wait only S1F time

S22

270 ± 40 ms

S23 + S24

765 ± 10 ms3752 ms

Detect scrambledbinary ‘1’s

B212

S1F

S1F

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62 Rev. 0.31

Figure 11. V.22 (NAT)

Figure 12. V.22bis

Originate

Transmitter

Receiver


S21

480 ms

S22

270 ms

S23 + S24

765 ± 10 ms3752 ms

S35

270 ± 40 ms270 ms


S3A

2.187s

S1F S20

155 ms


Answer

S1E

3s75 ms

Tx

RxS22

270 ± 40 ms

S23 + S24

765 ± 10 ms3752 ms

Detect scrambledbinary ‘1’s

Originate

Transmitter

Receiver

Scrambled binary 1 @ 1200 bpsScrambled

1s 2400 bpsS1Data

squelch Data

S21

456 ± 10480 ms

S25

100 ± 3100 ms

S26

600 ± 10640 ms

S27

200 ± 10200 ms

S28

No spec3413 ms

S31

?100 ms

S1FS20

155 ± 10155 ms

Detect unscrambledbinary ‘1’s

S35

270 ±40 ms

Direct SIor 270 ms

of scr.16.3.1.1.1.c

450 ± 10 msReceive @ 1200

450 ms

Detect 32 bits@ 2400

Equalizer enabled

Receive @ 2400

Scrambled binary 1 @ 1200 bpsScrambled

1s 2400 bpsS1Data

squelch Data

S25

100 ± 3100 ms

600 ± 10

S27

200 ± 10200 ms

S28

No spec3413 ms

S3A

215 ±.35s

2.187s

S20

155 ms

450 ± 10 msReceive @ 1200

Detect 32 bits@ 2400

Equalizer enabled

Receive @ 2400


Answer

S1E

3300 ± 7003s 75 ±

2075 ms 350 ms

52AWe align this andignore the 600Detect

S1

If S22 time of scrambled 1sdetected, use V.22

Tx

Rx

S1F

S1F

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Rev. 0.31 63

Figure 13. V.22bis

1200bps (1300 Hz)Si2401

Transmit

Si2401Receive

75bps (390 Hz)

75bps (390Hz)

S2D S2E

1200bps (1300 Hz)

S2B

CarrierDetect

‘v’Si2401TX pin

ALERTpin

1200bps (1300 Hz)Si2401

Transmit

Si2401Receive

75bps (390 Hz)

75bps (390 Hz)

S2D S2E

CarrierDetect

‘c’Si2401TX pin

ALERTpin

S2E

75bps (390 Hz)

S2B

Si2401 V.23 Reversal Behavior

1200 Hz

S2B

1200bps (1300 Hz)

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64 Rev. 0.31

4.6.2. Overall Protocol Supported by the Si2401 Fast Connect Sequence

Si2401 Originate Modem Answer Modem

Host initializes Modem (Note 1)

Host sends ATDT command (Note 2)

Modem Goes Off Hook, Dial.

Go Off Hook in response to Incoming Ring.

Wait for billing delay.

Begin Answer Tone for at least 100 ms up to 2.3 s.

Modem Detects Answer Tone for 100 ms

Modem sends 'c' to Host

Host must not transmit/receive for 300 ms to allow send-ing of Scrambled 1s or (HDLC Sync) to answering modem. Garbage data received during this time must be discarded.

Detect Scrambled 1s (or HDLC Sync) for 100 ms. Stop Answer Tone then send Scrambled 1s (or HDLC Sync) for 100 ms. Enter Data Mode, begin Receive and Transmit.

Once 300 ms has elapsed, begin data receive/transmit.

Notes:1. Register Initialization

ATS07=00 Bell212 mode, (if HDLC, use ATS07=80)ATS31=3 receive answer tone length = 100 msATS1F=00 transmit delay from answer tone end = 0ATS20=00 detection of unscrambled ones minimum time = 0ATS21=00 scrambled ones transmit delay = 0ATS22=00 scrambled ones transmit duration = 0ATS35=00 receive scrambled ones minimum duration = 0ATS23=00 V22 data delay lower byteATS24=00 V22 data delay upper byte

2. Dialing Procedure This sequence must be used instead of ATDT####<cr>, after the registers above have been initialized.ATDT####<cr> Originate CallWait for 'c'Wait an additional 300 ms to provide answering modem time to detect the scrambled 1s (or HDLC sync)

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Rev. 0.31 65

4.7. Low Level DSP ControlAlthough not necessary for most applications, the DSPlow-level control functions are available for users withvery specific applications requiring direct DSP control.

4.7.1. DSP Registers

Several DSP registers are accessible through theSi2401 microcontroller via S-registers SE5, SE6, andSE8. SE5 and SE6 are used as conduits to write data tospecific DSP registers and read status. SE8 defines thefunction of SE5 and SE6 depending on whether theyare being written to or read from. Care must beexercised when writing to DSP registers. DSP registerscan only be written while the Si2401 is on-hook and inthe command mode. Writing to any register address notlisted in Tables 15 and 16 or writing out-of-range valuesis likely to cause the DSP to exhibit unpredictablebehavior.

The DSP register address is 16-bits wide, and the DSPdata field is 14-bits wide. DSP register addresses anddata are written in hexadecimal. To write a value to aDSP register, the register address is written, and thenthe data is written. When SE8 = 0x00, SE5(DADL) iswritten with the low bits [7:0] of the DSP registeraddress, and SE6 (DADH) is written with the high bits[15:8] of the DSP address. When SE8 = 0x01,SE5 (DDL) is written with the low bits [7:0] of the DSPdata word corresponding to the previously writtenaddress, and SE6 (DDH) is written with the high bits[15:8] of the data word corresponding to the previouslywritten address. Example 1 illustrates the properprocedure for writing to DSP registers.

Example1: The user would like to program callprogress filter coefficient A2_k0 (0x15) to be 309(0x135).

Host Command:ATSE8=00SE6=00SE5=15SE8=01SE6=01SE5=35SE8=00

In this command, ATSE8=00 sets up registers SE5 andSE6 as DSP address registers. SE6=00 sets the highbits of the address, and SE5=15 sets the low bits.SE8=01 sets up registers SE5 and SE6 as DSP dataregisters for the previously-written DSP address (0x15).SE6=01 sets the six high bits of the 14-bit data word,and SE5=35 sets the eight low bits of the 14-bit dataword.

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66 Rev. 0.31

Table 15. Low-Level DSP Parameters

DSP Reg. Addr.Name Description Function Default

(dec)

0x0002 XMTL DAA modem full-scale transmit level, default = –10 dBm.

Level = 20log10 (XTML/4096)–10 dBm

4096

0x0003 DTML DTMF high-tone transmit level, default = –5.5 dBm.

Level = 20log10 (DTML/4868) –5.5 dBm

4868

0x0004 DTMT DTMF twist ratio (low/high),default = –2 dBm.

Level = 20log10 (DTMT/3277) –2 dB

3277

0x0005 UFRQ User-defined transmit tone frequency. See register SE5 (SE8=0x02 (Write Only)).

f = (9600/512) UFRQ (Hz) 91

0x0006 CPDL Call progress detect level (see Figure 14), default = –43 dBm.

Level = 20log10 (4096/CPDL) –43 dBm

4096

0x0007 UDFD1 User-defined frequency detector 1. Center frequency for detector 1.

UDFD1 = 8192 cos (2 f/9600) 4987


UDFD2 = 8192 cos (2f/9600) 536


UDFD3 = 8192 cos (2 f/9600) 4987

0x000A UDFD4 User-defined frequency detector 4. Center frequency for detector 4.

UDFD4 = 8192 cos (2 f/9600) 536

0x000B TGNL Tone generation level associated with TONC (SE5 (SE8 = 0x02) Write Only Definition), default = –10 dBm.

Level = 20log10 (TGNL/2896)– 10 dBm

2896

0x000E UDFSL Sensitivity setting for UDFD1–4 detectors, default = –43 dBm.

Sensitivity = 10log10(UDFSL/4096) –43 dBm

4096

0x0024 CONL Carrier ON level. Carrier is valid once it reaches this level.

Level = 20log10(2620/CONL) – 43 dBm

2620

0x0025 COFL Carrier OFF level. Carrier is invalid once it falls below this level.

Level = 20log10(3300/COFL) – 45.5 dBm

3300

0x0026 AONL Answer ON level. Answer tone is valid once it reaches this level.

Level = 10log10(AONL/107) – 43 dBm

67

0x0027 AOFL Answer OFF level. Answer tone is invalid once it falls below this level.

Level = 10log10(AOFL/58) – 45.5 dBm

37

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Rev. 0.31 67

Table 16 defines the relationship between SE5, SE6, and SE8.

4.7.2. Call Progress Filters

The programmable call progress filter coefficients are located in DSP address locations 0x0010 through 0x0023.There are two independent 4th order filters, A and B, each consisting of two biquads, for a total of 20 coefficients.Coefficients are 14 bits (–8192 to 8191) and are interpreted as, for example, b0 = value/4096, thus giving a floatingpoint value of approximately –2.0 to 2.0. Output of each biquad is calculated as follows:

The output of the filters is input to an energy detector and then compared to a fixed threshold with hysteresis (DSPregister CPDL). Defaults shown are a bandpass filter from 290–630 Hz (–3 dB). These registers are located in theDSP and, thus, must be written in the same manner described in "DSP Registers" on page 65.

The filters may be configured in either parallel or cascade through SE6[6] (CPCD) with SE8 = 0x02, and the outputof filter B may be squared by selecting SE6[7] (CPSQ) = 1. Figure 14 shows a block diagram of the call progressfilter structure.

Table 16. SE5, SE6, and SE8 Relationship

SE8 SE6 SE5

R/W Name Description Name Description

0x00 W DADH DSP register address bits [15:8] DADL DSP register address bits [7:0]

0x01 W DDH DSP register data bits [15:8] DDL DSP register data bits [7:0]

0x02 R DSP1 7 = DSP data available6 = Tone detected5 = Reserved4:0 = Tone type

0x02 W DSP3 7 = Enable squaring function6 = Call progress cascade disable5 = Reserved4 = User tone 3 and 4 reporting3 = User tone 1 and 2 reporting2 = V.23 tone reporting1 = Answer tone reporting0 = DTMF tone reporting

DSP2 7 = Reserved6:3 = DTMF tone to transmit2:0 = Tone type

w n k0 x n a1 w n 1– a2 w n 2– + +=

y n w n b1 w n 1– b2 w n 2– + +=

AN94

68 Rev. 0.31

Figure 14. Programmable Call Progress Filter Architecture

Table 17. Call Progress Filters

DSP Register Address

Coefficient Default (dec)

0x0010 A1_k0 256

0x0011 A1_b1 –8184

0x0012 A1_b2 4096

0x0013 A1_a1 7737

0x0014 A1_a2 –3801

0x0015 A2_k0 1236

0x0016 A2_b1 133

0x0017 A2_b2 4096

0x0018 A2_a1 7109

0x0019 A2_a2 –3565

0x001A B1_k0 256

0x001B B1_b1 –8184

0x001C B1_b2 4096

0x001D B1_a1 7737

0x001E B1_a2 –3801

0x001F B2_k0 1236

0x0020 B2_b1 133

0x0021 B2_b2 4096

0x0022 B2_a1 7109

0x0023 B2_a2 –3565

Filter B

1 0

1

0

1

0

Filter A

Filter Input

y = x2

CPSQ

Energy Detect

0

CPCD

Max (A,B)

Hysteresis

A > B?

20log10 (4096/CPDL) –43 dBm

TDET

A

BA

B

CPCD

Energy Detect

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Rev. 0.31 69

4.8. Programming ExamplesThe following are examples of how to configure theSi2401 and take advantage of key features.

4.8.1. Parallel Phone Detection

The ISOmodem® chipset is able to detect when anothertelephone, modem, or other device is using the phoneline. This allows the host to avoid interrupting anotherphone call when the phone line is already in use and tointelligently handle an interruption when the ISOmodemchipset is using the phone line.

4.8.1.1. On-Hook Intrusion Detection

When the ISOmodem chipset is sharing the telephoneline with other devices, it is important that it not interrupta call in progress. To detect when another device isusing the shared telephone line, the host can use theISOmodem chipset to monitor the TIP-RING dc voltagewith the LVS[7:0] bits (SDB). The LVS[7:0] bits have aresolution of 1 V per bit with an accuracy ofapproximately ±10%. Bits 0 through 6 of this 8-bit signed2s complement number indicate the value of the linevoltage, and the sign bit (bit 7) indicates the polarity ofTIP and RING.

When all devices on a particular telephone line are on-hook, there is no loop current flowing through TIP andRING. Therefore, the voltage across TIP and RING is ata maximum. (On most telephone lines, this on-hookvoltage is a minimum of 40 V.) Once a device goes off-hook, current flows through TIP and RING on thatdevice, and the TIP-RING voltage drops appreciably.(On most telephone lines, this off-hook voltage is amaximum of 20 V.)

If the host checks the TIP-RING voltage via LVS beforecausing the ISOmodem chipset to dial out or go off-hook, the host can determine if another device is usingthe telephone line. One way to do this is to verify thatthe voltage represented in LVS is above some fixedthreshold, such as 21 V.

4.8.1.2. Off-Hook Intrusion Detection

After it has been determined that it is safe to use thephone line without interrupting a call, the host caninstruct the ISOmodem chipset to begin a call or go off-hook. However, once the call has begun and theISOmodem chipset is in data mode, the serial port isused for modem data making it difficult for the host tomonitor registers. Therefore, when the ISOmodemchipset is off-hook, an algorithm is implemented toautomatically monitor the TIP-RING loop current via theLCS register (SF3). Because the TIP-RING voltagedrops significantly when off-hook, TIP-RING current is abetter indicator of another device using the phone line.The LCS[7:0] bits have a resolution of 1.1 mA per bit, as

long as the represented loop current value is greaterthan the minimum loop indicated by the MINI bit field(SF6[7:6]).

The off-hook intrusion algorithm monitors the value ofLCS (SF3) at a sample rate determined by the DGSR(SDF, bits 6:0) register (40 ms units). The algorithmcompares each LCS sample to the reference value inthe ACL register (S12). If LCS is lower than ACL by anamount greater than DCL (S11, bits 4:0), the algorithmwaits for another LCS sample, and if the next LCSsample is also lower than ACL by an amount greaterthan DCL, an interrupt occurs. This helps theISOmodem chipset avoid a false parallel phonedetection (PPD) interrupt due to glitches on the phoneline. The ACL is continually updated with the value ofLCS as outlined below. The algorithm can be outlinedas follows:

If LCS(t) = LCS(t – 40 ms x DGSR)

and

LCS(t) – ACL > DCL

then ACL = LCS(t)

If (ACL – LCS[t – 40 ms x DGSR]) > DCL)

and

(ACL – LCS[t]) > DCL)

then an intrusion is sent to the host.

Upon detecting an intrusion, an "i" result code is sent tothe host if it is in the call negotiation stage or commandmode. Otherwise, the modem can be programmed togenerate an interrupt to notify the host of the intrusion.

4.8.1.3. How MINI and LCS Affect Programming DCL

This section applies to applications expected to use alarge DCL value.

The value returned by the LCS register (SF3) isexpected to represent the loop current in 1.1 mA stepsas long as the actual loop current is greater than theminimum required indicated by MINI (SF6[7:6]). If theloop current available to the DAA is less than therequired minimum current, then the DAA returns a non-accurate LCS reading.

For example, if MINI is 11, the minimum loop current forproper operation of the DAA is 16 mA. If LCS returns0x10, this represents a loop current value of 17.6 mA.Since 17.6 mA is greater than 16 mA, then, the LCS isexpected to be accurate.

However, let's say that LCS returns the value of 0x0E.In this case, the implied loop current is 15.4 mA lessthan 16 mA. In this case, LCS is not accurate, and theactual loop current is most likely to be much less thanthe 15.4 mA represented.

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70 Rev. 0.31

If the loop current value returned by LCS is less than theloop current minimum (MINI), this condition should betreated as an intrusion event, even though thedifference, compared to the loop current reference, isless than the desired DCL difference.

However, the internal off hook intrusion algorithm doesnot automatically treat these low loop current values asan automatic intrusion event. Therefore, it is theresponsibility for host software to account for the abovenon-linear operation. This can be achieved bydynamically adjusting the DCL value based on thealgorithm shown below.

The subroutine shown in “Example IntrusionSubroutine” can be used to synthesize the 'actual DCL'to be written to register S11, when given ACL, MINI and'desired DCL'. This subroutine is best placed prior to anATDT command.

AN94

Rev. 0.31 71

4.8.2. Example Intrusion Subroutine

---------------------

//

// Inputs:

// ACL is the value derived from S12

// If ACL == 0, means this is first call

// otherwise, it is the ACL read from a previous call, representing loop current

// MINI is the value derived from SF6[7:6], representing minimum loop current required

// Valid Values:

// 0 - represents 10 mA

// 1 - 12

// 2 - 14

// 3 - 16

// DesiredDCL represents the desired delta current level, in milliamp units.

//

// Output:

// Returns the DCL value that is to be written into the register S11

//

int ActualDCL(int MINI, int ACL, int DesiredDCL)

{

int MinimumLoop;

//

// Translates MINI to a minimum loop current floor.

//

MinimumLoop = 10 + ( MINI << 1) ;

//

// Note that ACL==0 means that the up-coming call is expected to be the first call.

// The best guess is to set the DCL to DesiredDCL.

//

// There is a risk that on the first call, the intrusion may be missed if the

// DesiredDCL is large, and the loop current is low. However, the ACL for the next

// call will be set properly.

if (ACL == 0) return DesiredDCL;

//

// If the loop current is large enough, just use the desired DCL. Otherwise

// Adjust DCL based on the expected MinimumLoop conditions.

//

if ( (MinimumLoop + DesiredDCL) < ACL ) {

return DesiredDCL;

} else {

return (ACL - MinimumLoop);

}

//

// All cases should have been handled, and should never get here.

return ERROR;

}

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72 Rev. 0.31

The very first sample of LCS the algorithm uses aftergoing off-hook does not have any previous samples forcomparison. If LCS was measured during a previouscall, this value of LCS may be used as an initialreference. ACL may be written by the host with thisknown value of LCS. If ACL is non-zero, the ISOmodemchipset uses ACL as the first valid LCS sample in theoff-hook intrusion algorithm. If ACL is 0 (default afterreset), the ISOmodem chipset ignores the register anddoes not begin operating the algorithm until two LCSsamples have been received. Additionally, immediatelyafter a modem call, ACL is updated automatically withthe last valid LCS value before a parallel phonedetection (PPD) intrusion or going back on-hook.

The off-hook intrusion algorithm does not begin tooperate immediately after going off-hook. This is toavoid triggering an interrupt due to transients resultingfrom the ISOmodem chipset itself going from on-hook tooff-hook. The time that elapses between the ISOmodemchipset going off-hook and the intrusion algorithmstarting defaults to one second and may be adjusted viathe IST register (S82, bits 7:4). If ACL is written to anon-zero value before going off-hook, a parallel phoneintrusion that occurs during this IST interval andsustains through the end of the interval triggers aninterrupt.

The off-hook intrusion algorithm may additionally bedisabled for a period of time after dialing begins via theIB register (S82, bits 2:1). This avoids triggering aninterrupt due to pulse dialing, open-switch intervals, orline transients from central office switching. Intrusionmay be disabled from the start of dialing to the end ofdialing (IB = 01b), from the start of dialing to the timeoutof the IS (S29, bits 7:0) by setting IB = 10b(IB = 2) orfrom the start of dial to carrier detect by setting IB = 11b.The off-hook intrusion algorithm is only suspended (notdisabled) during this IB interval. Therefore, any intrusionthat occurs during the IB interval and sustains throughthe end of the interval triggers a PPD interrupt.

4.8.3. Interrupt Detection

The INT interrupt pin can be programmed to alert thehost of loss-of-carrier, loss-of-phone-line voltage/current, parallel phone detection, and other interruptslisted in the interrupt status mask (S08). After the hostreceives an interrupt via the INT pin, the host shouldissue the AT:I command. This command causes a read-clear of the WOR, PPD, NLD, RI, OCD, and REV bits ofthe S09 register and raises (deactivates) the INT pin. Allthe interrupt status bits in register S09 remain high afterbeing set until cleared by the AT:I command.

4.8.3.1. Loop Current Detection

In addition to monitoring parallel phone intrusion, it ispossible to monitor the loss of loop current. This featurecan be enabled by setting S08[4] (NLDM) = 1. Thisfeature is disabled by default. If the loop current is toolow for normal DAA operation, S09[4] (NLD) is set.During this event, if the NLR result code is enabled bysetting S62[1](NLR) = 1, the “l” result code is sent. Oncethe loop current returns to a normal current state, the “L”result code is sent. The INT pin is also asserted ifenabled.

4.8.3.2. Loss-of-Carrier Detection

The Si2401 has two methods of implementing a loss-of-carrier function. If GPIO4 is programmed as INT and ifS08[7](CDM) = 1, INT asserts in data mode when aloss-of-carrier is detected. The carrier detect functionmay also be implemented on GPIO2 by setting SE2[3:2](GPIO2) = 01 and SOC[7](CDE) = 1.

4.8.3.3. Overcurrent Detection

The Si2401 has an integrated overcurrent detectionfeature. The Si2401 begins monitoring for anovercurrent condition at a programmable time set byS32 (OCDT) after going off-hook (default = 20 ms). If anovercurrent condition is detected, the Si2401 setsS09[1] interrupt status. As long as GPIO4 isprogrammed as INT and the overcurrent mask bit isenabled by setting S08[1](OCDM) = 1, INT assertsduring an overcurrent situation. The host may thencheck S09[1] (OCD) via the AT:I command to confirmthat an overcurrent condition occurred.

4.8.3.3.1. Bug Summary

When an overcurrent event occurs, the Si2401 isexpected to “snooze” the event, much like pressing the“snooze” button on an alarm clock. The Si2401 will takeaction when the overcurrent event is reported fourtimes. In other words, it is a “deglitch” function, similar tothe concept we have for parallel phone intrusion events,but in a much shorter time-base.

The action taken by the Si2401 is to setISTAT_OVERCURRENT status after four overcurrentevents (or whatever is set in register SAA). If the INT*interrupt pin is enabled (SE2 = C0) and the overcurrentinterrupt is unmasked (S08 = 02), the host will get aninterrupt upon detection of this status. The host is thenexpected to respond to the interrupt event by goingback on hook.

The problem is the first event expects the overcurrentbit to be cleared by the toggling of OPE. Since thetoggling of the OPE is too fast for the Si3010, theovercurrent bit is not cleared, and the code keepsresponding to the single event. In other words, only one

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Rev. 0.31 73

overcurrent event is capable of causing the Si2401 toreport ISTAT_OVERCURRENT.

Therefore, there is a risk of false overcurrent eventreporting if the loop current is high and an open switchinterval event occurs.

The risk of a nuisance overcurrent detection is low sincemost phone lines are in the neighborhood of 30 mA loopcurrent. There are many other mitigating factors.

4.8.3.3.2. Software Workaround

Set SAA = 00 if the effect of a nuisance OSI event isworse than the risk of encountering a metallicovercurrent event. As it is currently written, the Si2401can pass a rather severe metallic off hook 600 Vrms(1A) for one second. SAA (opthresh) disables theovercurrent detection.

// Pseudo Code of Overcurrent Detection executed once every 6.67 msec

// Upon going off hook, the value in opthresh (SAA) is copied

// into opcnt (SCB).

// OPE and OPD is a representation of the DAA bits

//

if (OPD == 1 && OPE == 1 && opthresh != 0)

{

if (opcnt & 0x80) // MS-bit of opcnt is a 'flag'

{

// Case if MS-bit of opcnt is set ...

opcnt &= ~0x80 ; // clear opcnt msb

OPE = 0 ; // toggle OPE

OPE = 1 ; // !!!! BUG HERE !!!

OPD = 0 ; // clear OPD

} else {

// Case if MS-bit of opcnt is clear...

opcnt -= 1 ; // decrement opcnt

if (opcnt == 0) {

ISTAT_OVERCURRENT = 1 ;

} else {

opcnt |= 0x80 ; // This sets the flag

} // END if (opcnt == 0)

} // END if (opcnt & 0x80)

} // END if (OPD == 1 && OPE == 1 && opthresh != 0) //

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74 Rev. 0.31

4.8.4. Caller ID Decoding Operation

The Si2401 supports full caller ID detection and decodefor US Bellcore and UK standards. To use the caller IDdecoding feature, the following configuration isnecessary:

1. Set SE0[3] (ND) = 0b (set modem to 8N1 configuration).

2. Set S0C[7:6] (CIDM) = 01 (set modem to Bellcore type caller ID) or S13[2] (CIDB) = 1 (set modem to UK type caller ID).

4.8.4.1. Caller ID Monitor/Bellcore Caller ID

The Si2401 continuously monitors the phone line for thecaller ID mark signals. This can be useful in systemsthat require detection of caller ID data before the ringsignal, voice mail indicator signals, and Type II caller IDmonitor support. To force the Si2401 into caller IDmonitor mode, set SOC[6:5] (CIDM) = 11.

Note: CIDM should be disabled before going off-hook.

4.8.4.2. UK Caller ID Operation

The Si2401 starts searching for the Idle State Tone AlertSignal. When this signal has been detected, the Si2401transmits an “a” to the host. After the Idle State ToneAlert Signal is completed, the Si2401 applies thewetting pulse for the required 15 ms by quickly goingoff-hook and on-hook. From this point on, the algorithmis identical to that of Bellcore in that it searches for thechannel seizure signal and the marks before echoing an“m” and then reports the decoded caller ID data.

4.8.5. V.23 Operation/V.23 Reversing

The Si2401 supports full V.23 operation including theV.23 reversing procedure. V.23 operation is enabled bysetting S07 (MF1) = xx10x110b or xx01x110b. IfS07[5] (V23R) = 1b, the Si2401 transmits data at 75 bpsand receives data at 600 or 1200 bps. IfS07[4] (V23T) = 1b, the Si2401 receives data at 75 bpsand transmits data at 600 or 1200 bps. S07[2] (BAUD)is the 1200 or 600 bps indicator. BAUD = 1b enablesthe 1200/600 V.23 channel to run at 1200 bps, whileBAUD = 0b enables 600 bps operation.

When a V.23 connection is successfully established, themodem responds with a “c” character if the connectionis made with the modem transmitting at 1200/600 bpsand receiving at 75 bps. The modem responds with a“v” character if a V.23 connection is established with themodem transmitting at 75 bps and receiving at 1200/600 bps.

The Si2401 supports the V.23 turnaround procedure.This allows a modem that is transmitting at 75 bps toinitiate a “turnaround” procedure so that it can begintransmitting data at 1200/600 bps and receiving data at75 bps. The modem is defined as being in V.23 master

mode if it is transmitting at 75 bps, and it is defined asbeing in slave mode if the modem is transmitting at1200/600 bps. The following paragraphs give a detaileddescription of the V.23 turnaround procedure.

4.8.5.1. Modem in Master Mode

To perform a direct turnaround once a modemconnection is established, the master host goes intoonline-command-mode by sending an escapecommand (Escape pin activation, TIES, or ninth bitescape) to the master modem.

Note: The host can initiate a turnaround only if the Si2401 isthe master.

The host then sends the ATRO command to the Si2401to initiate a V.23 turnaround and return to the online(data) mode.

The Si2401 then changes its carrier frequency (from390 Hz to 1300 Hz) and waits to detect a 390 Hz carrierfor 440 ms. If the modem detects more than 40 ms of a390 Hz carrier in a time window of 440 ms, it echoes the“c” response character. If the modem does not detectmore than 40 ms of a 390 Hz carrier in a time window of440 ms, it hangs up and echoes the “N” (no carrier)character as a response.

4.8.5.2. Modem in Slave Mode

Configure GPIO4 as INT (SE2[7:6] [GPIO4] = 11b). TheSi2401 performs a reverse turnaround when it detects acarrier drop longer than 20 ms. The Si2401 thenreverses (changes its carrier from 1300 Hz to 390 Hz)and waits to detect a 1300 Hz carrier for 400 ms. If theSi2401 detects more than 40 ms of a 1300 Hz carrier ina time window of 400 ms, it sets the S09[7] bit, and thenext character echoed by the Si2401 is a “v”.

If the Si2401 does not detect more than 40 ms of the1300 Hz carrier in a time window of 400 ms, it reversesagain and waits to detect a 390 Hz carrier for 440 ms.Then, if the Si2401 detects more than 40 ms of a390 Hz carrier in a time window of 220 ms, it sets theS09[7] bit, and the next character echoed by the Si2401is a “c”.

At this point, if the Si2401 does not detect more than40 ms of the 390 Hz carrier in a time window of 440 ms,it hangs up, sets the S09[7] bit, and the next characterechoed by the Si2401 is an “N” (no carrier).

Successful completion of a turnaround procedure inmaster or slave mode automatically updatesS07[4] (V23T) and S07[5] (V23R) to indicate the newstatus of the V.23 connection.

To avoid using the INT pin, the host may also be notifiedof the INT condition by using 9-bit data mode. SettingS15[0] (NBE) = 1b and S0C[3] (9BF) = 0b configuresthe ninth bit on the Si2401 TXD path to function exactlyas the INT pin has been described.

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Rev. 0.31 75

4.8.6. V.42 HDLC Mode

The Si2401 supports V.42 through hardware HDLCframing in all modem data modes. Frame packing andunpacking including opening and closing flag generationand detection, CRC computation and checking, zeroinsertion and deletion, and modem data transmissionand reception are all performed by the Si2401. V.42error correction and V.42bis data compression must beperformed by the host.

The digital link interface in this mode uses the sameUART interface (8-bit data and 9-bit data formats) as inthe asynchronous modes, and the ninth data bit may beused as an escape by setting S15[0] (NBE) = 1b. Whenusing HDLC in 9-bit data mode, if the ninth bit is notused as an escape, it is ignored.

To use the HDLC feature on the Si2401, the host mustenable HDLC operation by setting S13[1] (HDEN) = 1b.The host may initiate the call or answer the call usingeither the “ATDT#”, the “ATA” command or the auto-answer mode. (The auto-answer mode is implementedby setting register S00 (NR) to a non-zero value.) Whenthe call is connected, a “c”, “d”, or a “v” is echoed to thehost controller. The host may now send/receive dataacross the UART using either the 8-bit data or 9-bit dataformats with flow control.

At this point, the Si2401 begins framing data into theHDLC format. On the transmit side, if no data isavailable from the host, the HDLC flag pattern is sentrepeatedly. When data is available, the Si2401computes the CRC code throughout the frame, and thedata is sent with the HDLC zero-bit insertion algorithm.

HDLC flow control operates in a similar manner tonormal asynchronous flow control across the UART andis shown in Figure 15. To operate flow control (using theCTS pin to indicate when the Si2401 is ready to accepta character), a DTE rate higher than the line rate shouldbe selected. The method of transmitting HDLC framesis as follows:

1. After the call is connected, the host should begin sending the frame data to the Si2401 using the CTS flow control to ensure data synchronicity.

2. When the frame is complete, the host should simply stop sending data to the Si2401. Since the Si2401 does not yet recognize the end-of-frame, it expects an extra byte and asserts CTS as shown in Figure 15A. If CTS is used to cause a host interrupt, this final interrupt should be ignored by the host.

3. When the Si2401 is ready to send the next byte, if it has not yet received any data from the host, it recognizes this as an end-of-frame, raises CTS, calculates the final CRC code, transmits the code, and begins transmitting stop flags.

4. After transmitting the first stop flag, the Si2401 lowers CTS indicating that it is ready to receive the next frame from the host. At this point, the process repeats as in Step 1.

The method of receiving HDLC frames is as follows:

1. After the call is connected, the Si2401 searches for flag data. Then, once the first non-flag word is detected, the CRC is continuously computed, and the data is sent across the UART (8-bit data or 9-bit data mode) to the host after removing the HDLC zero-bit insertion. The DTE rate of the host must be at least as high as that of data transmission. HDLC mode only works with 8-bit data words; the ninth bit is used only for escape on TXD and end-of-frame received (EOFR) on RXD.

2. When the Si2401 detects the stop flag, it sends the last data word in the frame as well as the two CRC bytes and determines if the CRC checksum matches. Thus, the last two bytes are not frame data but are the CRC bytes, which can be discarded by the host. If the checksum matches, the Si2401 echoes “G” (good). If the checksum does not match, the Si2401 echoes “e” (error). Additionally, if the Si2401 detects an abort (seven or more contiguous ones), it echoes an “A”. When the “G”, “e”, or “A” (referred to as a frame result word) is sent, the Si2401 raises the EOFR (end of frame receive) pin (see Figure 15B). The GPIO1 pin must be configured as EOFR by setting SE4[3] (GPE) = 1b. In addition to using the EOFR pin to indicate that the byte is a frame result word, if in 9-bit data mode (set S15[0] (NBE) = 1b), the ninth bit is raised if the byte is a frame result word. To program this mode, set S0C[3] (9BF) = 1b and SE0[3] (ND) = 1b.

3. When the next frame of data is detected, EOFR is lowered, and the process repeats at Step 1.

To summarize, when receiving HDLC frames, the hostbegins receiving data asynchronously from the Si2401.When each byte is received, the host should check theEOFR pin (or the ninth bit). If the EOFR pin (or the ninthbit) is low, the data is valid frame data. If the EOFR pin(or the ninth bit) is high, the data is a frame result word.

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76 Rev. 0.31

Figure 15. HDLC Timing

4.8.7. V.80 Synchronous Access Mode Interface

In addition to the V.42 HDLC interface in the previoussection, the Si2401 revision B implements V.80synchronous access mode in-band commands (seeTable 2 on page 5). Please refer to the ITU-TSpecification V.80 for additional backgroundinformation. The main advantage of using the V.80Synchronous Access Mode (SAM) Interface instead ofthe V.42 HDLC interface is that there are no longer anyhardware dependencies associated with CTS, EOFRtiming.

The SC0, SC1, SC2 and SC3 registers are V80configuration commands that are programmed by thehost prior to the ATDT command. Table 19 shows acommand summary. Also refer to documentation onregister SC0, SC1 and SC2.

ITC (in SC0) should be set according to how the host isexpected to implement flow control. For properoperation of SAM, the DTE rate must be programmed tobe greater than the expected DCE rate. At the veryleast, the baud rate must be 9600. Flow control in thetransmit control is mandatory for proper operation. Flowcontrol in the receive direction is optional.

To control flow in the transmit direction, the host isexpected to receive, and act on, signals from themodem. The modem asserts/negates CTS (hardwareflow control) or inserts XON/XOFF (software flowcontrol) onto the receive data path based on how full thetransmit buffer is. The thresholds for flow-on/flow-off areprogrammable through the SC1 and SC2 registers.

The Si2401 also supports flow control in the receivedirection. When receive flow control is activated, themodem obeys signals originating from the host, whetherit be the assertion/negation of RTS, or the transmission

of XON/XOFF characters in the transmit path. Receiveflow control is not a requirement because the DTE rateis expected to be greater than the DCE rate. Whenenabling RTS hardware flow control (ITC=10), the hostis expected to program the GPIO1 as a digital input priorto the ATDT command. RTS hardware flow controlbecomes active only when there is an active connection(after 'c' result code).

The ESA2 bit in the SC0 register determines whether ornot the Frame Check Sequence (FCS) is calculated andtransmitted, and whether or not the received frame CRCchecking is done. Most point-of-sale applications willrequire ESA2 = 1.

The Si2401 supports both the Framed and TransparentSub-modes described in the V.80. V.80 requires that themodem begin operating in the Transparent Submodeupon connection. The Si2401, through the TRANSP bitin the SC3 register, allows the modem to enter theFramed Submode directly without going through theTransparent Sub-mode initially.

Finally, the ESOM and ESAM fields in register SC0determine whether to enter V.80 SAM operation. TheESOM describes operation of the modem if it is theoriginating modem. The ESAM describes operation ofthe modem as an answering modem. Note that ESOM/ESAM must be cleared when the V.42 HDLC Mode isenabled (S12[1] = 1).

Once a connection has been established, the Si2401sends the respond code 'c' or 'd' to indicate theconnection speed. After the 'c' or 'd' result code, theSi2401 sends an <19> <BE> <20> <20> sequence,regardless of the actual DTE rate.

After the above connection sequence, the in-bandcommands apply. Refer to Table 2. The goal of many of

B. Frame Receive

A. Frame Transmit

TXD

RXD Start StopStart

Host begins frame N

Frame N StartStart Stop

Host finished sending frame N Host begins frame N + 1

CTS

Frame N + 1

CRC Byte 2 StopStop Start Start StopReceive Data

EOFR(or bit 9)

Si2400 ready for byte 1 of frame N

Note: Figure not to scale.

(CTS used as normal flow control.)Si2401 detects end of frame N.

Si2401 ready for byte 1of frame N + 1.

CRC Byte 1 Frame Result Word

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Rev. 0.31 77

the transparency commands is to ensure that thefollowing bytes are reserved for special purposes:

<19> can be used to represent EM

<99> can be used to represent EM

<11> can be used as DC1 (XON)

<13> can be used as DC3 (XOFF)

If the host implements EM-shielding properly, the abovebytes will appear at the Si2401-host interface, as thespecial functions they represent.

Once a connection has been established, the Si2401enters the Transparent Sub-mode or the Framed Sub-mode based on the setting of the TRANSP bit in registerSC3. If the modem is in the transparent mode, the datafollowing the above connect sequence is received, while0xFF are transmitted to the remote modem until thehost begins transmitting. At any time, the host can sendthe <B1> command to cause the modem to enterthe Framed Sub-mode. The Si2401 receiver then huntsfor HDLC flags responds with the <19><B2> when thereceiver detects an HDLC flag.

Once the connection has been established, if theSi2401 enters the Framed Sub-mode, the receiverhunts for HDLC flags and sends an <19><B1> once aflag has been detected. The Si2401 transmits HDLCflags to the remote modem until the host beginstransmitting.

When in the Framed Sub-mode, once the upperthreshold in SC1 is reached, the Si2401 begins totransmit actual data, while at the same time, indicating aflow-off status to the host. The host is expected to stoptransmission until the Si2401 sends a flow-on status.The Si2401 then begins to transmit, and empties thetransmit FIFO. Once the transmit FIFO reaches thethreshold in SC2, the Si2401 sends the flow-on status tothe host. The host is expected to respond with data bythe time the last byte in the transmit FIFO has beensent. To indicate an end of frame, the host sends the <B1> command at the end of a frame.

The Si2401, upon receipt of the <B1> indicator,appends the 16-bit FCS (frame check sequence,assuming ESA2=1) and then sends HDLC flags to endthe frame.

In the receive path, if ESA2 = 1, the Si2401 looks for thedata frame in-between the HDLC flags. Once thereceive data has been received, the appended FCS iscompared against a running CRC calculation as a checkfor the validity of the receive frame. A good frameresults in the Si2401 sending an <19> <B1> to the host,while a bad frame is indicated by a <19> <B2> indicator.Note that the transmitted frame check sequence is notsent to the host.

The Si2401 can also send indicators for transmitunderrun, transmit overrun and receiver overrunconditions. Host software must be modified to removethese error conditions by obeying proper flow controlmethods.

The host can send and escape command <BB>or an escape/carrier terminate command <BA>.In either case, the Si2401 transitions over to commandmode and terminates the transmit carrier (if <BA>). The Si2401 is kept in the off hook condition untilan ATH command has been sent to the modem.

If the remote modem terminates the carrier, the Si2401indicates this condition by sending the <19> <BA>indicator, enters the command state, but will remain inthe off hook condition until an ATH command isreceived.

Note that the Si2401 does not implement the samesyntax used by the V.80 standard to configure theSi2401 Synchronous Access Mode. Instead of usingAT+ commands, the Si2401 uses S-registers. Thefollowing AT+ commands are supported via S-registersettings:

+ES—Enable/disable synchronous mode

+ESA—Configure the operation of synchronous mode

+IFC—Specifies the flow control to be implemented

+ITF—Configure the transmit flow thresholds

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78 Rev. 0.31

Table 18. S-Register Example

AT+ command Si2401 equivalent Comments

AT+ES=6,8AT+ESA=0,0,0,1,0,255AT+IFC=0,2

ATSC0=15

SAM originate or answerCRC16CTS flow controlSingle S-register write does all three AT+ com-mands

AT+ITF=20,4 ATSC1=14SC2=04 Transmit Flow Control settings

no equivalent ATSC3=00 Upon connection, operate in Framed Submode. Note V.80 always begins in Transparent Submode, and provides no choice.

Table 19. Si2401 V80 HDLC Synchronous Access Mode Configuration Registers

S-Register Register Address

(hex)

Name Function Reset

SC0 0xC0 V80C This is a bit mapped register. 0x00

SC1 0xC1 ITF1 Transmit flow control off threshold. Threshold, in bytes, above which the modem will generate a flow off signal (maximum threshold value of 20).

0x14

SC2 0xC2 ITF2 Transmit flow control on threshold. Threshold, in bytes, below which the modem will generate a flow on signal. This value must be less than ITF1.

0x04

SC3 0xC3 V80M This is a bit mapped register. 0x00

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Rev. 0.31 79

4.8.8. Low Power Modes

The Si2401 has three low-power modes:

DSP Powerdown. The DSP processor can be powered down by setting register SEB[3] (PDDE) = 1. In this mode, the serial interface still functions, and the modem detects ringing and intrusion. However, no modem modes or tone detection features function.

Wake-Up-On-Ring. By issuing the ATz command, the Si2401 goes into a low-power mode where both the microcontroller and DSP are powered down. Only an incoming ring, a low TXD signal, or a total reset will power up the chip again. Return from wake-on-ring triggers the INT pin if S09[6] (WOR) = 1 (WOR = 0b by default).

Total Powerdown. Setting SF1[5] = 1 and SF1[6] = 1 places the Si2401 into a total powerdown mode. All logic is powered down including the crystal oscillator and clock-out pin. Only a hardware reset can restart the Si2401.

4.8.9. Global Configuration

The Si2401 chipset contains an integrated silicon directaccess arrangement (silicon DAA) that provides aprogrammable line interface to meet internationaltelephone line requirements. Table 20 on page 80 givesthe DAA register settings required to meet variouscountry PTT standards. A detailed description of theregisters in this table can be found in "DAA Operation"on page 10.

There have been several recent changes to variouscountry requirements. This section summarizes thesechanges. Check with your compliance laboratory toverify whether countries now accepting TBR-21 stillaccept their previous settings.

Countries now accepting TBR-21 include the following.

Egypt

Hungary

Slovakia

A recent change to TBR-21 drops the requirement forloop current limiting. Table 20 on page 80 is configuredto enable current limiting. If you want to disable loopcurrent limiting, Change the setting for SF5(ILIM)[3] =0b.

AN94

80 Rev. 0.31

Tab

le 2

0. S

i240

1 C

ou

ntr

y Ta

ble

Si2

401

Reg

iste

rS

F5

SF

5S

F6

SF

6

Co

un

try

OH

S2

OH

SIL

IMR

ZR

T2

RT

Co

mb

ined

MIN

I[1

:0]

DC

V[1

:0]

AC

IM[3

:0]

Co

mb

ined

AT

Co

mm

and

str

ing

Alg

eria

10

10

00

2800

10

0011

23A

TS

F5=

28S

F6

=23

Arg

ent

ina

00

00

00

0000

10

000

020

AT

SF

5=00

SF

6=20

Arm

enia

00

00

00

0000

10

000

020

AT

SF

5=0

0SF

6=

20

Aus

tral

ia0

10

00

010

100

100

1193

AT

SF

5=10

SF

6=93

Aus

tria

(E

U)

10

10

00

2800

10

0011

23A

TS

F5=

28S

F6

=23

Ba

ham

as0

00

00

000

001

00

000

20A

TS

F5=

00S

F6=

20

Ba

hrai

n1

01

00

028

001

000

1123

AT

SF

5=2

8SF

6=

23

Bel

arus

00

00

00

0000

10

000

020

AT

SF

5=00

SF

6=20

Be

lgiu

m (

EU

)1

01

00

028

001

000

1123

AT

SF

5=2

8SF

6=

23

Ber

mud

a0

00

00

000

001

00

000

20A

TS

F5=

00S

F6=

20

Bra

zil

00

00

00

0000

01

000

010

AT

SF

5=0

0SF

6=

10

Bru

nei

00

00

00

0000

10

000

020

AT

SF

5=00

SF

6=20

Bu

lgar

ia1

01

00

028

001

000

1123

AT

SF

5=2

8SF

6=

23

Can

ada

00

00

00

0000

10

000

020

AT

SF

5=00

SF

6=20

Car

ibb

ean

00

00

00

0000

10

000

020

AT

SF

5=0

0SF

6=

20

Chi

le0

00

00

000

001

00

000

20A

TS

F5=

00S

F6=

20

Chi

na—

Pe

ople

's R

epub

lic0

00

00

000

001

00

000

20A

TS

F5=

00S

F6

=20

Col

ombi

a0

00

00

000

001

00

000

20A

TS

F5=

00S

F6=

20

Cos

ta R

ica

00

00

00

0000

10

000

020

AT

SF

5=0

0SF

6=

20

Cro

atia

10

10

00

2800

10

0011

23A

TS

F5=

28S

F6=

23

Cyp

rus

EU

)1

01

00

028

001

000

1123

AT

SF

5=2

8SF

6=

23

Cze

ch R

epu

blic

(E

U)

10

10

00

2800

10

0011

23A

TS

F5=

28S

F6=

23

Den

mar

k (E

U)

10

10

00

2800

10

0011

23A

TS

F5=

28S

F6

=23

Dom

inic

an

Rep

ubl

ic0

00

00

000

001

00

000

20A

TS

F5=

00S

F6=

20

Dub

ai0

00

00

000

001

00

000

20A

TS

F5=

00S

F6

=20

Eq

uado

r0

00

00

000

001

00

000

20A

TS

F5=

00S

F6=

20

Egy

pt

10

10

00

2800

10

0011

23A

TS

F5=

28S

F6

=23

El S

alva

dor

00

00

00

0000

10

000

020

AT

SF

5=00

SF

6=20

Est

onia

(E

U)

10

10

00

2800

10

0011

23A

TS

F5=

28S

F6

=23

AN94

Rev. 0.31 81

Fin

land

(E

U)

10

10

00

2800

1000

1123

AT

SF

5=

28S

F6=

23

Fra

nce

(EU

)1

01

00

028

0010

0011

23A

TS

F5

=28

SF

6=23

Geo

rgia

00

00

00

0000

1000

0020

AT

SF

5=

00S

F6=

20

Ger

man

y (E

U)

10

10

00

2800

1000

1123

AT

SF

5=

28S

F6=

23

Gre

ece

(EU

)1

01

00

028

0010

0011

23A

TS

F5

=28

SF

6=23

Gua

del

oupe

10

10

00

2800

1000

1123

AT

SF

5=

28S

F6=

23

Gua

m0

00

00

000

0010

0000

20A

TS

F5

=00

SF

6=20

Ho

ng K

ong

00

00

00

0000

1000

0020

AT

SF

5=

00S

F6=

20

Hu

ngar

y (E

U)

10

10

00

2800

1000

1123

AT

SF

5=

28S

F6=

23

Icel

and

(CT

R-2

1)1

01

00

028

0010

0011

23A

TS

F5

=28

SF

6=23

Indi

a0

00

00

000

0010

0000

20A

TS

F5

=00

SF

6=20

Indo

nesi

a0

00

00

000

0010

0000

20A

TS

F5

=00

SF

6=20

Irel

and

(EU

)1

01

00

028

0010

0011

23A

TS

F5

=28

SF

6=23

Isra

el1

01

00

028

0010

0011

23A

TS

F5

=28

SF

6=23

Italy

(E

U)

10

10

00

2800

1000

1123

AT

SF

5=

28S

F6=

23

Japa

n0

00

00

000

1001

0000

90A

TS

F5

=00

SF

6=90

Jord

an0

00

00

000

1001

0000

90A

TS

F5

=00

SF

6=90

Kaz

akhs

tan

00

00

00

0000

0100

0010

AT

SF

5=

00S

F6=

10

Kor

ea0

00

10

004

0010

0000

20A

TS

F5

=04

SF

6=20

Kuw

ait

00

00

00

0000

1000

0020

AT

SF

5=

00S

F6=

20

Kyr

gyzs

tan

00

00

00

0000

1000

0020

AT

SF

5=

00S

F6=

20

Latv

ia (

EU

)1

01

00

028

0010

0011

23A

TS

F5

=28

SF

6=23

Leba

non

10

10

00

2800

1000

1123

AT

SF

5=

28S

F6=

23

Liec

hten

stei

n (

CT

R-2

1)

10

10

00

2800

1000

1123

AT

SF

5=

28S

F6=

23

Lith

uani

a (E

U)

10

10

00

2800

1000

1123

AT

SF

5=

28S

F6=

23

Luxe

mbo

urg

(E

U)

10

10

00

2800

1000

1123

AT

SF

5=

28S

F6=

23

Mac

ao0

00

00

000

0010

0000

20A

TS

F5

=00

SF

6=20

Mal

aysi

a0

00

00

000

1001

0000

90A

TS

F5

=00

SF

6=90

Mal

ta (

EU

)1

01

00

028

0010

0011

23A

TS

F5

=28

SF

6=23

Mar

tiniq

ue1

01

00

028

0010

0011

23A

TS

F5

=28

SF

6=23

Tab

le 2

0. S

i240

1 C

ou

ntr

y Ta

ble

(C

on

tin

ued

)

Si2

401

Re

gis

ter

SF

5S

F5

SF

6S

F6

Co

un

try

OH

S2

OH

SIL

IMR

ZR

T2

RT

Co

mb

ine

dM

INI[

1:0

]D

CV

[1:0

]A

CIM

[3:0

]C

om

bin

ed

AT

Co

mm

an

d s

trin

g

AN94

82 Rev. 0.31

Me

xico

00

00

00

000

010

000

02

0A

TS

F5=

00S

F6=

20

Mo

ldo

va0

00

00

000

00

1000

00

20

AT

SF

5=00

SF

6=2

0

Mo

rocc

o1

01

00

028

00

100

011

23

AT

SF

5=28

SF

6=2

3

Net

herla

nds

(EU

)1

01

00

028

00

100

011

23

AT

SF

5=28

SF

6=2

3

New

Ze

alan

d0

00

00

000

00

1001

00

24

AT

SF

5=00

SF

6=2

4

Nig

eria

10

10

00

280

010

001

12

3A

TS

F5=

28S

F6=

23

Nor

way

(C

TR

-21)

10

10

00

280

010

001

12

3A

TS

F5=

28S

F6=

23

Om

an0

00

00

000

10

0100

00

90

AT

SF

5=00

SF

6=9

0

Pak

ista

n0

00

00

000

10

0100

00

90

AT

SF

5=00

SF

6=9

0

Par

agu

ay0

00

00

000

00

1000

00

20

AT

SF

5=00

SF

6=2

0

Per

u0

00

00

000

00

1000

00

20

AT

SF

5=00

SF

6=2

0

Phi

lippi

nes

00

00

00

001

001

000

09

0A

TS

F5=

00S

F6=

90

Pol

and

(EU

)1

01

00

028

00

100

011

23

AT

SF

5=28

SF

6=2

3

Pol

yne

sia

(Fre

nch

)1

01

00

028

00

100

011

23

AT

SF

5=28

SF

6=2

3

Por

tuga

l (E

U)

10

10

00

280

010

001

12

3A

TS

F5=

28S

F6=

23

Pue

rto

Ric

o0

00

00

000

00

1000

00

20

AT

SF

5=00

SF

6=2

0

Qat

ar0

00

00

000

10

0100

00

90

AT

SF

5=00

SF

6=9

0

Reu

nio

n1

01

00

028

00

100

011

23

AT

SF

5=28

SF

6=2

3

Rom

ania

10

10

00

280

010

001

12

3A

TS

F5=

28S

F6=

23

Rus

sia

00

00

00

000

001

000

01

0A

TS

F5=

00S

F6=

10

Sau

di A

rab

ia0

00

00

000

00

1000

00

20

AT

SF

5=00

SF

6=2

0

Sin

gapo

re0

00

00

000

00

1000

00

20

AT

SF

5=00

SF

6=2

0

Slo

vaki

a (

EU

)1

01

00

028

00

100

011

23

AT

SF

5=28

SF

6=2

3

Slo

ven

ia (

EU

)1

01

00

028

00

100

011

23

AT

SF

5=28

SF

6=2

3

Sou

th A

fric

a0

00

10

004

00

100

011

23

AT

SF

5=04

SF

6=2

3

Spa

in (

EU

)1

01

00

028

00

100

011

23

AT

SF

5=28

SF

6=2

3

Sri

Lan

ka0

00

00

000

00

1000

00

20

AT

SF

5=00

SF

6=2

0

Sw

ede

n (E

U)

10

10

00

280

010

001

12

3A

TS

F5=

28S

F6=

23

Sw

itze

rland

(C

TR

-21)

10

10

00

280

010

001

12

3A

TS

F5=

28S

F6=

23

Taiw

an0

00

00

000

00

1000

00

20

AT

SF

5=00

SF

6=2

0

Tab

le 2

0. S

i240

1 C

ou

ntr

y Ta

ble

(C

on

tin

ued

)

Si2

401

Reg

iste

rS

F5

SF

5S

F6

SF

6

Co

un

try

OH

S2

OH

SIL

IMR

ZR

T2

RT

Co

mb

ined

MIN

I[1:

0]D

CV

[1:0

]A

CIM

[3:0

]C

om

bin

edA

T C

om

man

d s

trin

g

AN94

Rev. 0.31 83

Th

aila

nd0

00

00

00

000

0100

00

10

AT

SF

5=00

SF

6=10

Tun

isia

00

00

00

00

0010

000

02

0A

TS

F5=

00S

F6=

20

Tur

key

10

10

00

28

0010

001

12

3A

TS

F5=

28S

F6=

23

UA

E0

00

00

00

000

1000

00

20

AT

SF

5=00

SF

6=20

Ukr

ain

e0

00

00

00

000

1000

00

20

AT

SF

5=00

SF

6=20

Uni

ted

Kin

gdo

m (

EU

)1

01

00

02

800

100

011

23

AT

SF

5=28

SF

6=23

Uru

guay

00

00

00

00

0010

000

02

0A

TS

F5=

00S

F6=

20

US

A0

00

00

00

000

1000

00

20

AT

SF

5=00

SF

6=20

Uzb

ekis

tan

00

00

00

00

0010

000

02

0A

TS

F5=

00S

F6=

20

Ven

ezu

ela

00

00

00

00

0010

000

02

0A

TS

F5=

00S

F6=

20

Yem

en0

00

00

00

000

1000

00

20

AT

SF

5=00

SF

6=20

Za

mb

ia1

01

00

02

800

100

011

23

AT

SF

5=28

SF

6=23

Tab

le 2

0. S

i240

1 C

ou

ntr

y Ta

ble

(C

on

tin

ued

)

Si2

401

Re

gis

ter

SF

5S

F5

SF

6S

F6

Co

un

try

OH

S2

OH

SIL

IMR

ZR

T2

RT

Co

mb

ined

MIN

I[1:

0]D

CV

[1:0

]A

CIM

[3:0

]C

om

bin

edA

T C

om

man

d s

trin

g

AN94

84 Rev. 0.31

Table 21. Countries Grouped by Common AT Commands

AT Command string Country

ATSF5=00SF6=20 Argentina

Canada

Chile

Colombia

El Salvador

Guam

Hong Kong

India

Indonesia

Kuwait

Macao

Mexico

Peru

Saudi Arabia

Singapore

Taiwan

UAE

USA

Yemen

Armenia

Bahamas

Belarus

Bermuda

Brunei

Caribbean

China—People's Republic

Costa Rica

Dominican Republic

Dubai

Equador

Georgia

Kyrgyzstan

Moldova

Paraguay

Puerto Rico

Sri Lanka

Tunisia

Ukraine

Uruguay

Uzbekistan

Venezuela

ATSF5=00SF6=90 Japan

Jordan

Oman

Pakistan

Malaysia

Philippines

Qatar

ATSF5=00SF6=24 New Zealand

ATSF5=04SF6=20 Korea

ATSF5=28SF6=23 Bahrain

Bulgaria

Croatia

Egypt

Israel

Lebanon

Morocco

Nigeria

Romania

Algeria

Austria (EU)

Belgium (EU)

Cyprus (EU)

Czech Republic (EU)

Denmark (EU)

Estonia (EU)

Finland (EU)

France (EU)

Germany (EU)

Greece (EU)

Guadeloupe

Hungary (EU)

Iceland (CTR-21)

Ireland (EU)

Italy (EU)

Latvia (EU)

Liechtenstein (CTR-21)

Lithuania (EU)

Luxembourg (EU)

Table 21. Countries Grouped by Common AT Commands (Continued)


AN94

Rev. 0.31 85

Malta (EU)

Martinique

Netherlands (EU)

Norway (CTR-21)

Poland (EU)

Polynesia (French)

Portugal (EU)

Reunion

Slovakia (EU)

Slovenia EU)

Spain (EU)

Sweden (EU)

Switzerland (CTR-21)

Turkey

United Kingdom (EU)

Zambia

ATSF5=10SF6=93 Australia

ATSF5=00SF6=10 Brazil

Kazakhstan

Russia

Thailand

ATSF5=04SF6=23 South Africa

Table 21. Countries Grouped by Common AT Commands (Continued)


AN94

86 Rev. 0.31

Table 22. Si2401 Global Ringer and Busy Tone Cadence Settings

Country RTON RTOF RTOD BTON BTOF BTOD

S19 S1A S1B S16 S17 S18

Australia 0x07 0x03 0x01 0x25 0x25 0x04

Austria 0x12 0x5D 0x0A 0x1E 0x1E 0x03

Belgium 0x12 0x38 0x06 0x32 0x32 0x05

Brazil 0x12 0x4B 0x08 0x19 0x19 0x03

Bulgaria 0x12 0x4B 0x08 0x14 0x32 0x05

China 0x12 0x4B 0x08 0x23 0x23 0x04

Cyprus 0x1C 0x38 0x06 0x32 0x32 0x05

Czech Republic 0x12 0x4B 0x08 0x18 0x24 0x0A

Denmark 0x0E 0x8C 0x0F 0x19 0x19 0x03

Finland 0x0E 0x5D 0x0A 0x1E 0x1E 0x03

France 0x1C 0x41 0x07 0x32 0x32 0x05

Germany 0x12 0x4B 0x08 0x32 0x32 0x05

Great Britain 0x07 0x03 0x01 0x25 0x25 0x04

Greece 0x12 0x4B 0x08 0x1E 0x1E 0x03

Hong Kong, New Zealand 0x07 0x03 0x01 0x32 0x32 0x05

Hungary 0x17 0x46 0x0F 0x1E 0x1E 0x03

Iceland 0x16 0x58 0x09 0x19 0x19 0x03

India 0x07 0x03 0x01 0x4B 0x4B 0x08

Ireland 0x07 0x03 0x01 0x32 0x32 0x05

Italy, Netherlands, Norway, Thailand, Switzerland, Israel

0x12 0x4B 0x08 0x32 0x32 0x05

Japan, Korea 0x12 0x25 0x04 0x32 0x32 0x05

Luxembourg 0x12 0x4B 0x08 0x30 0x30 0x05

Malaysia 0x07 0x03 0x01 0x23 0x41 0x07

Malta 0x00 0x00 0x00 0x00 0x00 0x00

Mexico 0x12 0x4B 0x08 0x19 0x19 0x03

Poland 0x12 0x4B 0x10 0x32 0x32 0x05

Portugal 0x12 0x5D 0x0A 0x32 0x32 0x05

Singapore 0x07 0x03 0x01 0x4B 0x4B 0x08

Spain 0x1C 0x38 0x06 0x14 0x14 0x02

Sweden 0x12 0x5D 0x0A 0x19 0x19 0x03

Taiwan 0x12 0x25 0x04 0x32 0x32 0x05

U.S., Canada (default) 0x25 0x4B 0x08 0x32 0x32 0x05

AN94

Rev. 0.31 87

5. Si2401 Testing

Set SAA=00 prior to going off-hook with ATH1 tomeasure DCI curves.

5.1. CTR-21 Test InstructionsSection B: TEST MODES AND LEVELS

B.1

Please indicate the method for allowing the TE to loopthe line and draw direct current without transmittingsignals of any description:

ATSF6=33SF5=08

ATS07=46DT;

B.2

Please detail the method to enable pseudo random datato be transmitted to line indefinitely in the absence ofcarrier or other signals from the remote end: (The TEshould be capable of being placed in its 'Originate'signal state, with random modulation on the Originatecarrier and of being placed in its 'Answer' carriermodulated by random data)

ATSF6=23SF5=08 must be sent prior to the PTT TestScripts shown below. The specific script to send isdependent on which protocol is desired.

V.21 answer

ATS07=43S33=01S94=00S95=00SE8=04SE5=01SF0=01S83=0B

V.21 originate

ATS07=46S33=01S94=00S95=07SE8=05SE5=0DSF0=01S83=0B

ATS07=43S33=01S94=00S95=00SE8=04SE5=09SF0=01S83=0B

Bell103 answer

ATS07=41S33=01S94=00S95=00SE8=04SE5=03SF0=01S83=0B

Bell103 originate


ATS07=41S33=01S94=00S95=00SE8=04SE5=0BSF0=01S83=0B

V.22 answer

ATS07=42S33=01S94=00S95=01SE8=05SE5=01SF0=01S83=0B

V.22 answer w/ 1800 Hz Guard Tone

ATS07=42S33=01S94=00S95=01SE8=05SE5=11SF0=01S83=0B

V.22 answer w/ 550 Hz Guard Tone

ATS07=42S33=01S94=00S95=01SE8=05SE5=21SF0=01S83=0B

V.22 originate

ATS07=42S33=01S94=00S95=01SE8=05SE5=09SF0=01S83=0B

Bell212a answer

ATS07=40S33=01S94=00S95=01SE8=05SE5=01SF0=01S83=0B

Bell212a originate

ATS07=40S33=01S94=00S95=01SE8=05SE5=09SF0=01S83=0B

V.22bis answer

ATS07=46S33=01S94=00S95=07SE8=05SE5=05SF0=01S83=0B

V.22bis answer w/ 1800 Hz Guard Tone

ATS07=46S33=01S94=00S95=07SE8=05SE5=15SF0=01S83=0B

V.22bis answer w/ 550 Hz Guard Tone

ATS07=46S33=01S94=00S95=07SE8=05SE5=25SF0=01S83=0B

V.22bis originate


V.23 1200 bps transmit



ATS07=64S33=01S94=00S95=00SE8=04SE5=05SF0=01S83=0B

AN94

88 Rev. 0.31



B.3

For MF testing purposes, a continuous digit '9' isrequired. Please indicate below the method of obtainingthis:

ATSF6=23SF5=08

ATS07=46DT;

ATSE8=02SE6=00SE5=49

B.4

If the TE is capable of voice recording, please indicatethe method for the apparatus to seize and indefinitelyhold the line in recording and announcement modeswithout speech or tone transmissions to line.

ATSF6=23SF5=08

ATS07=46

ATDT;

B.5

Please indicate the method of disabling any dial tonedetection:

ATSF6=23SF5=08

ATS07=46

ATDT####

5.2. FCC68 Test InstructionsSection B: TEST MODES AND LEVELS

B.1

Please indicate the method for allowing the TE to loopthe line and draw direct current without transmittingsignals of any description:

apply reset to the Si2401

ATS07=46DT;

B.2

Please detail the method to enable pseudo random datato be transmitted to line indefinitely in the absence ofcarrier or other signals from the remote end: (The TE

should be capable of being placed in its 'Originate'signal state, with random modulation on the Originatecarrier and of being placed in its 'Answer' carriermodulated by random data)

Reset to the Si2401 must be applied prior to the PTTTest Scripts shown below. The specific script to send isdependent on which protocol is desired.

V.21 answer

ATS07=43S33=01S94=00S95=00SE8=04SE5=01SF7=00SF0=01S83=0B

V.21 originate

ATS07=46S33=01S94=00S95=07SE8=05SE5=0DSF7=00SF0=01S83=0B


Bell103 answer


Bell103 originate


ATS07=41S33=01S94=00S95=00SE8=04SE5=0BSF7=00SF0=01S83=0B

V.22 answer


V.22 originate


Bell212a answer


Bell212a originate


V.22bis answer

ATS07=46S33=01S94=00S95=07SE8=05SE5=05SF7

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Rev. 0.31 89

=00SF0=01S83=0B

V.22bis originate








B.3

For MF testing purposes, a continuous digit '9' isrequired. Please indicate below the method of obtainingthis:


ATS07=46DT;

ATSE8=02SE6=00SE5=49

B.4

If the TE is capable of voice recording, please indicatethe method for the apparatus to seize and indefinitelyhold the line in recording and announcement modeswithout speech or tone transmissions to line.


ATS07=46

ATDT;

B.5

Please indicate the method of disabling any dial tonedetection:


ATS07=46

ATDT####;

5.3. In-Circuit TestingThe Si2401’s advanced design provides the systemmanufacturer with increased ability to determine systemfunctionality during production line test as well assupport for end-user diagnostics.

There are many methods to check to discover whetherthe link between the Si2401 and Si3010 is operational.These tests do not require any loop current on the DAA.The first method is to check SF2[3] (FDT). If it is set, theSi2401 and the Si3010 are communicating. Anothermethod is to read SF8[7:4] (LRV) to verify that theSi3010 is properly sending its version number back tothe Si2401. Finally, the voltage between the Si3010VREG pin and the IGND pin may be measured andshould be approximately 2.3 V.

Once the clock, UART, and isolation links are provenfunctional, the production test can proceed to verifyoperation of the discrete components mounted on theboard. In general, there are two approaches to theproduction line test. The first approach is to executecomplete modem connections through a commercially-available telephone line simulator. This approach issimple to implement but incurs a relatively long per-unittest time. If per-unit test time is an importantconsideration, another approach is to use the internaltone generator on the Si2401 to generate a tone at TIP/RING. The Si3010 can be programmed to disable thehybrid (clearing SF1[2] [HBE]), thereby, allowing thetransmitted signal to be looped back through the receivepath. The Si2401 receives the loopback tone andshould be programmed to drive the tone to AOUT. Thisapproach requires loop current consistent with theequivalent circuit shown in Figure 16.Note: AOUT is a PWM signal and requires additional circuitry

to arrive at an analog waveform.

As an example, the following strings can be sent to theSi2401 to set up the 2225 Hz answer tone as thestimulus waveform.

1. ATE0SF1=08SF0=41 to go off-hook and to disable transmit hybrid

2. ATM2SF4=03 to drive AOUT with the received loopback tone from the line.

3. ATSE8=00SE6=00SE5=0BSE8=01SE6=08SE5=FCSE8=00 to set the tone amplitude to –12 dBm.

4. ATSE8=02SE5=04SE6=02 to begin the 2225 Hz answer tone.

With the above strings, a number of points can beprobed to determine if the DAA is functioning properly.Assuming a 30 mA loop current, the dc value of the TIP/RING voltage should be in the neighborhood of 7.5 V.The actual voltage is dependent on the chosen dctermination.

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When the hybrid is disabled, an internal dc offset isrealized. The size of this dc offset is approximately halfscale. To guarantee no clipping under all conditions, a–12 dBm maximum transmit level is recommended. If aslightly distorted signal is acceptable on AOUT, a signalexceeding –12 dBm may be implemented instead usingthe method shown previously in step 3.

To complete the production test, it may be necessary tosimulate a ring signal. A sine wave pulse of 500 ms witha 20 Hz frequency and an amplitude of 35 VRMS issufficient for the Si2401 to return an “R” result code.Additional production tests may be employed to checkthe DAA. For example, a 300 V dc test between TIP andRING can be used to ensure that the hookswitchtransistors are operational and are not leaking anysignificant amount of current. Also, a HIPOT (HighPotential, such as 1500 V) test applied longitudinallybetween TIP/RING and GND can be used to ensurethat the isolation barrier is not bridged inadvertently.

5.4. Board Test

Figure 16. Loop Test Circuit

The modem and DAA chips come from SiliconLaboratories 100% functionally tested on automatic testequipment to guarantee compliance with the publishedchip specifications. The functionality of a finishedproduct containing an ISOmodem chipset depends onnot only the functionality of the modem chipset afterassembly but also discrete parts and product-relatedsoftware. Therefore, finished product test requirementsand procedures depend on the manufacturer and theproduct. Consequently, no universal final test procedurecan be defined.

Testing the modem in a finished product is done forseveral reasons. First, it is important to be sure themodem chipset and peripheral components wereinstalled correctly during assembly and were notdamaged. Second, it is necessary to be sure the correctcomponent values were installed and that there are nomanufacturing problems, such as solder bridges, cold

solder joints, or missing components.

Functional testing can be used to test special features,such as intrusion detection, caller ID, and overcurrentdetection. An intrusion can be simulated by placing a1 k resistor across TIP and RING through a relay.Caller ID testing requires special test equipment, suchas the Advent AI-150.

Many manufacturers choose to use built-in self-testfeatures, such as the test described above. Others do acomplete functional test of the modem by originatingand answering a call and successfully passing a datafile in each direction. This process tests the modem andline-side chip functionality, the associated externalcomponents, and the software controlling the modem.This test can be done with a modem under test (MUT)and a known-good reference modem or between twomodems under test. Testing two modems under test atonce reduces test and setup time. Modem operationaltesting is time consuming and adds to product cost. It isup to the manufacturer to determine whetheroperational testing is warranted.

Analog modems (Bell 103 through V.34) can be testedby connecting the modems through a telephone linesimulator, such as Teltone TLS-3. A call can be placedor received in either direction at the speed set in themodems. A test script must be written for a computer tocontrol the dialing, monitor the call progress, send a file,and compare the received and sent file. Figure 17illustrates this test configuration.

Figure 17. Bell 103–V.34 Modem Functional Test Connection

IL

10 F

600

TIP+

–RING

VTRSi3010>20 mA

Teltone TLS 3

Modem UnderTest

Reference Modem

TestComputer

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Rev. 0.31 91

6. UL1950 3rd Edition

The Si2401 reference design complies with globalsafety standards including the EN60950, UL1950 3rdEdition and UL60950 as long as layout guidelines aremet.

Safety compliance for the United States may requireadditional power cross tests. However, exemption fromall power cross testing can be achieved if the system isshipped with a 26 AWG phone cord, user

documentation is clear, internal DAA spacingrequirements are met, and the system enclosure can beclassified as a fire enclosure. Consultation with a safetycompliance expert early in the product design cycle isrecommended to ensure that this option is available.

If compliance is to be accomplished through actualpower cross testing, an additional fuse (Teccor F1250Tor equivalent) or PTC (Raychem TR600-150) isrecommended. See circuit in Figure 18 for placement.

Figure 18. Fuse/PTC placement

RV1

Fuse/PTC

TIP

RING

1.25 A

DA

A B

OM

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92 Rev. 0.31

APPENDIX A—ISOMODEM® LAYOUT GUIDELINES

Layout Guidelines

The key to a good layout is proper placement ofcomponents. It is best to copy the placement shown inFigure 19. Alternatively, perform the following steps,referring to the schematics and Figure 20. It is stronglyrecommended that the checklist in Table 22 becompleted while reviewing the final layout.

1. All traces, open pad sites and vias connected to the following components are considered to be in the DAA section, and must be physically separated from non-DAA circuits by 5 mm to achieve best possible surge performance: R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R15, R16, U2, Z1, D1, FB1, FB2, RJ11, Q1, Q2, Q3, Q4, Q5, C3, C4, C5, C6, C7, C8, C9, C10, RV1, C1 pin 2 only, C2 pin 2 only, C8 pin 2 only, C9 pin 2 only.

2. The Isolation Capacitors C1, C2, C8 and C9 are the only components permitted to straddle between the DAA section and non-DAA section components and traces. This means that for each of these capacitors, one of the terminals is on the DAA-side, the other is not. Maximize the spacing between the terminals (between pin 1 to pin 2) of each of these capacitors.

3. Place and group the following components: U1, U2, R12, R13, C1, C2.

a.U1 and U2 are placed so that the right side of U1 faces the left side of U2.

b.C1 and C2 should be placed directly between U1 and U2.

c.Keep R12 and R13 close to U1.

d.Place U1, U2, C1, and C2 so that the recommended minimum creepage spacing for the target application is implemented.

e.Place C1 and C2 so that traces connected to U2 pin 5 (C1B) and U2 pin 6 (C2B) are physically separated from traces connected to:

i.C8, R15, FB1

ii.C9, R16, FB2

iii.U2 pin 8, R7

iv.U2 pin 9, R9

4. Place and group the following components around U2: C4, R9, C7, R2, C5, C6, R7, R8. These components should form the critical 'inner circle' of components around U2.

a.Place C4 close to U2 pin 3. This is best achieved by placing C4 northwest of U2.

b.Place R9 close to U2 pin 4. This is best achieved by placing R9 horizontally, directly to the north of U2.

c.Place C7 close to U2 pin 15. This is best achieved by placing C7 next to R9.

d.Place R2 next to U2 pin 16. This is best achieved by placing R2 northeast of U2.

e.Place C6 close to U2 pin 10. This is best achieved by placing C6 southeast of U2.

f.Place R7 and R8 close to U2. This is best achieved by placing these components to the south of U2.

g.Place C5 close to U2 pin 7. This is best achieved by placing C5 southwest of U2.

5. Place Q5 next to R2 so that the base of Q5 can be connected to R2 directly.

6. Place Q4 such that the base of Q4 can be routed to U2 pin 13 easily, and that the emitter of Q4 can be routed to U2 pin 12 easily. Route these two traces next to each other so that the loop area formed by these two traces are minimized.

7. Place and group the following components around the RJ11 jack: FB1, FB2, RV1, R15, R16, C8 and C9.

a.Use 20 mil width traces on this grouping to minimize impedance.

b.Place C8 and C9 close to the RJ11 jack, recognizing that, a GND trace will be routed between C8 and C9, back the Si2401GND pin, through a 20-mil width trace. The GND trace from C8 and C9 must be isolated from the rest of the Si3010 traces.

c.The trace from C8 to GND and the trace from C9 to GND must be short and equidistant.

8. After the previous step, there should be some space between the grouping around U2 and the grouping of components around the RJ11 jack. Place the rest of the components in this area, given the following guidelines:

a.Space U2, Q4, Q5, R1, R3, R4, R10 and R11 away from each other for best thermal performance.

b.The tightest layout can be achieved by grouping R6, C10, Q2, R3, R5 and Q1.

c.Place C3 next to D1.

d.Make the size of the Q3, Q4, and Q5 collector

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Rev. 0.31 93

pads each large enough for the transistor to safely dissipate 0.5 W under worst case conditions. See the transistor data sheet for thermal resistance and maximum operating temperature information. Implement collector pads on solder side as well and use vias between the component and solder side pads to improve heat transfer for best performance.

9. U2 pin 15 is also known as IGND. This is the ground return path for many of the discrete components, and requires special mention

a.Route traces associated with IGND using 20 mil traces.

b.The area underneath U2 should be ground-filled and connected to IGND (U2 pin 15). Ground fill both solder side and component side and stitch together using vias.

c.C5, C6, C7 IGND return path should be direct.

d.The IGND plane must not extend past Q4 and Q5.

10.The traces from R7 to FB1 and from R8 to FB2 should be well matched. This can be achieved by routing these traces next to each other as possible. Ensure that these traces are not routed close to the traces connected to C1 or C2.

11.Minimize all traces associated with Y1, C40, and C41.

12.Decoupling capacitors (size 0.22 µF and 0.1 µF capacitors connected to VA, VD) must be placed next to those pins. Traces of these decoupling capacitors back to the Si2401 GND pin should be direct and short.

Figure 19. Reference Placement

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94 Rev. 0.31

Figure 20. Illustrated Layout Guidelines

GNIR

PIT

A4B4

C4

D4

E4F4

G4F4

5

6

A3

E3 C3

B3A3

E3

E3

E3E3

A7

C7C7B7 B7B7

A9

01

01

11

2121

21

11

C8

D8

D8

B9

C9C9

C9

11

2

2

22

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1 ,secarT saiv dna setis dap desolcne AAD eht ni era xob ni ,noitces detarapes eb tsum dna lla morf .mm 5 yb stiucric rehto

eht ni debircsed era secnerefer delcricnE :etoN derebmun .A xidneppA ni shpargarap

9R

8R

9C

2BF

14C

1VR

21R

+-

1D

7R

61R

1C

5C

8C

05C

1Y1 2

1042iS1U

ILATX1

OLATX2

DV4

DNG12

A1C 01

A2C 9

AV13

0103iS2U

EQ1

TCD2

XR3

BI4

B1C5

B2C6

GERV7

1GNR8

2TCD 61

DNGI 51

3TCD 41

BQ 31

2EQ 21

CS 11

2GERV 01

2GNR 9

51R

04C

5Q

2R

2C

7C

4Q

+

4C

6C

1BF

15C

31R

3C

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Rev. 0.31 95

Si2401 Layout Check ListFigure 23 is a checklist that the designer can use during the layout process to ensure all the recommendations inthis application note have been implemented.

Table 23. Si2401 Layout Check List

# Layout Items Required

1 U1 and U2 are placed so that pins 9–16 of U1 are facing pins 1–8 of U2. C1 and C2 are placed directly between U1 and U2.

2 Place U1, U2, C1, and C2 so that the recommended minimum creepage spacing for the target application is implemented. R12 and R13 should be close to U1.

3 C1 and C2 should be placed directly between U1 and U2. Short, direct traces should be used to connect C1 and C2 to U1 and U2. These traces should never be longer than two inches and should be minimized in length. Place C2 such that its accompanying trace to the C2B pin (pin 6) on the Si3010 is not close to the trace from R7 to the RNG1 pin on the Si3010 (pin 8).

4 Place R7 and R8 as close as possible to the RNG1 and RNG2 pins (pins 8 and 9), ensuring a minimum trace length from the RNG1 or RNG2 pin to the R7 or R8 resistor. In order to space the R7 component further from the trace from C2 to the C2B pin, it is acceptable to orient it 90 degrees relative to the RNG1 pin (pin 8).

5 The area of the loop from C50 to U1 pin 4 and from C51 to pin 13 back to pin 12 (DGND) should be minimized. The return traces to U2 pin 12 (DGND) should be on the compo-nent side.

6 The loop formed by XTALI, Y1, and XTALO should be minimized and routed on one layer. The loop formed by Y1, C40, and C41 should be minimized and routed on one layer.

7 The digital ground plane is made as small as possible, and the ground plane has rounded corners.

8 Series resistors on clock signals are placed near source.

9 Use a minimum of 15 mil width traces in DAA section, use a minimum of 20 mil width traces for IGND.

10 C3 should be placed across the diode bridge, and the area of the loop formed from Si3010 pin 11 through C3 to the diode bridge and back to Si3010 pin 15 should be mini-mized.

11 FB1, FB2, and RV1 should be placed as close as possible to the RJ11.

12 C8 and C9 should be placed so that there is a minimal distance between the nodes where they connect to chassis ground.

13 Use a minimum of 20 mil wide trace from RJ11 to FB1, FB2, RV1, C8, C9, and F1.

14 The routing from TIP and RING of the RJ11 through F1 to the ferrite beads should be well matched.

15 The traces from the RJ11 through R7 and R8 to U2 pin 8 and pin 9 should be well matched. These traces may be up to 10 cm long.

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16 Distance from TIP and RING through EMC capacitors C8 and C9 to chassis ground is short.

17 There should be no digital ground plane in the DAA Section.

18 Minimize the area of the loop from U2 pin 7 and pin 10 to C5 and C6 and from those components to U2 pin 15 (IGND).

19 R2 should be placed next to the base of Q5, and the trace from R2 to U2 pin16 should be less than 20 mm.

20 Place C4 close to U2 and connect C4 to U2 using a short, direct trace.

21 The area of the loop formed from U2 pin 13 to the base of Q4 and from U2 pin 12 to the emitter of Q4 should be minimized.

22 The trace from C7 to U2 pin 15 should be short and direct.

23 The trace from C3 to the D1/D2 node should be short and direct.

24 Provide a minimum of 5 mm creepage (or use the capacitor terminal plating spacing as a guideline for small form factor applications) from any TNV component, pad or trace to any SELV component, pad or trace.

25 Minimize the area of the loop formed from U2 pin 4 to R9 to U2 pin 15.

26 Cathode marking for Z1.

27 Pin 1 marking for U1 and U2.

28 Space and mounting holes to accommodate for fire enclosure if necessary.

29 IGND plane does not extend under C3, D1, FB1, FB2, R15, R16, C8, C9, or RV1.

30 Size Q3, Q4, and Q5 collector pads to safely dissipate 0.5 W (see text).

31 Submit layout to Silicon Laboratories for review.

Table 23. Si2401 Layout Check List (Continued)

# Layout Items Required

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Module Design and ApplicationConsiderations

Modem modules are more susceptible to radiated fieldsand ESD discharges than modems routed directly onthe motherboard because the module ground plane isdiscontinuous and elevated above the motherboardground plane. This separation also creates thepossibility of loops that couple these interfering signalsto the modem. Additionally, system designers canadversely impact the ESD and EMI immunity andperformance of a properly-designed module with a poormotherboard layout.

Module DesignParticular attention should be paid to power supplybypassing and reset line filtering when designing amodem module. Trace routing is normally very short onmodules since they are generally designed to be assmall as possible. Care should be taken to use groundand power planes in the low-voltage circuitry wheneverpossible and to minimize the number of vias in theground and power traces. Ground and power shouldeach be connected to the motherboard through one pinonly to avoid the creation of loops. Bypassing andfiltering components should be placed as close to themodem chip as possible with the shortest possibletraces to a solid ground. It is recommended that a pi

filter be placed in series with the module VCC pin with afilter, such as the one shown in Figure 21, on the resetline. This filter also provides a proper power-on reset tothe modem. Careful module design is critical since themodule designer frequently has little control over themotherboard design and the environment the modulewill be used in.

Motherboard DesignMotherboard design is critical to proper modem moduleperformance and immunity to EMI and ESD events.First and foremost, good design and layout practicesmust be followed. Use ground and power planeswhenever possible. Keep all traces short and direct.Use ground fill on top and bottom layers. Use adequatepower supply bypassing and use special precautionswith the power and reset lines to the modem module.Bypass VCC right at the modem module connector. Besure the modem module is connected to VCC through asingle pin. Likewise, be sure ground is connected to themodem module through one pin connected to themotherboard ground plane. The modem reset line issensitive and must be kept very short and routed wellaway from any circuitry or components that could besubjected to an ESD event. Finally, mount the modemmodule as close to the motherboard as possible. Avoidhigh-profile sockets that increase the separationbetween the modem module and the motherboard.

Figure 21. Modem Module VCC and RESET Filter

RESET

MotherboardConnector

1.0 F .01 F .01 F 1.0 F10 k

2.2 F

To RESET

GND

To Modem Chip V D(Si2401 pin 4)

(Si2401 pin 8)

GND

3.3 V

Murata BLM 21A G601 SN1

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APPENDIX B—PROTOTYPE BRING-UP GUIDE

Introduction

This appendix provides help with the debugging of initialprototypes. Although most ISOmodem prototypedesigns function as expected, there is the potential forlayout errors, omitted or incorrect components used inthe initial assembly run, and host software problems. Ifthe prototype modem does not function correctly, thetechniques outlined in this guide will help quickly isolatethe problem and get the prototype functioning correctly.A functional Si2401URT-EVB and data sheet and acomputer with HyperTerm is required for some of thetroubleshooting steps. It is assumed that the designerhas read the data sheet, used the reference design andrecommended bill-of-materials, and has carefullyfollowed the layout guidelines presented in“Appendix A—ISOmodem® Layout Guidelines”. Thetroubleshooting steps begin with system-level checks,and then proceed to the component level.

Visual InspectionBefore troubleshooting, be certain that the circuit boardsand components are clean. Carefully wash the boardsto remove all solder flux and solder flakes. Inspect themodem circuitry to ensure all components are installed,and inspect all solder joints for incomplete connections,cold solder joints, and solder bridges. Check allpolarized components, such as diodes, Zener diodes,and capacitors for correct orientation. Thoroughly cleanthe circuit board after replacing a component orsoldering any connections.

Reset the ModemBe sure the modem is properly reset after power isapplied and stable.

Basic Troubleshooting Steps

Check PowerWith power off, use an Ohm meter to verify system ground is connected to Si2401 pin 12. Turn on system power and measure the voltage between pin 4 and pin 12 and between pin 13 and pin 12 on the Si2401. In both cases, the voltage should be 3.3 V. If this is not the case, check the power routing. If power is present, go to the next step.

Check Phone LineCheck the phone line with a manual telephone to be sure there is a dial tone and dialing is possible. The dc voltage across TIP and RING should read approximately 40–52 V with the phone on-hook.

Reset ModemDo a manual reset on the modem. Hold Si2401 pin 8 (RESET) low for 300 ms, return to VDD (3.3 V) in less than 5 ms and wait for at least 300 ms before executing the first AT command.

Check DTE SetupBe sure the DTE (Host) serial port is configured the same as the modem. The default condition is eight data bits, no parity-bit, one stop-bit, and a DTE rate of 2400 bps.

Check DTE ConnectionCheck the DTE interface connection. Be sure the CTS (Si2401 pin 7) signal is low.

Check pullup/pulldown configuration resistor.

Check modem configuration

Read back the modem register settings and correct anyinconsistencies. Use the ATSR or ATr# commands tolist the contents of the S-Registers.

If the problem was not located with these basictroubleshooting steps, it is time to narrow the problemdown to the host system (hardware and software), theSi2401 chip (and associated components), or theSi3010 (and associated components).

AT OK?

The modem responds with an “O” to the command“AT<cr>.”

This indicates the host processor/software iscommunicating with the modem controller and problemsare in one of the following areas:

Inappropriate CommandsVerify that all AT commands used are supported by the Si2401 and comply with the proper format. Be sure the command and argument are correct. Do not mix upper and lower case alpha characters in an AT command (except the “r”, “m”, “q”, and “w” commands).

Command TimingThe execution time for an AT command is approximately 200 ms. Execution is complete when the “O” is received. Subsequent AT commands should wait for the “O” message, which appears within 100 ms after the carriage return. The reset recovery time (the time between a hardware reset or the carriage return of an ATZ command and the time the next AT command can be executed) is approximately 100 ms. When a data connection is being established, do not try to escape to the

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command mode until after the protocol message.

Si3010 and/or Associated Components If the modem goes off-hook and draws loop current as a result of giving the ATH1 command, go to the Si3010 Troubleshooting section.If the modem does not go off-hook and draw loop current as a result of giving the ATH1 command and receiving an “O” message, begin troubleshooting on the Si2401 side of the isolation barrier. First check all solder joints on the isolation capacitors, Si3010, and associated external components. If no problems are found, proceed to the following Troubleshooting section to verify whether the problem is on the Si2401 or the Si3010 side of the isolation capacitors. If the problem is found to be on the Si2401 side, check C50, C51, C53, the corresponding PCB traces, and Si2401 pins. Correct any problems. If no problems are found with the external components, replace the Si2401.If the problem is found to be on the Si3010 side of the isolation barrier, go to the Si3010 Troubleshooting section.If the modem does NOT respond with an “O” to the command ”AT<cr>,”this indicates the host processor/software is not communicating with the modem controller, and the problem can be isolated as follows.

Si2401 Clock is OscillatingFirst be sure the Si2401 is properly reset and RESET, pin 8, is at 3.3 V. Next, check the DTE connection with the host system. If this does not isolate the problem, go to the Host Interface Troubleshooting section.

Si2401 Clock is Not OscillatingCheck the voltage on the Si2401, pin 4, to be sure the chip is powered. Also, check that pin 12 is grounded. Next, check the solder joints and connections (PCB traces) on C40, C41, Y1 and the Si2401 pin 1 and pin 2. Measure C26 and C27 (or replace them with known good parts) to ensure they are the correct value. If these steps do not isolate the problem, replace the Si2401.

Host Interface Troubleshooting

The methods described in this section are useful as astarting point for debugging a prototype system or as acontinuation of the troubleshooting process describedabove. The procedures presented in this section requirea known good Si2401URT-EVB evaluation board anddata sheet. This section describes how to substitute theevaluation board for the entire modem circuitry in theprototype system. Substituting a known operationalmodem can help to quickly isolate problems. The firststep is to substitute the evaluation board for the

complete modem solution in the prototype system. Thisdemonstrates immediately whether any modemfunctionality problems are in the prototype modemcircuitry or in the host processor, interface, or software.

Verify Si2401URT-EVB FunctionalityConnect the evaluation board to a PC and a phone line or telephone line simulator. Using a program such as HyperTerm, make a data connection between the evaluation board and a remote modem. Remove power and the RS232 cable from the evaluation board and proceed to the next step.

Connect Evaluation Board to Prototype SystemCompletely disconnect the embedded modem from the host interface in the prototype system. Connect the Si2401URT-EVB to the host interface using JP3 as described in the Si2401URT-EVB data sheet section titled Direct Access Interface. This connection is illustrated in Figure 22. Be sure to connect the evaluation board ground to the prototype system ground. Power up and manually reset the evaluation board then power up the prototype system and send “AT<cr>.” If an “OK” response is received, make a connection to the remote modem as in the previous step. If no “OK” response is received, debug host interface and/or software. If a connection is successfully made, go to the next step to isolate the problem in the prototype modem.An alternative approach is to connect the prototype modem to the Si2401URT-EVB motherboard in place of the daughter card and use a PC and HyperTerm to test the prototype modem. See Figure Figure 23 for details.

Troubleshooting

Connect Evaluation Board to Prototype Modem Si3010.Remove C1 on the evaluation board and on theprototype system. Solder one end of the evaluationboard, C1, to the Si2401-side pad leaving the other endof C1 unconnected. Next, solder a short jumper wirefrom the unconnected side of C1 on the evaluationboard to the Si3010-side C1 pad on the prototypesystem. This connection is illustrated in Figure 24.Connect the phone line to the prototype system RJ-11jack.

Power up and manually reset the evaluation board, thenpower up the prototype system. Attempt to make aconnection using the host processor and software, theevaluation board Si2401 and the prototype systemSi3010 and associated external components. If thisconnection is successful, the problem lies with the PCBlayout, the external components associated with theSi2401 or the Si2401 device itself.

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If the connection attempt is not successful, the problemlies with the Si3010 and/or associated components.Proceed to the section, “Si3010 Troubleshooting”.

This diagnosis can be validated by connecting the Hostisolation capacitors to the Si3010 on the evaluationboard as shown in Figure 25.

Si3010 Troubleshooting

Start by measuring the on-hook and off-hook voltages atthe Si3010 pins with respect to IGND (pin 15). Comparethese voltages to those in Figure 26. This may indicatean area of circuitry to investigate further using theComponent Troubleshooting techniques. The voltagesyou measure should be close to (although not exactlythe same as) those in the figure.

If any of the on-hook and off-hook Si3010 pin voltagesare grossly different than those in Figure 26 and nothingseems wrong with the external circuitry after using theComponent Troubleshooting techniques, replace theSi3010.

Component Troubleshooting

A digital multi-meter is a valuable tool to verifyresistance across components, diode direction,transistor polarity and node voltages. During this phaseof troubleshooting, it is highly useful to have a knowngood Si2401URT-EVB to compare againstmeasurements taken from the prototype system. Theresistance values and voltages listed in Tables 24, 25,and 26 will generally be sufficient to troubleshoot all butthe most unusual problem.

Start with power off and the phone line disconnected.Measure the resistance of all Si3010 pins with respectto pin 15 (IGND). Compare these measurements withthe values in Table 24. Next, measure the resistanceacross the components listed in Table 25 and comparethe readings to the values listed in the table. Finally,using the diode checker function on the multi-meter,check the polarities of the transistors and diodes asdescribed in Table 26. The combination of thesemeasurements should indicate the faulty component orconnection. If none of the measurements appearsunusual and the prototype modem is not working,replace the Si3010.

Figure 22. Test the Host Interface

HostController

HostUART Si2401 Si3010 Discretes

RS232Transceiver Si2401 Si3010 Discretes

EVB

Prototype System

ToPhoneLine

Connect prototype system ground to EVB ground Disable RS232 transceiver outputs (check evaluation board data sheet) Disconnect prototype modem interface Connect the evaluation board to the target system

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Rev. 0.31 101

Figure 23. Test the Prototype Modem

Figure 24. Test the Prototype Si3010 Circuitry

HostController



EVB

Prototype System

Connect prototype system ground to EVB ground Remove modem module from EVB Disconnect host outputs from prototype modem Connect EVB RS232 transceivers to prototype modem Use PC with HyperTerminal to test prototype modem

ToPhoneLine

PC

ToPhoneLine

HostController



EVB

Connect the prototype ground to the EVB ground. Lift prototype C1 and C2 and EVB C1 and C2 so the Si3010 is disconnected from the Si2401 on both

modems . Connect EVB C1 and C2 to the Si3010 pad of prototype system C1 and C2. Connect the phone line to the RJ11 jack on the prototype system. Use PC and HyperTerm and attempt to establish a modem connection.

PC

C2

C1

C2

Prototype SystemC1

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102 Rev. 0.31

Figure 25. Verify Prototype Si3010 Failure

Figure 26. Si3010 Typical Voltages

ToPhoneLine

HostController



EVB

Connect the prototype ground to the EVB ground Lift prototype and EVB C1 and C2 to decouple the line side from the DSP side. Do same on evaluation board. Connect prototype system C1 and C2 to the Si3010 pad of EVB C1 and C2 Connect the phone line to the RJ11 jack on the EVB Run the prototype system softw are to attempt a modem connection

C2

C1

C2

C1Prototype System

On-Hook

0 V

~1.0 V

~2.3 V

0.7

0.8 V

0 V

0 V

0 V

QE

RNG1

VREG

C2B

C1B

IB

RX

DCT

0 V

~1.0 V

0 V

0 V

0 V

0 V

0 V

DCT2

RNG2

VREG2

SC

QE2

QB

DCT3

IGND

Off-Hook

1.6 V

1.0 V

2.3 V

0.8 V

0.8 V

0 V

2.5 V

3.4 V

QE

RNG1

VREG

C2B

C1B

IB

RX

DCT

2.2 V

0.9 V

1.8 V

0 V

2.1 V

2.8 V

1.6 V

Reference

DCT2

RNG2

VREG2

SC

QE2

QB

DCT3

IGND

Voltages measured with respect to IGND (Si3010 pin 15)

Reference

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Rev. 0.31 103

Table 24. Resistance to Si3010 Pin 15

Si3010 Resistance

Pin 1 >6 M

Pin 2 >5 M

Pin 3 >2 M

Pin 4 1 M

Pin 5 >5 M

Pin 6 >5 M

Pin 7 >1 M

Pin 8 >2 M

Pin 9 >2 M

Pin 10 >1 M

Pin 11 0

Pin 12 >2 M

Pin 13 >5 M

Pin 14 >14 M

Pin 16 >5 M

Table 25. Resistance across Components

Si3010 Resistance

FB1 <1

FB2 <1

RV1 >20 M

R1 1.07 K

R2 150

R3 3.65 K

R4 2.49 K

R5 100 K

R6 100 K

R7 4.5 M or 16 M

R8 4.5 M or 16 M

R9 >800 k

R10 536

R11 73

R12 <1

R13 <1

R15 <1

R16 <1

C1 >20 M

C2 >20 M

C3 >3 M

C4 3.5 M or 9.7 M

C7 2 M or 5 M

C8 >20 M

C9 >20 MNote: If two values are given, the resistance measured is

dependent on polarity.

Table 26. Voltage across Components with Diode Checker

Component Voltage

Q1, Q3, Q4, Q5Base to EmitterBase to CollectorVerifies transistors are NPN

0.6 V0.6 V

Q2Emitter to BaseCollector to BaseVerifies transistor is PNP

0.6 V0.6 V

Q2 collector to Si3010 pin 1If test fails, Z1 is reversed

>1 V

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104 Rev. 0.31

Si2401 Host Software Design Checklist and Troubleshooting

Introduction

The following information is intended to aid thedevelopment of an Si2401 application. The pointscontained in the design checklist must be carefullyconsidered before a design incorporating the Si2401 iscompleted. While it is impossible to cover all issues forevery design, the important topics for most systems,including a modem, are discussed. In addition to adesign checklist, a troubleshooting guide is presented.This guide offers tips for debugging potential problemsinvolving the integration of the Si2401 chipset into asystem.

Design ChecklistIn most applications the exact conditions and physicalenvironment of the modem in the field are variable.Therefore, it is generally a good idea to include somesoftware on the host that can adapt to the changingconditions the modem might encounter. Some of thevariables a system could encounter in the field are asfollows:

Is the phone line extremely noisy or does it exhibit adverse conditions in relation to one of the modem algorithms?

Is the modem connected to a phone line?

Does the phone line supply a dial tone?

Does the phone line support tone dialing or pulse dialing only?

The following host software checklist will help handlethese situations.

Software fallback mechanism.

Because the V.22bis algorithm does not includeautomatic fallback, the host must supply a fallbackmechanism to deal with extremely noisy or adverse lineconditions. It is highly recommended that any hostsoftware include this simple feature to absolutely ensuremodem connections will be established by your productin the field. One thing to note is that the V.22bisalgorithm allows for connection at 1200 bps if theconnecting modem is a V.22 modem. This is not thesame as a retrain. The following steps outline an easyprocedure to implement a fallback mechanism:

1. Set the Si2401 to V.22bis mode and attempt a connection (ATS07=06ATDT#). If the Si2401 does not connect (“c” result code echoed if the other modem is V.22bis compatible, and “d” result code of the other modem is V.22 only), then the host should hang up the modem and go to step 2.

2. Set the Si2401 to V.22 mode and attempt a connection (ATS07=02ATDT#). If the Si2401 does not connect (“c” result code), then the host should hang up and go to step 3.

3. Set the Si2401 to V.21 mode or Bell 103 mode and attempt a connection (ATS07=03ATDT# or ATS07=01ATDT#).

Because each of the different modem protocols usedifferent algorithms, the likelihood of establishing aconnection under any line conditions is extremely highusing these steps.

Software checks phone line connection.

Check the value of SDB (ATSDB?) while on-hook. If thereading of this register is anything other than 0x00, theSi2401 is connected to an active phone line.

Software checks for parallel phone off-hook.

Several methods for implementing this are detailed inthe Si2401 data sheet and the troubleshooting guide.

Software checks dial tone.

The host software must comprehend that afterattempting to dial (ATDT# or ATDP#), the first responseechoed by the Si2401 will be a “t” if a dial tone ispresent and an “n” followed by a hang up if no dial toneis present. Additionally, the following procedure may beused to check for dial tone before any attempt is madeto dial out: Issue the command “ATS01=01S02=01” (orany arbitrarily small number). S01 sets the number ofseconds the modem waits after going off-hook beforedialing, and S02 sets the number of seconds themodem waits for a dial tone before hanging up. Nextissue the command “ATDT5;” (the 5 is arbitrary), if thereis no dial tone, the Si2401 will hang up and echo an “n”.If there is a dial tone the Si2401 will echo a “t”.

Software checks phone line for tone or pulsedialing support.

One method to check for tone dialing is to simply try toconnect with “ATDT#”, and if unsuccessful try toconnect with “ATDP#”. Additionally, the Si2401 has anautomatic tone/pulse detect dial modifier. See "ATCommand Set Description" on page 18 for more details.

Software checks for off-hook parallel phoneintrusion.

To check for a parallel phone intrusion while the Si2401is off-hook, the host must configure GPIO4 (or ninth bit)as the ALERT pin and send AT:I when ALERT is set asdescribed in the Si2401 data sheet.

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Rev. 0.31 105

TroubleshootingThe following sections describe some of the features ofthe Si2401 and the related areas where a correctionmay be found. Additionally, these sections discussdesign tips and deliver a more detailed description ofeach feature than is provided in the Si2401 andSi2401URT-EVB data sheets.

Parallel Phone Detection

The Si2401 includes an automatic parallel phoneintrusion detection algorithm while off-hook. While theSi2401 is off-hook it continually monitors for parallelphone intrusions. The INTb pin (or ninth bit INTb) mustbe enabled (ATSE2=C0). The two most significant bitsenable INTb, the others can be any value(SE2[GPIO] = 11xx,xxxxb). When an intrusion isdetected, it pulls the INTb pin high and the hostprocessor must act on the intrusion or ignore it. TheINTb function is a sticky bit and must be cleared bysending AT:I.

UART

Care should be taken to ensure that the host UART andSi2401 UART are set to the same rate. In particular, aV.22bis connection has the ability to fallback to1200 baud if the other modem only supports V.22. Inthis case, the Si2401 will echo a “d” instead of “c”.

If CTS flow control is not implemented, it is necessaryupon receipt of the “d” to escape into command mode,change the Si2401 UART to 1200 baud, change thehost UART to 1200 baud, and put the Si2401 back online with “ATO”. If CTS is implemented, then thisprocedure is not necessary. The use of CTS isrecommended to simplify the host software.

The Si2401 UART is also capable of different baudrates separate from the line rate. It is configurable viaregister SE0 to be 300, 1200, 2400, 9600, 19200,38,400, 115,200, and 307200 bps. When programminga new baud rate, the following procedure should befollowed (example shows a change to 9600 baud).

1. Issue the command “ATSE0=23”.

2. Wait for the host UART to empty, indicating that the entire command has been sent.

3. Change the host UART to 9600 baud.

4. Issue a carriage return to ensure that the Si2401 is ready to accept a new command.

For most applications, it is recommended that theSi2401 UART be set to 9600 baud, and to implementCD handshaking. This setting allows for the widestmargin under varying DCE rate conditions.

Reset

RESET is the only method to return all of the Si2401registers to their power-up state. (“ATZ” does not affectSE0, SE2, SE4, SE5, SE6, SE7, SEA, SF8, SF9 orinternal registers.) Reset is also the only way to take theSi2401 out of total powerdown mode. For thesereasons, it is recommended that reset be connected toa software controllable pin. It is also important that resetmeets the specifications in the data sheet (held low forat least 5 ms). During RESET, CTS should be held high.This can be implemented with a pull-up resistor to VCC.After releasing RESET, the host must wait 3 ms prior totransmitting any characters to the Si2401.

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106 Rev. 0.31

APPENDIX C—TRANSITIONING FROM THE Si2400 TO THE Si2401

Overview

The new Si2401 ISOmodem chipset integrates SiliconLaboratories third-generation DAA technology withmany new and improved features. While the Si2401 islargely software compatible with the Si2400, there are afew changes that must be considered. This document isintended to ease software transition and reducedevelopment time for existing Si2400 ISOmodemcustomers redesigning with the Si2401. For mostcustomers, only minor Si2400 software changes will berequired to be compatible with the Si2401, such as newDAA register settings. Utilizing the Si2401’s enhancedfeatures and updated register settings may also requiresoftware changes.

Enhanced featuresThe Si2401 has several new features that may requiresoftware changes; a summary of these features is listedin Table 27. Refer to the Si2401 data sheet for a moredetailed functional description.

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Rev. 0.31 107

Table 27. Enhanced Si2401 Features

Feature Description

27 MHz clock input A 27 MHz clock input option has been added to the Si2401. To enable this option, a pulldown resistor <10 k must be placed between GPIO4 (pin 11) and GND. The Si2401 default clock mode (no resistor present on pin 11) requires a 4.9152 MHz crystal or clock input.

Transmit FIFO The Si2401 has an integrated 10-byte transmit FIFO and allows for two distinct CTS reporting methods. By default, Si2401 CTS operation is the same as the Si2400; every incoming byte causes a CTS transition. However, on the Si2401, the host pro-cessor can continue to send up to 9 more bytes after CTS asserts. In addition, by programming the transmit control register TC (SFC) to 0x80, CTS is asserted when the FIFO is ¾ full and cleared when the FIFO is ¾ empty.

Line voltage monitoring Line voltage monitoring has improved from a resolution of 3 V to 1 V with a 127 V range. Tip and ring polarity are reported, and the Si2401 has the capability of return-ing line voltage while off-hook.

Line current monitoring Line current monitoring resolution has improved from 3 mA to 1.1 mA allowing more accurate control over the off-hook intrusion algorithm. The Si2401 has a loop cur-rent reporting range of 120 mAs.

Interrupt reporting An interrupt status register INTS (S09) and an interrupt mask register INTM (S08) were created to simplify software design. A new command has been added (AT:I), which reports the contents of INTS and clears the GPIO pin automatically without writing to the GPIO data register GPD (SE3).

Ring detection Ring detection offers more flexibility for detecting distinctive rings.

GPIO5 / RI pin Pin 3 has been programmed to function as a general purpose input/output (GPIO) pin or a ring indicator pin.

DTE rates New DTE rates are available. The 228,613 bps and 245,760 bps rates have been replaced by the more common 38,400 bps and 115,200 bps rates.

Echoing Unlike the Si2400, the Si2401 does not echo in data mode. Also, the Si2401 defaults to verbose mode (ATV1), which proceeds and follows each response with a carriage return and linefeed. Like the Si2400, command echoing occurs in com-mand mode.

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108 Rev. 0.31

Register ChangesTo accommodate the third generation DAA and other new features, several registers have been modified. Ifsoftware written for the Si2400 utilizes the registers listed in Table 28, the software may need to be modified inorder to support the Si2401.0

Table 28. Modified Register Settings

Register Si2400

Name

Si2401

Name

Si2400 Function Si2401 Function

S07 MF1 MF1 Bit 7—HDLC enable (moved to S13) Reserved

S08 MNRP INTM Minimum ring period 1 Interrupt mask 2

S09 MXRP INTS Maximum ring period 1 Interrupt status 2

S0A ROT — Ringer off time 1 Reserved

S0B MNRO — Minimum ringer off time 1 Reserved

S0D RPE — Ringer off time allowed error 1 Reserved

S11 ONHI OFHI On-hook intrusion settings 3 7:4—Reserved3:0—Differential current level

S12 OFHI ACL Off-hook intrusion settings Absolute current level

S13 MF3 MF3 Bit 7—Japan CID Bit 3—On-hook intrusion methodBit 1—Bellcore CID (moved to S0C)Bit 0—PCM data mode

Bit 7—Reserved Bit 3—Reserved Bit 1—HDLC enable Bit 0—Reserved

S14 MF4 — Bit 7—Disable result codes (Now con-trolled by S62) Bit 5—TIES EnableBits 3:0—Line status (moved to S09)

By default TIES is enabled, to disable set register S10 to 0xFF.

S33 MDMO MDMO Bit 6—On-hook intrusion disable3

Bit 5—Off-hook intrusion disableBit 6—ReservedBit 5—Reserved

S3B RP — Minimum number of ring pulses per ring burst1

Reserved

SD1 INTS — Intrusion state Reserved

SDB LVCS LVS LVCS LVS—A 2s complement number with finer resolution.2

SE0 CF1 CF1 DTE rates 228613 and 245760 removed.

DTE rates 38400 and 115200 added.

SE1 CLK1 GPIO1 Bits 7:6—Microcontroller clock rateBit 5—ReservedBit 4:0—CLK_OUT divider

Bits 7:2—Reserved (Clock rate is no longer programmable)Bits 1:0—CLK_OUT is now a GPIO 2

SE2 GPIO GPIO2 GPIO register settings AIN option on GPIOs removedALERT is now INTb (active low)GPIO4 can be used as AOUT 2

SE3 GPD GPD Bits 7:6—AIN gain control Bits 7:6—Reserved

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Rev. 0.31 109

SE4 CF5 CF5 Bit 4—DRT voice and codec modes Bit 1—Analog codecBit 0—Secondary serial port

Bit 4—ReservedBit 1:0—Reserved

SEC — RDC1 Reserved Bit 7—Ring validation enable1

Bits 6:4—Ring delayBits 3:1—Ring confirmation count

SED — RAS Reserved Bits 5:0—Ring assertion time1

SEE — RDC2 Reserved Bits 7:4—Ring timeout1

Bits 3:0—Ring assertion maximum count

SF0 DAA0 DAA0 Bits 7:6—Reserved Bits 7:6—Fast off-hook selection

SF4 DAA4 DAA4 Bit 7—Ring squelchBits 6:4—Analog receive gain

Bits 7:4—Reserved

SF5 DAA5 DAA5 Bit 7—Full scaleBit 6—DC termination offBit 5—On-hook speedBit 4—AC terminationBits 3:2—DC terminationBit 1—Ringer impedance

Bits 7:6—ReservedBits 5:4—On-hook speedBit 3—Current limiting enableBit 2—Ringer impedanceBit 1—Reserved

SF6 DAA6 DAA6 Bits 7:4—ReservedBit 3—Force Japan DC terminationBit 2—DTMF dialing modeBit 1—Line voltage adjustBit 0—Force low voltage mode

Bits 7:6—Minimum loop currentBits 5:4—Tip/ring voltage adjustBits 3:0—AC termination select

SF7 DAA7 DAA7 Bit 4—LMOBit 3—Current limiting enable

Reserved

SF8 DAA8 DAA8 Bits 3:0—Reserved Bit 1—DC impedance selectionBit 0—Over protect enable

SF9 DAA9 DAA9 Bit 6—Receive overload (non-sticky)Bit 0—Reserved

Bit 6—Reserved Bit 0—Overcurrent protect detect

Notes:1. On the Si2401, ring detection features are programmed using registers SEC, SED, and SEE.2. See Si2401datasheet for further details.3. On-hook voltage detection must be performed by the host controller. This can be accomplished by reading the

line voltage status register (SDB) before going off-hook.

Table 28. Modified Register Settings (Continued)

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110 Rev. 0.31

Default Register SettingsThe default settings for several registers in the Si2401 are different than the Si2400 default settings in order tocomply with standard modem values. If software written for the Si2400 relies on any of the default values listed inTable 29, the software may need to be modified for the Si2401.

Table 29. Updated Default Register Settings

Reg. Si2400 default

Si2401 default

Description

S01 0x03 0x02 Number of seconds modem waits before dialing after going off-hook changed from 3 seconds to 2 seconds

S02 0x14 0x03 Number of additional seconds modem waits for a dial tone before hang-up changed from 20 seconds to 3 seconds

S07 0x01 0x06 Default modem modulation changed from Bell 103 to V.22bis

S10 0x07 0x03 Default TIES guard band changed from 3 seconds to 1.3 seconds

S15 0x84 0x04 Answer tone phase reversal changed to be disabled by default

S2E 0x84 0xF0 V.23 reversal turnaround tim-eout changed from 220 ms to 400 ms

S62 0x00 0x41 Result codes ‘x’, ‘i’, ‘I’, ‘l’, and ‘L’ changed to be disabled by default and result code ‘R’ changed to be enable by default

S82 0x00 0x08 Loop current loss detect changed to be enabled by default

SDF 0x00 0x0C Deglitching sample rate changed to 480 ms

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Rev. 0.31 111

Prototyping an Si2401 on an Si2400 designThe Si2401 evaluation board, along with an existingSi2400 design, can be configured to easily test Si2400software for use with the Si2401 and reduce softwaredevelopment time. Jumper wires can by used toconnect from the host processor in an existing designdirectly to the Si2401 on the Si2401URT-EVBevaluation board bypassing the existing Si2400 circuit.A minimum of three jumper wires is required to pass theTX, RX, and GND signals. However, depending on thenumber of signals utilized by the existing Si2400 design,additional jumper wires may be required. TheSi2401URT-EVB evaluation board can provide powerand clock signals. If using Revision 3.1 of theISOmodem motherboard, place a jumper on JP8 todisable the RS232-mux. If using an earlier version of themotherboard, remove the jumper on JP8 and all of thejumpers on JP6. This will allow the extra header (JP3)to be driven by the jumper wires. On the existing Si2400design, depopulate the Si2400 and jumper wiresbetween the pads and JP3 of the Si2401URT-EVBevaluation board according to Table 30.

Table 30. Jumper Wiring Pinout

Si2400 Pad Si2400 Pinout Description

Si2401 EVB JP3 Pins

4 VD 15

5 RXD 7

6 TXD 9

7 CTS 11

8 RESET 13

9 AOUT 16

10 ALERT/GPIO4 16

12 GND 6

14 ESC/GPIO3 8

15 CD/GPIO2 4

16 EOFR/GPIO1 2

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112 Rev. 0.31

APPENDIX D—Si3008 SUPPLEMENT

Si3008 Introduction

The Si3008 is a small form factor line-side device with areduced peripheral component count. The Si3008meets the telephone network compatibility requirementsfor North America and many other countries. Thisappendix describes the Si3008 and its use with theSi2401 ISOmodem. The Si3008 features are describedand compared to those of the Si3010, and a referencedesign is presented. Si3008 layout guidelines and asample layout are also included. Finally, a prototypebring-up guide is presented for Si3008-based designs.

Si3008 Capabilities and LimitationsFeatures supported

The Si3008 uses Silicon Laboratories' patentedisolation technology to communicate with the Si2401ISOmodem and provide high-voltage isolation. TheSi3008 meets the telephone network interfacerequirements of the countries listed in Table 31 andprovides up to 6 kV of surge performance with Y2isolation capacitors. The Si2401/3008 chipset meets allglobal requirements for EMI, EMC, and safety if properlayout guidelines are followed. The informationpresented here is a summary. For complete details seethe Si2401/Si3008 data sheet.

Table 31. Country Compatibility

Argentina Macao

Canada Malaysia**

Chile Mexico

China Oman

Colombia Pakistan

Ecuador Peru

Egypt Romania

El Salvador Russia

Guam Saudi Arabia

Hong Kong Singapore

Hungary Slovakia

India Taiwan

Indonesia UAE

Japan* USA

Jordan Yemen

Kazakhstan ** Loop current >20 mA

Kuwait

* Requires waiver for <300

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Rev. 0.31 113

A feature comparison between the Si3010 and the Si3008 is presented in Table 32. This table is designed topresent a quick capability comparison of the Si3010 and the Si3008 to enable the selection of the best DAA chip fora particular design.

The Si3008 supports parallel handset off-hook/on-hook detection in both the on and off-hook modes. Loop currentis measured with 3.3 mA/bit resolution by the LCS bits. The LCS bits V loop current response is shown inFigure 27, and the LCS transfer function is explained in Table 33. The DC I/V characteristic is illustrated inFigure 28 and meets the requirements of the countries listed in Table 31. The Si3008 provides a ringer impedanceof approximately 5 Mand has an on-hook line monitor mode that supports Type 1, Type 2, and UK Caller ID.

The Si3008 meets the DTMF and pulse dialing requirements for the countries in Table 31. Higher DTMF signallevels than those required can be achieved.

Sufficiently high DTMF levels will clip due to the output signal level limitations of the Si3008. DTMF distortionbetween 10–20% is generally acceptable.

Loop current limiting (previously required by CTR/TBR-21 countries such as France) is not supported by theSi3008. Although current limiting is no longer required for certification, some customers require it for backwardcompatibility.

Table 32. Si3010/Si3008 Feature Comparison

Feature Name Si3010 Si3008

Type I Caller ID

Type II Caller ID Snoop

UK Caller ID

Parallel phone detection

On-hook intrusion

Loop current limiting ICL

Loop current loss detection LCLD

Minimum loop current MINI

Loop voltage adjust DCV

DC impedance selection DCR

AC impedance selection ACT

Ringer impedance RZ

Billing tone enable BTE

Billing tone detect BTD

On-hook speed OHS

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114 Rev. 0.31

Figure 27. Typical LCS Transfer Function

Table 33. Loop Current Sense Transfer Function

LCS[4:0] Condition

00000b – 00011 b Insufficient line current for normal operation. Use the DODI bit(Offset 0x34, bit 3) to determine if a line is still connected.

00100 b – 11110 b Normal operation.

11111 b Loop current is excessive (>160 mA).

0

32

64

96

128

160

192

224

256

0 16 32 48 64 80 96 112 128 144Loop Current (mA)

LC

S B

its

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Rev. 0.31 115

Figure 28. DC/IV Characteristics

Reference DesignThe Si3008 requires fewer peripheral components (specifically, fewer expensive high voltage transistors) than theSi3010. Table 34 compares the Si3010 and Si3008 peripheral component requirements.

Table 34. Si3010 vs. Si3008 Peripheral Component Requirements

Component Si3010 Si3008

Resistors 1/16 W 9 12

Resistors 3/4 W 3 2

Capacitors (NP) 11 9

Capacitors (polar) 1 0

Y2 capacitors 4 4

Diode bridge 1 1

Zener diodes 1 2

pnp transistors 1 1

npn transistors 4 2

Ferrite beads 4 4

SiDactor 1 1

Crystal 1 1

Total Components 41 39

DCIV

0

5

10

15

20

25

0 20 40 60 80 100 120 140 160 180

Loop Curre nt (m A)

Vti

p-r

ing

(V

olt

s)

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116 Rev. 0.31

GP

IO1/

EO

FRG

PIO

2/C

D_

GP

IO3/

ES

CG

PIO

4/A

OU

T/IN

T_

TXD

RE

SE

T_

RX

D

CTS

_

GP

IO5/

RI_

VD

D

TIP

RIN

G

External

crystal

option Em

issions

option

Ple

ase

subm

it la

yout

to S

ilico

n La

bs fo

r rev

iew

prio

r to

PC

B fa

bric

atio

n.

Note: Z1 can be replaced by an MOV or MLV.

Ferrite beads are used for best EMI

performance. In some situations, R15/R16

can be replaced with 0 ohm resistors.

No

Gro

und

Pla

ne In

DA

A S

ectio

n

R1Y

R1Y

Q3

Q3

C3

C3

R5

R5

R19

R19

R1Z

R1Z

C51

C51

R2X

R2X

C50

C50

C1

C1

Q2

Q2

C9

C9

R8

R8

C2

C2

C41

C41

C5

C5

R2Y

R2Y

R4

R4

FB1

FB1

C11

C11

R7

R7

R21

R21

R16

R16

Z1Z1

R20

R20

C40

C40

R13

R13

C8

C8

Q1

Q1

C4

C4

R1X

R1X

R2Z

R2Z

XTA

LI/C

LKIN

1

XTA

LO2

GP

IO5

3

VD4

RX

D5

TXD

6C

TS7

RE

SE

T8

C2A

9

C1A

10

GP

IO4

11

GND 12

VA 13

GP

IO3

14G

PIO

215

GP

IO1

16

U1

Si2

401

U1

Si2

401

-+ D

1

-+ D

1

R12

R12

R10

R10

R6

R6

1 2Y1

Y1

FB2

FB2

RV

1R

V1

R18

R18

R15

R15

C1B

1

C2B

2

VR

EG

3

CID

4

RX

8

DC

T7

IGND epad 9

QE

5

QB

6

U2

U2

Fig

ure

29.S

chem

atic

of

Si2

401

wit

h S

i300

8

AN94

Rev. 0.31 117

Bill of Materials: Si24xx Daughter Card

Table 35. Bill of Materials: Si24xx Daughter Card

Item Qty Reference Value Rating Tolerance Foot Print Dielectric Manufacturer Number Manufacturer

1 2 C1,C2 33 pF Y2 ±20% C1808-GF-Y2 X7R GA342D1XGF330JY02L Murata

2 1 C3 10 nF 250 V ±20% CC0805 X7R C0805X7R251-103MNE Venkel

3 1 C4 1.0 µF 25 V (50 V used)

±20% CC1206 X7R GRM31MR71H105KA88L Murata

4 4 C5,C50,C55,C56 0.1 µF 16 V ±20% CC0603 X7R C0603X7R160-104MNE Venkel

5 2 C8,C9 680 pF Y3 ±10% C1808-GD-Y3 X7R GA342QR7GD681KW01L Murata

6 1 C11 330 pF 50 V ±20% CC0603 X7R C0603X7R500-331MNE Venkel

7 2 C40,C41 33 pF 16 V ±5% CC0603 NPO C0603NPO160-330JNE Venkel

8 1 C51 0.22 µF 16 V ±20% CC0603 X7R C0603X7R160-224MNE Venkel

9 1 C54 1.0 µF 10 V ±10% 3216_EIAA Tant TA010TCM105-KAL Venkel

10 1 D1 HD04 400 V MINIDIP4 HD04-T Diodes, Inc.

11 5 FB1,FB2,FB5,R15,R16

Ferrite Bead RC0603 BLM18AG601SN1B Murata

12 1 JP1 HEADER 8X2

CONN2X8-100-SMT TSM-108-01-T-DV Samtec

13 1 JP2 4X1 Head-er_0

CONN1X4-100-SMT 68000-403 Berg

14 2 Q1,Q3 NPN 300 V SOT-23 MMBTA42LT1 Motorola

15 1 Q2 PNP 300 V SOT-23 MMBTA92LT1 Motorola

16 1 RV1 SiDactor 275 V 100 A SOD6 P3100SB Teccor

17 3 R1X,R1Y,R1Z 619 1/4 W ±1% RC1206 CR1206-4W-6190FT Venkel

18 3 R2X,R2Y,R2Z 732 1/4 W ±1% RC1206 CR1206-4W-7320FT Venkel

19 1 R4 3.9 K 1/16 W ±5% RC0603 CR0603-16W-392JT Venkel

20 2 R5,R6 100 K 1/16 W ±5% RC0603 CR0603-16W-104JT Venkel

21 2 R7,R8 10 M 1/8 W ±5% RC0805 CR0805-8W-106JT Venkel

22 1 R10 1 K 1/16 W ±5% RC0603 CR0603-16W-102JT Venkel

23 2 R12,R13 56 1/16 W ±5% RC0603 CR0603-16W-560JT Venkel

24 1 R18 1.5 M 1/16 W ±5% RC0603 CR0603-16W-155JT Venkel

25 1 R19 180 K 1/16 W ±5% RC0603 CR0603-16W-184JT Venkel

26 2 R20,R21 3 M 1/16 W ±5% RC0603 CR0603-16W-305JT Venkel

27 1 U1 Si2401 SO16 Si2401-FT Silicon Labs

28 1 U2 Si3008 SO8E Si3008-FS Silicon Labs

29 1 Y1 4.9152 MHz 20 pF load, 150 ESR

50 ppm XTAL-ATS-SM 559-FOXSD049-20 CTS Reeves

30 1 Z1 20 V Dual Zener

1/4 W SOT-23 AZ23C20 Vishay

AN94

118 Rev. 0.31

Layout Guidelines

The key to a good layout is proper placement ofcomponents. It is best to copy the placement shown onour evaluation boards (see the reference layoutincluded in this appendix). Alternatively, perform thefollowing steps, referring to the schematics.

1. All traces, open pad sites, and vias connected to the following components are considered to be in the DAA section and must be physically separated from non-DAA circuits by 5 mm to achieve best possible surge performance: R1, R2, R4, R5, R6, R7, R8, R10, R15, R16, R18, R19, R20, R21, U2, Z1, D1, FB1, FB2, RJ11, Q1, Q2, Q3, C3, C4, C5, C8, C9, C11, RV1, C1 pin 2 only, C2 pin 2 only, C8 pin 2 only, C9 pin 2 only.

2. The isolation capacitors C1, C2, C8, and C9 are the only components permitted to straddle between the DAA section and non-DAA section components and traces. This means that for each of these capacitors, one of the terminals is on the DAA-side, the other is not. Maximize the spacing between the terminals (between pin 1 to pin 2) of each of these capacitors.

3. Place and group the following components: U1, U2, R12, R13, C1, C2.

a.U1 and U2 are placed so that the right side of U1 faces the left side of U2.

b.C1 and C2 should be placed directly between U1 and U2.

c.Keep R12 and R13 close to U1.

d.Place U1, U2, C1, and C2 to realize the recommended minimum creepage spacing for the target application.

e.Place C1 and C2 so that traces connected to U2 pin 1 (C1B) and U2 pin 2 (C2B) are physically separated from traces connected to:

iC8, R15, FB1

ii.C9, R16, FB2

4. Place and group the following components around U2: C4, R18, R19, R20, R21, C5, C11, R7, R8. These components should form the critical “inner circle” of components around U2. Refer to Figure 30 for proper placement.

5. Place and group the following components around the RJ11 jack: FB1, FB2, RV1, R15, R16, C8 and C9.

a.Use 20 mil width traces on this grouping to minimize impedance.

b.Place C8 and C9 close to the RJ11 jack, recognizing that, a GND trace will be routed

between C8 and C9, back to the Si24xx GND pin, through a minimum 20 mil width trace. The GND trace from C8 and C9 must be isolated from the rest of the Si3008 traces.

c.The trace from C8 to GND and from C9 to GND must be short and equidistant.

6. After the previous step, there should be some space between the grouping around U2 and the grouping of components around the RJ11 jack. Place the rest of the components in this area, given the following guidelines:

a.Space U2, Q1, Q2, Q3, R1, R2, and R10 away from each other for best thermal performance. R1 and R2 can each dissipate nearly 0.75 W under worst case conditions.

b.Place C3 next to D1.

c.Make the size of the Q1, Q2, and Q3 collector pads each large enough to safely dissipate 0.15 W under worst case conditions. See the transistor data sheet for thermal resistance and maximum operating temperature information. Implement collector pads on solder side and use vias between them to improve heat transfer for best performance.

7. The epad of U2 (pin 9) is also known as IGND. This is the ground return path for many of the discrete components, and requires special mention

a.Route traces associated with IGND using 20 mil traces.

b.The area underneath U2 should be ground-filled and connected to IGND (U2 pin 9). Ground fill both solder side and component side and stitch together using vias.

c.C5, IGND return path should be direct.

d.The IGND plane must not extend past the diode bridge.

8. The traces from R7 to FB1 and from R8 to FB2 should be well matched. This can be achieved by routing these traces next to each other as possible. Ensure that these traces are not routed close to the traces connected to C1 or C2.

9. Minimize all traces associated with Y1, C40, and C41 and allow NO other traces to be routed through this circuitry.

10.Decoupling capacitors (0.22 µF and 0.1 µF capacitors) connected to VA, VD must be placed next to those pins. Traces of these decoupling capacitors back to the Si2401 GND pin should be direct and short.

AN94

Rev. 0.31 119

Table 36. Si2401/Si3008 Layout Checklist

# Layout Requirement

1 Place U1 and U2 so pins 9-16 of U1 are facing pins 1-4 of U2.

2 Place U1, U2, C1 and C2 to provide minimum required creepage distance.

3 Place R12 and R13 close to U1.

4 Place C1 and C2 directly between U1 and U2, connect with short direct traces.

5 Place R7, R8 and C11 close to U2 keeping away from U2 pins 1 and 2.

6 Provide large collector pads for heat sinking Q2 and Q3.

7 Use >15mil trace widths in DAA section and >20 mil IGND trace widths.

8 Place C3 directly across D1 and minimize IGND trace length.

9 Place FB1, FB2, R15, R16, and RV1 close to the RJ-11 jack.

10 Place C8 and C9 to minimize trace length to chassis ground.

11 The traces from the RJ-11 through C8 and C9 to chassis ground must be short.

12 Keep C8 and C9 away from C1 and C2 or place at 90 degrees.

13 Use >20mil trace widths between RJ-11, FB1-2, R15, R16, RV1 C8 and C9.

14 Match the routing from the RJ-11 to FB1 and FB2.

15 Match traces from FB1, R7, C11 to U2 to those from FB2, R8, R18 to U2.

16 There must be no digital ground or power plane in DAA area.

17 Place C4 close to U2 and connect with very short direct traces.

18 Minimize U2 pin6, Q4 base, Q4 emitter to U2 pin5 loop area.

19 >5 mm creepage between any TNV and SELV component, pad or trace.

20 Mark U1 pin 1 and U2 pin1.

21 Allow space and mounting holes for fire enclosure if required.

22 IGND plane does NOT extend under C3, D1, FB1-2, R15-16, C8-9 or RV1.

23 All traces connecting C50, C51, C52 and U1 must be short and direct.

24 The XTALI, Y1, XTALO loop must be minimized and routed on one layer.

25 The Y1, C40, C41 loop must be minimized and routed on one layer.

26 No traces can be routed through the Y1, C40, C41 loop.

27 Space U2, Q1, Q2, Q3, R1, R2, and R10 for best thermal performance.

28 Size Q1, Q2, and Q3 collector pads to safely dissipate 0.15 W (see text).

29 Submit layout to Silicon Laboratories for review.

AN94

120 Rev. 0.31

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Module Design and ApplicationConsiderations

Modem modules are more susceptible to radiated fieldsand ESD discharges than modems routed directly onthe motherboard because the module ground plane isdiscontinuous and elevated above the motherboardground plane. This separation also creates thepossibility of loops that couple these interfering signalsto the modem. Additionally, system designers canadversely impact the ESD and EMI immunity andperformance of a properly-designed module with a poormotherboard layout.

Module DesignParticular attention should be paid to power supplybypassing and reset line filtering when designing amodem module. Trace routing is normally very short onmodules since they are generally designed to be assmall as possible. Care should be taken to use groundand power planes in the low-voltage circuitry wheneverpossible and to minimize the number of vias in theground and power traces. Ground and power shouldeach be connected to the motherboard through one pinonly to avoid the creation of loops. Bypassing andfiltering components should be placed as close to themodem chip as possible with the shortest possibletraces to a solid ground. It is recommended that a pi

filter be placed in series with the module VCC pin with afilter, such as the one shown in Figure 36, on the resetline. This filter also provides a proper power-on reset tothe modem. Careful module design is critical since themodule designer frequently has little control over themotherboard design and the environment the modulewill be used in.

Motherboard DesignMotherboard design is critical to proper modem moduleperformance and immunity to EMI and ESD events.First and foremost, good design and layout practicesmust be followed. Use ground and power planeswhenever possible. Keep all traces short and direct.Use ground fill on top and bottom layers. Use adequatepower supply bypassing and use special precautionswith the power and reset lines to the modem module.Bypass VCC right at the modem module connector. Besure the modem module is connected to VCC through asingle pin. Likewise, be sure ground is connected to themodem module through one pin connected to themotherboard ground plane. The modem reset line issensitive and must be kept very short and routed wellaway from any circuitry or components that could besubjected to an ESD event. Finally, mount the modemmodule as close to the motherboard as possible. Avoidhigh-profile sockets that increase the separationbetween the modem module and the motherboard.

Figure 36. Modem Module VCC and RESET Filter

RESET

MotherboardConnector

1.0 F .01 F .01 F 1.0 F10 k

2.2 F

To RESET

GND

To Modem Chip VCC(Si2401 pins 5, 21)

(Si2401 pin 12)

GND

VCC

Murata BLM 18AG601 SN1

AN94

Rev. 0.31 127

APPENDIX E—Si3006 SUPPLEMENT

Si3006 Introduction

The Si3006 is a small form factor line-side device with areduced peripheral component count. The Si3006meets the telephone network compatibility requirementsfor countries worldwide. This appendix describes theSi3006 and its use with the Si2401 ISOmodem. TheSi3006 features are described and compared to thoseof the Si3010 and the Si3008. A reference design ispresented. Si3006 layout guidelines and a samplelayout are also included.

Si3006 Capabilities and Limitations

Supported FeaturesThe Si3006 uses Silicon Laboratories' patentedisolation technology to communicate with the Si2401ISOmodem and provide high-voltage isolation. TheSi3006 meets the telephone network interfacerequirements of the countries listed in Table 37. Itprovides up to 6 kV of surge performance with Y2isolation capacitors. The Si2401/3006 chipset meets themost stringent requirements for EMI, EMC, and safety ifproper layout guidelines are followed. The informationpresented here is a summary. For complete details, seethe Si2401/Si3006 data sheet.

Table 37. Country Support List

Supported Countries

Argentina Lebanon

Australia1 Luxembourg (EU)

Austria (EU) Macao

Bahrain Malaysia3

Belgium (EU) Malta (EU)

Brazil2 Mexico3,6

Bulgaria (EU) Morocco

Canada Netherlands (EU)

Chile New Zealand4

China Nigeria

Columbia Norway

Croatia Oman

Cyprus (EU) Pakistan

Czech Republic (EU) Paraguay

Denmark (EU) Peru

Ecuador Philippines

Egypt Poland (EU)

El Salvador Portugal (EU)

Finland (EU) Romania (EU)

AN94

128 Rev. 0.31

France (EU) Russia

Germany (EU) Saudi Arabia

Greece (EU) Singapore

Guam Slovakia (EU)

Hong Kong Slovenia (EU)

Hungary (EU) South Africa5,6

Iceland South Korea6

India Spain (EU)

Indonesia Sweden (EU)

Ireland (EU) Switzerland

Israel Taiwan

Italy (EU) Thailand

Japan3 UAE

Jordan United Kingdom (EU)

Kazakhstan USA

Kuwait Yemen

Latvia (EU)

Notes:1. Additional components required; contact Silicon Labs. Per current PTT

recommendations, only DTMF dialing is supported.2. Component value changes required; Contact Silicon Labs.3. DCT bit must be set to 1.4. 600 ac termination requires disclaimer in product documentation.5. Additional surge components required; Contact Silicon Labs.6. Additional components required to pass on-hook or ringer impedance

specifications. See "Ringer Impedance" on page 131.

Table 37. Country Support List (Continued)

Supported Countries

AN94

Rev. 0.31 129

A feature comparison between the Si3010, Si3008, and Si3006 is presented in Table 38. This table is designed topresent a quick capability comparison of the three parts to enable the selection of the best DAA chip for a particulardesign.

The Si3006 supports parallel handset off-hook/on-hook detection in both the on- and off-hook modes. Loop currentis measured with 1.1 mA/bit resolution by the LCS bits. The LCS bits V loop current response is shown in Figure 27on page 114, and the LCS transfer function is explained in Table 33 on page 114. The DC I/V characteristic isillustrated in Figure 28 on page 115. It meets the requirements of the countries listed in Table 37 on page 127. TheSi3006 provides a ringer impedance of approximately 5 M. It has an on-hook line monitor mode that supportsType 1, Type 2 and UK Caller ID.

The Si3006 meets the DTMF and pulse dialing requirements for the countries in Table 37. Higher DTMF signallevels than those required can be achieved.

Sufficiently high DTMF levels will clip due to the output signal level limitations of the Si3006. DTMF distortionbetween 10–20% is generally acceptable.

Loop current limiting (previously required by CTR/TBR-21 countries such as France) is not supported by theSi3006. Although current limiting is no longer required for certification, some customers require it for backwardcompatibility.

Table 38. DAA Feature Comparison

Feature Name Name Si3010 Si3008 Si3006

Type I Caller ID X X X

Type II Caller ID Snoop X X X

UK Caller ID X X X

Parallel phone detection X X X

On-hook intrusion X X X

Loop current limiting ILIM X

Loop current loss detection LCLD X X

Minimum loop current MINI X

Loop voltage adjust DCV X

DC impedance selection DCR X

AC impedance selection ACT X

Ringer impedance RZ X

Billing tone enable BTE X

Billing tone detect BTD X

On-hook speed OHS X

AN94

130 Rev. 0.31

Reference DesignThe Si3006 and Si3008 require fewer peripheral components, in particular fewer expensive high voltagetransistors, that the Si3010. Table 39 compares the Si3010, Si3008 and Si3006 requirements for peripheralcomponents.

Table 39. Si3010, Si3008, Si3006 Peripheral Component Requirements

Component Si3010 Si3008 Si3006

Resistors 1/16 W 9 12 10





Capacitors (NPO) 11 2 2

Capacitors (X7R) 0 8 8

Capacitors (polar) 1 0 0

Y2/Y3 capacitors 4 4 4

Diode bridge 1 1 1

Zener diodes 1 2 2

pnp transistors 1 1 2

npn transistors 4 2 1

Ferrite beads 4 4 4

SiDactor 1 1 1

Crystal 1 1 1

Total Components 41 39 39

AN94

Rev. 0.31 131

Ringer ImpedanceThe ring detector in many DAAs is ac-coupled to the line with a large 1 µF, 250 V decoupling capacitor. The ringdetector on the Si3006 is resistively coupled to the line. The network presents a high ringer impedance to the lineof approximately 5 M to meet the majority of PTT specifications, including FCC. Certain countries have specificon-hook and/or ringer impedance requirements, e.g., Mexico, South Africa, and South Korea. The ringerimpedance network shown in Figure 37 is required for compliance with these specifications.

This network is only required if the application will be deployed in one of these countries. However, it isrecommended that it be included on all DAA PCB layouts, space permitting. This provides maximum flexibility.International telecommunications requirements are subject to change. The test setup and the interpretation of aspecification can vary from one test facility to another. If the network is not required, the components are simply notpopulated. The network components for each country are detailed in Tables 40, 41, and 42.

Figure 37. Universal Oh-Hook/Ringer Impedance Network

R55b

Z2

Z3

RING

R56

C15

R55a

TIP

AN94

132 Rev. 0.31

Table 40. South Korea Ringer Impedance Network Components

Component Value PCB Footprint Part Number Supplier(s)

C15 1 µF, 25 V CC0805 ECJ-2FB1E105K Panasonic

R55a1 15 k, 5%, 1/4 W, 200 V R1206 CR1206-4W-153J Venkel

R55b1 15 k, 5%, 1/4 W, 200 V R1206 CR1206-4W-153J Venkel

R56 Not installed N/A N/A N/A

Z2 18 V, 200 mW SOD3232 BZT52C18S Diodes, Inc.


Notes:1. R55 may be a single resistor of equal or higher power and voltage rating.2. Z2 and Z3 may be a dual device in a SOT23 or similar package of equal or greater power rating.

Table 41. South Africa Ringer Impedance Network Components


C15 0.47 µF, 50 V CC0805 GRM21BR71H474KA88L Murata

R55a1 15 k, 5%, 1/4 W, 200 V R1206 CR1206-4W-153J Venkel

R55b1 15 k, 5%, 1/4 W, 200 V R1206 CR1206-4W-153J Venkel

R56 Not installed N/A N/A N/A



Notes:1. R55 may be a single resistor of equal or higher power and voltage rating.2. Z2 and Z3 may be a dual device in a SOT23 or similar package of equal or greater power rating.

Table 42. Mexico On-Hook Impedance Network Components


C15 0.047 µF, 250V CC0805 C0805X7R101-473JNE Venkel

R55a* 11.5 k, 1%, 1/8 W R1206 CR1206-8W-1152FT Venkel

R55b* 11.5 k, 1%, 1/8 W R1206 CR1206-8W-1152FT Venkel

R56 0 R0402 CR0402-16W-000T Venkel

Z2 Not installed N/A N/A N/A

Z3 Not installed N/A N/A N/A

*Note: R55 may be a single resistor of equal or higher power and voltage rating.

AN94

Rev. 0.31 133

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134 Rev. 0.31

Table 43. Bill of Materials: Si24xx Daughter Card

Component Description PCB Footprint Part Number Supplier(s)

C1,C2 33 pF, Y2 X7R ±10% C1808-GF-Y2 GA342D1XGF330JY02L Panasonic, Murata, Vishay

C4 1.0 µF, 35 V, Elect X7R ±20% CC1206 GRM31MR71H105KA88L Panasonic

C5 0.1 µF, 16 V, X7R ±20% CC0603 C0603X7R160-104MNE Venkel, SMEC

C6 1.5 nF, 250 V, X7R ±20% CC0805 C0805X7R251-153MNE Venkel, SMEC

C8,C9 680 pF, Y3, X7R ±10% C1808-GD-Y3 GA342QR7GD681KW01L Panasonic, Murata, Vishay

C11 27 pF, 250 V, X7R ±20% CC0603 C1608C0G2E270J TDK, Venkel, SMEC

C40,C411 33 pF, 16 V, NPO ±5% CC0603 C0603NPO160-330JNE Venkel, SMEC

C50,C51,C52,C53

0.1 µF, 16 V, X7R ±20% CC0603 C0603X7R160-104MNE Venkel, SMEC

D1, D2 Dual Diode 300 V2 SOT-23 MMBD2400S Central Semiconductor

FB1,FB2,R15,R16

Ferrite Bead / Resistor3 RC0603 CR0603-16W-104JT Murata

Q1 PNP 300 V4 SOT-234 MMBT6520LT1 On Semiconductor

Q2 PNP 300 V SOT-234 MMBTA92LT1 On Semiconductor

Q3 NPN 300 V SOT-23 MMBTA42LT1 On Semiconductor

RV1 Sidactor 275 V, 100 A4 SDO6 P3100SB Teccor, LittelFuse,ST Micro,Protek

R1 158 , 3/4 W5,6,7, ±1% RC1206 x 3 CR2010-1W-1580FT Venkel, SMEC, Panasonic

R2 261 , 1/2 W8 ±1% RC1206 x 2 CR1210-2W-2610FT Venkel, SMEC, Panasonic

R5 200 4, 1/16 W ±5% RC0603 CR0603-16W-201JT Venkel, SMEC, Panasonic

R8 2.2 M, 1/8 W ±5% RC0805 CR0805-8W-225JT Venkel, SMEC, Panasonic

R10 1 k, 1/16 W ±5% RC0603 CR0603-16W-102JT Venkel, SMEC, Panasonic

R12,R13 56 , 1/16 W ±1% RC0603 CR0603-16W-560FT Venkel, SMEC, Panasonic

R14 910 , 1/4 W ±5% RC1206 CR1206-4W-911JT Venkel, SMEC, Panasonic

Notes:1. In STB applications, C40, C41, and Y1 can be removed by using the 27 MHz clock input feature.2. Diode Bridge (D1, D2) can be four diodes such as 1N4001, dual diodes such as MMBD3004S as shown, or a single-

chip diode bridge, such as DF04S.3. R15 and R16 may be populated with either ferrite beads or 0 resistors as needed to comply with radiated emissions.4. For Brazil, use 2SA1776 for Q1 and 170 V sidactor (Littlefuse PI800SBLRP).5. Three (3) 475 , 1/4 W resistors in parallel may be used to achieve the resistance value and power rating shown.6. For Chile, the value of R1 must be raised to 200 @ 3/4W or three 604 1/4 W resistors.7. For Australia, make R1 = 130 , 3/4 W, while RZ is a series combination of an RZA (120 , 1/4 W) and an RZB (150 ,

1/4 W). Shunt RZB with a 150 nF, 50 V, 20%, X7R capacitor.8. Two (2) 523 , 1/4W resistors in parallel may be used to achieve the resistance value and power rating shown.9. To ensure compliance with ITU specifications frequency tolerance must be less than 100 ppm including initial accuracy,

5-year aging, 0 to 70 °C, and capacitive loading. 50 ppm initial accuracy crystals typically satisfy this requirement.

AN94

Rev. 0.31 135


R20,R21 3 M, 1/16 W ±5% RC0603 CR0603-16W-305JT Venkel, SMEC, Panasonic

R31 6.2 k, 1/16 W ±5% RC0603 CR0603-16W-622JT Venkel, SMEC, Panasonic


R35 2.7 M, 1/16 W ±5% RC0603 CR0603-16W-275JT Venkel, SMEC, Panasonic

U1 Modem IC SOIC-16 Si2401-FS Silicon Laboratories

U2 DAA IC MSOP-10 Si3006-B-FT Silicon Laboratories

Y11,7,9 4.9152 MHz, 20 pF, 100 ppm, 150 ESR7,8

XTAL-ATS-SM 559-FOXSD049-20 CTS Reeves, ECS, Siward

Z1 20 V, 1/4 W AZ23C20 SOT-23 AZ23C20 Vishay

Table 43. Bill of Materials: Si24xx Daughter Card (Continued)

Component Description PCB Footprint Part Number Supplier(s)

Notes:1. In STB applications, C40, C41, and Y1 can be removed by using the 27 MHz clock input feature.2. Diode Bridge (D1, D2) can be four diodes such as 1N4001, dual diodes such as MMBD3004S as shown, or a single-

chip diode bridge, such as DF04S.3. R15 and R16 may be populated with either ferrite beads or 0 resistors as needed to comply with radiated emissions.4. For Brazil, use 2SA1776 for Q1 and 170 V sidactor (Littlefuse PI800SBLRP).5. Three (3) 475 , 1/4 W resistors in parallel may be used to achieve the resistance value and power rating shown.6. For Chile, the value of R1 must be raised to 200 @ 3/4W or three 604 1/4 W resistors.7. For Australia, make R1 = 130 , 3/4 W, while RZ is a series combination of an RZA (120 , 1/4 W) and an RZB (150 ,

1/4 W). Shunt RZB with a 150 nF, 50 V, 20%, X7R capacitor.8. Two (2) 523 , 1/4W resistors in parallel may be used to achieve the resistance value and power rating shown.9. To ensure compliance with ITU specifications frequency tolerance must be less than 100 ppm including initial accuracy,

5-year aging, 0 to 70 °C, and capacitive loading. 50 ppm initial accuracy crystals typically satisfy this requirement.

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APPENDIX F—Si2401/Si3008 PROTOTYPE BRING-UP GUIDE

Introduction

This appendix provides help with the debugging of initialprototypes. Although most ISOmodem® prototypedesigns function as expected, there is the potential forlayout errors, omitted or incorrect components used inthe initial assembly run, and host software problems. Ifthe prototype modem does not function correctly, thetechniques outlined in this guide will help quickly isolatethe problem and get the prototype functioning correctly.A functional Si2401URT-EVB and data sheet and acomputer with HyperTerm is required for some of thetroubleshooting steps. It is assumed that the designerhas read the data sheet, used the reference design andrecommended bill-of-materials, and has carefullyfollowed the layout guidelines presented in“Appendix A—ISOmodem® Layout Guidelines”. Thetroubleshooting steps begin with system-level checks,and then proceed to the component level.

Visual InspectionBefore troubleshooting, be certain that the circuit boardsand components are clean. Carefully wash the boardsto remove all solder flux and solder flakes. Inspect themodem circuitry to ensure all components are installed,and inspect all solder joints for incomplete connections,cold solder joints, and solder bridges. Check allpolarized components, such as diodes, Zener diodes,and capacitors for correct orientation. Thoroughly cleanthe circuit board after replacing a component orsoldering any connections.

Reset the ModemBe sure the modem is properly reset after power isapplied and stable.

Basic Troubleshooting Steps

Check PowerWith power off, use an Ohm meter to verify system ground is connected to Si2401 pin 12. Turn on system power and measure the voltage between pin 4 and pin 12 and between pin 13 and pin 12 on the Si2401. In both cases, the voltage should be 3.3 V. If this is not the case, check the power routing. If power is present, go to the next step.

Check Phone LineCheck the phone line with a manual telephone to be sure there is a dial tone and dialing is possible. The dc voltage across TIP and RING should read approximately 40–52 V with the phone on-hook.

Reset ModemDo a manual reset on the modem. Hold Si2401 pin 8 (RESET) low for 300 ms, return to VDD (3.3 V) in less than 5 ms and wait for at least 300 ms before executing the first AT command.

Check DTE SetupBe sure the DTE (Host) serial port is configured the same as the modem. The default condition is eight data bits, no parity-bit, one stop-bit, and a DTE rate of 2400 bps.

Check DTE ConnectionCheck the DTE interface connection. Be sure the CTS (Si2401 pin 7) signal is low.

Check pullup/pulldown configuration resistor.

Check modem configuration

Read back the modem register settings and correct anyinconsistencies. Use the ATSR or ATr# commands tolist the contents of the S-Registers.

If the problem was not located with these basictroubleshooting steps, it is time to narrow the problemdown to the host system (hardware and software), theSi2401 chip (and associated components), or theSi3008 (and associated components).

AT OK?

The modem responds with an “O” to the command“AT<cr>.”

This indicates the host processor/software iscommunicating with the modem controller and problemsare in one of the following areas:

Inappropriate CommandsVerify that all AT commands used are supported by the Si2401 and comply with the proper format. Be sure the command and argument are correct. Do not mix upper and lower case alpha characters in an AT command (except the “r”, “m”, “q”, and “w” commands).

Command TimingThe execution time for an AT command is approximately 200 ms. Execution is complete when the “O” is received. Subsequent AT commands should wait for the “O” message, which appears within 100 ms after the carriage return. The reset recovery time (the time between a hardware reset or the carriage return of an ATZ command and the time the next AT command can be executed) is approximately 100 ms. When a data connection is being established, do not try to escape to the

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Rev. 0.31 143

command mode until after the protocol message.

Si3008 and/or Associated Components If the modem goes off-hook and draws loop current as a result of giving the ATH1 command, go to the Si3008 Troubleshooting section.If the modem does not go off-hook and draw loop current as a result of giving the ATH1 command and receiving an “O” message, begin troubleshooting with the isolation capacitor at the Si2401. First check all solder joints on the isolation capacitors, Si3008, and associated external components. If no problems are found, proceed to the following Troubleshooting section to verify whether the problem is on the Si2401 or the Si3008 side of the isolation barrier. If the problem is found to be on the Si2401 side, check C50, C51, C53, the corresponding PCB traces, and Si2401 pins. Correct any problems. If no problems are found with the external components, replace the Si2401.If the problem is found to be on the Si3008 side of the isolation barrier, go to the Si3008 Troubleshooting section.If the modem does NOT respond with an “O” to the command ”AT<cr>,”this indicates the host processor/software is not communicating with the modem controller, and the problem can be isolated as follows.

Si2401 Clock is OscillatingFirst be sure the Si2401 is properly reset and RESET, pin 8, is at 3.3 V. Next, check the DTE connection with the host system. If this does not isolate the problem, go to the Host Interface Troubleshooting section.

Si2401 Clock is Not OscillatingCheck the voltage on the Si2401, pin 4, to be sure the chip is powered. Also, check that pin 12 is grounded. Next, check the solder joints and connections (PCB traces) on C40, C41, Y1 and the Si2401 pin 1 and pin 2. Measure C26 and C27 (or replace them with known good parts) to ensure they are the correct value. If these steps do not isolate the problem, replace the Si2401.

Host Interface Troubleshooting

The methods described in this section are useful as astarting point for debugging a prototype system or as acontinuation of the troubleshooting process describedabove. The procedures presented in this section requirea known good Si2401URT-EVB evaluation board anddata sheet. This section describes how to substitute theevaluation board for the entire modem circuitry in theprototype system. Substituting a known operationalmodem can help to quickly isolate problems. The firststep is to substitute the evaluation board for the

complete modem solution in the prototype system. Thisdemonstrates immediately whether any modemfunctionality problems are in the prototype modemcircuitry or in the host processor, interface, or software.

Verify Si2401URT-EVB FunctionalityConnect the evaluation board to a PC and a phone line or telephone line simulator. Using a program such as HyperTerm, make a data connection between the evaluation board and a remote modem. Remove power and the RS232 cable from the evaluation board and proceed to the next step.

Connect Evaluation Board to Prototype SystemCompletely disconnect the embedded modem from the host interface in the prototype system. Connect the Si2401URT-EVB to the host interface using JP3 as described in the Si2401URT-EVB data sheet section titled Direct Access Interface. This connection is illustrated in Figure 22. Be sure to connect the evaluation board ground to the prototype system ground. Power up and manually reset the evaluation board then power up the prototype system and send “AT<cr>.” If an “OK” response is received, make a connection to the remote modem as in the previous step. If no “OK” response is received, debug host interface and/or software. If a connection is successfully made, go to the next step to isolate the problem in the prototype modem.An alternative approach is to connect the prototype modem to the Si2401URT-EVB motherboard in place of the daughter card and use a PC and HyperTerm to test the prototype modem. See Figure Figure 23 for details.

Troubleshooting

Connect Evaluation Board isolation capacitors toPrototype Modem Si3008. Remove C1 on theevaluation board and on the prototype system. Solderone end of the evaluation board, C1, to the Si2401-sidepad leaving the other end of C1 unconnected. Next,solder a short jumper wire from the unconnected side ofC1 on the evaluation board to the Si3008-side C1 padon the prototype system. This connection is illustrated inFigure 24. Connect the phone line to the prototypesystem RJ-11 jack.

Power up and manually reset the evaluation board, thenpower up the prototype system. Attempt to make aconnection using the host processor and software, theevaluation board Si2401 and the prototype systemSi3008 and associated external components. If thisconnection is successful, the problem lies with the PCBlayout, the external components associated with theSi2401 or the Si2401 device itself.

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If the connection attempt is not successful, the problemlies with the Si3008 and/or associated components.Proceed to the section, “Si3008 Troubleshooting”.

This diagnosis can be validated by connecting the Hostisolation capacitors to the Si3008 on the evaluationboard as shown in Figure 25.

Si3008 Troubleshooting

Start by measuring the on-hook and off-hook voltages atthe Si3008 pins with respect to IGND (pin 15). Comparethese voltages to those in Figure 26. This may indicatean area of circuitry to investigate further using theComponent Troubleshooting techniques. The voltagesyou measure should be close to (although not exactlythe same as) those in the figure.

If any of the on-hook and off-hook Si3008 pin voltagesare grossly different than those in Figure 26 and nothingseems wrong with the external circuitry after using theComponent Troubleshooting techniques, replace theSi3008.

Component Troubleshooting

A digital multi-meter is a valuable tool to verifyresistance across components, diode direction,transistor polarity and node voltages. During this phaseof troubleshooting, it is highly useful to have a knowngood Si2401URT-EVB to compare againstmeasurements taken from the prototype system. Theresistance values and voltages listed in Tables 24, 25,and 26 will generally be sufficient to troubleshoot all butthe most unusual problem.

Start with power off and the phone line disconnected.Measure the resistance of all Si3008 pins with respectto pin 9 (IGND). Compare these measurements with thevalues in Table 24. Next, measure the resistance acrossthe components listed in Table 25 and compare thereadings to the values listed in the table. Finally, usingthe diode checker function on the multi-meter, check thepolarities of the transistors as described in Table 26.The combination of these measurements shouldindicate the faulty component or connection. If none ofthe measurements appears unusual and the prototypemodem is not working, replace the Si3008.

Figure 45. Test the Host Interface

HostController



EVB

Prototype System

ToPhoneLine

Connect prototype system ground to EVB ground Disable RS232 transceiver outputs (check evaluation board data sheet) Disconnect prototype modem interface Connect the evaluation board to the target system

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Rev. 0.31 145

Figure 46. Test the Prototype Modem

Figure 47. Test the Prototype Si3008 Circuitry

Host Controller

Host UART Si2401 Si3008 Discretes

RS232 Transceiver Si2401 Si3008 Discretes

EVB

Prototype System

Connect prototype system ground to EVB ground Remove modem module from EVB Disconnect host outputs from prototype modem Connect EVB RS232 transceivers to prototype modem Use PC with HyperTerminal to test prototype modem

To Phone Line

PC

ToPhoneLine

Host Controller


RS232 Transceiver Si2401 Si3008 Discretes

EVB

Connect the prototype ground to the EVB ground. Lift prototype C1 and C2 and EVB C1 and C2 so the Si3008 is disconnected from the Si2401 on both modems. Connect EVB C1 and C2 to the Si3008 pad of prototype system C1 and C2. Connect the phone line to the RJ11 jack on the prototype system. Use PC and HyperTerm and attempt to establish a modem connection.

PC

C2

C1

C2

Prototype SystemC1

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146 Rev. 0.31

Figure 48. Verify Prototype Si3008 Failure

Figure 49. Si3008 Typical Voltages

Figure 50. Si3008 In-Circuit Resistance to IGND (Si3008 Pin 9)

To Phone Line

Host Controller


RS232 Transceiver

Si2401 Si3008 Discretes

EVB

Connect the prototype ground to the EVB ground Lift prototype and EVB C1 and C2 to decouple the line side from the DSP side. Do same on evaluation board. Connect prototype system C1 and C2 to the Si3008 pad of EVB C1 and C2 Connect the phone line to the RJ11 jack on the EVB Run the prototype system software to attempt a modem connection

C2

C1

C2

C1Prototype System

On-Hook

0.54 V

1.0 V

2.3 V

0.88 V

C1B

CID

VREG

C2B

0.04 V

0.52 V

0.06 V

0.05 V

DCT2

VREG2

QE2

DCT3

Voltages measured with respect to IGND (Si3008 pin 9)

Off-Hook

N/A

1.0 V

2.3 V

N/A

C1B

CID

VREG

C2B

1.1 V

1.7 V

2.3 V

3.0 V

Rx

QE

QB

DCT

Resistance measured with power and phone line removed

2.7 M

1.6 M

480 k

C1B

CID

VREG

C2B

180 k

Rx

QE

QB

DCT2.7 M

2.6 M

1.4 M

1.4 M

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Rev. 0.31 147

Table 44. Resistance across Components

Si3008 Circuit Component Resistance

FB1 <1 FB2 <1 RV1 >10 MR1 206 R2 243 R4 3.8 kR5 4.0 kR6 100 kR7 2.7 M/8.4 MR8 2.7 M/8.7 M

R10 1.0 kR12 56 R13 56 R15 <1 R16 <1 R18 1.3 M/ 1.6 MR19 165 kR20 1.6 MR21 1.6 MC1 >20 MC2 >20 MC3 2.8 M/>20 MC4 4.5 M/3.3 MC5 440 kC8 >20 MC9 >20 MC11 3.2 M/3.0 M

Note: If two values are given, the resistance measured is dependent upon polarity.

Table 45. Voltage across Components with Diode Checker

Component Voltage

Q1, Q3Base to EmitterBase to CollectorVerifies transistors are NPN

0.6 V0.6 V

Q2Emitter to BaseCollector to BaseVerifies transistor is PNP

0.6 V0.6 V

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DOCUMENT CHANGE LIST

Revision 0.1 to Revision 0.2 Changed heading levels.

Updated Table 20, “Si2401 Country Table,” on page 80.

Added "Appendix D—Si3008 Supplement" on page 112.

Revision 0.2 to Revision 0.3 Added "Appendix E—Si3006 Supplement" on page

127.

Revision 0.3 to Revision 0.31 Updated Table 20, “Si2401 Country Table,” on

page 80.

Updated Table 21, “Countries Grouped by Common AT Commands,” on page 84.

Updated Table 31, “Country Compatibility,” on page 112.

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AAC Termination 10Answer 18assembly 90, 98, 142AT Command Set 18BBasic Troubleshooting Steps 98, 142Bias Circuitry 6, 8Ccall progress monitor 20Caller ID 22, 34, 36, 38, 74, 113Carrier Detect 5, 32, 33, 34, 72Carrier detect 27Command

mode 17Timing 98

Compliance 4compliance 4, 6, 7Component Troubleshooting 100Controller 17controller 5, 6, 7, 10, 98Crystal Oscillator 6crystal oscillator 6DDAA (Line-Side) Chip 7default settings 110Digital Interface 15DSP 15, 65, 66DTE 75, 76, 107

Connection 98, 142Setup 98, 142

EEMC 7, 9, 13, 96, 112EMI 9, 13, 97, 112, 126Emissions 10emissions 6, 7Escape 35escape 16, 17, 20, 21

methods 1, 15HHardware

Design Reference 5reset 20

HDLC 36, 64, 75, 78IIntrusion Detection 69intrusion detection 105Isolation 92, 99, 112

Interface 7ISOmodem 69, 92LLayout Guidelines 92, 94, 118Loop

Current 10, 99, 113, 114Voltage 113

Mmanual reset 98, 142memory 6, 15Modem 6modem 4, 5Modulations 5OOff-Hook 12, 18, 19, 22, 36, 69, 72, 108On-Hook 8, 11, 18, 35, 56, 69, 108, 109, 113Oscillator 6PPLL 6Power

Control 15Supply 6, 8

Program ROM 15Programming Examples 69Protocols 5Prototype Bring-Up Guide 98, 142RReceive Carrier 5Reference Design 6, 115, 130RESET 97, 126Reset 17, 20, 25, 97, 98, 105, 142Result Codes 20, 22, 39Ringer

Impedance 131Network 8

ROM 15RTS 41, 76SSafety 91Serial Interface 6, 7, 15, 16Si3010 Troubleshooting 100S-Registers 25, 65, 77, 98, 142surge performance 92, 112, 118switch-hook 5System Interface 7TTesting 87, 89, 90, 91Transmit Carrier 5Troubleshooting 98, 99, 100, 104, 105, 142, 143, 144Typical Voltages 102, 146UUART 15, 16, 75, 105VVisual Inspection 98, 142

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DisclaimerSilicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Without prior notification, Silicon Labs may update product firmware during the manufacturing process for security or reliability reasons. Such changes will not alter the specifications or the performance of the product. Silicon Labs shall have no liability for the consequences of use of the information supplied in this document. This document does not imply or expressly grant any license to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any FDA Class III devices, applications for which FDA premarket approval is required or Life Support Systems without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. Silicon Labs disclaims all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of a Silicon Labs product in such unauthorized applications.

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an94: si2401 modem designer’s guide...packages, this solution includes a dsp data pump, modem...

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