an on-chip spectrum analyzer for analog built-in testingvega.unitbv.ro/~olteanu/tehnici de masurare...

JOURNAL OF ELECTRONIC TESTING: Theory and Applications 21, 205–219, 2005c© 2005 Springer Science + Business Media, Inc. Manufactured in The United States.

An On-Chip Spectrum Analyzer for Analog Built-In Testing

MARCIA G. MENDEZ-RIVERA, ALBERTO VALDES-GARCIA, JOSE SILVA-MARTINEZAND EDGAR SANCHEZ-SINENCIO

Analog & Mixed-Signal Center, Texas A&M University, College Station, TX, 77843-3128, [email protected]

Received March 8, 2004; Revised October 19, 2004

Editor: A. Rueda

Abstract. This paper presents an analog built-in testing (BIT) architecture and its implementation. It enables thefrequency response and harmonic distortion characterizations of an integrated device-under-test (DUT) through adigital off-chip interface. External analog instrumentation is avoided, reducing test time and cost. The proposedon-chip testing scheme uses a digital frequency synthesizer and a simple signal generator synchronized with aswitched capacitor bandpass filter. A general methodology for the use of this structure in the functional verificationof a DUT is also provided. The circuit-level design and experimental results of an integrated prototype in standardCMOS 0.5 µm technology are presented to demonstrate the feasibility of the proposed BIT technique.

Keywords: built-in testing, analog IC test, frequency response, switched-capacitor circuits

1. Introduction

The advance of microelectronic fabrication technolo-gies has made it possible to put millions of transistorson a single chip for the realization of complex tasks. Inmany cases, mixed-signal solutions (analog and digi-tal functions in the same chip) are a must. As a result,the speed and quality of modern integrated systemstests have become major factors when determining fi-nal production costs and the arrival time of products tothe market.

The use of BIT techniques can make a significantdifference in terms of test time and cost in comparisonto traditional testing with off-chip equipment. The di-versity of analog circuit designs, the multitude of theirperformance parameters and their limited observabil-ity, make analog and mixed-signal circuit BIT a verychallenging problem compared to pure digital circuitBIT. Performing the built-in characterization of all thepossible parameters would completely avoid the needof external testing, but the required design time and

silicon area overhead would often make that optionunaffordable. Nevertheless, a reduction of the testingtime, through the built-in aided test of a sub-set of theperformance parameters of a mixed-signal IC, can pos-itively influence the final cost of the chip. A variety ofsolutions have been proposed for analog and mixed-signal BIT [15]. Some techniques have focused on thedetection of faults through alternate tests such as, tran-sient response analysis [24], DC analysis [6] and thewidely explored oscillation-based test [1, 10].

Frequency response characterization is a major taskin the testing process of an analog circuit and one ofthe most expensive, due to the required equipment. Al-though the most important specifications of an analogcircuit such as a filter, programmable gain amplifier,or buffer are related to their frequency response, themajority of the reported BIT and design-for-testability(DFT) techniques for those circuits have proposed in-direct testing methods for the detection of faults anddo not verify the target specifications directly [15].Some of the existing methods for the estimation of the

206 Mendez-Rivera et al.

Fig. 1. Conceptual diagram of the proposed BIT strategy.

frequency response of a DUT are based on DSP tech-niques [8, 9, 18], and the use of analog multipliers [23].

A possible solution to the automated frequency char-acterization problem is the built-in inclusion of a rel-atively compact and simple spectrum analyzer alongwith the analog IC/block to be tested [14]. In addition,since circuit defects and parameter deviations may in-troduce undesired distortions to the signals of interest,having harmonic distortion measurement capabilitiesmay significantly improve the fault coverage of an on-chip testing scheme.

This work presents a BIT architecture that enablesthe frequency response characterization and harmonicdistortion of an analog integrated DUT through a digi-tal interface. The general concept of the described ap-proach for analog testing is shown in Fig. 1. The pro-posed architecture and the design of its main build-ing blocks are described in Sections 2 and 3, re-spectively. Section 4 deals with the experimental re-sults obtained from an IC prototype fabricated throughthe MOSIS service. Conclusions are given in the lastsection.

Fig. 2. On-chip spectrum analyzer architecture.

2. System Description

2.1. System Architecture

The block diagram of the proposed system for the on-chip characterization of analog circuits is shown inFig. 2. It consists of a digital frequency synthesizer,a switched-capacitor (SC) sinewave generator, a SCbandpass filter, a variable gain amplifier (VGA) and afinal stage for the amplitude detection and/or digitiza-tion of the VGA output. Based on an external masterclock, the digital frequency synthesizer generates theappropriate non-overlapping clock signals for the sig-nal generator and the SC filter. In the implementationdescribed in this work, the sinewave generator, basedon SC techniques, delivers a sinusoidal signal with afrequency of 1/16 of the master clock frequency. Theamplitude of the generated signal is adjustable to makeit suitable for the input range of the DUT. The pro-grammable, high-Q bandpass SC filter is a key build-ing block; its function is to select the proper harmoniccomponent at the output of the DUT (Fi , 2 · Fi , 3 · Fi )

An On-Chip Spectrum Analyzer for Analog Built-In Testing 207

for magnitude response or harmonic distortion charac-terization. As it will be explained later, not only thecenter frequency of the bandpass filter, but also its Qfactor can be controlled through the clock signals gen-erated by the digital frequency synthesizer. A digitallycontrolled VGA is included at the output of the filter tofurther improve the dynamic range of the system.

In order to evaluate the magnitude response and har-monic distortion of the DUT at a given frequency, onlythe amplitude of the signal (not the entire waveform)at the output of the VGA needs to be measured. De-pending on the characteristics of the integrated systemin which the DUT is embedded and of the externaltest system, different options can be employed for theoutput building block. A peak detector can measureand hold the amplitude of the signal at the output ofthe VGA; this DC voltage may be directly measuredby the external test system (i.e. if the IEEE 1149.4mixed-signal test bus standard [10, 13] is employed)or digitized on-chip. On the other hand, if an ADC isavailable on-chip, the output of the VGA could be di-rectly digitized. In the latter case, through simple DSPtechniques, in addition to the magnitude and harmonicdistortion of the DUT, the phase response of the DUTcan be evaluated since the phase of the input signal tothe DUT is known and determined by the synthesizer.For the SC spectrum analyzer circuit implementationpresented in this work, a conventional 8-bit algorith-mic ADC was designed and integrated with the rest ofthe system. This block is similar to the one reported in[12], hence it is not further discussed in this work.

One of the main advantages of the proposed system isits inherent synchronization; both the stimuli frequency(Fi ) and the filter center frequency (FBP) are accu-rately controlled by the master clock; when it is swept,both the signal generator and the filter follow theseadjustments. Furthermore, since the Q of the band-pass filter and the gain of the VGA are digitally pro-grammable, the on-chip characterization parameters(frequency, bandwidth, gain) can be fully controlledfrom the external digital tester. The proposed testingstrategy does not require any DUT re-configuration andis able to directly test frequency response related spec-ifications. The overhead of relating the results fromalternate tests to circuit defects is thus avoided.

It is important to mention that, before the character-ization of the DUT, the functionality of the proposedBIT hardware can be easily verified by bypassing theoutput of the signal generator to the bandpass filter asillustrated with a dashed-line arrow in Fig. 2. In this

way, any eventual problem with the BIT system can bedetected and erroneous DUT diagnosis can be avoided.As it will be explained in Section 3, the amplitude ofthe signal generator as well as the gain of the bandpassfilter and the VGA can be precisely controlled. There-fore, in a bypass configuration, each control vector (setof operation parameters for the building blocks) canbe related to an specific expected output amplitude.Not only catastrophic but also parametric faults withinthe BIT circuitry can be detected. For example, asignificant degradation in the gain-bandwidth productof any of the involved Op Amps would always resultin a reduction of the output amplitude and this effectcould not be masked by having an unexpectedly largegain-bandwidth in another Op Amp.

2.2. Modified Architecture for Testingat High Frequencies

Due to the use of SC techniques, the frequency ofoperation of the architecture shown in Fig. 2 is lim-ited to the range of few MHz for implementations in0.5 µm CMOS technology. Nevertheless, the proposedBIT technique can judiciously be extended to the char-acterization of high-frequency components as shownin Fig. 3. Notice that the section within the dashed boxis just a re-drawn version of the architecture in Fig. 2.

The modified architecture incorporates a high-frequency generator, an up-converter (mixer), and adown-converter; these building blocks are available invarious high-frequency integrated systems such as awireless transceiver [22]. In this case, the transfer func-tion characterization can be performed in a bandwidthequivalent to the tuning range of the programmablesinewave generator. The center frequency for the char-acterization (FH) is given by the high-frequency gener-ator. It is important to note that the up-conversion op-eration generates two tones, (at FH + FL and FH − FL )which are applied simultaneously to the DUT. This isan important advantage of the architecture since, inaddition to the magnitude response characterization, atwo-tone intermodulation test (which is very importantto estimate the nonlinearity in high frequency circuits)can be performed without having two explicit high-frequency sources and a power combiner as it is usu-ally done when off-chip equipment is employed. Asillustrated in Fig. 3, after the down-conversion the fun-damental and inter-modulation tones are present (inaddition to other higher frequency tones) and can beanalyzed separately through the SC BP Filter. Before


Fig. 3. Proposed architecture for high frequency DUT characterization.

the characterization of the DUT, the output of the up-converter can be bypassed to the input of the down-converter, as shown with dashed lines in Fig. 3, so thatthe functionality of the BIT hardware can be verified.In addition, in this step, the gain of the up-conversion–down-conversion chain can be measured so that theycan be later subtracted from the measurements per-formed on the DUT.

2.3. Methodology for Built-In Testing

This section presents an algorithm for the automatedtest of a DUT using the proposed BIT scheme. Thecontrol and output variables involved in this BIT systemare summarized in Table 1.

Table 1. Test variables.

F Frequency of the signal applied to DUT

IN Amplitude of the signal applied to DUT

G Gain of the VGA

FBP Center frequency of the band-pass filter

OUT1 Amplitude of the fundamental tone

OUT2 Amplitude of the 2nd harmonic

OUT3 Amplitude of the 3rd harmonic

From the specifications of the DUT, a set of N testfrequencies [F1 F2 . . . . FN ] is defined. Through ade-quate fault modeling, the smaller N to attain the de-sired fault coverage can be found. For each frequency,the appropriate amplitude [Ai ] for the input signal andgain for the VGA [Gi ] are chosen. The amplitude [INi]for the input signal does not necessarily have to bedifferent for each frequency but should be chosen toavoid saturation in the DUT. From the expected mag-nitude response and harmonic distortion of the DUT,each test vector [Fi Ai Gi ] is associated with accept-able boundaries for the output vector [OUT1i OUT2i

OUT3i ]. Note that OUT [1, 2, 3] are the amplitudesof the frequency components at the output of the DUTafter being scaled by the factor G which can be con-trolled accurately. Using the described test parameters,the algorithm shown in Fig. 4 can be employed for theefficient functional verification of the DUT.

3. Building Block Design

3.1. Sinewave Generator

Several approaches for generating sinusoidal signalson-chip have been reported using SC [19, 21] and


Fig. 4. Testing procedure.

sigma-delta modulation [7, 9] techniques. In many ap-plications, these signals can be generated using digitaltechniques and a Digital to Analog Converter (DAC).The amplitude values of an ideally sampled sinusoidalsignal are stored in a Read-Only Memory (ROM) and

Fig. 5. SC sinewave generator.

converted into an analog signal. The obtained sig-nals have very low distortion and are very accurate,however, the required area for the implementation islarge. Another approach uses a frequency synthesizer[24]; this technique, however, is not very robust dueto its complexity and requires a digitally controlledprescaler.

The proposed sinewave generator is based on SCtechniques; Fig. 5 shows the schematic diagram. Itconsists of a programmable gain amplifier whose pre-set gain stages correspond to the values of an ide-ally sampled and held sine wave. The SC signal gen-erator has 4 different gain stages, which generate asinusoidal signal output with 16 steps per period.The ideal capacitor ratios are determined accordingto:

C4

C5= sin

(π

8

)(3.1)

C3

C5+ C4

C5= sin

(2 · π

8

)(3.2)

C2

C5+ C3

C5+ C4

C5= sin

(3 · π

8

)(3.3)

C1

C5+ C2

C5+ C3

C5+ C4

C5= sin

(4 · π

8

)(3.4)

In general, Eqs. (3.1) through (3.4) can be expressedas:

1

C5

N∑i=1

CN−i = sin

(N · π

8

); N ∈ [1, 4] (3.5)

The switch PZ sets the zero of the sinusoidal wave-form. The switches PA1 through PD1 are closed


sequentially (from PA1 to PD1) for one clock period togenerate the four steps of the sine wave. The chargeinjected by the input capacitors is integrated in C5to generate the first quarter-period of the sinusoidalwaveform. Once the maximum value is obtained, theswitches close sequentially for one clock period inthe opposite direction (from PD1 to PA1) to generatethe second quarter-period; in this case the polarity ofthe reference voltage is changed. Pcon switches from+Vref to −Vref to generate negative and positive in-tegration, respectively. An important advantage of thisstructure is that the amplitude of the sinusoidal gen-erator output can be easily programmed by adjustingthe reference voltages or using a bank of capacitors toadjust C5.

The control signals for the switches are generated inthe digital frequency synthesizer block. The requiredcircuitry is simple, resulting in a very compact imple-mentation. It is composed of a 5-bit bi-directional shiftregister with clear and preset controls. The control sig-nals generated by the shift register are synchronizedby two master non-overlapping clock phases φ1 andφ2. Fig. 6 shows the simulated results for the controlsignals and the sinusoidal output.

While the fundamental frequency is well defined, theharmonic distortion components depend on the preci-

Fig. 6. Simulated results: control signals and output of the sine wave generator.

sion of the capacitor ratios that define the segments ofthe sine wave. If layout techniques such as common-centroid are used, the capacitor mismatch can be re-duced to around 0.1%. This error corresponds to a res-olution of 10 bits. A tradeoff between accuracy, systemrobustness and implementation complexity takes us tolimit the maximum resolution of the system to 8 bits(THD ∼ −48 dB), which is the value we used as har-monic distortion specification for both the sine wavegenerator and switched capacitor band pass filter.

The gain-bandwidth product (GBW) of the opera-tional transconductance amplifier (OTA) limits the op-eration frequency of the signal generator. Complexswitched-capacitor circuits using a clock frequencyin the range of 100 MHz have been implemented inCMOS 0.5 µm technology [4, 16]; hence the signalgenerator might operate up to 6 MHz if 16 segmentsare used for the sine wave and the OTA is properly de-signed. In this work, lower frequencies are employedto implement a proof-of-concept of the proposedtechnique.

The signal generators reported in [7, 8] (which arebased on the use of sigma-delta modulation techniques)were implemented in 0.8 µm BiCMOS and 0.35 µmCMOS technologies and show output frequencies of10 MHz and 20 MHz respectively, with a SFDR of


approximately 60 dB. Even though these solutions em-ploy mostly digital circuits, they require analog filteringto remove the out-of-band noise created by the sigma-delta modulator. A possible topology for the requiredfilter is suggested in [8] and employs 2 Op Amps. Itis worth to emphasize that the proposed signal gen-erator requires a single OpAmp and its total numberof transistors is at least one order of magnitude smallerthan the implementations in [7, 8] which use a memoryof 1024 bits. For applications that do not demand anSFDR greater than 50 dB, the proposed signal genera-tor is an efficient solution due to its robust and compactimplementation.

3.2. SC Bandpass Filter

The quality of the harmonic distortion measurement ishighly dependent on the Q of the second order BP filter.The higher the Q, the more accurate the measurementof the harmonic distortion is. However, a practical limitmust be set for the Q of the filter. For a third orderharmonic distortion (HD3) measurement of −50 dB,the fundamental component must be attenuated by afactor of more than 400. This yields to a quality factorof 400 if a single biquadratic section is used. Usuallyhigh Q-factor implementations are translated into largecapacitive spreads.

A second issue to consider is the precision of the cen-ter frequency of the BP filter. A small deviation of thecenter frequency can lead to incorrect measurements.This effect is severe when high Q filters are used. Bothmagnitude and harmonic distortion measurements aresensitive to these errors. Center frequency deviationsof ± 0.5% limits the filter bandwidth to be ∼ f0/100, orQ ∼ 100.

The main issues here are twofold: high-Q implemen-tations and high precision. High-Q filters usually re-quire large capacitor ratios; for better transfer functionprecision a pre-distorted bilinear transformation is thebest choice. Hence, a second order switched-capacitorfilter using the bilinear approximation is employed. Thefilter specifications to be met are fo/ fs = 1/16 in orderto avoid aliasing and Q > 100. First, a conventional de-sign approach is considered. Fig. 7(a) shows a possiblefilter realization; its transfer function is given by:

H (z) =C4 · C5C1 · C3

· z−2 + (C0C1

− C4·C5C1·C3

) · z−1 − C0C1

z−2 + (C2·C4C1·C3

− CQ

C1− 2

) · z−1 − (1 − CQ

C1

) .

(4)

Table 2. Capacitor values for the SC bandpass filter.

Capacitors Typical approach Two clock phases

C0 = CQ 0.1 pF 0.1 pF

C1 = C3 25.6 pF 6.39 pF

C2 = C4 5.02 pF 1.25 pF

C5 0.51 pF 0.51 pF

CTotal 62.9 pF 16.0 pF

The capacitors listed in the second column of Table 2are obtained using conventional switched capacitor de-sign techniques [20].

From Table 2 it can be seen that the capacitor spreadis very large (1:256). Notice that the smallest capacitorsare C Q and C0, which control the quality factor andthe peak gain of the filter. The large capacitive spreadimplies many problems in the design of the filter: hugesilicon area is required and the OTA specifications aremore demanding.

Now, a non-conventional approach for the imple-mentation of a SC bandpass filter is discussed [2]. Tostart with, note that the resistance (Req) of the switched-capacitor CQ , for a high sampling rate, can be approx-imated as:

Req ≈ 1

fs · CQ(5)

where fs is the sampling frequency and CQ is the ca-pacitor that emulates the resistor. If we decrease fs bya factor N , then the equivalent resistance increases bythe same factor N as follows:

R′eq = N · Req = 1( fs

N

) · CQ

= 1

fs · (CQ

N

) (6)

To take advantage of this property of SC-networks[20], with the exception of clocks lumped to CQ , thecapacitors can be scaled down by factor N; this is illus-trated in Fig. 7(b). CQ is also scaled down due to theaction of the slower clocks, as shown in Eq. (6). In theactual implementation, neither C0 nor C5 were scaleddown. The new capacitor values are shown in the thirdcolumn of Table 2. The final values are much smallerthan the original ones, leading to a total capacitanceof only 16 pF. Fig. 8 shows a comparison between thesimulation results of the bandpass filter responses withtypical circuit and two-clock realization (N = 4 for thiscase). The peak gain of the filter and the Q factor areincreased by a factor of 4. In the implemented filter, the


Fig. 7. SC bandpass filter to measure the harmonic distortion of the DUT: (a) Conventional SCbandpass filter. (b) Bandpass filter with additional sampling frequency in CQ. (f1′ = 1

4 · f1 andf2′ = 1

4 · f2).

Fig. 8. Switcap simulation for the filters: One clock and two-clock realization.


Table 3. Capacitor valuesfor the VGA.

Capacitor Value

C0, C1, C7 0.34 pF

C2 , C f 0.2 pF

C3 0.315 pF

C4 0.5 pF

C5 0.792 pF

C6 1.241 pF

Q factor is controlled through the sampling frequencyof CQ ( fSCQ) which comes from the digital frequencysynthesizer. An external 2-bit digital word controls afrequency divider so that fSCQ can be made fS/2 orfS/4 (implementing N factors of 2 and 4 respectively).

3.3. Variable Gain Amplifier

The function of the VGA is to accommodate the am-plitude of the signal coming from the bandpass filter toproperly cover the complete dynamic range of the ADCavoiding saturation or a reduction in resolution due toa small signal at the output of the bandpass filter. Forthis application, amplification factors in 4 dB steps areused; the maximum amplification is 20 dB. The VGAis a capacitive amplifier with capacitors C1 through C7

setting the desired gain and controlled by switches Dthrough H ; Fig. 9 shows the circuit schematic. TheVGA is offset compensated and has low sensitivity tofinite gain errors of the amplifier due to the action ofcapacitors C0 and C7 [17]. C f minimizes the glitchesduring the transition times.

4. Experimental Results

The proposed system was fabricated in the standarddigital technology AMI CMOS 0.5 µm. The chip mi-crophotograph is shown in Fig. 10. The total active areais 0.5 mm2. The largest block is the algorithmic ADCwhich uses 420 µm×330 µm. The total area can be fur-ther reduced if a SC peak detector is employed insteadof the ADC. The integrated built-in testing system pre-sented in [8] is able to perform the frequency responsecharacterization of an analog DUT in the range of MHz;the employed area is 0.67 mm2 in 0.35 µm CMOStechnology. It should be noted that in order to evaluatethe frequency response, the mentioned system requires

Fig. 9. SC variable gain amplifier.

Fig. 10. Microphotograph of the prototype chip.

additional digital signal processing, which would takeapproximately 1.5 mm × 1.5 mm of area [8].

This proof-of-concept prototype is capable of char-acterizing a DUT for frequencies up to 10 KHz. Thelimiting factor in this case is the GBW of the OTA em-ployed in the SC circuits. This OTA uses a bias currentof only 10 µA. At the expense of higher power, SCcircuits implemented in similar technologies can oper-ate in the range of MHz. The high-speed SC circuitsreported in [4, 16] use a clock frequencies in the rangeof 100 MHz and achieve a signal-to-noise ratio greater


Fig. 11. SC sinewave generator measurement results: (a) Measured output signal of the sinewave generator for 3 different output levels. (b)Measured sinusoidal signal spectrum at 10 kHz and ±500 mV reference voltage.

than 50 dB. The clock jitter is not expected to affect thedynamic range of the proposed system if higher clockfrequencies are employed. The obtained experimentalresults for the individual building blocks and the opera-tion of the overall system are presented in the followingsubsections.

4.1. Sinewave Generator

Fig. 11(a) shows three output waveforms from thesinewave generator. The frequency of the signals is10KHz. The amplitude in each case is given by the ref-erence voltages (±Vref in Fig. 5) employed: ±200 mV,±400 mV and ±800 mV. Fig. 11(b) shows the mea-sured spectrum for a 10 KHz signal with amplitude of4 dBm (1Vpp). The second and third order harmonicdistortions are −38 dB. For a 1 KHz signal, the mea-sured total harmonic distortion reduces to −49 dB. Theactive area and power of this on-chip signal generatorare only 280 µm×330 µm (0.09 mm2) and 50 µWrespectively. The smaller of the 2 signal generatorsreported in [7] uses 0.49 mm2 (in BiCMOS 0.8 µm) andthe one in [24] employs 0.2 mm2 (in CMOS 0.35 µm).

4.2. SC Bandpass Filter

Fig. 12 shows the transfer function and programma-bility of the high-Q bandpass filter. For this test,the sampling frequency is 320 kHz, which corre-sponds to a 10 kHz center frequency. The measured

Q-factor/Gains are 120/30 dB, 60/24 dB and 30/18dB. The measured center frequency error when theclock frequency is swept from 32 kHz up to 320 kHzis less than 0.4%; for higher frequencies the errorincreases due to the limited GBW/fs ratio of the SCintegrators. The third order intermodulation distortion(IM3) for the filter is measured as −75 dB. The activearea of this filter is 420 µm × 330 µm and its powerconsumption is 110 µW.

4.3. Variable Gain Amplifier (VGA)

Fig. 13 shows output waveforms from the VGA for 5different gains: 0, 8 12, 16 and 20 dB. The input is a1KHz sinusoidal signal with 160 mVpp of amplitude.The obtained results have a gain error below 0.25 dBfor all cases. The measured HD3 is −44 dB. The activearea of the VGA is 200 µm × 210 µm and its powerconsumption is 50 µW.

4.4. Operation of the Spectrum Analyzer

To evaluate the performance of the proposed techniqueand its implementation, the magnitude response char-acterization of a DUT was carried out with both, thedescribed system and a commercial spectrum analyzer(HP89410A). The test setup is shown in Fig. 14. Theemployed DUT is an Active-RC 2nd order low passfilter with a cut-off frequency of 1 KHz.

Fig. 15 shows a comparison between the resultsachieved with each system. The error in the gain


Table 4. Area overhead analysis.

Overhead of SCRef. Description Technology Area spectrum analyzer

[3] Audio processor (Analog section) 0.5 µm CMOS 12 mm2 4%

[5] Line driver for ADSL 0.25 µm CMOS 5.3 mm2 10%

[22] Cellular transceiver 0.25 µm CMOS 15.4 mm2 3%

Fig. 12. SC bandpass filter measured transfer function for three different Q settings.

Fig. 13. VGA output for different gains.


Fig. 14. Test setup for the proposed system.

Fig. 15. Performance of the proposed system vs. commer-cial test equipment.

Fig. 16. Harmonic distortion characterization results.

measurement (taking as reference the result from thecommercial spectrum analyzer) is less than 0.5 dB forfrequencies up to 9 KHz. For higher frequencies theerror mainly grows due to the shift in the center fre-quency of the bandpass filter, which reduces the effec-tive gain at the frequency of interest. This effect resultsin an overestimation of the attenuation introduced bythe DUT. By increasing the GBW of the OTA, the fre-quency deviation error can be decreased up to a limitwhere the high-speed switches would become the mainlimitation.

To verify the harmonic-distortion measurement ca-pabilities of the proposed system, the output of the DUTis set as a −10 dBm signal with a frequency of 2 KHzand an HD3 of −30 dB (as measured by the HP89410Spectrum Analyzer). The obtained waveforms at the


output of the VGA are shown in Fig. 16. The up-per waveform corresponds to the fundamental com-ponent and the lower waveform to the third harmonic,they are obtained by setting the center frequency ofthe band pass filter to 2 KHz and 6 KHz respectively.The measured HD3 with the implemented prototype is−29.3 dB.

4.5. Application Examples and AreaOverhead Analysis

The described integrated spectrum analyzer can be em-ployed to test analog components such as a line driver[5], analog signal processors [3] and even high fre-quency communications systems [22] as discussed inSection 2.2. Table 4 lists the overhead that the 0.5mm2

employed by the proposed system would add to the areaof recently reported analog circuits [3, 5, 22] which areappropriate DUT candidates.

5. Conclusions

A practical BIT technique for analog circuits has beenpresented. It allows the direct measurement (withoutany additional analog or digital off-chip signal process-ing) of both, the magnitude and harmonic distortioncharacteristics of a DUT at various frequencies. Theuse of complex analog instrumentation is avoided, po-tentially reducing the test time and cost. A CMOS im-plementation of the proposed system was carried out; tothis end, a simple on-chip signal generator and a high Qbandpass filter were developed. Circuit-level consider-ations and experimental results for the different build-ing blocks were provided demonstrating the feasibilityof a built-in spectrum analyzer. With respect to the exis-tent state-of-the-art implementations for analog built-intesting designed in similar technologies, the techniquedescribed in this work is potentially more cost-effectivesolution (due to its robustness and, low area and lowprocessing overhead) for characterizations that do notrequire a dynamic range higher than 50 dB.

Acknowledgments

This work was supported by the Semiconductor Re-search Corporation (SRC) Task ID#957.001. Authorsthank Feyza Berber for her valuable assistance in thecharacterization setup and the MOSIS educational ser-vice for the fabrication of the prototype IC.

References

1. K. Arabi and B. Kaminska, “Oscillation Built-In Self Test(OBIST) for Functional and Structural Testing of Analog andMixed-Signal Integrated Circuits,” Proc. Int. Test Conference,1997, pp. 786–795.

2. J.L. Ausin, J.F. Duque-Carrillo, G. Torelli and E. Sanchez-Sinencio, “Switched-Capacitor Circuits with Periodical Nonuni-form Individual Sampling,” IEEE Trans. on Circuits and SystemsII, vol. 50, no. 8, 2003.

3. F. Balestro, V. Fraisse, G. Martel, D. Morche, P. Senn,G. Le Tourneur, and Y. Mahieux, “A 3-V 0.5-µm CMOSA/D Audio Processor for a Microphone Array,” IEEE Jour-nal of Solid-State Circuits, vol. 32, no. 7, pp. 1122–1126,1997.

4. A. Baschirotto, F. Servi, and R. Castello, “A 200-Ms/s 10-mW Switched-Capacitor Filter un 0.5-µm CMOS Technology,”IEEE Journal Solid-State Circuits, vol. 35, no. 8, pp. 1215–1219,2000.

5. A. Bicakci, C.-S Kim, S.-S. Lee, and C. Conroy, “A 700 mWCMOS Line Driver for ADSL Central Office Applications,”Proc. IEEE Int. Solid-State Circuits Conference, pp. 414–503,2003.

6. A. Chatterjee, B.C. Kim, and N. Nagi, “DC Built-In Self-Testfor Linear Analog Circuits,” IEEE Design & Test of Computers,pp. 26–33, 1996.

7. B. Dufort and G.W. Roberts, “On-Chip Analog Signal Genera-tion for Mixed-Signal Built-In Self-Test,” IEEE Journal Solid-State Circuits, vol. 34, no. 3, pp. 318–330, 1999.

8. M.M. Hafed, N. Abaskharoun, G.W. Roberts, “A 4-GHz Effec-tive Sample Rate Integrated Test Core for Analog and Mixed-Signal Circuits,” IEEE Journal Solid-State Circuits, vol. 37, no.4, pp. 499–514, 2002.

9. J. Huang and K. Cheng, “A Sigma-Delta Modulation BasedBIST Scheme for Mixed-Signal Circuits,” in Proc. IEEE De-sign Automation Conference, 2000, pp. 605–610.

10. G. Huertas, D. Vazquez, E.J. Peralıas, A. Rueda, and J.L.Huertas, “Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell,” IEEE Design and Test ofComputers, vol. 33, no.7, pp. 73–82, 2002.

11. IEEE Std. 1149.4-1999, IEEE Standard for a Mixed-Signal TestBus, IEEE, 1999.

12. D.A. Johns and K. Martin, Analog Integrated Circuit Design,John Wiley & Sons, 1997, pp. 504–507.

13. U. Kac, F. Novac, F. Azais, P. Nouet, and M. Renovell, “Extend-ing IEEE Std. 1149.4 Analog Boundary Modules to EnhanceMixed-Signal Test,” IEEE Design & Test of Computers, vol. 20,no. 2, pp. 32–39, 2003.

14. M. Mendez-Rivera, J. Silva-Martinez, and E. Sanchez-Sinencio,“On-Chip Spectrum Analyzer for Built-in Testing Analog ICs,”Proc. of the IEEE Int. Symposium on Circuits and Systems, vol.5, pp. 61–64, 2003.

15. L.S. Milor, “A Tutorial Introduction to Research on Analog andMixed-Signal Circuit Testing,” IEEE Trans. on Circuits and Sys-tems II, vol. 45, no. 10, pp. 1389–1047, 1998.

16. U.-K. Moon, “CMOS High-Frequency Switched-Capacitor Fil-ters for Telecommunication Applications,” IEEE Journal Solid-State Circuits, vol. 35, no. 2, pp. 212–220, 2000.

17. S. Nagaraj, “A Parasitic-Insensitive Area-Efficient Approachto Realizing Very large Time Constants in Switched-Capacitor


Circuits,” IEEE Trans. on Circuits and Systems II, vol. 36, no.9, pp. 1210–1216, 1989.

18. M. Negreiros, L. Carbo and A.A. Susin, “A Statistical Samplerfor a New On-Line Analog Test Method,” Journal of ElectronicTesting, vol. 19, no. 5, pp. 585–595, 2003.

19. H.C. Patangia and B. Zenone, “A Programmable Switched-Capacitor Sinewave Generator,” Proc. IEEE Midwest Sympo-sium on Circuits and Systems, vol. 1, pp. 165–168, 1994.

20. R. Schaumann and M.E. Van Valkenburg, Design of Analog Fil-ters, Oxford University Press, 2001, pp. 697–704.

21. J. Silva-Martinez and E. Sanchez-Sinencio, “Excess Phase-Jitter Cancellation Method for SC Relaxation Oscillators,” IEEETransactions on Circuits and Systems-II, vol. 34, no. 6, pp. 695–700, 1987.

22. M. Steyaert, J. Janssens, B. De Muer, M. Borremans, and N. Itoh,“A 2-V CMOS Cellular Transceiver Front-End,” IEEE JournalSolid-State Circuits, vol. 35, no. 12, pp. 1895–1907, 2000.

23. A. Valdes-Garcia, J. Silva-Martinez, and E. Sanchez-Sinencio,“An On-Chip Transfer Function Characterization System forAnalog Built-in Testing,” in Proc. IEEE VLSI Test Symposium,2004, pp. 261–266.

24. A.Y. Valero-Lopez, A. Valdes-Garcia, and E. Sanchez-Sinencio,“Frequency Synthesizer for On-Chip Testing and AutomatedTuning,” in Proc. IEEE Int. Symposium on Circuits and Systems,May 2004, pp. 565–568.

25. P.N. Variyam and A. Chatterjee, “Digital-Compatible BIST forAnalog Circuits Using Transient Response Sampling,” IEEE De-sign & Test of Computers, pp. 106–115, July–Sept. 2000.

Marcia G. Mendez-Rivera was born in Irapuato, Mexico in 1972.She received the Communications and Electronics Engineering De-gree from the Universidad de Guanajuato, Guanajuato, Mexico. in1996, the M.Sc. degree from the Instituto Nacional de Astrofisica,Optica y Electronica (INAOE), Puebla, Mexico in 1998 and the M.Sc.from Texas A&M University, College Station in 2002. Her researchinterest is in the design and fabrication of analog and mixed-signalcircuits.

Alberto Valdes-Garcia born in 1978, grew up in San Mateo Atenco,Mexico. He received the B.S. in Electronic Systems Engineering de-gree from the Monterrey Institute of Technology (ITESM), CampusToluca, Mexico in 1999 (with honors as the best score from all ma-jors). Since the fall of 2000 he has been working towards the Ph.D.degree at Analog and Mixed-Signal Center (AMSC), Texas A&MUniversity. During the spring and summer of 2000 he was a DesignEngineer with Motorola Broadband Communications Sector. In thesummer of 2002 he was with the Read Channel Design Group atAgere Systems where he investigated wide tuning range GHz LCVCOs for mass storage applications. During the summer of 2004he was with the Mixed-Signal Communications IC Design Group atthe IBM T. J. Watson Research Center, where worked on design andanalysis of SiGe power amplifiers for millimeter wave radios. Sincethe fall of 2001 he has been a Semiconductor Research Corporation(SRC) research assistant at the AMSC working on the developmentof analog built-in testing techniques. Since the fall of 2000, Albertohas been the recipient of a scholarship from the Mexican NationalCouncil for Science and Technology (CONACYT). He representedMexico in the 1994 ‘Odyssey of the Mind’ World Creativity Contestand in the 1997 International Exposition for Young Scientists. Hispresent research interests include built-in testing implementations

for analog and RF circuits, system level design for wireless receiversand RF circuit design for UltraWideBand (UWB) communications.

Jose Silva-Martinez was born in Tecamachalco, Puebla, Mexico.He received the B.S. degree in electronics from the UniversidadAutonoma de Puebla, Mexico, in 1979, the M.Sc. degree from theInstituto Nacional de Astrofısica Optica y Electronica (INAOE),Puebla, Mexico, in 1981, and the Ph.D. degree from the KatholiekeUnivesiteit Leuven, Leuven Belgium in 1992. From 1981 to 1983,he was with the Electrical Engineering Department, INAOE, wherehe was involved with switched-capacitor circuit design. In 1983, hejoined the Department of Electrical Engineering, Universidad Au-tonoma de Puebla, where he remained until 1993; He was a co-founder of the graduate program on Opto-Electronics in 1992. From1985 to 1986, he was a Visiting Scholar in the Electrical EngineeringDepartment, Texas A&M University. In 1993, he re-joined the Elec-tronics Department, INAOE, and from May 1995 to December 1998,was the Head of the Electronics Department; He was a co-founderof the Ph.D. program on Electronics in 1993. He is currently withthe Department of Electrical Engineering (Analog and Mixed SignalCenter) Texas A&M University, at College Station, where He holdsthe position of Associate Professor. His current field of research is inthe design and fabrication of integrated circuits for communicationand biomedical application. Dr. Silva-Martinez has served as IEEECASS Vice President Region-9 (1997–1998), and as Associate Editorfor IEEE Transactions on Circuits and Systems part-II from 1997–1998 and May 2002–December 2003. Since January 2004 is servingas Associate Editor of IEEE TCAS Part-I. He was the main orga-nizer of the 1998 and 1999 International IEEE-CAS Tour in region9, and Chairman of the International Workshop on Mixed-Mode ICDesign and Applications (1997–1999). He is the inaugural holder ofthe TI Professorship-I in Analog Engineering, Texas A&M Univer-sity. He was a co-recipient of the 1990 European Solid-State CircuitsConference Best Paper Award.

Edgar Sanchez-Sinencio was born in Mexico City, Mexico. Hereceived the degree in communications and electronic engineering(Professional degree) from the National Polytechnic Institute of Mex-ico, Mexico City, the M.S.E.E. degree from Stanford University,CA, and the Ph.D. degree from the University of Illinois at Urbana-Champaign, in 1966, 1970, and 1973, respectively. In 1974 he heldan industrial Post-Doctoral position with the Central Research Lab-oratories, Nippon Electric Company, Ltd., Kawasaki, Japan. From1976 to 1983 he was the Head of the Department of Electronics atthe Instituto Nacional de Astrofısica, Optica y Electronica (INAOE),Puebla, Mexico. He was a Visiting Professor in the Department ofElectrical Engineering at Texas A&M University, College Station,during the academic years of 1979–1980 and 1983-1984. He is cur-rently the TI J Kilby Chair Professor and Director of the Analog andMixed-Signal Center at Texas A&M University. He was the Gen-eral Chairman of the 1983 26th Midwest Symposium on Circuitsand Systems. He was an Associate Editor for IEEE Trans. on Cir-cuits and Systems, (1985–1987), and an Associate Editor for theIEEE Trans. on Neural Networks. He is the former Editor-in-Chiefof the Transactions on Circuits and Systems II. He is co-authorof the book Switched Capacitor Circuits (Van Nostrand-Reinhold1984), and co-editor of the book “Low Voltage/Low-Power Inte-grated Circuits and Systems (IEEE Press 1999). In November 1995he was awarded an Honoris Causa Doctorate by the National In-stitute for Astrophysics, Optics and Electronics, Mexico. The first


honorary degree awarded for Microelectronic Circuit Design contri-butions. He is co-recipient of the 1995 Guillemin-Cauer for his workon Cellular Networks. He is a former IEEE CAS Vice President-Publications. He was also the co-recipient of the 1997 DarlingtonAward for his work on high-frequency filters He received the Cir-cuits and Systems Society Golden Jubilee Medal in 1999. He was

the IEEE Circuits and Systems Society, Representative to the Solid-State Circuits Society (2000–2002). He is presently a member ofthe IEEE Solid-State Circuits Fellow Award Committee. His presentinterests are in the area of RF-Communication circuits and analogand mixed-mode circuit design. He is an IEEE Fellow Member since1992.

an on-chip spectrum analyzer for analog built-in testingvega.unitbv.ro/~olteanu/tehnici de masurare...

Documents