an introduction to the logic of silicon chips introduction to the logic of silicon chips here is a...
TRANSCRIPT
An Introduction to the Logic
of
Silicon Chips
Here is a photo of a typical silicon chip, taken alongside the tip of my little finger. Modern chips canbe made a good deal smaller than the one shown - just a few millimetres across The chipcomprises a (very small) piece of semiconductor material encapsulated in a plastic package, whichhas a number of metal terminal pins connected to the semiconductor and leading out of thepackage. The chip in the photo has 14 pins.
Most silicon chips have a set of 'input' pins, 'output' pins and power-supply pins, and the function ofthe chip is to control the voltages on the output terminals in response to the voltages measured onthe input terminals. Chips are manufactured in tjhousands of different types, and a key differencebetween these is the relationship the chip effects between its inputs and outputs.
Digital chips are primarily associated with inputs and outputs that can only take two legitimatevalues - traditionally called 'nought' and 'one', though the actual voltages may well not be zero andone. But they will have two distinct values and you should not expect to see an output voltagewhich is not one of these two acceptable values. Analogue chips more commonly deal withvoltages that can take an arbitrary (infinite) number of legitimate values between a lower and upperlimit.
This presentation will cover some simple digital chips, explain some of their internal logic, and showhow repeated use of the simplest components can build towards a system of astonishingcomplexity.
In 1
In 2
Out
+ v
0 vBasic 'Nand' gate
Standard Logic Symbol
In 1
In 2Out
Truth Table
In1 In2 Out 0 0 1 1 0 1 0 1 1 1 1 0
In 1
In 2
Out
+ v
0 vBasic 'Nand' gate
Standard Logic Symbol
In 1
In 2Out
Truth Table
In1 In2 Out 0 0 1 1 0 1 0 1 1 1 1 0
0
In 1
In 2
Out
+ v
0 vBasic 'Nand' gate
Standard Logic Symbol
In 1
In 2Out
Truth Table
In1 In2 Out 0 0 1 1 0 1 0 1 1 1 1 0
0 1
In 1
In 2
Out
+ v
0 vBasic 'Nand' gate
Standard Logic Symbol
In 1
In 2Out
Truth Table
In1 In2 Out 0 0 1 1 0 1 0 1 1 1 1 0
0 1
0
In 1
In 2
Out
+ v
0 vBasic 'Nand' gate
Standard Logic Symbol
In 1
In 2Out
Truth Table
In1 In2 Out 0 0 1 1 0 1 0 1 1 1 1 0
1 0
1
Basic Latch
In 1
In 2
Out 1 ('Q')
Out 2 ('/Q')
Truth Table
In1 In2 Q /Q 0 0 1 1 0 1 1 0 1 0 0 1 1 1 Q /Q
Basic Latch
In 1
In 2
Out 1 ('Q')
Out 2 ('/Q')
Truth Table
In1 In2 Q /Q 0 0 1 1 0 1 1 0 1 0 0 1 1 1 Q /Q
1
1
Basic Latch
In 1
In 2
Out 1 ('Q')
Out 2 ('/Q')
Truth Table
In1 In2 Q /Q 0 0 1 1 0 1 1 0 1 0 0 1 1 1 Q /Q
1
11
Basic Latch
In 1
In 2
Out 1 ('Q')
Out 2 ('/Q')
Truth Table
In1 In2 Q /Q 0 0 1 1 0 1 1 0 1 0 0 1 1 1 Q /Q
1
1
10
01
Basic Latch
In 1
In 2
Out 1 ('Q')
Out 2 ('/Q')
Truth Table
In1 In2 Q /Q 0 0 1 1 0 1 1 0 1 0 0 1 1 1 Q /Q
1
1
?
?
Basic Latch
In 1
In 2
Out 1 ('Q')
Out 2 ('/Q')
Truth Table
In1 In2 Q /Q 0 0 1 1 0 1 1 0 1 0 0 1 1 1 Q /Q
0
1
?
?
Basic Latch
In 1
In 2
Out 1 ('Q')
Out 2 ('/Q')
Truth Table
In1 In2 Q /Q 0 0 1 1 0 1 1 0 1 0 0 1 1 1 Q /Q
0
1
1
?
Basic Latch
In 1
In 2
Out 1 ('Q')
Out 2 ('/Q')
Truth Table
In1 In2 Q /Q 0 0 1 1 0 1 1 0 1 0 0 1 1 1 Q /Q
0
1
1
?1
Basic Latch
In 1
In 2
Out 1 ('Q')
Out 2 ('/Q')
Truth Table
In1 In2 Q /Q 0 0 1 1 0 1 1 0 1 0 0 1 1 1 Q /Q
0
1
1
01
Basic Latch
In 1
In 2
Out 1 ('Q')
Out 2 ('/Q')
Truth Table
In1 In2 Q /Q 0 0 1 1 0 1 1 0 1 0 0 1 1 1 Q /Q
0
1
1
01
0
Basic Latch
In 1
In 2
Out 1 ('Q')
Out 2 ('/Q')
Truth Table
In1 In2 Q /Q 0 0 1 1 0 1 1 0 1 0 0 1 1 1 Q /Q
1
1
1
01
0
InOut
Edge Generator
In
Out
Timing Diagram
InOut
Edge Generator
In
Out
Timing Diagram
0
1 1
00
InOut
Edge Generator
In
Out
Timing Diagram
1
1
10
1
InOut
Edge Generator
In
Out
Timing Diagram
1
1
10
0
InOut
Edge Generator
In
Out
Timing Diagram
0
1
10
0
InOut
Edge Generator
In
Out
Timing Diagram
0
0
10
0
InOut
Edge Generator
In
Out
Timing Diagram
0
0
11
0
Data
Clock
Pulse Switching Logic
Data
Clock
Pulse Switching Logic
0
0
Data
Clock
Pulse Switching Logic
0
0
0
0
1
Data
Clock
Pulse Switching Logic
0
0
0
0
1
1
1
Data
Clock
Pulse Switching Logic
1
0
0
0
1
1
1
Data
Clock
Pulse Switching Logic
1
0
0
1(pulse)
1
1
1
1(pulse)
Data
Clock
Pulse Switching Logic
1
0
0
1(pulse)
10
(pulse)
1
1(pulse)
Data
Clock
Pulse Switching Logic
1
0
Data
Clock
Pulse Switching Logic
1
0
0
0
0
1
1
Data
Clock
Pulse Switching Logic
1
1
1(pulse)
0
1
0(pulse)
1(pulse)
1
Data
Clock
Q
/Q
D Type Latch
Q
/QClock
Data
Standard Logic Symbol
Data
Clock
Q
/Q
D Type Latch
Q
/QClock
Data
Standard Logic Symbol
0
0
Data
Clock
Q
/Q
D Type Latch
Q
/QClock
Data
Standard Logic Symbol
0
010
1 101
Data
Clock
Q
/Q
D Type Latch
Q
/QClock
Data
Standard Logic Symbol
0
010
1 101
0
1
Data
Clock
Q
/Q
D Type Latch
Q
/QClock
Data
Standard Logic Symbol
1
Data
Clock
Q
/Q
D Type Latch
Q
/QClock
Data
Standard Logic Symbol
1
010
Data
Clock
Q
/Q
D Type Latch
Q
/QClock
Data
Standard Logic Symbol
1
010
0
1
010
010
Data
Clock
Q
/Q
D Type Latch
Q
/QClock
Data
Standard Logic Symbol
1
010
0
1
010
010
101
Data
Clock
Q
/Q
D Type Latch
Q
/QClock
Data
Standard Logic Symbol
1
010
0
1
010
010
1011
0
0
Q
Clock
Data
Q
Clock
Data
Q
Clock
Data
Q
Clock
Data
4-bit data latch
?
?
?
?
0
Q
Clock
Data
Q
Clock
Data
Q
Clock
Data
Q
Clock
Data
4-bit data latch
?
?
?
?
0
0
1
1
010
Q
Clock
Data
Q
Clock
Data
Q
Clock
Data
Q
Clock
Data
4-bit data latch
?
?
?
?
0
0
1
1
010
Q
Clock
Data
Q
Clock
Data
Q
Clock
Data
Q
Clock
Data
4-bit data latch
0
0
1
1
0
0
1
1
0
Q
Clock
Data
Q
Clock
Data
Q
Clock
Data
Q
Clock
Data
4-bit data latch
1
1
1
0
0
0
1
1
Q
/Q
Clock
Data
Clock
Q
D Latch as Divide by 2
0
0
0 0
1
1
Q
/Q
Clock
Data
Clock
Q
D Latch as Divide by 2
1
1
1 1
0
0
Q
/Q
Clock
Data
Clock
Q
D Latch as Divide by 2
10
0 1
0
0
Q
/Q
Clock
Data
Clock
Q
D Latch as Divide by 2
0
1
1 0
1
1
Q
/Q
Clock
Data
Clock
Q
D Latch as Divide by 2
0
0
0 0
1
1
Q
/Q
Clock
Data
Clock
Q
D Latch as Divide by 2
1
1
1 1
0
0
QClock
Data /Q
QClock
Data /Q
QClock
Data /Q
1 2 3
Q Q Q
D latches as 3 stage binary counter
Clock In0
1
0
1 1
00
QClock
Data /Q
QClock
Data /Q
QClock
Data /Q
1 2 3
Q Q Q
D latches as 3 stage binary counter
Clock In1
0
0
1 1
0010
QClock
Data /Q
QClock
Data /Q
QClock
Data /Q
1 2 3
Q Q Q
D latches as 3 stage binary counter
Clock In0
1
1
0 1
0010
QClock
Data /Q
QClock
Data /Q
QClock
Data /Q
1 2 3
Q Q Q
D latches as 3 stage binary counter
Clock In1
0
1
0 1
0010
QClock
Data /Q
QClock
Data /Q
QClock
Data /Q
1 2 3
Q Q Q
D latches as 3 stage binary counter
Clock In0
1
0
1 0
1010
QClock
Data /Q
QClock
Data /Q
QClock
Data /Q
1 2 3
Q Q Q
D latches as 3 stage binary counter
Clock In1
0
0
1 0
1010
QClock
Data /Q
QClock
Data /Q
QClock
Data /Q
1 2 3
Q Q Q
D latches as 3 stage binary counter
Clock In0
1
1
0 0
1010
QClock
Data /Q
QClock
Data /Q
QClock
Data /Q
1 2 3
Q Q Q
D latches as 3 stage binary counter
Clock In1
0
1
0 0
1010
QClock
Data /Q
QClock
Data /Q
QClock
Data /Q
1 2 3
Q Q Q
D latches as 3 stage binary counter
Clock In0
1
0
1 1
0010
?
Binary Arithmetic
Reminder of Decimal Arithmetic
The 2 key facts are:-
* Symbols available are 0 1 2 3 4 5 6 7 8 9* n 0 has the value 10 x n (e.g. 40 = 4 x 10, 500 = 5 x 10 x 10)
e.g 2 6 + 3 7
====== 6 3
Binary Arithmetic has equivalent facts:-
* Symbols available are 0 1* n 0 has the value 2 x n (e.g. 10 = 1 x 2, 100 = 1 x 2 x 2)
ExamplesDecimal Binary2 1 0
+ 3 1 1 ==== =====
5 1 0 1
3 1 1 * 2 1 0
===== =====6 1 1 0
5 1 0 1 - 2 1 0 ==== =======
3 0 1 1
CarryOut
In A In B In C
DataOut
! (A & B)
! (B & C)
! (A & C)
One-Bit Binary Adder (with carry)
! (A & B & C)
A + B + C
2 or 3 i/ps
In A
In B
In C
DataOut
CarryOut
CarryOut
In A In B In C
DataOut
! (A & B)
! (B & C)
! (A & C)
One-Bit Binary Adder (with carry)
! (A & B & C)
A + B + C
2 or 3 i/ps
In A
In B
In C
DataOut
CarryOut
0 0 0
1
1
1
0
01
1
1
0
1
10
CarryOut
In A In B In C
DataOut
! (A & B)
! (B & C)
! (A & C)
One-Bit Binary Adder (with carry)
! (A & B & C)
A + B + C
2 or 3 i/ps
In A
In B
In C
DataOut
CarryOut
1 0 0
1
1
1
0
01
1
1
1
0
01
CarryOut
In A In B In C
DataOut
! (A & B)
! (B & C)
! (A & C)
One-Bit Binary Adder (with carry)
! (A & B & C)
A + B + C
2 or 3 i/ps
In A
In B
In C
DataOut
CarryOut
1 1 0
0
1
1
1
10
0
1
1
1
10
CarryOut
In A In B In C
DataOut
! (A & B)
! (B & C)
! (A & C)
One-Bit Binary Adder (with carry)
! (A & B & C)
A + B + C
2 or 3 i/ps
In A
In B
In C
DataOut
CarryOut
1 1 1
0
0
0
1
11
1
0
1
0
01
In A
In B
In C
DataOut
CarryOut
In A
In B
In C
DataOut
CarryOut
In A
In B
In C
DataOut
CarryOut
In A
In B
In C
DataOut
CarryOut
4-bit binary adder
In A1
In B1
In A2
In B2
In A3
In B3
In A4
In B4
CarryIn
CarryOut
Out 1
Out 2
Out 3
Out 4
In A
In B
In C
DataOut
CarryOut
In A
In B
In C
DataOut
CarryOut
In A
In B
In C
DataOut
CarryOut
In A
In B
In C
DataOut
CarryOut
4-bit binary adder
In A1
In B1
In A2
In B2
In A3
In B3
In A4
In B4
CarryIn
CarryOut
Out 1
Out 2
Out 3
Out 4
1
1
1
0
0
0
0
In A
In B
In C
DataOut
CarryOut
In A
In B
In C
DataOut
CarryOut
In A
In B
In C
DataOut
CarryOut
In A
In B
In C
DataOut
CarryOut
4-bit binary adder
In A1
In B1
In A2
In B2
In A3
In B3
In A4
In B4
CarryIn
CarryOut
Out 1
Out 2
Out 3
Out 4
1
1
1
0
0
0
0
1
0
0 0
1
1 1
0
QClock
Data /Q
QClock
Data /Q
QClock
Data /Q
1 2 3
Q Q Q
D latches as 3 stage shift register
Clock In
Data In
Data Out
QClock
Data /Q
QClock
Data /Q
QClock
Data /Q
1 2 3
Q Q Q
D latches as 3 stage shift register
Clock In
Data In
Data Out
0 01
0
0 0 1 0
1 0 0 1
1 1 0 0
0 1 1 0
QClock
Data /Q
QClock
Data /Q
QClock
Data /Q
1 2 3
Q Q Q
D latches as 3 stage shift register
Clock In
Data In
Data Out
0 10
1
0 0 1 0
1 0 0 1
1 1 0 0
0 1 1 0
QClock
Data /Q
QClock
Data /Q
QClock
Data /Q
1 2 3
Q Q Q
D latches as 3 stage shift register
Clock In
Data In
Data Out
1 00
1
0 0 1 0
1 0 0 1
1 1 0 0
0 1 1 0
QClock
Data /Q
QClock
Data /Q
QClock
Data /Q
1 2 3
Q Q Q
D latches as 3 stage shift register
Clock In
Data In
Data Out
1 01
0
0 0 1 0
1 0 0 1
1 1 0 0
0 1 1 0
Q1 Q2 Q3 /Q1 /Q2 /Q3
Out 0
Out 1
Out 2
Out 3
Out 4
Out 5
Out 6
Out 7
3-bit decoder