An FPGA Case Study:

Narrowband COFDM Video

Transceiver for Drones, UAV, and UGV

#eelive Produced by EE Times

An FPGA Case Study

• System Definition

• Implementation

• Verification and Validation

CNT1 Narrowband COFDM Video Transmitter for Surveillance and Law Enforcement

CNR1 Narrowband COFDM Video Receiver for Surveillance and Law Enforcement

4

TransmitterCOFDM

TransmitterDAC

I/QVAD

COFDM Receiver

I/QVAD

Filter ADC

Receiver

V = Analog NTSC or PAL Standard Definition Composite VideoA = 2 Channels 25kHz 16 bit AudioD = up to 115.2kbps RS-232 type DataI/Q = complex baseband signal

Target Applications• Close range, Non-LOS, Multipath

– Rapid Deployment Video Surveillance

– Body Worn Video

– Urban Environments

– Unmanned Ground Vehicle Systems

• Long range, Directional LOS

– Unmanned Air Vehicle Systems

• Low power, small form factor, low weight

• Commercial Off The Shelf (COTS)

COFDM Advantage over Legacy

• Coded Orthogonal Frequency Division Modulation

(COFDM)

• Security

– 256 bit AES and proprietary Transmission Scheme

• Bandwidth Conservation

– Video, Audio and Data in 10% occupied bandwidth

• Multipath Immunity

• Leading Technology for Digital Broadcast

– DVB-T, DAB, WiMax (802.16)

Advantage over Competition

• Size and Power Efficiency

• Cost

• Security

• Scalability

• Bandwidth Conservation

• Sensitivity

COFDM

FEC MapperIFFTFFT

Prefix & Preamble

Reed Solomon Encoder

Symbol Interleaver

ConvolutionalEncoder

Bit Interleaver

Viterbi Decoder

VAD I/Q

COFDM Transmitter /

Receiver

DAC / ADC

Transmitter / Receiver

V = Analog NTSC or PAL Standard Definition Composite VideoP = ITU-R BT.656 Pixel Video at 216MbpsJ = JPEG 2000 compressed video 300 to 5500 MbpsA = 0 - 2 channels 16 bit Audio at 4 to 25 Khz (0 to 400 Mbps)D = UART data at 0 to 115200 BAUD (0 to 115 kbps)I/Q = complex baseband signal

I/QSD Video

CodecJPEG

Codec

Audio Codec

V P J

A

D

COFDM – Transmitter / Receiver

J

A

D

I / Q

PHY Layer

External InterfacesJ = 32 bit DMAA = 3 Wire Serial SlaveD = UART

Frame BuffersOverflow and Underflow

Audio Compression

PacketizationData IdentificationData Protection

ThrottlingEncryption

Application Layer

Medium Access Controller

COFDM – Receiver PHYPacket

DetectionTiming

Carrier Frequency

Offset Correction

Channel Estimation

Training Symbol

Data

FFTTraining Symbol

Data FFTPilot

TrackingDemapper FEC

Channel Equalization

RF RequirementsDigital Down

Converter

IF - I/Q

Digital Down

ConverterFilter DAC

AGC

AGC

Antenna Diversity

Baseband - I/Q

Filter DAC

An FPGA Case Study

• System Definition

• Implementation

• Verification and Validation

IP Sources

• Altera

– MegaCores

• FFT, Reed Solomon, Viterbi, Down Convert Filters

– Open Source

• Cordic

• Other Open Source

– AES, UART, I2C (opencores.org), CRC (easics.com)

• Literature and Matlab Modeling

– Convolutional Encoder, DPCM, CRC, Interleavers, AGC, Timing

Correlation, Carrier Frequency Offset Correction, MRC

Equalizer, Pilot Tracking, MLM Demapper

Sustainable and Extensible Design

• Modular Architecture

– PHY(COFDM,CDR1,CDR2)

– MAC (network capable)

– Applications(JAD,SPI,Ethernet)

• Consistent Hierarchical Schematics and Code

• Meaningful Variable Names, Parameterization and Text Macros

– Retarget Coding Schemes

– Bandwidth Optimization

• Internal Interfaces

– Common, Simple, Standard

– Altera IP uses Avalon

• Plan for managed Clock Domains to optimize power

Design Challenges

• Complex and Matrix Mathematics

FFT / IFFTIn Phase (I)

QuadraturePhase (Q)

Real (Re)

Imaginary(Im)

64 QAMConstellation

Design Challenges

• Complex and Matrix Mathematics

Design Challenges

• Fixed Point Arithmetic

0000.00 = 0.00000.01 = 0.250000.10 = 0.50001.00 = 1.00010.00 = 2.00100.00 = 4.01000.00 = 8.0

0100.00 * 0000.10 =

4.0 * 0.5 = 2.0

010000 * 000010 = 000000100000

16.0 * 2.0 = 32.0

0100.00 * 0000.10 = 00000010.0000

= 0010.00

Design Challenges

• Cordic Usage

(Re, Im)

M

A

Re = M*COS(A)Im = M*SIN(A)

Design Challenges

• Fast Divide“Reciprocal Multiplication, a tutorial”, Douglas W. Jones,

THE UNIVERSITY OF IOWA Department of Computer

Science, 1999

A 24 bit reciprocal is estimated in 7 clock cycles using 795

registers

Design Challenges

• Optimizing Throughput and Resources

– Pipelining

– Resource

Sharing

Design Challenges

• IP integration

– Black box IP

• FFT Did not follow Avalon Interface

• Viterbi

– Open Source IP

• 128 bit AES extended to 256 bit

• Cordic Scaling

• UART Page/Device Addressing Extensions

– ASIC IP

• JPEG Codec

• Functional sensitivity to reads and writes, both order and timing

• Frame creation and delivery had finicky flow control

Design Challenges

• Packet Error and Flow Control

– Video

• Throttling Bandwidth

– Compression Rate

– Frames Per Second

• Handling Frame Loss at Delivery

– Audio

• Synchronization to Video

• Handling Data Loss

– Data

• Application Must Support Data Loss

Not a Design Challenge

• Remote Design Team

– 2 Quad Core Workstations

• 8 Processes concurrently (Simulations or Compiles)

– VPN and VNC

• Dedicated LAB PCs for Evaluation

– LogmeIn and RDP

• Remote File access and desktop sharing

– Skype

• Inexpensive personal and conference style communications with additional

desktop and file sharing

– Webcams

• Bench Evaluation and improved communications

– Ethernet Connected Instrumentation

An FPGA Case Study

• System Definition

• Implementation

• Verification and Validation

Validation of Coded AlgorithmsUsing Excel to Develop Signal Processing Models (Analysis ToolPak)

Matlab vs Modelsim vs Bench

• Continuous Repeatable Transmission Mode

• Intermediate Data Capture Multiple Receiver Processing Points

• Stimulus and Results Comparison Conduit between all 3 Methods

– Captured Data Insertions to Matlab and/or Modelsim Simulations

– Matlab Generated Data Insertions into Modelsim

Regression Testing

• Targeted Testing

– AGC, Down Convert, Timing, CFO

– Application Layer

– MAC Layer

– PHY Layer

• Comprehensive Testing

– Rates, Modes, Configuration

• Stress Testing

– Randomized Stimulus Generated by Matlab Channel Models

– Modulation Scheme vs SNR, CFO, Delay Spread

• Automated Comparison of Quality of Results (QOR)

– Bit Error Rate (BER)

– Error Vector Magnitude (EVM)

Error Vector Magnitude (EVM)

Advanced Use of Signaltap

• Signaltap is a soft Logic Analyzer for Altera FPGA

– Xilinx has Chipscope with similar capabilities

• State Based Trigger and Sample

• Complex Trigger and Sample Conditions

• Segmented Captures

• Multiple Instances

– Simultaneous Capture at Different Rates

Advanced Use of Signaltap

Bench Instrumentation