an efficient implementation of floating point multiplier.doc
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8/14/2019 An Efficient Implementation of Floating Point Multiplier.doc
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A Novel Low Power and High Speed Wallace Tree Multiplier for RISC
Processor
AIM
The main aim of the project is to design !A Novel Low Power and High
Speed Wallace Tree Multiplier for RISC Processor"#
A$STRACT
Power dissipation of integrated circuits is a major concern for VLSI circuit
designers. A Wallace tree multiplier is an improved version of tree based multiplier
architecture. It uses carr save addition algorithm to reduce the latenc . This paper
aims at additional reduction of latenc and power consumption of the Wallace tree
multiplier. This is accomplished b the use of !"#$ %"# compressors and b the use
of S&lans& adder. The result shows that the proposed architecture is !!.!' faster
than the conventional ()*S architecture$ along with ++' of reduced powerconsumption reali,ation at #--) ,. The simulations have been carried out using
the TA//01 02A tool emplo ing the 3%-nm ()*S technolog librar file from
Austria )icro S stem.
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$L%C& 'IA(RAM
4ig" Proposed Wallace tree )ultiplier.
T%%LS
5ilin6 7.#IS0$ )odelsim8.!c.
APPLICATI%N A')ANTA(*S
• The latenc of e6isting Wallace tree multiplier which is found to be #9 has
been reduced to +%.
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• At !--) ,$ the power consumed is found to be ++.!-#mW$ which is a
8.38' reduction of that obtained from the e6isting architecture.
R*+*R*NC*S
• List I. Abdellatif$ 0. )ohamed$ :Low;Power 2igital VLSI 2esign$ (ircuits
and S stems$< =luwer Academic Publishers.
• . /eil. Weste and =amran 0shraghian$ :Principles of ()*S VLSI design;
A S stems Perspective$< Pearson 0dition Pvt Ltd. 3rd edition.
• Sreehari Veeramachaneni$ =irthi )$ =rishna Lingamneni Avinash
Sree&anth 1edd Puppala ).>. Srinivas$ :/ovel Architectures for igh;
Speed and Low;Power 3;#$ !;# and %;# (ompressors$< #-th International
(onference on VLSI 2esign$ Pp. 3#!;3#7.
• =. Prasad and =. =. Parhi$ :Low;power !;# and %;# compressors$< in Proc.
of the 3%th Asilomar (onf. on Signals$ S stems and (omputers$ Vol. +$ pp.
+#7?+33.
• Perneti >alasree&anth 1edd and V. S. =anchana >haas&aran$ 2esign of
Adiabatic Tree Adder Structures for Low Power$ International (onference
on 0mbedded S stems @I(0S #-+- organi,ed b (IT$ (oimbatore and
*&lohoma State Bniversit $ +!;+8.
V.Mallikarjuna (Project manager) Mobile No: +91-8297578555 .ISO: 9001- 2008 CERTIFIED COMPANY Branch !: "#$ ra%a$ &Na'()r