Application Note

MB86297A ‘Carmine’

PCB Design Guide

© Fujitsu Microelectronics Europe GmbH History Date Author Version Comment 11.08.2005 MM 1.00 First version 16.08.2005 MM 1.10 Power consumption values added 18.04.2007 AvT 1.20 Update using japanese version 0.3 input (PPT) 04.06.2007 AvT 1.30 Correction Loop Group termination (p. 41) 08.02.2008 AvT 1.40 Correction to table on page 17

1

Warranty and Disclaimer To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts its warranties and its liability for all products delivered free of charge (eg. software include or header files, application examples, Application Notes, target boards, evaluation boards, engineering samples of IC’s etc.), its performance and any consequential damages, on the use of the Product in accordance with (i) the terms of the License Agreement and the Sale and Purchase Agreement under which agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying written materials. In addition, to the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of the Product and any consequential damages in cases of unauthorised decompiling and/or reverse engineering and/or disassembling. Note, all these products are intended and must only be used in an evaluation laboratory environment. 1. Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in

accordance with the accompanying written materials for a period of 90 days form the date of receipt by the customer. Concerning the hardware components of the Product, Fujitsu Microelectronics Europe GmbH warrants that the Product will be free from defects in material and workmanship under use and service as specified in the accompanying written materials for a duration of 1 year from the date of receipt by the customer.

2. Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH´s entire liability

and the customer´s exclusive remedy shall be, at Fujitsu Microelectronics Europe GmbH´s sole discretion, either return of the purchase price and the license fee, or replacement of the Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in original packing and without further defects resulting from the customer´s use or the transport. However, this warranty is excluded if the defect has resulted from an accident not attributable to Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH.

3. To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH

disclaims all other warranties, whether expressed or implied, in particular, but not limited to, warranties of merchantability and fitness for a particular purpose for which the Product is not designated.

4. To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH´s

and its suppliers´ liability is restricted to intention and gross negligence. NO LIABILITY FOR CONSEQUENTIAL DAMAGES To the maximum extent permitted by applicable law, in no event shall Fujitsu

Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever (including but without limitation, consequential and/or indirect damages for personal injury, assets of substantial value, loss of profits, interruption of business operation, loss of information, or any other monetary or pecuniary loss) arising from the use of the Product.

Should one of the above stipulations be or become invalid and/or unenforceable, the remaining stipulations shall stay in full effect.

2

Table of Contents 1 Introduction....................................................................................................................................... 4 2 External Interface Orientation........................................................................................................... 5 3 Power Net Design ............................................................................................................................ 6

3.1 Capacitor Recommendations................................................................................................. 6 3.2 Power Net Wiring ................................................................................................................... 7 3.3 PLL Power Source ................................................................................................................. 7 3.4 Power On and Reset Sequence............................................................................................. 9 3.5 Maximum Power Consumption Values ................................................................................ 10

4 Clock Supply................................................................................................................................... 11 5 PCB Laminating.............................................................................................................................. 12 6 Recommended DDR Memories ..................................................................................................... 14 7 Memory Connection Recommendations ........................................................................................ 15

7.1 Signal Grouping.................................................................................................................... 15 7.2 Damping and Terminal Resistors......................................................................................... 16

7.2.1 Round Trip Time .............................................................................................................. 18 7.2.2 Standard wire length of LOOP wiring .............................................................................. 19

7.2.2.1 With termination, drive mode 2, DDR2 configuration, surface layer ....................... 20 7.2.2.2 With termination, drive mode 2, DDR2 configuration, inner layer........................... 21 7.2.2.3 With termination, drive mode 2, DDR4 configuration, surface layer ....................... 22 7.2.2.4 With termination, drive mode 2, DDR4 configuration, inner layer........................... 23 7.2.2.5 With termination, drive mode 1, DDR2 configuration, surface layer ....................... 24 7.2.2.6 With termination, drive mode 1, DDR2 configuration, inner layer........................... 25 7.2.2.7 With termination, drive mode 1, DDR4 configuration, surface layer ....................... 26 7.2.2.8 With termination, drive mode 1, DDR4 configuration, inner layer........................... 27 7.2.2.9 No termination, drive mode 2, DDR2 configuration, surface layer.......................... 28 7.2.2.10 No termination, drive mode 2, DDR2 configuration, inner layer ............................. 29 7.2.2.11 No termination, drive mode 2, DDR4 configuration, surface layer.......................... 30 7.2.2.12 No termination, drive mode 2, DDR4 configuration, inner layer ............................. 31 7.2.2.13 No termination, drive mode 1, DDR2 configuration, surface layer.......................... 32 7.2.2.14 No termination, drive mode 1, DDR2 configuration, inner layer ............................. 33 7.2.2.15 No termination, drive mode 1, DDR4 configuration, surface layer.......................... 34 7.2.2.16 No termination, drive mode 1, DDR4 configuration, inner layer ............................. 35

7.2.3 Wire Spacing.................................................................................................................... 36 7.3 Differential Impedance ......................................................................................................... 37 7.4 Wiring Topology ................................................................................................................... 38 7.5 Spice Simulation Results ..................................................................................................... 42

8 Other Hints and Recommendations ............................................................................................... 44

3

1 Introduction This application note provides recommendations for signal wiring and describes PCB design constraints necessary to account for the electrical requirements of the MB86297A ‘Carmine graphics controller. Details about the features of the graphics controller and its relevant features and settings can be obtained from the most current version of the MB86297A ‘Carmine’ Hardware Manual, which is available from the following website: http://www.fujitsu.com/emea/services/microelectronics/gdc/gdcdevices/mb86297a-carmine.html

4

2 External Interface Orientation External connections from and to the Carmine device should be roughly oriented as shown in the following diagram. Note that the recommended signal lengths (~5cm in the diagram below) for the DDR connections should be kept symmetrical.

5

3 Power Net Design

3.1 Capacitor Recommendations The power net structure of Carmine consists of seperate nets for 1.2V (Core), 2.5V (DDR-IO) and 3.3V (other IO). The following table indicates how the nets should be buffered around the MB86297A ‘Carmine’ device.

Recommended Buffer Capacitors (min. values) Net No of pins 100uF 10uF 1uF 0.1uF

Comment

VDDI 40 1 2 8 8 Core VDDE 24 1 2 10 10 3.3V IOs

VDDE1 9 3 3 DDR DATA4-7 VDDE2 6 2 2 DDR ADDR VDDE3 9

1

1

3 3 DDR DATA0-3 VTT - 1 1 16 16 For termination

resistors VREF See below

• Place the 0.1uF and 1uF caps as close as possible to the GND pins. • For 0.1uF and 1uF caps (size 1005, 1.0mm x 0.5mm) we recommend using ceramic capacitors. • Use 1608 size components where mounting conditions make it difficult to use 1005 size

components. • Use low ESL (Equivalent Series Inductance) value components where possible in order to

decrease noise generally. • Verify that it is possible to physically place all the capacitors required in their respective locations

using a simulation and manual review. Please refer to the following diagram concerning the connection of VREF

For standard Carmine terminal pins (2mm or smaller) please always place a capacitor of type C2 between the power source V ref and GND.

6

3.2 Power Net Wiring If the overall noise conditions in the core power net are bad, MB86297A ‘Carmine’ can malfunction. For optimal high frequency noise removal, please keep to the guidelines shown below for core power nets (0.1uF and 1uF connections) design. The inductance value due to wiring will be minimized and noise influences are avoided if the power nets are connected close to Carmine’s GND pins as shown.

3.3 PLL Power Source The following diagram show the recommended PLL power source wiring:

Warning: Wiring of PLL_VDDn - please avoid contiguity with the high-speed signal. Digital, power source and wiring to R1 - please keep short (R1 direct or very short connection). Direct please mount R1 and C1 close together.

7

Mount C2 directly under the LSI terminal (2mm or less is standard). C1~PLL_VDDn wiring to the pin - please keep short (above 1mm width, 10mm or less is the standard width). Do not share the GND connection via of C1 and C2 with the vias of other capaictors.

8

3.4 Power On and Reset Sequence The power nets should be asserted in the following sequence : 1. VDDI 1.2V core power net 2. VDDE 2.5V and 3.3V power nets (in any order) 3. any external signals Reset Sequence : 1. At the time of power-on, please input L level to all resets (PLLRESET, TRST, XRST and

DLL_RST). 2. Immediately after the power-on, input a clock to the PLLCLK terminal. 3. Keep PLLRESET and TRST low for at least 1 μs 4. After the release of PLLREST, wait for 200µs until XRST is released 5. Before releasing the PLLRESET, be sure the supplied clock has fully stabilized. 6. Keep the XRST "Low" for a minimum of 10 clocks to safely reset all internal blocks 7. Wait for 1µs until DLL_RST is released 8. Wait for 200μs until the interface systems and external memory controller has stabilized 9. Register access is now possible

Notes • Make sure the PLLVDD pins (PLL power voltage) do not receive a higher voltage than VDDI • VDDE1,2,3 , VREF and VTT depend on the DDR-SDRAM specifications. There are no specific

restrictions on the Carmine side

VDDE

VDDE1,2,3(DRAM)

PLLRESET

XRST

TRST

Note : Clock period shown is just symbolic

PLLCLK

DLL RST

200 μs or more 1 μs or more 200 μs or morePLL LockUp Time DLL LockUp Time

VDDI

1μs or more

9

3.5 Maximum Power Consumption Values The following values are estimated maximum power consumption figures for the different power nets. They should be used for power regulator design. Note At the time this document was written the Carmine chip was still in a pre-massproduction phase. Therefore these values are are subject to change.

Power Net Voltage (V) Peak Current (A) Power Consumption (W)

VDDI 1.2V 1.875 2.25 VDDE 3.3V 0.045 0.15 VDDE1 2.5V 0.16 0.4

Total 2.08 2.8

10

4 Clock Supply Connect a crystal oscillator module directly to the Carmine’s CLK pin. One of the following 4 frequency options below can be selected. The clock select pins CLKSEL0,1 have to be set accordingly.

CLKSEL1 CLKSEL0 Input clock frequency

Multiplication rate

PLL clock output

L L 13.5 MHz × 39 526.500MHz L H 14.32 MHz × 37 529.840MHz H L 17.73 MHz × 30 531.900MHz H H 33.33 MHz × 16 533.280MHz

11

5 PCB Laminating The following tables show the recommended laminating parameters of a PCB for a signal impedance of 50 Ohms. The recommended parameters for 6 and 8 layer PCB’s are shown separately. 6 layer baseplate: Layer Material Thickness

µm Classification Zo1

Ohm Xtalk2

% Tpd ps/cm

L1 Copper foil + plating prepreg

18+17 100

SIG.

56Ω 11%

67ps/cm

L2 Copper foil core material

18 100

V/G

L3 Copper foil prepreg

18 12003

SIG.

54Ω

10%

72ps/cm

L4 Copper foil core material

18 100

SIG.

54Ω

10%

72ps/cm

L5 Copper foil prepeg

18 100

V/G

L6 Copper foil + plating 18+17 SIG. 56Ω 11% 67ps/cm Total = 1742 µm 8 layer baseplate: Layer Material Thickness

µm Classification Zo1

Ohm Xtalk2

% Tpd ps/cm

L1 Copper foil + plating prepreg

18+17 100

SIG.

56Ω 11%

67ps/cm

L2 Copper foil core material

18 100

V/G

L3 Copper foil prepreg

18 7003

SIG.

53Ω

10%

72ps/cm

L4 Copper foil core material

18 100

V/G

L5 Copper foil prepeg

18 7003

SIG

54Ω

10%

72ps/cm

L6 Copper foil core material

18 100

SIG. 54Ω 10% 72ps/cm

L7 Copper foil prepeg

18 100

V/G

L8 Copper foil + plating 18+17 SIG. 56Ω

11% 67ps/cm

Total = 2078 µm

12

Notes The copper thickness stated is 18µm, however 35µm can also be used. In this case, the crosstalk will increase by about 1% and Zo will decrease. 1 based on a baseplate of 100µm, material FR-4 (Er=4.7) 2 based on pattern width=100µm ; pattern pitch=318µm 3 change the board thickness in this case

13

6 Recommended DDR Memories DDR memory devices that can be used with Carmine’s DDR Interface are listed below. Other, similar types can of course be used instead if the interface is identical and other relevant parameters for the application (e.g. temperature range, speed grade etc) are fullfilled. Note that the devices marked with an asterisk (*) are the recommended memory types and those used in the simulations shown in this guideline (please refer to the specifications of the relevant manufacturer for details on the operating temperature conditions etc. of the respective devices). Elpida : EDD1216AATA （8M words × 16 bits，TSOP-66） *

EDD2516KCTA （16M words × 16 bits，TSOP-66）

Samsung : K4D261638E （8M words × 16 bits，TSOP-66） *

K4H561638F （16M words × 16 bits， TSOP-66）

Hynix : HY5DU281622ET （8M words × 16 bits，TSOP-66）

HY5DU561622CT （16M words × 16 bits，TSOP-66）

Micron : MT46V8M16TG （8M words × 16 bits，TSOP-66）

MT46V16M16TG （16M words × 16 bits，TSOP-66）

14

7 Memory Connection Recommendations

7.1 Signal Grouping The following table lists the IO connections of the Carmine DDR memory. The DDR interface connections are classified in the following 14 groups : Signal Group Group Name IO pin names 1 CLK0 MCK0 XMCK0 2 CLK1 MCK1 XMCK1 3 DATA0 MDQS0 MDQ0-7 MDM0 4 DATA1 MDQS1 MDQ8-15 MDM1 5 DATA2 MDQS2 MDQ16-23 MDM2 6 DATA3 MDQS3 MDQ24-31 MDM3 7 DATA4 MDQS4 MDQ32-39 MDM4 8 DATA5 MDQS5 MDQ40-47 MDM5 9 DATA6 MDQS6 MDQ48-55 MDM6 10 DATA7 MDQS7 MDQ56-63 MDM7 11 ADDR MA0-13,

MWE MBA0-1, MCKE

MRAS, MCS

MCAS

12 LOOP0 LOOP0 LOOP0 13 LOOP1 LOOP1 LOOP1 14 RST DLL_RST CKE_START The wiring signal impedance should be 50 Ω. For the layer constitution described in section 4, the wiring width is 100µm. Connections to Vcc/Gnd planes should be able to guarantee sufficient current. Please wire the differential signals of CLK0_Group and CLK1_Group parallel to each other. In addition, also make sure that the positions and number of layer transfers (vias) are the same, keeping the total number of layer transfers as low as possible. Signal wiring should be done on the inner PCB layers in order to decrease EMI and crosstalk (this applies especially to the groups CLK0_Group, CLK1_Group and LOOP_Group). The recommended conditions and the simulation ripple mark diagrams which are shown later in this document apply to the parameters described in previous sections. If the parameters and conditions differ greatly from those described above, you will have to pay special attention to the wiring. Resistors Select resistor values for components stated in the guideline from the E12 series. However, where more precision is necessary and there is no suitable value in the E12 series, select a value from the E24 series. E12 factor line: 10, 12, 15, 18, 22, 27, 33, 39, 47, 56, 68, 82 E24 factor line: 10,11,12,13,15,16,18,20,22,24,27,30,33,36,39,43,47,51,56,62,68,75,82,91 Value of resistance tolerances: please try to select one from the ones listed below For damping resistors: under ±5%

For terminal resistors: under ±5% VTT and division resistors for VREF: under ±1%

15

7.2 Damping and Terminal Resistors The use of terminal resistors is recommended, but a design without terminal resistances can also be done if enough experience is available. Please refer to the following table for resistance values in each case. The mentioned values are calculated in order to match the wiring impedance.

Notes *Rd value: Damping resister value. 1 - Concerning the wire length of LOOP0/1, signal delay and the signal round trip time of LOOP0/1 (CLK signal delay + DQS signal delay on Read): please select wire lengths that produce equal timing values. 2 - The table above assumes that Carmine is in normal DDR drive mode 2.

Notes *Rd value: Damping resister value. 1 - Concerning the wire length of LOOP0/1, signal delay and the signal round trip time of LOOP0/1 (CLK signal delay + DQS signal delay on Read): please select wire lengths that produce equal timing values. 2 - The table above assumes that Carmine is in DDR drive mode 1, weak.

16

The following table shows the wire dispersion (spacing) within the individual groups. The wire length within the group determines the necessary spacing shown below.

Note Concerning the wire length of LOOP0/1, signal delay and the signal round trip time of LOOP0/1 (CLK signal delay + DQS signal delay on Read): please select wire lengths that produce equal timing values. The following table shows the wire dispersion (spacing) between the individual groups. The wire length between the groups determines the necessary spacing shown below.

10 CLK1 vs. ADDR Below 30mm 11 CLK1 vs. DATA4 Below 20mm 12 CLK1 vs. DATA5 Below 20mm 13 CLK1 vs. DATA6 Below 20mm 14 CLK1 vs. DATA7 Below 20mm 15 CLK1 + DATA4 vs. LOOP1 (Note) 16 CLK1 + DATA5 vs. LOOP1 (Note) 17 CLK1 + DATA6 vs. LOOP1 (Note) 18 CLK1 + DATA7 vs. LOOP1 (Note)

Note Concerning the wire length of LOOP0/1, signal delay and the signal round trip time of LOOP0/1 (CLK signal delay + DQS signal delay on Read): please select wire lengths that produce equal timing values.

17

7.2.1 Round Trip Time Concerning the wire length of LOOP0/1, signal delay and the signal round trip time of LOOP0/1 (CLK signal delay + DQS signal delay on Read): please select wire lengths that produce equal timing values. CLK signal delay ①: The time required for the voltage VDDI/2 to cross over to ② and ③ should be the same

DQS signal delay④: The time required for the voltage VDDI/2 to cross over to⑤ should be the same. The signal delay of LOOP~LOOPI ⑥: The time required for the voltage VDDI/2 to cross over to ⑦ should be the same.

18

7.2.2 Standard wire length of LOOP wiring The following table and sections describe the wire lengths of the CLK signal, DQS signal and LOOP0/1 respectively for each wiring configuration. Please determine the LOOP0/1 wire length according to the characteristics of the required CLK and DQS signals.

The following sections describe the parameters for the different configurations shown in the table above.

19

7.2.2.1 With termination, drive mode 2, DDR2 configuration, surface layer

20

7.2.2.2 With termination, drive mode 2, DDR2 configuration, inner layer

21

7.2.2.3 With termination, drive mode 2, DDR4 configuration, surface layer

22

7.2.2.4 With termination, drive mode 2, DDR4 configuration, inner layer

23

7.2.2.5 With termination, drive mode 1, DDR2 configuration, surface layer

24

7.2.2.6 With termination, drive mode 1, DDR2 configuration, inner layer

25

7.2.2.7 With termination, drive mode 1, DDR4 configuration, surface layer

26

7.2.2.8 With termination, drive mode 1, DDR4 configuration, inner layer

27

7.2.2.9 No termination, drive mode 2, DDR2 configuration, surface layer

28

7.2.2.10 No termination, drive mode 2, DDR2 configuration, inner layer

29

7.2.2.11 No termination, drive mode 2, DDR4 configuration, surface layer

30

7.2.2.12 No termination, drive mode 2, DDR4 configuration, inner layer

31

7.2.2.13 No termination, drive mode 1, DDR2 configuration, surface layer

32

7.2.2.14 No termination, drive mode 1, DDR2 configuration, inner layer

33

7.2.2.15 No termination, drive mode 1, DDR4 configuration, surface layer

34

7.2.2.16 No termination, drive mode 1, DDR4 configuration, inner layer

35

7.2.3 Wire Spacing In order to avoid too much crosstalk between the memory signals and a consequent data corruption, the below design conditions are recommended for the Carmine - DDR connections. The spacing of all signal wires within the same group excluding CLK0,CLK1,LOOP,RST and MDQS0-7 should be >200µm

The spacing of signals which are not in the same group excluding CLK0,CLK1,LOOP,RST and MDQS0-7 should be >500µm

The spacing of CLK0,CLK1,LOOP,RST and MDQS0-7 signals to other signals should be >1000µm. If it is difficult to guarantee the 1000µm gap, separate the wires using a GND strip (taking the decrease in wiring impedance into account).

Notes Try to avoid parallel wiring on the top and bottom layers to avoid crosstalk between these layers. The air gap is not required if crosstalk between the top and bottom layers does not occur due to the PCB constitution. If the wiring impedance is higher than 50Ω, crosstalk noise will increase. In this case, increase the wiring spacing over the described values shown above.

36

7.3 Differential Impedance A differential impedance Zdiff=100Ω is recommended. The diagram below shows the relevant conditions.

37

7.4 Wiring Topology The signal wiring topologies for the different configurations are illustrated below. Note The red numerical values apply to normal buffer mode, the blue values are for weak buffer mode. CLK0, CLK1 Group : Using 2 DDR devices without terminal resistors :

Isometric

Using 4 DDR devices without terminal resistors :

Isometric

Using 2 DDR devices with terminal resistors (recommended) :

Isometric Isometric

Keep short <

38

Using 4 DDR devices with terminal resistors (recommended) :

Isometric

DATA Group : Without terminal resistors, using DDR2 configuration:

With terminal resistors (recommended), using DDR2 configuration:

39

ADDR Group : Without terminal resistors (recommended), using DDR2 configuration :

With terminal resistors (recommended), using DDR4 configuration:

40

LOOP Group: Without terminal resistors:

With terminal resistors (recommended) :

Note: Concerning LOOP~LOOPI, signal delay and round trip of LOOP~LOOPI time (=CLK signal delay +DQS signal delay (@Read) – please choose wire lengths that produce equal signal run times (refer to section 7.2.1).

41

7.5 Spice Simulation Results Based on the DDR interface recommendation in this design guide, a SPICE ripple simulation is shown for some signals as reference. Concerning process, temperature and voltage everything was conducted with typical values. The diagrams show DDR pin edge ripple marks (DDR pin side). CLK0, CLK1 Group : Using 2 DDR devices without terminal resistors: Using 2 DDR devices with terminal resistors: (Rec.)

Using 4 DDR devices without terminal resistors: Using 4 DDR devices with terminal resistors: (Rec.)

DATA Group : Using 2 DDR devices, WRITE signal, without terminal resistors: WRITE signal, with terminal resistors: (Rec.)

READ signal, without terminal resistors: READ signal, with terminal resistors: (Rec.)

42

ADDR Group : Using 2 DDR devices, without terminal resistors: (Rec.) Using 4 DDR devices, without terminal resistors: (Rec.)

LOOP Group : LOOPI Pin under typical conditions

43

8 Other Hints and Recommendations

• Please note that the pin multiplexing for the video input pins is different from Coral PA ! The following pin assignment is valid for Carmine : VIN[5:0] = BI[5:0] VIN[7:6] = GI[1:0]

• Please note that the timing spec of PCI bus conforms to the PCI-66 specification ! Especially

take care about the output delay: the taget spec is min.1ns (max.6ns). This meets the PCI-66 spec, but the PCI-33 requires min.2ns (max 11ns) ! See PCI specifications (Timing Parameters of 66MHz and 33MHz Timing) for details !

44